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MT4LC4M4E8DJS
Datasheet
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MICRON MT4LC4M4E8DJ, MT4LC4M4E8DJS Datasheet

TECHNOLOGY, INC.
VCC DQ1 DQ2 WE#
RAS#
*NC/A11
A10
A0 A1 A2 A3
V
CC
1 2 3 4 5 6
8 9 10 11 12 13
26 25 24 23 22 21
19 18 17 16 15 14
VSS DQ4 DQ3 CAS# OE# A9
A8 A7 A6 A5 A4 V
SS
DRAM
4 MEG x 4
EDO DRAM
MT4LC4M4E8, MT4C4M4E8 MT4LC4M4E9, MT4C4M4E9
FEATURES
• Industry-standard x4 pinout, timing, functions and
PIN ASSIGNMENT (Top View)
packages
• State-of-the-art, high-performance, low-power CMOS silicon-gate process
24/26-Pin SOJ
(DA-2)
24/26-Pin TSOP
(DB-2)
• Single power supply (+3.3V ±0.3V or +5V ±10%)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, HIDDEN and CAS#­BEFORE-RAS# (CBR)
• Optional Self Refresh (S) for low-power data retention
• 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh)
• Extended Data-Out (EDO) PAGE MODE access cycle
• 5V-tolerant inputs and I/Os on 3.3V devices
DQ1 DQ2 WE#
RAS#
*NC/A11
A10
V
1 2 3 4 5 6
8
A0
9
A1
10
A2
11
A3
12
CC
13
SS
26
V DQ4
25
DQ3
24
CAS#
23
OE#
22
A9
21
A8
19
A7
18
A6
17
A5
16
A4
15
SS
V
14
V
CC
OPTIONS MARKING
• Voltages
3.3V LC 5V C
• Refresh Addressing 2,048 (i.e. 2K) Rows E8 4,096 (i.e. 4K) Rows E9
• Packages Plastic SOJ (300 mil) DJ Plastic TSOP (300 mil) TG
• Timing 50ns access -5 60ns access -6
• Refresh Rates Standard Refresh None Self Refresh (128ms period) S
• Part Number Example: MT4LC4M4E8DJ-6
Note: The 4 Meg x 4 EDO DRAM base number differentiates the offerings in two places - MT4LC4M4E8. The third field distinguishes the low voltage offering: LC designates VCC = 3.3V and C designates VCC = 5V. The fifth field distinguishes various options: E8 designates a 2K refresh and E9 designates a 4K refresh for EDO DRAMs.
* NC on 2K refresh and A11 on 4K refresh options.
Note: The “#” symbol indicates signal is active LOW.
4 MEG x 4 EDO DRAM PART NUMBERS
PART NUMBER Vcc REFRESH PACKAGE REFRESH
KEY TIMING PARAMETERS
SPEEDtRC
t
RAC
t
PC
t
AA
t
CACtCAS
-5 84ns 50ns 20ns 25ns 13ns 8ns
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
-6 104ns 60ns 25ns 30ns 15ns 10ns
GENERAL DESCRIPTION
The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 con­figuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the column address
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TECHNOLOGY, INC.
,
,,
,,
,,,
,,
GENERAL DESCRIPTION (continued)
(the latter 11 bits for 2K and the latter 10 bits for 4K, address pins A10 and A11 are “don’t care”). READ and WRITE cycles are selected with the WE# input.
A logic HIGH on WE# dictates READ mode, while a logic LOW on WE# dictates WRITE mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# is taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z regardless of the state of OE#. During LATE WRITE or READ-MODIFY­WRITE cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFY-WRITE is attempted while keeping OE# LOW, no write will occur, and the data outputs will drive read data from the accessed location.
The four data inputs and the four data outputs are routed through four pins using common I/O, and pin direction is controlled by WE# and OE#.
PAGE ACCESS
PAGE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE) within a row address­defined page boundary. The PAGE cycle is always initiated
4 MEG x 4
EDO DRAM
with a row address strobed-in by RAS#, followed by a column address strobed-in by CAS#. CAS# may be toggled-in by holding RAS# LOW and strobing-in different column addresses, thus executing faster memory cycles. Returning RAS# HIGH terminates the PAGE MODE of operation, i.e., closes the page.
EDO PAGE MODE
The 4 Meg x 4 EDO DRAM provides EDO PAGE MODE, which is an accelerated FAST PAGE MODE cycle. The primary advantage of EDO is the availability of data-out even after CAS# returns HIGH. EDO allows CAS# precharge time (tCP) to occur without the output data going invalid. This elimination of CAS# output control allows pipeline READs.
FAST PAGE MODE DRAMs have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. EDO PAGE MODE DRAMs operate like FAST PAGE MODE DRAMs, except data will remain valid or become valid after CAS# goes HIGH during READs, pro­vided RAS# and OE# are held LOW. If OE# is pulsed while RAS# and CAS# are LOW, data will toggle from valid data to High-Z and back to the same valid data. If OE# is toggled or pulsed after CAS# goes HIGH while RAS# remains LOW, data will transition to and remain High-Z (refer to
RAS#
CAS#
ADDR
OE#
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IOH
DQ
V
IOL
V
IH
V
IL
ROW
OPEN
COLUMN (A)
VALID DATA (A)
t
OD
t
OES
The DQs go back to Low-Z if
t
OE
t
OES is met.
COLUMN (B)
VALID DATA (A)
VALID DATA (B)
t
OD
t
OEHC
The DQs remain High-Z until the next CAS# cycle
t
if
OEHC is met.
COLUMN (C)
VALID DATA (C)
t
OD
t
OEP
The DQs remain High-Z until the next CAS# cycle
t
if
OEP is met.
COLUMN (D)
VALID DATA (D)
DON’T CARE
UNDEFINED
Figure 1
OE# CONTROL OF DQs
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
2
TECHNOLOGY, INC.
,
,
,
,,,
4 MEG x 4
EDO DRAM
Figure 1). WE# can also perform the function of disabling the output devices under certain conditions, as shown in Figure 2.
During an application, if the DQ outputs are wire OR’d, OE# must be used to disable idle banks of DRAMs. Alter­natively, pulsing WE# to the idle banks during CAS# high time will also High-Z the outputs. Independent of OE# control, the outputs will disable after tOFF, which is refer­enced from the rising edge of RAS# or CAS#, whichever occurs last.
REFRESH
Preserve correct memory cell data by maintaining power and executing any RAS# cycle (READ, WRITE) or RAS# refresh cycle (RAS#-ONLY, CBR or HIDDEN) so that all combinations of RAS# addresses (2,048 for 2K and 4,096 for 4K) are executed within tREF (MAX), regardless of se­quence. The CBR and Self Refresh cycles will invoke the internal refresh counter for automatic RAS# addressing.
An optional Self Refresh mode is also available on the S version. The “S” option allows the user the choice of a fully static, low-power data retention mode or a dynamic refresh mode at the extended refresh period of 128ms. The optional Self Refresh feature is initiated by performing a CBR Re-
fresh cycle and holding RAS# LOW for the specified tRASS. Additionally, the “S” option allows for an extended refresh period of 128ms, or 31.25µs per row for a 4K refresh and
62.5µs per row for a 2K refresh if using distributed CBR Refresh. This refresh rate can be applied during normal operation, as well as during a standby or BATTERY BACKUP mode.
The Self Refresh mode is terminated by driving
RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the
RAS# LOW-to-HIGH transition. If the DRAM controller uses a distributed refresh se­quence, a burst refresh is not required upon exiting Self Refresh RAS#-ONLY or refreshed within the average internal refresh rate
. However, if the DRAM controller utilizes
burst refresh sequence, all rows must be
, prior to
the resumption of normal operation.
STANDBY
Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the RAS# HIGH time.
a
RAS#
CAS#
ADDR
DQ
WE#
OE#
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IOH
V
IOL
V
IH
V
IL
V
IH
V
IL
ROW
OPEN
COLUMN (A)
COLUMN (B)
VALID DATA (A)
t
WHZ
t
WPZ
The DQs go to High-Z if WE# falls and, if tWPZ is met, will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated).
VALID DATA (B)
COLUMN (C)
INPUT DATA (C)
t
WHZ
WE# may be used to disable the DQs to prepare for input data in an EARLY WRITE cycle. The DQs will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated).
DON’T CARE
UNDEFINED
COLUMN (D)
Figure 2
WE# CONTROL OF DQs
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
3
TECHNOLOGY, INC.
4 MEG x 4
EDO DRAM
FUNCTIONAL BLOCK DIAGRAM - 2K REFRESH
WE#
CAS#
A10
RAS#
4
4
4
4
(1 OF 2) ROW TRANSFER
ROW TRANSFER
(1 OF 2)
DD
V VSS
DQ1 DQ2 DQ3 DQ4
OE#
DATA-IN BUFFER
NO. 2 CLOCK GENERATOR
COLUMN
ADDRESS
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
11
11
NO. 1 CLOCK GENERATOR
BUFFER(11)
REFRESH
CONTROLLER
REFRESH COUNTER
11
ROW
ADDRESS
BUFFERS (11)
11
10
ROW
DECODER
1
2048
2048
2048
2048
2048
SELECT
COMPLEMENT
DATA-OUT
BUFFER
COLUMN
DECODER
1024
SENSE AMPLIFIERS
I/O GATING
1024
4096 x 1024 x 4
MEMORY
ARRAY
(2 of 4096)
ROW SELECT
WE#
CAS#
A0 A1 A2 A3 A4 A5 A6 A7 A8
A9 A10 A11
RAS#
NO. 2 CLOCK GENERATOR
10
12
NO. 1 CLOCK GENERATOR
FUNCTIONAL BLOCK DIAGRAM - 4K REFRESH
COLUMN
ADDRESS
BUFFER(10)
REFRESH
CONTROLLER
REFRESH COUNTER
12
ROW
ADDRESS
BUFFERS (12)
12
10
ROW
DECODER
4096
4096
4096
SELECT
COMPLEMENT
ROW SELECT
DATA-IN BUFFER
DATA-OUT
BUFFER
COLUMN
DECODER
1024
SENSE AMPLIFIERS
I/O GATING
1024
4096 x 1024 x 4
MEMORY
ARRAY
(1 of 4096)
4
4
DQ1 DQ2 DQ3 DQ4
4
OE#
4
DD
V V
SS
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
4
4 MEG x 4
TECHNOLOGY, INC.
TRUTH TABLE
ADDRESSES DATA-IN/OUT
FUNCTION RAS# CAS# WE# OE#
t
R
Standby H H→XXXXX High-Z READ L L H L ROW COL Data-Out EARLY WRITE L L L X ROW COL Data-In READ WRITE L L H→LL→H ROW COL Data-Out, Data-In EDO-PAGE-MODE 1st Cycle L H→L H L ROW COL Data-Out READ 2nd Cycle L H→L H L n/a COL Data-Out EDO-PAGE-MODE 1st Cycle L H→L L X ROW COL Data-In EARLY WRITE 2nd Cycle L H→L L X n/a COL Data-In
Any Cycle L L→H H L n/a n/a Data-Out EDO-PAGE-MODE 1st Cycle L H→LH→LL→H ROW COL Data-Out, Data-In READ-WRITE 2nd Cycle L H→LH→LL→H n/a COL Data-Out, Data-In HIDDEN READ L→H→L L H L ROW COL Data-Out REFRESH WRITE L→H→L L L X ROW COL Data-In RAS#-ONLY REFRESH L H X X ROW n/a High-Z CBR REFRESH H→L L H X X X High-Z SELF REFRESH H→L L H X X X High-Z
t
C DQ1-DQ4
EDO DRAM
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
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TECHNOLOGY, INC.
4 MEG x 4
EDO DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Pin Relative to VSS:
3.3V ................................................................ -1V to +4.6V
5V ...................................................................... -1V to +7V
Voltage on NC, Inputs or I/O Pins Relative to VSS:
3.3V ................................................................ -1V to +5.5V
5V ...................................................................... -1V to +7V
Operating Temperature, TA (ambient) .......... 0°C to +70°C
Storage Temperature (plastic).................... -55°C to +150°C
Power Dissipation ............................................................. 1W
Short Circuit Output Current ..................................... 50mA
*Stresses greater than those listed under “Absolute Maxi­mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indi­cated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1)
3.3V 5V
PARAMETER/CONDITION SYMBOL MIN MAX MIN MAX UNITS NOTES
Supply Voltage VCC 3.0 3.6 4.5 5.5 V Input High Voltage:
Valid Logic 1; all inputs, I/Os and any NC VIH 2.0 5.5 2.4 VCC +1 V Input Low Voltage:
Valid Logic 0; all inputs, I/Os and any NCVIL-1.00.8-0.5 0.8V Input Leakage Current:
Any input at VIN (0V ≤ VIN ≤ VIH [MAX]); II -2 2 -2 2 µA 4
all other pins not under test = 0V
Output High Voltage: IOUT = -2mA (3.3V), -5mA (5V) VOH 2.4 - 2.4 - V
Output Low Voltage: IOUT = 2mA (3.3V), 4.2mA (5V) VOL - 0.4 - 0.4 V
Output Leakage Current: Any output at VOUT (0V ≤ VOUT ≤ 5.5V); IOZ -5 5 -5 5 µA DQ is disabled and in High-Z state
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
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4 MEG x 4
TECHNOLOGY, INC.
Icc OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3)
3.3V 5V
2K 4K 2K 4K
PARAMETER/CONDITION SYM SPEED Refresh Refresh Refresh Refresh UNITS NOTES
STANDBY CURRENT: TTL ICC1 ALL1111mA (RAS# = CAS# = VIH)
STANDBY CURRENT: CMOS (non-S version only) ICC2 ALL 500 500 500 500 µA (RAS# = CAS# = other inputs = VCC -0.2V)
STANDBY CURRENT: CMOS (S version only) ICC2 ALL 150 150 150 150 µA (RAS# = CAS# = other inputs = VCC -0.2V)
OPERATING CURRENT: Random READ/WRITE -5 110 90 140 120 mA 5, 6 Average power supply current ICC3 -6 100 80 130 110 (RAS#, CAS#, address cycling: tRC = tRC [MIN])
OPERATING CURRENT: EDO PAGE MODE -5 110 100 110 100 mA 5, 6 Average power supply current (RAS# = VIL,ICC4 -6 100 90 100 90 CAS#, address cycling: tPC = tPC [MIN])
REFRESH CURRENT: RAS#-ONLY -5 110 90 140 120 mA 5, 6 Average power supply current ICC5 -6 100 80 130 110 (RAS# cycling, CAS# = VIH: tRC = tRC [MIN])
REFRESH CURRENT: CBR -5 110 90 140 120 mA 5, 7 Average power supply current ICC6 -6 100 80 130 110 (RAS#, CAS#, address cycling: tRC = tRC [MIN])
REFRESH CURRENT: Extended (S version only) Average power supply current: CAS# = 0.2V or ALL 300 300 300 300 µA 5, 7 CBR cycling; RAS# = tRAS (MIN); WE# = ICC7 VCC -0.2V; A0-A11,OE# and DIN = VCC -0.2V or
0.2V (DIN may be left open) REFRESH CURRENT: Self (S version only)
Average power supply current: CBR with RAS# ≥ tRASS (MIN) and CAS# held LOW; WE# = ICC8 ALL 300 300 300 300 µA 5, 7 VCC -0.2V; A0-A11, OE# and DIN = VCC -0.2V or 0.2V (DIN may be left open)
t
RC 62.5 31.25 62.5 31.25 µs25
EDO DRAM
4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. D47.pm5 – Rev. 3/97 1997, Micron Technology, Inc.
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