MICRON MT4LC4M4A1TG-6S, MT4LC4M4B1DJ-6, MT4LC4M4B1DJ-6S, MT4LC4M4A1DJ-6, MT4LC4M4A1DJ-6S Datasheet

1

4 Meg x 4 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.

4 MEG x 4

FPM DRAM

4 MEG x 4 FPM DRAM PART NUMBERS

REFRESH

PART NUMBER V

CC ADDRESSING PACKAGE REFRESH

MT4LC4M4B1DJ-6 3.3V 2K SOJ Standard
MT4LC4M4B1DJ-6 S 3.3V 2K SOJ Self
MT4LC4M4B1TG-6 3.3V 2K TSOP Standard
MT4LC4M4B1TG-6 S 3.3V 2K TSOP Self
MT4LC4M 4A1DJ-6 3.3V 4K SOJ Standard
MT4LC4M4A1DJ-6 S 3.3V 4K SOJ Self
MT4LC4M4A1TG-6 3.3V 4K TSOP Standard
MT4C4M4A1TG-6 S 3.3V 4K TSOP Self
MT4C4M4B1DJ-6 5V 2K SOJ Standard
MT4C4M4B1DJ-6 S 5V 2K SOJ Self
MT4C4M4B1TG-6 5V 2K TSOP Standard
MT4C4M4B1TG-6 S 5V 2K TSOP Self
MT4C4M4A1DJ-6 5V 4K SOJ Standard
MT4C4M4A1DJ-6 S 5V 4K SOJ Self
MT4C4M4A1TG-6 5V 4K TSOP Standard
MT4C4M4A1TG-6 S 5V 4K TSOP Self

MT4LC4M4B1, MT4C4M4B1
MT4LC4M4A1, MT4C4M4A1

For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/mti/msp/html/datasheet.html

DRAM

FEATURES

• Industry-standard x4 pinout, timing, functions,
and packages

• High-performance, low-power CMOS silicon-gate
process

• Single power supply (+3.3V ±0.3V or +5V ±0.5V)

• All inputs, outputs and clocks are TTL-compatible

• Refresh modes: RAS#-ONLY, HIDDEN and CAS#­BEFORE-RAS# (CBR)

• Optional self refresh (S) for low-power data
retention

• 11 row, 11 column addresses (2K refresh) or
12 row, 10 column addresses (4K refresh)

• FAST-PAGE-MODE (FPM) access

• 5V tolerant inputs and I/Os on 3.3V devices

OPTIONS MARKING

• Voltage

3.3V LC
5V C

• Refresh Addressing
2,048 (2K) rows B1
4,096 (4K) rows A1

• Packages
Plastic SOJ (300 mil) DJ
Plastic TSOP (300 mil) TG

• Timing
50ns access -5
60ns access -6

• Refresh Rates
Standard Refresh None
Self Refresh (128ms period) S*

NOTE: 1. The 4 Meg x 4 FPM DRAM base number differenti-

ates the offerings in one place—MT4LC4M4B1. The
fifth field distinguishes various options: B1
designates a 2K refresh and A1 designates a 4K
refresh for FPM DRAMs.

2. The # symbol indicates signal is active LOW.

*Contact factory for availability

Part Number Example:

MT4LC4M4B1DJ

**NC on 2K refresh and A11 on 4K refresh options.

PIN ASSIGNMENT (Top View)

V

CC

DQ0
DQ1

WE#

RAS#

**NC/A11

A10

A0
A1
A2
A3

V

CC

1
2
3
4
5
6

8
9
10
11
12
13

26
25
24
23
22
21

19
18
17
16
15
14

V

SS

DQ3
DQ2

CAS#
OE#

A9
A8

A7
A6
A5
A4

V

SS

V

CC

DQ0
DQ1

WE#

RAS#

**NC/A11

A10

A0
A1
A2
A3

V

CC

1
2
3
4
5
6

8
9
10
11
12
13

26
25
24
23
22
21

19
18
17
16
15
14

V

SS

DQ3
DQ2

CAS#
OE#

A9

A8
A7
A6
A5
A4

V

SS

24/26-Pin SOJ 24/26-Pin TSOP

KEY TIMING PARAMETERS

SPEEDtRC

t

RAC

t

PC

t

AAtCAC

t

RP

-5 84ns 50ns 20ns 25ns 13ns 30ns

-6 110ns 60ns 35ns 30ns 15ns 40ns

2

4 Meg x 4 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.

4 MEG x 4

FPM DRAM

Additional columns may be accessed by providing valid
column addresses, strobing CAS# and holding RAS#
LOW, thus executing faster memory cycles. Returning
RAS# HIGH terminates the page mode of operation,
i.e., closes the page.

DRAM REFRESH

Preserve correct memory cell data by maintaining
power and executing any RAS# cycle (READ, WRITE)
or RAS# REFRESH cycle (RAS#-ONLY, CBR, or HID­DEN) so that all combinations of RAS# addresses (2,048
for 2K and 4,096 for 4K) are executed within tREF
(MAX), regardless of sequence. The CBR and SELF
REFRESH cycles will invoke the internal refresh counter
for automatic RAS# addressing.

An optional self refresh mode is also available the
“S” version. The self refresh feature is initiated by
performing a CBR REFRESH cycle and holding RAS#
LOW for the specified tRASS. The “S” option allows the
user the choice of a fully static, low-power data reten­tion mode or a dynamic refresh mode at the extended
refresh period of 128ms, or 31.25µs per row for a 4K
refresh and 62.5µs per row for a 2K refresh, when using
a distributed CBR REFRESH. This refresh rate can be
applied during normal operation, as well as during a
standby or battery backup mode.

The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of tRPS. This delay allows for
the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH
transition. If the DRAM controller uses a distributed
CBR refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM con­troller utilizes RAS#-ONLY or burst CBR refresh se­quence, all rows must be refreshed with a refresh rate of

t

RC minimum prior to resuming normal operation.

STANDBY

Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.

GENERAL DESCRIPTION

The 4 Meg x 4 DRAM is a randomly accessed, solid­state memory containing 16,777,216 bits organized in
a x4 configuration. RAS# is used to latch the row
address (first 11 bits for 2K and first 12 bits for 4K). Once
the page has been opened by RAS#, CAS# is used to latch
the column address (the latter 11 bits for 2K and the
latter 10 bits for 4K; address pins A10 and A11 are “Don’t
Care”).

READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. If WE# goes
LOW prior to CAS# going LOW, the output pins
remain open (High- Z) until the next CAS# cycle,
regardless of OE#.

A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE
occurs when WE# falls after CAS# is taken LOW. During
EARLY WRITE cycles, the data outputs (Q) will remain
High-Z regardless of the state of OE#. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE# must be
taken HIGH to disable the data outputs prior to
applying input data. If a LATE WRITE or READ­MODIFY-WRITE is attempted while keeping OE# LOW,
no WRITE will occur, and the data outputs will drive
read data from the accessed location.

The four data inputs and the four data outputs are
routed through four pins using common I/O, and pin
direction is controlled by WE# and OE#.

The MT4LC4M4B1 and MT4LC4M4A1 must be
refreshed periodically in order to retain stored data.

FAST PAGE MODE ACCESS

Page operations allow faster data operations (READ,
WRITE or READ-MODIFY-WRITE) within a row­address-defined page boundary. The page cycle is al­ways initiated with a row address strobed in by RAS#,
followed by a column address strobed in by CAS#.

3

4 Meg x 4 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.

4 MEG x 4

FPM DRAM

FUNCTIONAL BLOCK DIAGRAM – 2K REFRESH

4,096

A0
A1
A2
A3
A4
A5
A6
A7
A8

A9
A10
A11

RAS#

12

12

10

NO. 2 CLOCK
GENERATOR

REFRESH

CONTROLLER

NO. 1 CLOCK
GENERATOR

V

DD

Vss

12

WE#

CAS#

10

COLUMN­ADDRESS

BUFFER(10)

ROW-

ADDRESS

BUFFERS (12)

ROW

DECODER

4,096

1,024

COLUMN

DECODER

OE#

DQ0
DQ1
DQ2
DQ3

4

4

4

4

REFRESH
COUNTER

1,024

4,096 x 1,024 x 4

MEMORY

ARRAY

SENSE AMPLIFIERS

I/O GATING

DATA-OUT

BUFFER

DATA-IN
BUFFER

COMPLEMENT

SELECT

4,096

ROW SELECT

(1 of 4096)

2,048

2,048

A0
A1
A2
A3
A4
A5
A6
A7
A8
A9

A10

RAS#

11

11

11

NO. 2 CLOCK
GENERATOR

REFRESH

CONTROLLER

NO. 1 CLOCK
GENERATOR

V

DD

V

SS

11

WE#

CAS#

10

COLUMN­ADDRESS

BUFFER(11)

ROW-

ADDRESS

BUFFERS (11)

2,048

ROW

DECODER

2,048

1,024

COLUMN

DECODER

OE#

DQ0
DQ1
DQ2
DQ3

4

4

4

4

REFRESH
COUNTER

1

ROW TRANSFER

(2 OF 2)

ROW TRANSFER

(1 OF 2)

1,024

4,096 x 1,024 x 4

MEMORY

ARRAY

SENSE AMPLIFIERS

I/O GATING

DATA-OUT

BUFFER

DATA-IN
BUFFER

COMPLEMENT

SELECT

2,048

ROW SELECT

(2 of 4,096)

FUNCTIONAL BLOCK DIAGRAM – 4K REFRESH

4

4 Meg x 4 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.

4 MEG x 4

FPM DRAM

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Pin Relative to VSS

3.3V............................................. ......... -1V to +4.6V

5V................................................ ............ -1V TO +7V

Voltage on NC, Inputs or I/O Pins Relative to VSS

3.3V............................................. ......... -1V to +5.5V

5V................................................ ............ -1V TO +7V

Operating Temperature, TA (ambient) ....0°C to +70°C

Storage Temperature (plastic) ............ -55°C to +150°C

Power Dissipation ................................................... 1W

*Stresses greater than those listed under “Absolute Maxi­mum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional opera­tion of the device at these or any other conditions above
those indicated in the operational sections of this speci­fication is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect
reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 5, 6) (VCC (MIN) £ VCC£ VCC (MAX))

3.3V 5V

PARAMETER/CONDITION SYMBOL M IN MAX MIN MAX UNITS NOTES

SUPPLY VOLTAGE VCC 3 3.6 4.5 5.5 V
INPUT HIGH VOLTAGE:

Valid Logic 1; All inputs, I/Os and any NC VIH 2 5.5 2.4 Vcc+1 V 24
INPUT LOW VOLTAGE:

Valid Logic 0; All inputs, I/Os and any NC VIL -1.0 0.8 -0.5 0.8 V 24
INPUT LEAKAGE CURRENT:

Any input at VIN [0V £ VIN £ VCC (MAX)]; II -2 2 -2 2 µA
All other pins not under test = 0V

OUTPUT HIGH VOLTAGE:
IOUT = -2mA VOH 2.4 – 2.4 – V

OUTPUT LOW VOLTAGE:
IOUT = 2mA VOL – 0.4 – 0.4 V

OUTPUT LEAKAGE CURRENT:
Any output at VOUT [0V £ VOUT £ VCC (MAX)]; IOZ -5 5 -5 5 µA
DQ is disabled and in High-Z state

5

4 Meg x 4 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.

4 MEG x 4

FPM DRAM

ICC OPERATING CONDITIONS AND MAXIMUM LIMITS

(Notes: 1, 2, 3, 5, 6) [Vcc (MIN) £ Vcc £ Vcc (MAX)]

3.3V 5V

2K 4K 2K 4K

PARAMETER/CONDITION SYM SPEED REFRESH REFRESH REFRESH REFRESH UNITS NOTES

STANDBY CURRENT: TTL I

CC

1 ALL1111mA

(RAS# = CAS# = VIH)
STANDBY CURRENT: CMOS (non-“S” version only) I

CC

2 ALL 500 500 500 500 mA

(RAS# = CAS# = other inputs = VCC - 0.2V)
STANDBY CURRENT: CMOS (“S” version only) I

CC

2 ALL 150 150 150 150 µ A

(RAS# = CAS# = other inputs = VCC - 0.2V)
OPERATING CURRENT: Random READ/WRITE -5 110 90 140 120

Average power supply current I

CC

3 -6 100 80 130 110 m A 23

(RAS#, CAS#, address cycling: tRC = tRC [MIN])
OPERATING CURRENT: FAST PAGE MODE -5 110 100 110 100

Average power supply current I

CC

4 -6 100 90 100 90 m A 23

(RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN])
REFRESH CURRENT: RAS#-ONLY -5 110 90 140 120

Average power supply current I

CC

5 -6 100 80 130 110 m A

(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])
REFRESH CURRENT: CBR -5 110 90 140 120

Average power supply current I

CC

6 -6 100 80 130 110 mA 4, 7

(RAS#, CAS#, address cycling: tRC = tRC [MIN])
REFRESH CURRENT: Extended (“S” version only) ALL 300 300 30 0 300 µ A 4, 7

Average power supply current: CAS# = 0.2V or I

CC

7

CBR cycling; RAS# = tRAS (MIN); WE# = VCC - 0.2V;
A0-A11, OE# and DIN = VCC - 0.2V or 0.2V

t

RC 62.5 31.25 62.5 31.25 µs 23

(DIN may be left open)
REFRESH CURRENT: Self (“S” version only)

Average power supply current: CBR with I

CC

8 ALL 300 300 300 300 µA 4, 7

RAS#  tRASS (MIN) and CAS# held LOW;
WE# = VCC - 0.2V; A0-A11, OE# and
DIN = VCC - 0.2V or 0.2V (DIN may be left open)

CAPACITANCE

(Note: 6)

PARAMETER SYMBOL MAX UNITS

Input Capacitance: Address pins CI1 5pF
Input Capacitance: RAS#, CAS#, WE#, OE# CI2 7pF
Input/Output Capacitance: DQ CIO 7pF

6

4 Meg x 4 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D49_5V.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.

4 MEG x 4

FPM DRAM

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12) [Vcc (MIN) £ Vcc £ Vcc (MAX)]

AC CHARACTERISTICS -5 -6
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Access time from column address

t

AA 25 30 ns

Column-address hold time (referenced to RAS#)

t

AR 38 45 ns

Column-address setup time

t

ASC 0 0 ns

Row-address setup time

t

ASR 0 0 ns

Column address to WE# delay time

t

AWD 42 49 ns 18

Access time from CAS#

t

CAC 13 15 ns

Column-address hold time

t

CAH 8 10 ns

CAS# pulse width

t

CAS 8 10,000 10 10,000 ns

CAS# LOW to “Don’t Care” during Self Refresh

t

CHD 15 15 ns

CAS# hold time (CBR Refresh)

t

CHR 8 10 ns 4

CAS# to output in Low-Z

t

CLZ 0 0 ns 22

CAS# precharge time

t

CP 8 10 ns 13

Access time from CAS# precharge

t

CPA 28 35 ns

CAS# to RAS# precharge time

t

CRP 5 5 ns

CAS# hold time

t

CSH 38 45 ns

CAS# setup time (CBR Refresh)

t

CSR 5 5 ns 4

CAS# to WE# delay time

t

CWD 28 35 ns 18

WRITE command to CAS# lead time

t

CWL 8 10 ns

Data-in hold time

t

DH 8 10 ns 19

Data-in setup time

t

DS 0 0 ns 19

Output disable

t

OD 0 12 0 15 ns 22

Output enable

t

OE 12 15 ns 20

OE# hold time from WE# during

t

OEH 8 10 ns

READ-MODIFY-WRITE cycle
Output buffer turn-off delay

t

OFF 0 12 0 15 ns 17, 22

OE# setup prior to RAS# during HIDDEN REFRESH cycle

t

ORD 0 0 ns

FAST-PAGE-MODE READ or WRITE cycle time

t

PC 20 25 ns

FAST-PAGE-MODE READ-WRITE cycle time

t

PRWC 47 56 ns

Access time from RAS#

t

RAC 50 60 ns

RAS# to column-address delay time

t

RAD 9 12 ns 15

Row-address hold time

t

RAH 9 10 ns

RAS# pulse width

t

RAS 50 10,000 60 10,000 ns

RAS# pulse width (FAST PAGE MODE)

t

RASP 50 125,000 60 125,000 ns

RAS# pulse width during Self Refresh

t

RASS 100 100 µs

Random READ or WRITE cycle time

t

RC 84 104 ns

RAS# to CAS# delay time

t

RCD 11 14 ns 14

READ command hold time (referenced to CAS#)

t

RCH 0 0 ns 16

READ command setup time

t

RCS 0 0 ns

Refresh period (2,048 cycles)

t

REF 32 32 ms

Refresh period (4,096 cycles)

t

REF 64 64 ms