MICRON MT4LC1M16C3TG-6, MT4LC1M16C3TG-6S, MT4LC1M16C3DJ-6, MT4LC1M16C3DJ-6S Datasheet
1 MEG x 16
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
NC
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
NC
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
V
SS
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
NC
NC
WE#
RAS#
NC
NC
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
NC
CASL#
CASH#
OE#
A9
A8
A7
A6
A5
A4
V
SS
FPM DRAM
FPM DRAM
FEATURES
• JEDEC- and industry-standard x16 timing,
functions, pinouts, and packages
• High-performance, low-power CMOS silicon-gate
process
• Single power supply (+3.3V ±0.3V or 5V ±0.5V)
• All inputs, outputs and clocks are TTL-compatible
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR) and HIDDEN
• Optional self refresh (S) for low-power data
retention
• BYTE WRITE and BYTE READ access cycles
• 1,024-cycle refresh (10 row, 10 column addresses)
• FAST-PAGE-MODE (FPM) access
OPTIONS MARKING
• Voltage
3.3V LC
5V C
1
MT4C1M16C3, MT4LC1M16C3
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/datasheets
PIN ASSIGNMENT (Top View)
42-Pin SOJ
44/50-Pin TSOP
• Packages
Plastic SOJ (400 mil) DJ
NOTE: The # symbol indicates signal is active LOW.
Plastic TSOP (400 mil) TG
• Timing
50ns access -5
60ns access -6
• Refresh Rates
Standard Refresh (16ms period) None
Self Refresh (128ms period) S
2
• Operating Temperature Range
Commercial (0oC to +70oC) None
Extended (-20oC to +80oC) ET
Part Number Example:
3
MT4LC1M16C3DJ-5
NOTE: 1. The third field distinguishes the low voltage offering:
KEY TIMING PARAMETERS
SPEEDtRCtRAC
-5 84ns 50ns 20ns 25ns 15ns 30ns
-6 110ns 60ns 35ns 30ns 15ns 40ns
1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.
LC designates VCC = 3.3V and C designates VCC = 5V.
2. Contact factory for availability.
t
PC
t
AAtCAC
3. Available only on MT4C1M16C3 (5V)
t
RP
1 MEG x 16 FPM DRAM PART NUMBERS
PART NUMBER SUPPLY PACKAGE REFRESH
MT4LC1M16C3DJ-6 3.3V SOJ Standard
MT4LC1M16C3DJ-6 S 3.3V SOJ Self
MT4LC1M16C3TG-6 3.3V TSOP Standard
MT4LC1M16C3TG-6 S 3.3V TSOP Self
MT4C1M16C3DJ-6 5V SOJ Standard
MT4C1M16C3TG-6 5V TSOP Standard
GENERAL DESCRIPTION
The 1 Meg x 16 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in
a x16 configuration. The 1 Meg x 16 DRAM has both
BYTE WRITE and WORD WRITE access cycles via two
CAS# pins (CASL# and CASH#). These function identically to a single CAS# on other DRAMs in that either
CASL# or CASH# will generate an internal CAS#.
The CAS# function and timing are determined by
the first CAS# (CASL# or CASH#) to transition LOW and
1
GENERAL DESCRIPTION (continued)
the last CAS# to transition back HIGH. Use of only one
of the two results in a BYTE access cycle. CASL#
transitioning LOW selects an access cycle for the lower
byte (DQ0-DQ7), and CASH# transitioning LOW selects an access cycle for the upper byte (DQ8-DQ15).
Each bit is uniquely addressed through the 20 address bits during READ or WRITE cycles. These are
entered ten bits (A0-A9) at a time. RAS# is used to latch
the first ten bits and CAS# the latter ten bits. The CAS#
function is determined by the first CAS# (CASL# or
CASH#) to transition LOW and the last one to transition
back HIGH. The CAS# function also determines
whether the cycle will be a refresh cycle (RAS#-ONLY)
or an active cycle (READ, WRITE, or READ-WRITE) once
RAS# goes LOW.
The CASL# and CASH# inputs internally generate a
CAS# signal that functions identically to a single CAS#
input on other DRAMs. The key difference is that each
CAS# input (CASL# and CASH#) controls its corre-
1 MEG x 16
FPM DRAM
sponding DQ tristate logic (in conjunction with OE#
and WE#). CASL# controls DQ0-DQ7 and CASH# controls DQ8-DQ15. The two CAS# controls give the
1 Meg x 16 DRAM BYTE WRITE cycle capabilities.
A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE#
or CAS, whichever occurs last. Taking WE# LOW will
initiate a WRITE cycle, selecting DQ0-DQ15. If WE#
goes LOW prior to CAS# going LOW, the output pin(s)
remain open (High-Z) until the next CAS# cycle. If WE#
goes LOW after CAS# goes LOW and data reaches the
output pins, data-out (Q) is activated and retains the
selected cell data as long as CAS# and OE# remain LOW
(regardless of WE# or RAS#). This late WE# pulse results in a READ-WRITE cycle.
The 16 data inputs and 16 data outputs are routed
through 16 pins using common I/O. Pin direction is
controlled by OE# and WE#.
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
WE#
CASL#
CASH#
10
10
NO. 2 CLOCK
GENERATOR
COLUMN-
ADDRESS
BUFFER
REFRESH
CONTROLLER
REFRESH
COUNTER
10
ROW-
ADDRESS
BUFFERS (10)
CAS#
FUNCTIONAL BLOCK DIAGRAM
DATA-IN BUFFER
COLUMN
10
DECODER
1,024
SENSE AMPLIFIERS
I/O GATING
1,024 x 16
10
ROW
DECODER
1,024
1,024 x 1,024 x 16
MEMORY
ARRAY
DQ0
16
DQ15
DATA-OUT
BUFFER
16
16
OE#
RAS#
1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.
NO. 1 CLOCK
GENERATOR
2
V
DD
V
SS
1 MEG x 16
FPM DRAM
GENERAL DESCRIPTION (continued)
The MT4LC1M16C3 must be refreshed periodically
in order to retain stored data.
FAST PAGE MODE ACCESS
FAST-PAGE-MODE operations allow faster data operations (READ, WRITE or READ-MODIFY-WRITE)
within a row-address-defined (A0-A9) page boundary.
The FAST-PAGE-MODE cycle is always initiated with a
row address strobed in by RAS#, followed by a column
address strobed in by CAS#. Additional columns may
be accessed by providing valid column addresses,
strobing CAS# and holding RAS# LOW, thus executing
faster memory cycles. Returning RAS# HIGH terminates the FAST-PAGE-MODE operation.
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standbylevel. The chip is also preconditioned for the
next cycle during the RAS# HIGH time. Memory cell
data is retained in its correct state by maintaining power
WORD WRITE LOWER BYTE WRITE
RAS#
and executing anyRAS# cycle (READ, WRITE) or RAS#
REFRESH cycle (RAS# ONLY, CBR or HIDDEN) so that
all 1,024 combinations of RAS# addresses (A0-A9) are
executed at least every 16ms (128ms on the “S” version), regardless of sequence. The CBR REFRESH cycle
will also invoke the refresh counter and controller for
row-address control.
BYTE ACCESS CYCLE
The BYTE WRITEs and BYTE READs are determined
by the use of CASL# and CASH#. Enabling CASL# will
select a lower byte access (DQ0-DQ7), while enabling
CASH# will select an upper byte access (DQ0-DQ15).
Enabling both CASL# and CASH# selects a WORD
WRITE cycle.
The 1 Meg x 16 DRAM may be viewed as two 1 Meg x
8 DRAMs that have common input controls, with the
exception of the CAS# inputs. Figure 1 illustrates the
BYTE WRITE and WORD WRITE cycles. Figure 2 illustrates BYTE READ and WORD READ cycles.
CASL#
CASH#
WE#
LOWER BYTE
(DQ0-DQ7)
OF WORD
UPPER BYTE
(DQ8-DQ15)
OF WORD
STORED
DATA
X = NOT EFFECTIVE (DON'T CARE)
INPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
0
0
1
0
0
0
0
0
X
X
X
X
X
X
X
X
ADDRESS 0
INPUT
DATA
STORED
STORED
DATA
DATA
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
Figure 1
WORD and BYTE WRITE Example
INPUT
DATA
1
1
0
1
1
1
1
1
X
X
X
X
X
X
X
X
ADDRESS 1
INPUT
DATA
STORED
DATA
1
1
0
1
1
1
1
1
1
0
1
0
1
1
1
1
1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.
3
1 MEG x 16
FPM DRAM
Additionally, both bytes must always be of the same
mode of operation if both bytes are active. A CAS#
precharge must be satisfied prior to changing modes of
operation between the upper and lower bytes. For example, an EARLY WRITE on one byte and a LATE WRITE
on the other byte are not allowed during the same cycle.
However, an EARLY WRITE on one byte and a LATE
WRITE on the other byte, after a CAS# precharge has
been satisfied, are permissible.
DRAM REFRESH
Preserve correct memory cell data by maintaining
power and executing any RAS# cycle (READ, WRITE) or
RAS# REFRESH cycle (RAS#-ONLY, CBR or HIDDEN)
so that all 1,024 combinations of RAS# addresses are
executed within tREF (MAX), regardless of sequence.
The CBR and EXTENDED and SELF REFRESH cycles
will invoke the internal refresh counter for automatic
RAS# addressing.
An optional self refresh mode is available on the “S”
version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LOW
for the specified tRASS. The “S” option allows the user
WORD READ LOWER BYTE READ
RAS#
the choice of a fully static, low-power data retention
mode or a dynamic refresh mode at the extended refresh period of 128ms, or 125µs per row, when using a
distributed CBR REFRESH. This refresh rate can be
applied during normal operation, as well as during a
standby or battery backup mode.
The self refresh mode is terminated by driving
RAS# HIGH for a minimum time of tRPS. This delay
allows for the completion of any internal refresh cycles
that may be in process at the time of the RAS# LOWto-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not
required upon exiting self refresh. However, if the
DRAM controller utilizes a RAS#-ONLY or burst CBR
refresh sequence, all 1,024 rows must be refreshed using a minimum tRC refresh rate prior to resuming normal operation.
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.
CASL#
CASH#
LOWER BYTE
(DQ0-DQ7)
OF WORD
UPPER BYTE
(DQ8-DQ15)
OF WORD
WE#
STORED
Z = High-Z
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
STORED
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
STORED
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
OUTPUT
Figure 2
WORD and BYTE READ Example
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
ADDRESS 1ADDRESS 0
OUTPUT
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
STORED
DATA
1
1
0
1
1
1
1
1
0
1
0
1
0
0
0
0
1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.
4
1 MEG x 16
FPM DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Pin Relative to VSS
3.3V ..................................................... -1V to +4.6V
5V ........................................................... -1V TO +7V
Voltage on NC, Inputs or I/O Pins Relative to V
3.3V ..................................................... -1V to +5.5V
5V ........................................................... -1V TO +7V
Operating Temperature
TA (commercial) ...................................... 0°C to +70°C
TA (extended "ET") ............................ -20°C to +80°C
Storage Temperature (plastic) ............-55°C to +150°C
Power Dissipation ........................................................ 1W
SS
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 5, 6; notes can be found on page 9); VCC (MIN) ≤ VCC ≤ VCC (MAX)
3.3V 5V
PARAMETER/CONDITION SYMBOL MIN MAX MIN MAX UNITS NOTES
SUPPLY VOLTAGE VCC 3 3.6 4.5 5.5 V
INPUT HIGH VOLTAGE:
Valid Logic 1; All inputs, I/Os and any NC VIH 2 5.5 2.4 VCC + 1 V
INPUT LOW VOLTAGE:
Valid Logic 0; All inputs, I/Os and any NC VIL -1.0 0.8 -0.5 0.8 V
INPUT LEAKAGE CURRENT:
Any input at VIN (0V ≤ VIN ≤ VCC + 0.3V); II -2 2 -2 2 µA
All other pins not under test = 0V
OUTPUT HIGH VOLTAGE:
IOUT = -2mA VOH 2.4 – 2.4 – V
OUTPUT LOW VOLTAGE:
IOUT = 2mA VOL – 0.4 – 0.4 V
OUTPUT LEAKAGE CURRENT:
Any output at VOUT [0V ≤ VOUT ≤ VCC (MAX)]; IOZ -5 5 -5 5 µA
DQ is disabled and in High-Z state
1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.
5
1 MEG x 16
FPM DRAM
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3, 5, 6; notes can be found on page 9); VCC (MIN) ≤ VCC ≤ VCC (MAX)
PARAMETER/CONDITION SYMBOL SPEED 3.3V 5V UNITS NOTES
STANDBY CURRENT: TTL ICC1 ALL 1 2 mA
(RAS# = CAS# = VIH)
STANDBY CURRENT: CMOS (non-“S” version only) I
(RAS# = CAS# = other inputs = VCC - 0.2V)
STANDBY CURRENT: CMOS (“S” version only) ICC2 ALL 150 150 µA
(RAS# = CAS# = other inputs = VCC - 0.2V)
OPERATING CURRENT: Random READ/WRITE -5 180 190
Average power supply current I
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
OPERATING CURRENT: FAST PAGE MODE -5 110 120
Average power supply current ICC4 -6 90 110 mA 23
(RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN])
REFRESH CURRENT: RAS#-ONLY -5 180 190
Average power supply current ICC5 -6 170 180 mA
(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])
REFRESH CURRENT: CBR -5 180 180
Average power supply current ICC6 -6 170 180 mA 4, 7
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
REFRESH CURRENT: Extended (“S” version only)
Average power supply current: CAS# = 0.2V or CBR cycling; ICC7 A LL 300 300 µA 4, 7
RAS# = tRAS (MIN); WE# = VCC - 0.2V; A0-A11, OE# and
DIN = VCC - 0.2V or 0.2V (DIN may be left open)
REFRESH CURRENT: Self (“S” version only)
Average power supply current: CBR with RAS# ž ICC8 ALL 300 300 µA 4, 7
t
RASS (MIN) and CAS# held LOW; WE# = VCC - 0.2V;
A0-A11, OE# and DIN = VCC - 0.2V or 0.2V
(DIN may be left open)
CC2 ALL 500 500 µ A
CC3 -6 170 180 mA 23
CAPACITANCE
(Note: 2; notes can be found on page 9);
PARAMETER SYMBOL MAX UNITS
Input Capacitance: Addresses CI1 5pF
Input Capacitance: RAS#, CASL#, CASH#, WE#, OE# CI2 7pF
Input/Output Capacitance: DQ CIO 7pF
1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.
6
1 MEG x 16
FPM DRAM
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12; notes can be found on page 9); VCC (MIN) ≤ VCC ≤ VCC (MAX)
AC CHARACTERISTICS -5 -6
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Access time from column address
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Column address to WE# delay time
Access time from CAS
Column-address hold time
CAS# pulse width
CAS# LOW to “Don’t Care” during Self Refresh
CAS# hold time (CBR Refresh)
Last CAS# going LOW to first CAS# to return HIGH
CAS# to output in Low-Z
CAS# precharge time
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
WRITE command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable
Output enable
OE# hold time from WE# during
READ-MODIFY-WRITE cycle
Output buffer turn-off delay
OE# setup prior to RAS# during HIDDEN Refresh cycle
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
RAS# to column-address delay time
Row-address hold time
RAS# pulse width
RAS# pulse width (FAST PAGE MODE)
RAS# pulse width (Self Refresh)
Random READ or WRITE cycle time
RAS# to CAS# delay time
READ command hold time (referenced to CAS)
READ command setup time
Refresh period (1,024 cycles)
Refresh period (1,024 cycles) “S” version
RAS# precharge time
RAS# to CAS# precharge time
RAS# precharge time (Self Refresh)
READ command hold time (referenced to RAS#)
RAS# hold time
READ-WRITE cycle time
t
AA 25 30 ns
t
AR 38 45 ns
t
ASC 0 0 ns 27
t
ASR 0 0 ns
t
AWD 42 49 ns 18
t
CAC 15 15 ns 29
t
CAH 8 10 ns 27
t
CAS 8 10,000 10 10,000 ns 32, 35
t
CHD 15 15 ns
t
CHR 8 10 ns 4, 28
t
CLCH 10 10 ns 30
t
CLZ 0 0 ns 26, 29
t
CP 8 5 ns 30
t
CPA 28 35 ns 28
t
CRP 5 5 ns 28
t
CSH 38 45 ns 28
t
CSR 5 5 ns 4, 27
t
CWD 28 35 ns 18, 27
t
CWL 8 10 ns 23, 29
t
DH 8 10 ns 19, 29
t
DS 0 0 ns 19, 29
t
OD 0 12 0 15 ns 17, 26, 29
t
OE 12 15 ns 22
t
OEH 8 10 ns 20
t
OFF 0 12 0 15 ns 11, 17, 23
t
ORD 0 0 ns
t
PC 20 25 ns 31
t
PRWC 47 56 ns 31
t
RAC 50 60 ns
t
RAD 9 12 ns 20
t
RAH 9 10 ns
t
RAS 50 10,000 60 10,000 ns
t
RASP 50 125,000 60 125,000 ns
t
RASS 100 100 µs
t
RC 84 104 ns
t
RCD 11 14 ns 14, 27
t
RCH 0 0 ns 16, 28
t
RCS 0 0 ns 27
t
REF 16 16 ms
t
REF 128 128 ms
t
RP 30 40 ns
t
RPC 5 5 ns
t
RPS 90 105 ns
t
RRH 0 0 ns 16
t
RSH 13 15 ns 36
t
RWC 116 140 ns
1 Meg x 16 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D51_5V_B.p65 – Rev. B; Pub 3/01 ©2001, Micron Technology, Inc.
7
Loading...