MICRON MT4LC16M4H9TG-6S, MT4LC16M4H9DJ-6S, MT4LC16M4H9TG-5, MT4LC16M4H9TG-5S, MT4LC16M4H9DJ-5 Datasheet

...

16 MEG x 4

DQ0 DQ1

NC NC NC NC

WE#

RAS#

A0 A1 A2 A3 A4 A5

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

Vss

DQ3 DQ2

NC NC NC CAS# OE# NC

/A12**

A11 A10 A9 A8 A7 A6

Vss

EDO DRAM

DRAM

FEATURES

• Single +3.3V ±0.3V power supply

• Industry-standard x4 pinout, timing, functions, and packages

• 12 row, 12 column addresses (H9) or 13 row, 11 column addresses (G3)

• High-performance CMOS silicon-gate process

• All inputs, outputs and clocks are LVTTL-compatible

• Extended Data-Out (EDO) PAGE MODE access

• Optional self refresh (S) for low-power data retention

• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH distributed across 64ms

OPTIONS MARKING

• Refresh Addressing 4,096 (4K) rows H9 8,192 (8K) rows G3

• Plastic Packages 32-pin SOJ (400 mil) DJ 32-pin TSOP (400 mil) TG

MT4LC16M4G3, MT4LC16M4H9

For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/mti/msp/html/datasheet.html

PIN ASSIGNMENT (Top View)

32-Pin SOJ 32-Pin TSOP

Vss

1 2

DQ0

DQ1

WE#

RAS#

**NC on H9 version, A12 on G3 version

16 MEG x 4 EDO DRAM PART NUMBERS

DQ3

DQ2

CAS#

OE#

NC/A12**

A11

A10

Vss

• Timing 50ns access -5 60ns access -6

• Refresh Rates Standard Refresh None Self Refresh (128ms period) S*

NOTE: 1. The 16 Meg x 4 EDO DRAM base number

differentiates the offerings in one place— MT4LC16M4H9. The fifth field distinguishes the address offerings: H9 designates 4K addresses and G3 designates 8K addresses.

PART NUMBER ADDRESSING PACKAGE REFRESH

MT4LC16M4H9DJ-x 4K SOJ Standard MT4LC16M4H9DJ-x S 4K SOJ Self MT4LC16M4H9TG-x 4K TSOP Standard MT4LC16M4H9TG-x S 4K TSOP Self MT4LC16M4G3DJ-x 8K SOJ Standard MT4LC16M4G3DJ-x S 8K SOJ Self MT4LC16M4G3TG-x 8K TSOP Standard MT4LC16M4G3TG-x S 8K TSOP Self

x = speed

REFRESH

2. The “#” symbol indicates signal is active LOW.

*Contact factory for availability

Part Number Example:

MT4LC16M4H9DJ-6

KEY TIMING PARAMETERS

SPEEDtRC

-5 84ns 50ns 20ns 25ns 13ns 8ns

-6 104ns 60ns 25ns 30ns 15ns 10ns

RAC

AAtCACtCAS

GENERAL DESCRIPTION

The 16 Meg x 4 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to

3.6V. The MT4LC16M4H9 and MT4LC16M4G3 are functionally organized as 16,777,216 locations containing 4 bits each. The 16,777,216 memory locations are arranged in 4,096 rows by 4,096 columns on the H9 version and 8,192 rows by 2,048 columns on the G3 version. During READ or WRITE cycles, each location is

FUNCTIONAL BLOCK DIAGRAM

MT4LC16M4G3 (13 row addresses)

16 MEG x 4 EDO DRAM

WE#

CAS#

A0 A1 A2 A3 A4 A5 A6 A7 A8

A9 A10 A11 A12

RAS#

NO. 2 CLOCK

GENERATOR

COLUMN-

ADDRESS

BUFFER(11)

REFRESH

CONTROLLER

REFRESH

COUNTER

ROW-

ADDRESS

BUFFERS (13)

NO. 1 CLOCK

GENERATOR

CONTROL

LOGIC

ROW

DECODER

8,192

SELECT

COMPLEMENT

ROW SELECT

FUNCTIONAL BLOCK DIAGRAM

MT4LC16M4H9 (12 row addresses)

DATA-IN

BUFFER

DATA-OUT

BUFFER

COLUMN

DECODER

2,048

SENSE AMPLIFIERS

I/O GATING

2,048

8,192 x 2,048 x 4

MEMORY

ARRAY

DQ0 DQ1 DQ2 DQ3

OE#

WE#

CAS#

A9 A10 A11

RAS#

NO. 2 CLOCK GENERATOR

COLUMN-

ADDRESS

BUFFER(12)

REFRESH

CONTROLLER

REFRESH

COUNTER

ROW-

ADDRESS

BUFFERS (12)

NO. 1 CLOCK GENERATOR

DATA-IN

BUFFER

CONTROL

LOGIC

ROW

DECODER

4,096

SELECT

COMPLEMENT

DATA-OUT

BUFFER

COLUMN DECODER

4,096

SENSE AMPLIFIERS

I/O GATING

4,096

4,096 x 4,096 x 4

ROW SELECT

MEMORY

ARRAY

DQ0 DQ1 DQ2 DQ3

OE#

V V

GENERAL DESCRIPTION (Continued)

uniquely addressed via the address bits. First, the row address is latched by the RAS# signal, then the column address is latched by CAS#. The device provides EDOPAGE-MODE operation, allowing for fast successive data operations (READ, WRITE, or READ-MODIFYWRITE) within a given row.

The 16 Meg x 4 DRAM must be refreshed periodically

in order to retain stored data.

DRAM ACCESS

Each location in the DRAM is uniquely addressable, as mentioned in the General Description. The data for each location is accessed via the four I/O pins (DQ0DQ3). A logic HIGH on WE# dictates read mode, while a logic LOW on WE# dictates write mode. During a WRITE cycle, data-in (D) is latched by the falling edge of WE# or CAS#, whichever occurs last. An EARLY WRITE occurs when WE# is taken LOW prior to CAS# falling. A LATE WRITE or READ-MODIFY-WRITE occurs when WE# falls after CAS# is taken LOW. During EARLY WRITE cycles, the data outputs (Q) will remain High-Z, regardless of the state of OE#. During LATE WRITE or READ-MODIFY-WRITE cycles, OE# must be taken HIGH to disable the data outputs prior to applying input data. If a LATE WRITE or READ-MODIFYWRITE is attempted while keeping OE# LOW, no WRITE will occur, and the data outputs will drive read data from the accessed location.

EDO PAGE MODE

DRAM READ cycles have traditionally turned the output buffers off (High-Z) with the rising edge of CAS#. If CAS# went HIGH and OE# was LOW (active), the output buffers would be disabled. The 16 Meg x 4 DRAM offers an accelerated page mode cycle by eliminating output disable from CAS# HIGH. This option is called EDO and it allows CAS# precharge time (tCP) to occur without the output data going invalid (see READ and EDO-PAGE-MODE READ waveforms).

EDO operates like any DRAM READ or FAST-PAGEMODE READ, except data is held valid after CAS# goes HIGH, as long as RAS# and OE# are held LOW and WE# is held HIGH. OE# can be brought LOW or HIGH while CAS# and RAS# are LOW, and the DQs will transition between valid data and High-Z. Using OE#, there are two methods to disable the outputs and keep them disabled during the CAS# HIGH time. The first method is to have OE# HIGH when CAS# transitions HIGH and keep OE# HIGH for tOEHC thereafter. This will disable the DQs, and they will remain disabled (regardless of the state of OE# after that point) until CAS# falls again. The second method is to have OE# LOW when CAS#

16 MEG x 4 EDO DRAM

transitions HIGH and then bring OE# HIGH for a minimum of tOEP anytime during the CAS# HIGH period. This will disable the DQs, and they will remain disabled (regardless of the state of OE# after that point) until CAS# falls again. (Please refer to Figure 1.) During other cycles, the outputs are disabled at tOFF time after RAS# and CAS# are HIGH or at tWHZ after WE# transitions LOW. The tOFF time is referenced from the rising edge of RAS# or CAS#, whichever occurs last. WE# can also perform the function of disabling the output drivers under certain conditions, as shown in Figure 2.

EDO-PAGE-MODE operations are always initiated with a row address strobed in by the RAS# signal, followed by a column address strobed in by CAS#, just like for single location accesses. However, subsequent column locations within the row may then be accessed at the page mode cycle time. This is accomplished by cycling CAS# while holding RAS# LOW and entering new column addresses with each CAS# cycle. Returning RAS# HIGH terminates the EDO-PAGE-MODE operation.

DRAM REFRESH

The supply voltage must be maintained at the specified levels, and the refresh requirements must be met in order to retain stored data in the DRAM. The refresh requirements are met by refreshing all 8,192 rows (G3) or all 4,096 rows (H9) in the DRAM array at least once every 64ms. The recommended procedure is to execute 4,096 CBR REFRESH cycles, either uniformly spaced or grouped in bursts, every 64ms. The MT4LC16M4G3 internally refreshes two rows for every CBR cycle, whereas the MT4LC16M4H9 refreshes one row for every CBR cycle. So with either device, executing 4,096 CBR cycles covers all rows. The CBR refresh will invoke the internal refresh counter for automatic RAS# addressing. Alternatively, RAS#-ONLY REFRESH capability is inherently provided. However, with this method, some compatibility issues may become apparent. For example, both G3 and H9 versions require 4,096 CBR REFRESH cycles, yet each requires a different number of RAS#-ONLY REFRESH cycles (G3 = 8,192 and H9 = 4,096). JEDEC strongly recommends the use of CBR REFRESH for this device.

An optional self refresh mode is also available on the “S” version. The self refresh feature is initiated by performing a CBR REFRESH cycle and holding RAS# LOW for the specified tRASS. The “S” option allows for an extended refresh period of 128ms, or 31.25µs per row for a 4K refresh and 15.625µs per row for an 8K refresh, when using a distributed CBR REFRESH. This refresh rate can be applied during normal operation, as well as during a standby or battery backup mode.

DRAM REFRESH (Continued)

The self refresh mode is terminated by driving RAS# HIGH for a minimum time of tRPS. This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS# LOW-to-HIGH transition. If the DRAM controller uses a distributed CBR refresh sequence, a burst refresh is not required upon exiting self refresh. However, if the DRAM controller uses RAS#-ONLY or burst CBR refresh, all rows

RAS#

CAS#

ADDR

IOH

IOL

OE#

ROW COLUMN (A)

OPEN

VALID DATA (A)

COLUMN (B)

VALID DATA (A)

OES

16 MEG x 4 EDO DRAM

must be refreshed with a refresh rate of tRC minimum prior to resuming normal operation.

STANDBY

Returning RAS# and CAS# HIGH terminates a memory cycle and decreases chip current to a reduced standby level. The chip is preconditioned for the next cycle during the RAS# HIGH time.

VALID DATA (B)

OEHC

COLUMN (C)

VALID DATA (C)

OEP

COLUMN (D)

VALID DATA (D)

RAS#

CAS#

ADDR

WE#

The DQs go back to

Low-Z if

OES is met.

The DQs remain High-Z until the next CAS# cycle

OEHC is met.

The DQs remain High-Z until the next CAS# cycle

OEP is met.

Figure 1

OE# Control of DQs

IOH

IOL

OE#

ROW COLUMN (A)

OPEN

COLUMN (B)

VALID DATA (A)

WHZ

WPZ

The DQs go to High-Z if WE# falls and, if tWPZ is met, will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated).

VALID DATA (B)

COLUMN (C)

INPUT DATA (C)

WHZ

WE# may be used to disable the DQs to prepare for input data in an EARLY WRITE cycle. The DQs will remain High-Z until CAS# goes LOW with WE# HIGH (i.e., until a READ cycle is initiated).

COLUMN (D)

DON’T CARE

UNDEFINED

Figure 2

WE# Control of DQs

16 MEG x 4 EDO DRAM

ABSOLUTE MAXIMUM RATINGS*

Voltage on VCC Relative to VSS ................ -1V to +4.6V

Voltage on NC, Inputs or I/O Pins

Relative to VSS ....................................... -1V to +4.6V

Operating Temperature, TA (ambient) ... 0°C to +70°C

Storage Temperature (plastic) ............ -55°C to +150°C

Power Dissipation ................................................... 1W

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Note: 1) (VCC = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES

SUPPLY VOLTAGE VCC 3 3.6 V INPUT HIGH VOLTAGE:

Valid Logic 1; All inputs, I/Os and any NC VIH 2VCC + 0.3 V 26 INPUT LOW VOLTAGE:

Valid Logic 0; All inputs, I/Os and any NC VIL -0.3 0.8 V 26 INPUT LEAKAGE CURRENT:

Any input at VIN (0V ≤ VIN ≤ VCC + 0.3V); II -2 2 µA 27 All other pins not under test = 0V

OUTPUT HIGH VOLTAGE: IOUT = -2mA VOH 2.4–V

OUTPUT LOW VOLTAGE: IOUT = 2mA VOL – 0.4 V

OUTPUT LEAKAGE CURRENT: Any output at VOUT (0V ≤ VOUT ≤ VCC + 0.3V); IOZ -5 5 µA DQ is disabled and in High-Z state

16 MEG x 4 EDO DRAM

ICC OPERATING CONDITIONS AND MAXIMUM LIMITS

(Notes: 1, 2, 3, 5, 6) (VCC = +3.3V ±0.3V)

4K 8K

PARAMETER/CONDITION SYMBOL SPEED REFRESH REFRESH UNITS NOTES

STANDBY CURRENT: TTL I (RAS# = CAS# = VIH)

STANDBY CURRENT: CMOS (RAS# = CAS#  VCC - 0.2V; DQs may be left open; I Other inputs: VIN  VCC - 0.2V or VIN ≤ 0.2V)

OPERATING CURRENT: Random READ/WRITE I Average power supply current -6 160 120 (RAS#, CAS#, address cycling: tRC = tRC [MIN])

OPERATING CURRENT: EDO PAGE MODE I Average power supply current -6 120 120 (RAS# = VIL, CAS#, address cycling: tPC = tPC [MIN])

REFRESH CURRENT: RAS#-ONLY I Average power supply current -6 160 120 (RAS# cycling, CAS# = VIH: tRC = tRC [MIN])

REFRESH CURRENT: CBR I Average power supply current -6 150 150 (RAS#, CAS#, address cycling: tRC = tRC [MIN])

REFRESH CURRENT: Extended (“S” version only) Average power supply current: CAS# = 0.2V or CBR cycling; I RAS# = tRAS (MIN); WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open)

REFRESH CURRENT: Self (“S” version only) Average power supply current: CBR with RAS#  tRASS (MIN) and CAS# held LOW; I WE# = VCC - 0.2V; A0-A11, OE# and DIN = VCC - 0.2V or 0.2V (DIN may be left open)

ALL 1 1 mA

ALL 500 500 µA

-5 170 130 mA 25

-5 150 150 mA 25

-5 170 130 mA 22

-5 160 160 mA 4, 7

ALL 400 400 µA 4, 7

16 MEG x 4 EDO DRAM

CAPACITANCE

(Note: 2)

PARAMETER SYMBOL MAX UNITS

Input Capacitance: Address pins CI1 5pF Input Capacitance: RAS#, CAS#, WE#, OE# CI2 7pF Input/Output Capacitance: DQ CIO 7pF

AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V)

AC CHARACTERISTICS -5 -6 PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES

Access time from column address Column-address setup to CAS# precharge Column-address hold time (referenced to RAS#) Column-address setup time Row-address setup time Column address to WE# delay time Access time from CAS# Column-address hold time CAS# pulse width CAS# LOW to “Don’t Care” during Self Refresh CAS# hold time (CBR Refresh) CAS# to output in Low-Z Data output hold after CAS# LOW CAS# precharge time Access time from CAS# precharge CAS# to RAS# precharge time CAS# hold time CAS# setup time (CBR Refresh) CAS# to WE# delay time WRITE command to CAS# lead time Data-in hold time Data-in setup time Output disable Output enable time OE# hold time from WE# during

READ-MODIFY-WRITE cycle OE# HIGH hold time from CAS# HIGH

OE# HIGH pulse width OE# LOW to CAS# HIGH setup time Output buffer turn-off delay

AA 25 30 ns

ACH 12 15 ns

AR 38 45 ns

ASC 0 0 ns

ASR 0 0 ns

AWD 42 49 ns 18

CAC 13 15 ns

CAH 8 10 ns

CAS 8 10,000 10 10,000 ns

CHD 15 15 ns

CHR 8 10 ns 4

CLZ 0 0 ns

COH 3 3 ns

CP 8 10 ns 13

CPA 28 35 ns

CRP 5 5 ns

CSH 38 45 ns

CSR 5 5 ns 4

CWD 28 35 ns 18

CWL 8 10 ns

DH 8 10 ns 19

DS 0 0 ns 19

OD 0 12 0 15 ns 23, 24

OE 12 15 ns 20

OEH 8 10 ns 24

OEHC 5 10 ns

OEP 5 5 ns

OES 4 5 ns

OFF 0 12 0 15 ns 17, 23

+ 15 hidden pages

MICRON MT4LC16M4H9TG-6S, MT4LC16M4H9DJ-6S, MT4LC16M4H9TG-5, MT4LC16M4H9TG-5S, MT4LC16M4H9DJ-5 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

OPTIONS MARKING

16 MEG x 4 EDO DRAM PART NUMBERS

KEY TIMING PARAMETERS

GENERAL DESCRIPTION

MT4LC16M4G3 (13 row addresses)

MT4LC16M4H9 (12 row addresses)

DRAM ACCESS

EDO PAGE MODE

DRAM REFRESH

STANDBY

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

ICC OPERATING CONDITIONS AND MAXIMUM LIMITS

CAPACITANCE

AC ELECTRICAL CHARACTERISTICS