MICRON MT4LC16M4A7TG-6, MT4LC16M4A7TG-6S, MT4LC16M4A7TG-5, MT4LC16M4A7DJ-6S, MT4LC16M4A7DJ-5 Datasheet
...
16 MEG x 4
VCC
DQ0
DQ1
NC
NC
NC
NC
WE#
RAS#
A0
A1
A2
A3
A4
A5
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VSS
DQ3
DQ2
NC
NC
NC
CAS#
OE#
A12/NC**
A11
A10
A9
A8
A7
A6
V
SS
FPM DRAM
DRAM
FEATURES
• Single +3.3V ±0.3V power supply
• Industry-standard x4 pinout, timing, functions,
and packages
• 13 row, 11 column addresses (A7)
12 row, 12 column addresses (T8)
• High-performance CMOS silicon-gate process
• All inputs, outputs and clocks are LVTTL-compatible
• FAST-PAGE-MODE (FPM) access
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
• Optional self refresh (S) for low-power data
retention
OPTIONS MARKING
• Refresh Addressing
4,096 (4K) rows T8
8,192 (8K) rows A7
• Plastic Packages
32-pin SOJ (400 mil) DJ
32-pin TSOP (400 mil) TG
MT4LC16M4A7, MT4LC16M4T8
For the latest data sheet, please refer to the Micron Web
site: www.micronsemi.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT (Top View)
32-Pin TSOP32-Pin SOJ
V
V
CC
1
DQ0
2
DQ1
3
NC
4
NC
5
NC
6
NC
7
WE#
8
RAS#
9
A0
10
A1
11
A2
12
A3
13
A4
14
A5
15
CC
V
16
**A12 on A7 version and NC on T8 version
16 MEG x 4 FPM DRAM PART NUMBERS
32
SS
DQ3
31
DQ2
30
NC
29
NC
28
NC
27
CAS#
26
OE#
25
A12/NC**
24
A11
23
A10
22
A9
21
A8
20
A7
19
A6
18
SS
V
17
• Timing
50ns access -5
60ns access -6
• Refresh Rates
Standard Refresh None
Self Refresh (128ms period) S*
PART NUMBER ADDRESSING PACKAGE REFRESH
MT4LC16M4A7DJ-x 8K SOJ Standard
MT4LC16M4A7DJ-x S 8K SOJ Self
MT4LC16M4A7TG-x 8K TSOP Standard
MT4LC16M4A7TG-x S 8K TSOP Self
REFRESH
MT4LC16M4T8DJ-x 4K SOJ Standard
NOTE: 1. The 16 Meg x 4 FPM DRAM base number
differentiates the offerings in one place—
MT4LC16M4A7. The fifth field distinguishes
various options: A7 designates an 8K refresh and
T8 designates a 4K refresh for FPM DRAMs.
2. The # symbol indicates signal is active LOW.
*Contact factory for availability
Part Number Example:
MT4LC16M4A7DJ
KEY TIMING PARAMETERS
SPEED
16 Meg x 4 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D21_2.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.
t
RC
-5 90ns 50ns 30ns 25ns 13ns
-6 110ns 60ns 35ns 30ns 15ns
t
RAC
t
PC
t
AA
t
CAC
MT4LC16M4T8DJ-x S 4K SOJ Self
MT4LC16M4T8TG-x 4K TSOP Standard
MT4LC16M4T8TG-x S 4K TSOP Self
x = speed
GENERAL DESCRIPTION
The 16 Meg x 4 DRAMs are high-speed CMOS,
dynamic random-access memory devices contain-ing
67,108,864 bits organized in a x4 configuration. The
MT4LC16M4A7 and MT4LC16M4T8 are functionally
organized as 16,777,216 locations containing four bits
each. The 16,777,216 memory locations are arranged in
8,192 rows by 2,048 columns for the MT4LC16M4A7 or
4,096 rows by 4,096 columns for the MT4LC16M4T8.
During READ or WRITE cycles, each location is uniquely
1
FUNCTIONAL BLOCK DIAGRAM
MT4LC16M4A7 (13 row addresses)
16 MEG x 4
FPM DRAM
WE#
CAS#
A10
A11
A12
RAS#
DATA-IN
BUFFER
CONTROL
NO. 2 CLOCK
LOGIC
GENERATOR
COLUMNA0
A1
A2
A3
A4
A5
A6
A7
A8
A9
11
13
ADDRESS
BUFFER(11)
REFRESH
CONTROLLER
REFRESH
COUNTER
13
ROW-
ADDRESS
BUFFERS (13)
NO. 1 CLOCK
GENERATOR
13
ROW
DECODER
11
8,192
8,192
SELECT
COMPLEMENT
DATA-OUT
BUFFER
COLUMN
DECODER
2,048
SENSE AMPLIFIERS
I/O GATING
2,048
8,192 x 2,048 x 4
ROW SELECT
MEMORY
ARRAY
4
4
DQ0
DQ1
DQ2
DQ3
4
OE#
4
DD
V
V
SS
FUNCTIONAL BLOCK DIAGRAM
MT4LC16M4T8 (12 row addresses)
WE#
CAS#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
RAS#
12
12
NO. 2 CLOCK
GENERATOR
COLUMN-
ADDRESS
BUFFER(12)
REFRESH
CONTROLLER
REFRESH
COUNTER
12
ROW-
ADDRESS
BUFFERS (12)
NO. 1 CLOCK
GENERATOR
4
DQ0
DQ1
DQ2
4
DQ3
4
CONTROL
LOGIC
DATA-IN
BUFFER
DATA-OUT
BUFFER
OE#
12
COLUMN
DECODER
4,096
SENSE AMPLIFIERS
I/O GATING
4
4,096
4,096 x 4,096 x 4
MEMORY
ARRAY
12
ROW
DECODER
4,096
SELECT
4,096
ROW SELECT
COMPLEMENT
V
DD
V
SS
16 Meg x 4 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D21_2.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.
2
GENERAL DESCRIPTION (continued)
addressed via the address bits. First, the row address is
latched by the RAS# signal, then the column address by
CAS#. Both devices provide FAST-PAGE-MODE operation, allowing for fast successive data operations (READ,
WRITE, or READ-MODIFY-WRITE) within a given row.
The MT4LC16M4A7 and MT4LC16M4T8 must be
refreshed periodically in order to retain stored data.
FAST PAGE MODE ACCESS
Each location in the DRAM is uniquely addressable
as mentioned in the General Description. The data for
each location is accessed via the four I/O pins (DQ0DQ3). The WE# signal must be activated to execute a
WRITE operation; otherwise, a READ operation will be
performed. The OE# signal must be activated to enable
the DQ output drivers for a read access and can be
deactivated to disable output data if necessary.
FAST-PAGE-MODE operations are always initiated
with a row address strobed in by the RAS# signal,
followed by a column address strobed in by CAS#, just
like for single location accesses. However, subsequent
column locations within the row may then be accessed
at the page mode cycle time. This is accomplished by
cycling CAS# while holding RAS# LOW and entering
new column addresses with each CAS# cycle. Returning
RAS# HIGH terminates the FAST-PAGE-MODE operation.
DRAM REFRESH
The supply voltage must be maintained at the specified levels, and the refresh requirements must be met in
order to retain stored data in the DRAM. The refresh
requirements are met by refreshing all 8,192 rows (A7)
or all 4,096 rows (T8) in the DRAM array at least once
every 64ms. The recommended procedure is to execute
4,096 CBR REFRESH cycles, either uniformly spaced or
grouped in bursts, every 64ms. The MT4LC16M4A7
internally refreshes two rows for every CBR cycle,
16 MEG x 4
FPM DRAM
whereas the MT4LC16M4T8 refreshes one row for every
CBR cycle. So with either device, executing 4,096 CBR
cycles covers all rows. The CBR refresh will invoke the
internal refresh counter for automatic RAS# addressing. Alternatively, RAS#-ONLY REFRESH capability is
inherently provided. However, with this method only
one row is refreshed at a time; so for the MT4LC16M4A7,
8,192 RAS#-ONLY REFRESH cycles must be executed
every 64ms to cover all rows. Some compatibility issues
may become apparent. JEDEC strongly recommends
the use of CBR REFRESH for this device.
An optional self refresh mode is also available on the
“S” version. The self refresh feature is initiated by
performing a CBR REFRESH cycle and holding RAS#
LOW for the specified tRASS. The “S” option allows for
an extended refresh period of 128ms, or 31.25µs per
row for a 4K refresh and 15.625µs per row for an 8K
refresh, when using a distributed CBR REFRESH. This
refresh rate can be applied during normal operation, as
well as during a standby or battery backup mode.
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of tRPS. This delay allows for
the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH
transition. If the DRAM controller uses a distributed
CBR refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM controller utilizes RAS#-ONLY or burst CBR refresh sequence, all rows must be refreshed within the average
internal refresh rate prior to the resumption of normal
operation.
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. The chip is preconditioned for the next
cycle during the RAS# HIGH time.
16 Meg x 4 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D21_2.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.
3
16 MEG x 4
FPM DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Relative to VSS ................ -1V to +4.6V
Voltage on NC, Inputs or I/O Pins
Relative to VSS ..................................... -1V to +4.6V
Operating Temperature, TA (ambient) ... 0°C to +70°C
Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ................................................... 1W
*Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 5, 6) (VCC = +3.3V ±0.3V)
PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES
SUPPLY VOLTAGE VCC 3 3.6 V
INPUT HIGH VOLTAGE:
Valid Logic 1; All inputs, I/Os and any NC VIH 2VCC + 0.3 V 26
INPUT LOW VOLTAGE:
Valid Logic 0; All inputs, I/Os and any NC VIL -0.3 0.8 V 26
INPUT LEAKAGE CURRENT:
Any input at VIN (0V ≤ VIN ≤ VCC + 0.3V); II -2 2 µA
All other pins not under test = 0V
OUTPUT HIGH VOLTAGE:
IOUT = -2mA VOH 2.4–V
OUTPUT LOW VOLTAGE:
IOUT = 2mA VOL – 0.4 V
OUTPUT LEAKAGE CURRENT:
Any output at VOUT (0V ≤ VOUT ≤ VCC + 0.3V); IOZ -5 5 µ A
DQ is disabled and in High-Z state
16 Meg x 4 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D21_2.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.
4
16 MEG x 4
FPM DRAM
ICC OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3, 5, 6) (VCC = +3.3V ±0.3V)
4K 8K
PARAMETER/CONDITION SYMBOL SPEED REFRESH REFRESH UNITS NOTES
STANDBY CURRENT: TTL ICC1 ALL 1 1 mA
(RAS# = CAS# = VIH)
STANDBY CURRENT: CMOS
(RAS# = CAS# VCC - 0.2V, DQs may be left open, ICC2 ALL 500 500 µA
other inputs: VIN VCC - 0.2V or VIN ≤ 0.2V)
OPERATING CURRENT: Random READ/WRITE ICC3 -5 170 130 mA 25
Average power supply current -6 160 120
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
OPERATING CURRENT: FAST PAGE MODE ICC4 -5 100 100 mA 25
Average power supply current (RAS# = VIL,-69090
CAS#, address cycling: tPC = tPC [MIN])
REFRESH CURRENT: RAS#-ONLY ICC5 -5 170 130 mA 22
Average power supply current -6 160 120
(RAS# cycling, CAS# = VIH: tRC = tRC [MIN])
REFRESH CURRENT: CBR ICC6 -5 170 130 mA 4, 7
Average power supply current -6 160 120
(RAS#, CAS#, address cycling: tRC = tRC [MIN])
REFRESH CURRENT: Extended (“S” version only)
Average power supply current: CAS# = 0.2V or
CBR cycling; RAS# = tRAS (MIN); WE# = VCC - 0.2V; ICC7 ALL 400 400 µA 4, 7
A0-A11, OE# and DIN = VCC - 0.2V or 0.2V
(DIN may be left open)
REFRESH CURRENT: Self (“S” version only)
Average power supply current: CBR with ICC8 ALL 400 400 µA 4, 7
RAS# tRASS (MIN) and CAS# held LOW;
WE# = VCC - 0.2V; A0-A11, OE# and DIN =
VCC - 0.2V or 0.2V (DIN may be left open)
16 Meg x 4 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D21_2.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.
5
16 MEG x 4
FPM DRAM
CAPACITANCE
(Note: 2)
PARAMETER SYMBOL M AX UNITS
Input Capacitance: Address pins CI1 5pF
Input Capacitance: RAS#, CAS#, WE#, OE# CI2 7pF
Input/Output Capacitance: DQ CIO 7pF
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (VCC = +3.3V ±0.3V)
AC CHARACTERISTICS -5 -6
PARAMETER SYMBOL MIN MAX MIN MAX UNITS NOTES
Access time from column address
Column-address hold time (referenced to RAS#)
Column-address setup time
Row-address setup time
Column address to WE# delay time
Access time from CAS#
Column-address hold time
CAS# pulse width
CAS# LOW to “Don’t Care” during Self Refresh
CAS# hold time (CBR Refresh)
CAS# to output in Low-Z
CAS# precharge time (FAST PAGE MODE)
Access time from CAS# precharge
CAS# to RAS# precharge time
CAS# hold time
CAS# setup time (CBR Refresh)
CAS# to WE# delay time
WRITE command to CAS# lead time
Data-in hold time
Data-in setup time
Output disable
Output enable time
OE# hold time from WE# during
READ-MODIFY-WRITE cycle
Output buffer turn-off delay
OE# setup prior to RAS# during
HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
FAST-PAGE-MODE READ-WRITE cycle time
Access time from RAS#
RAS# to column-address delay time
t
AA 25 30 ns
t
AR 40 45 ns
t
ASC 0 0 ns
t
ASR 0 0 ns
t
AWD 48 55 ns 18
t
CAC 13 15 ns
t
CAH 8 10 ns
t
CAS 13 10,000 15 10,000 ns
t
CHD 15 15 ns
t
CHR 15 15 ns 4
t
CLZ 3 3 ns
t
CP 8 10 ns 13
t
CPA 30 35 ns
t
CRP 5 5 ns
t
CSH 50 60 ns
t
CSR 5 5 ns 4
t
CWD 36 40 ns 18
t
CWL 13 15 ns
t
DH 8 10 ns 19
t
DS 0 0 ns 19
t
OD 3 13 3 15 ns 23, 24
t
OE 13 15 ns 20
t
OEH 13 15 ns 24
t
OFF 3 13 3 15 ns 17, 23
t
ORD 0 0 ns
t
PC 30 35 ns
t
PRWC 76 85 ns
t
RAC 50 60 ns
t
RAD 13 15 ns 15
16 Meg x 4 FPM DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
D21_2.p65 – Rev. 5/00 ©2000, Micron Technology, Inc.
6
Loading...