MICRON MT48LC2M32B2TG-6, MT48LC2M32B2TG-7, MT48LC2M32B2TG-5, MT48LC2M32B2TG-55 Datasheet

64Mb: x32

SDRAM

2 Meg x 32

Configuration 512K x 32 x 4 banks Refresh Count 4K Row Addressing 2K (A0-A10) Bank Addressing 4 (BA0, BA1) Column Addressing 256 (A0-A7)

PIN ASSIGNMENT (TOP VIEW)

86-PIN TSOP

FEATURES

• PC100 functionality

• Fully synchronous; all signals registered on positive edge of system clock

• Internal pipelined operation; column address can be changed every clock cycle

• Internal banks for hiding row access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes

• Self Refresh Mode

• 64ms, 4,096-cycle refresh (15.6µs/row)

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

• Supports CAS latency of 1, 2, and 3

OPTIONS MARKING

• Configuration 2 Meg x 32 (512K x 32 x 4 banks) 2M32B2

• Plastic Package - OCPL

86-pin TSOP (400 mil) TG

• Timing (Cycle Time)

5ns (200 MHz) -5

5.5ns (183 MHz) -55 6ns (166 MHz) -6 7ns (143 MHz) -7

• Operating Temperature Range Commercial (0° to +70°C) None Extended (-40°C to +85°C) IT

NOTE: 1. Off-center parting line

2. Available on -7

Part Number Example:

MT48LC2M32B2TG-7

Note: The # symbol indicates signal is active LOW.

DQ0

DQ1 DQ2

DQ3 DQ4

DQ5 DQ6

DQ7

DQM0

WE#

CAS# RAS#

CS#

NC BA0 BA1

A10

DQM2

DQ16

DQ17 DQ18

DQ19 DQ20

DQ21 DQ22

DQ23

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

DQ15

DQ14 DQ13

DQ12 DQ11

DQ10 DQ9

DQ8

DQM1

CLK CKE

A9 A8 A7 A6 A5 A4 A3

DQM3 V

DQ31

DQ30 DQ29

DQ28 DQ27

DQ26 DQ25

DQ24

SYNCHRONOUS DRAM

MT48LC2M32B2 - 512K x 32 x 4 banks

For the latest data sheet, please refer to the Micron Web site: www.micron.com/sdramds

KEY TIMING PARAMETERS

SPEED CLOCK ACCESS TIME SETUP HOLD

GRADE FREQUENCY CL = 3* TIME TIME

-5 200 MHz 4.5ns 1.5ns 1ns

-55 183 MHz 5ns 1.5ns 1ns

-6 166 MHz 5.5ns 1.5ns 1ns

-7 143 MHz 5.5ns 2ns 1ns

*CL = CAS (READ) latency

64Mb: x32

SDRAM

The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence.

The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing one of the other three banks will hide the precharge cycles and provide seamless, high-speed, random-access operation.

The 64Mb SDRAM is designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access.

GENERAL DESCRIPTION

The 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 67,108,864-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank, A0-A10 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

64Mb (x32) SDRAM PART NUMBER

PART NUMBER ARCHITECTURE

MT48LC2M32B2TG 2 Meg x 32

64Mb: x32

SDRAM

TABLE OF CONTENTS

Functional Block Diagram - 2 Meg x 32 ................. 4

Pin Descriptions ..................................................... 5

Functional Description ......................................... 6

Initialization ...................................................... 6

Mode Register ............................................... 6

Burst Length ............................................ 6

Burst Type ............................................... 7

CAS Latency ............................................ 8

Operating Mode ...................................... 8

Write Burst Mode .................................... 8

Commands ............................................................ 9

Truth Table 1 (Commands and DQM Operation) ............ 9

Command Inhibit ............................................. 10

No Operation (NOP) .......................................... 10

Load Mode Register ........................................... 10

Active ................................................................ 10

Read ................................................................ 10

Write ................................................................ 10

Precharge ........................................................... 10

Auto Precharge .................................................. 10

Burst Terminate ................................................. 11

Auto Refresh ...................................................... 11

Self Refresh ........................................................ 11

Operation ............................................................... 12

Bank/Row Activation ........................................ 12

Reads ................................................................ 13

Writes ................................................................ 19

Precharge ........................................................... 21

Power-Down ...................................................... 21

Clock Suspend .................................................. 22

Burst Read/Single Write .................................... 22

Concurrent Auto Precharge .............................. 23

Write with Auto Precharge ............................... 24

Truth Table 2 (CKE) ................................................ 25

Truth Table 3 (Current State, Same Bank) ..................... 26

Truth Table 4 (Current State, Different Bank) ................. 28

Absolute Maximum Ratings .................................. 30

DC Electrical Characteristics

and Operating Conditions ...................................... 30

DD Specifications and Conditions ......................... 30

Capacitance ............................................................ 32

AC Electrical Characteristics (Timing Table) .... 32

AC Electrical Characteristics ................................... 34

Timing Waveforms

Initialize and Load Mode Register .................... 36

Power-Down Mode .......................................... 37

Clock Suspend Mode ........................................ 38

Auto Refresh Mode ........................................... 39

Self Refresh Mode ............................................. 40

Reads

Read – Single Read ....................................... 41

Read – Without Auto Precharge ................. 42

Read – With Auto Precharge ....................... 43

Alternating Bank Read Accesses .................. 44

Read – Full-Page Burst ................................. 45

Read – DQM Operation .............................. 46

Writes

Write – Single Write ..................................... 47

Write – Without Auto Precharge ................ 48

Write – With Auto Precharge ...................... 49

Alternating Bank Write Accesses ................. 50

Write – Full-Page Burst ................................ 51

Write – DQM Operation ............................. 52

64Mb: x32

SDRAM

FUNCTIONAL BLOCK DIAGRAM

2 Meg x 32 SDRAM

RAS#

CAS#

CLK

CS#

WE#

CKE

A0-A10,

BA0, BA1

DQM0DQM3

256

(x32)

8192

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(2,048 x 256 x 32)

BANK0

ROW-

ADDRESS

LATCH

DECODER

2048

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0- DQ31

DATA INPUT

DATA

OUTPUT

BANK1

BANK0

BANK2

BANK3

4 4

REFRESH

COUNTER

MODE REGISTER

CONTROL

LOGIC

COMMAND

DECODE

ROW-

ADDRESS

MUX

ADDRESS REGISTER

COLUMNADDRESS

COUNTER/

LATCH

64Mb: x32

SDRAM

PIN DESCRIPTIONS

PIN NUMBERS SYMBOL TYPE DESCRIPTION

68 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are

sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers.

67 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.

Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH.

20 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code.

17, 18, 19 WE#, CAS#, Input Command Inputs: WE# , CAS#, and RAS# (along with CS#) define the

RAS# command being entered.

16, 71, 28, 59 DQM0- Input Input/Output Mask: DQM is sampled HIGH and is an input mask signal

DQM3 for write accesses and an output enable signal for read accesses. Input data

is masked during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) during a READ cycle. DQM0 corresponds to DQ0DQ7; DQM1 corresponds to DQ8-DQ15; DQM2 corresponds to DQ16-DQ23; and DQM3 corresponds to DQ24-DQ31. DQM0-DQM3 are considered same state when referenced as DQM.

22, 23 BA0, BA1 Input Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,

WRITE or PRECHARGE command is being applied.

25-27, 60-66, 24 A0-A10 Input Address Inputs: A0-A10 are sampled during the ACTIVE command (row-

address A0-A10) and READ/WRITE command (column-address A0-A7 with A10 defining auto precharge) to select one location out of the memory array in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also provide the op-code during a LOAD MODE REGISTER command.

2, 4, 5, 7, 8, 10, 11, 13, DQ0-DQ31 Input/ Data I/Os: Data bus. 74, 76, 77, 79, 80, 82, 83, Output 85, 31, 33, 34, 36, 37, 39, 40, 42, 45, 47, 48, 50, 51,

53, 54, 56

14, 21, 30, 57, 69, 70, 73 NC – No Connect: These pins should be left unconnected. Pin 70 is reserved

for SSTL reference voltage supply.

3, 9, 35, 41, 49, 55, 75, 81 VDDQ Supply DQ Power Supply: Isolated on the die for improved noise immunity.

6, 12, 32, 38, 46, 52, 78, 84 VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise immunity.

1, 15, 29, 43 V

Supply Power Supply: +3.3V ±0.3V. (See note 27 on page 35.)

44, 58, 72, 86 V

Supply Ground.

64Mb: x32

SDRAM

FUNCTIONAL DESCRIPTION

In general, this 64Mb SDRAM (512K x 32 x 4 banks) is a quad-bank DRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32-bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0-A10 select the row). The address bits (A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or a NOP. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied.

Once the 100µs delay has been satisfied with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for Mode Register programming. Because the Mode Register will power up in an unknown state, it should be loaded prior to applying any operational command.

MODE REGISTER

The Mode Register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 1. The Mode Register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power.

Mode Register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 is reserved for future use.

The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.

Burst Length

Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types, and a fullpage burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when the burst length is set to two; by A2-A7 when the burst length is set to four; and by A3-A7 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached.

64Mb: x32

SDRAM

NOTE: 1. For a burst length of two, A1-A7 select the block-

of-two burst; A0 selects the starting column within the block.

2. For a burst length of four, A2-A7 select the blockof-four burst; A0-A1 select the starting column within the block.

3. For a burst length of eight, A3-A7 select the blockof-eight burst; A0-A2 select the starting column within the block.

4. For a full-page burst, the full row is selected and A0-A7 select the starting column.

5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

6. For a burst length of one, A0-A7 select the unique column to be accessed, and mode register bit M3 is ignored.

Table 1

Burst Definition

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

00-1 0-1 11-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full n = A0-A7

Cn, Cn + 1, Cn + 2

Page

Cn + 3, Cn + 4...

Not Supported

(256) (Location 0 -256)

…Cn - 1,

Cn…

Figure 1

Mode Register Definition

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.

000

001

010

011

100

101

110

111

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard operation

All other states reserved

0-0-Defined

Burst Type

Sequential

Interleave

CAS Latency

Reserved

000

001

010

011

100

101

110

111

Burst Length

Burst lengthCAS Latency B T

A6 A5 A4

A3A8A2A1A0

Mode Register (Mx)

Address Bus

654

382

M1M2

M4M5M6

M6 - M0

Op Mode

A10

Reserved* WB

Write Burst Mode

Programmed Burst Length

Single Location Access

1. *Should program

A10, BA0, and BA1= “0” to ensure compatibility with future device

64Mb: x32

SDRAM

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS CAS CAS

SPEED LATENCY = 1 LATENCY = 2 LATENCY = 3

- 5 - - ≤ 200

-55 - - ≤ 183

- 6 ≤ 50 ≤ 100 ≤ 166

- 7 ≤ 50 ≤ 100 ≤ 143

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.

CAS Latency

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used.

Figure 2

CAS Latency

Table 2

CAS Latency

CLK

T2T1 T3T0

CAS Latency = 3

OUT

COMMAND

NOPREAD

NOP

DON’T CARE

UNDEFINED

CLK

T2T1T0

CAS Latency = 1

OUT

COMMAND

NOPREAD

CLK

T2T1 T3T0

CAS Latency = 2

OUT

COMMAND

NOPREAD

NOP

64Mb: x32

SDRAM

TRUTH TABLE 1 – COMMANDS AND DQM OPERATION

(Note: 1)

NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQs NOTES

COMMAND INHIBIT (NOP) H XXXX X X

NO OPERATION (NOP) L H H H X X X

ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3

READ (Select bank and column, and start READ burst) L H L H L/H8Bank/Col X 4

WRITE (Select bank and column, and start WRITE burst) L H L L L/H8Bank/Col Valid 4

BURST TERMINATE L H H L X X Active

PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5

AUTO REFRESH or SELF REFRESH L L L H X X X 6, 7 (Enter self refresh mode)

LOAD MODE REGISTER L L L L X Op-Code X 2

Write Enable/Output Enable ––––L – Active 8

Write Inhibit/Output High-Z ––––H – High-Z 8

appear following the Operation section; these tables provide current state/next state information.

Commands

Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-A10 define the op-code written to the Mode Register.

3. A0-A10 provide row address, BA0 and BA1 determine which bank is made active.

4. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0 and BA1 determine which bank is being read from or written to.

5. A10 LOW: BA0 and BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0 and BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0 controls DQ0-DQ7; DQM1 controls DQ8-DQ15; DQM2 controls DQ16-DQ23; and DQM3 controls DQ24-DQ31.

64Mb: x32

SDRAM

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

LOAD MODE REGISTER

The mode register is loaded via inputs A0-A10. See mode register heading in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A0-A10 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.

READ

The READ command is used to initiate a burst read access to an active row. The value on the BA0 and BA1 (B1) inputs selects the bank, and the address provided on inputs A0-A7 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs subject to the logic level on the DQM inputs two clocks earlier. If a given DQMx signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQMx signal was registered LOW, the corresponding DQs will provide valid data. DQM0 corresponds to DQ0-DQ7, DQM1 corresponds to DQ8-DQ15, DQM2 corresponds to DQ16DQ23 and DQM3 corresponds to DQ24-DQ31.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value on the BA0 and BA1 inputs selects the bank, and the address provided on inputs A0-A7 selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0 and BA1 select the bank. Otherwise BA0 and BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.

AUTO PRECHARGE

Auto precharge is a feature which performs the same individual-bank PRECHARGE function described above, without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A PRECHARGE of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where auto precharge does not apply. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command.

Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet.

64Mb: x32

SDRAM

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the SDRAM and is analagous to CAS#-BEFORE-RAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required.

The addressing is generated by the internal refresh controller. This makes the address bits “Don’t Care” during an AUTO REFRESH command. The 64Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (tREF), regardless of width option. Providing a distributed AUTO REFRESH command every 15.625µs will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4,096 AUTO REFRESH commands can be issued in a burst at the minimum cycle rate (tRC), once every 64ms.

SELF REFRESH

The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care” with the exception of CKE, which must remain LOW.

Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own AUTO REFRESH cycles. The SDRAM must remain in self refresh mode for a minimum period equal to

RAS and may remain in self refresh mode for an indefi-

nite period beyond that.

The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for

XSR because time is required for the completion of any

internal refresh in progress.

Upon exiting SELF REFRESH mode, AUTO REFRESH commands must be issued every 15.625ms or less as both SELF REFRESH and AUTO REFRESH utililze the row refresh counter.

64Mb: x32

SDRAM

Operation

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. See Figure 3.

After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be issued. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks, rounded to 3. This is reflected in Figure 4, which covers any case where 2 < tRCD (MIN)/tCK - 3. (The same procedure is used to convert other specification limits from time units to clock cycles.)

A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by

RRD.

Figure 4

Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK - 3

CLK

T2T1 T3T0

COMMAND

NOPACTIVE

READ or

WRITE

NOP

RCD (MIN)

RCD (MIN) = 20ns, tCK = 8ns

RCD (MIN) x tCK

where x = number of clocks for equation to be true.

RCD (MIN) +0.5 tCK

DON’T CARE

Figure 3

Activating a Specific Row in a

Specific Bank

CS#

WE#

CAS#

RAS#

CKE

CLK

A0–A10

ROW

ADDRESS

HIGH

BA0, BA1

BANK

ADDRESS

64Mb: x32

SDRAM

Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.)

Data from any READ burst may be truncated with a subsequent READ command, and data from a fixedlength READ burst may be immediately followed by data from a READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 7 for CAS latencies of one, two and

READs

READ bursts are initiated with a READ command,

as shown in Figure 5.

The starting column and bank addresses are provided with the READ command, and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 6 shows general timing for each possible CAS latency setting.

Figure 5

READ Command

Figure 6

CAS Latency

CLK

T2T1 T3T0

CAS Latency = 3

OUT

COMMAND

NOPREAD

NOP

DON’T CARE

UNDEFINED

CLK

T2T1T0

CAS Latency = 1

OUT

COMMAND

NOPREAD

CLK

T2T1 T3T0

CAS Latency = 2

OUT

COMMAND

NOPREAD

NOP

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN ADDRESS

A0–A7

A10

BA0, 1

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

A8, A9

64Mb: x32

SDRAM

three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. This 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any

Figure 7

Consecutive READ Bursts

clock cycle following a previous READ command. Fullspeed random read accesses can be performed to the same bank, as shown in Figure 8, or each subsequent READ may be performed to a different bank.

CLK

OUT

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK, COL n

NOP

BANK,

COL b

OUT

n + 1

OUT

n + 2

OUT

n + 3

OUT

READ

X = 0 cycles

NOTE: Each READ command may be to either bank. DQM is LOW.

CAS Latency = 1

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK, COL n

NOP

BANK,

COL b

OUT

n + 1

OUT

n + 2

OUT

n + 3

OUT

READ

X = 1 cycle

CAS Latency = 2

CLK

OUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK, COL n

NOP

BANK,

COL b

OUT

n + 1

OUT

n + 2

OUT

n + 3

OUT

READ

NOP

X = 2 cycles

CAS Latency = 3

DON’T CARE

64Mb: x32

SDRAM

Figure 8

Random READ Accesses

CLK

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP

BANK, COL n

DON’T CARE

OUT

READ

NOTE: Each READ command may be to either bank. DQM is LOW.

READ READ NOP

BANK, COL a

BANK,

COL x

BANK,

COL m

CLK

OUT

T2T1 T4T3 T5T0

COMMAND

ADDRESS

READ NOP

BANK, COL n

OUT

READ READ READ NOP

BANK, COL a

BANK,

COL x

BANK, COL m

CLK

OUT

T2T1 T4T3T0

COMMAND

ADDRESS

READ NOP

BANK, COL n

OUT

READ READ READ

BANK, COL a

BANK,

COL x

BANK, COL m

CAS Latency = 1

CAS Latency = 2

CAS Latency = 3

64Mb: x32

SDRAM

Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixedlength READ burst may be immediately followed by data from a WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command.

DON’T CARE

READ NOP NOPNOP NOP

DQM

CLK

OUT

T2T1 T4T3T0

COMMAND

ADDRESS

BANK, COL n

WRITE

DIN b

BANK,

COL b

NOTE: A CAS latency of three is used for illustration. The

READ command

may be to any bank, and the WRITE command may be to any bank.

Figure 10

READ to WRITE with

Extra Clock Cycle

Figure 9

READ to WRITE

DON’T CARE

READ NOP NOP

WRITE

NOP

CLK

T2T1 T4T3T0

DQM

DOUT n

COMMAND

DIN b

ADDRESS

BANK, COL n

BANK, COL b

NOTE: A CAS latency of three is used for illustration. The

READ

command ma

be to any bank, and the WRITE command

The DQM input is used to avoid I/O contention, as shown in Figures 9 and 10. The DQM signal must be asserted (HIGH) at least two clocks prior to the WRITE command (DQM latency is two clocks for output buffers) to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z), regardless of the state of the DQM signal; provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was low during T4 in Figure 10, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.

The DQM signal must be de-asserted prior to the WRITE command (DQM latency is zero clocks for input buffers) to ensure that the written data is not masked. Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 10 shows the case where the additional NOP is needed.

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