Micron MT48LC1M16A1 User Manual

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16Mb: x16

IT SDRAM

SYNCHRONOUS DRAM

FEATURES

• PC100 functionality

• Fully synchronous; all signals registered on positive edge of system clock

• Internal pipelined operation; column address can be changed every clock cycle

• Internal banks for hiding row access/precharge 1 Meg x 16 - 512K x 16 x 2 banks architecture with 11 row, 8 column addresses per bank

• Programmable burst lengths: 1, 2, 4, 8 or full page

• Auto Precharge Mode, includes CONCURRENT AUTO PRECHARGE

• Self Refresh and Adaptable Auto Refresh Modes

- 32ms, 2,048-cycle refresh or

- 64ms, 2,048-cycle refresh or

- 64ms, 4,096-cycle refresh

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

• Supports CAS latency of 1, 2 and 3

• Industrial temperature range: -40°C to +85°C

OPTIONS MARKING

• Configuration 1 Meg x 16 (512K x 16 x 2 banks) 1M16A1

• Plastic Package - OCPL* 50-pin TSOP (400 mil) TG

• Timing (Cycle Time) 6ns (166 MHz) -6 7ns (143 MHz) -7 8ns (125 MHz) -8A

MT48LC1M16A1 SIT - 512K x 16 x 2 banks INDUSTRIAL TEMPERATURE

For the latest data sheet, please refer to the Micron Web site:

www.micronsemi.com/datasheets/sdramds.html

PIN ASSIGNMENT (Top View)

50-Pin TSOP

Vss

VDD

DQ0 DQ1

VssQ

DQ2 DQ3

DDQ

DQ4 DQ5

VssQ

DQ6 DQ7

DDQ

DQML

WE#

CAS# RAS#

CS#

A10

A0 A1 A2 A3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

DQ15

DQ14

VssQ

DQ13

DQ12

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

DDQ

DQ11 DQ10

VssQ

DQ9 DQ8

DDQ

NC DQMH CLK CKE NC

A9 A8 A7 A6 A5 A4

Vss

Note: The # symbol indicates signal is active LOW.

1 Meg x 16

Configuration 512K x 16 x 2 banks Refresh Count 2K or 4K Row Addressing 2K (A0-A10) Bank Addressing 2 (BA) Column Addressing 256 (A0-A7)

16MB (X16) SDRAM PART NUMBER

• Refresh 2K or 4K with Self Refresh Mode at 64ms S

PART NUMBER ARCHITECTURE

MT48LC1M16A1TG SIT 1 Meg x 16

• Operating Temperature

-40°C to +85°C IT

Part Number Example:

MT48LC1M16A1TG-7SIT

KEY TIMING PARAMETERS

SPEED CLOCK ACCESS TIME SETUP HOLD

CL = 3**

-6 166 MHz 5.5ns 2ns 1ns

-7 143 MHz 5.5ns 2ns 1ns

-8A 125 MHz 6ns 2ns 1ns

*Off-center parting line **CL = CAS (READ) latency

GENERAL DESCRIPTION

The 16Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 16,777,216 bits. It is internally configured as a dual 512K x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16-bit banks is organized as 2,048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA selects the bank, A0-A10 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row

16Mb: x16

IT SDRAM

precharge that is initiated at the end of the burst sequence.

The 1 Meg x 16 SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing the alternate bank will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation.

The 1 Meg x 16 SDRAM is designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic columnaddress generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.

TABLE OF CONTENTS

16Mb: x16

IT SDRAM

Functional Block Diagram - 1 Meg x 16 ................. 3

Pin Descriptions ........................................................ 4

Functional Description ........................................ 5

Initialization ........................................................ 5

Mode Register ................................................ 5

Burst Length .............................................. 5

Burst Type ................................................. 5

CAS Latency .............................................. 7

Operating Mode ....................................... 7

Write Burst Mode ..................................... 7

Commands .............................................................. 8

Truth Table 1 (Commands and DQM Operation) .............. 8

Command Inhibit ............................................... 9

No Operation (NOP) .......................................... 9

Load Mode Register ............................................ 9

Active .................................................................. 9

Read .................................................................. 9

Write .................................................................. 9

Precharge ............................................................. 9

Auto Precharge .................................................... 9

Burst Terminate ................................................... 9

Auto Refresh ........................................................ 10

Self Refresh .......................................................... 10

Operation................................................................ 11

Bank/Row Activation ......................................... 11

Reads .................................................................. 12

Writes .................................................................. 18

Precharge ............................................................. 20

Power-Down ....................................................... 20

Clock Suspend .................................................... 21

Burst Read/Single Write ...................................... 21

Concurrent Auto Precharge ................................ 22

Truth Table 2 (CKE) ................................................... 24

Truth Table 3 (Current State, Same Bank) ....................... 25

Truth Table 4 (Current State, Different Bank) ................... 27

Absolute Maximum Ratings .................................... 29

DC Electrical Characteristics and

Operating Conditions ........................................... 29

DD Specifications and Conditions .......................... 29

Capacitance .............................................................. 30

AC Electrical Characteristics (Timing Table) .... 30

Timing Waveforms

Initialize and Load Mode Register ...................... 33

Power-Down Mode ............................................ 34

Clock Suspend Mode .......................................... 35

Auto Refresh Mode ............................................. 36

Self Refresh Mode ............................................... 37

Reads

Read - Single Read ......................................... 38

Read - Without Auto Precharge .................... 39

Read - With Auto Precharge .......................... 40

Alternating Bank Read Accesses .................... 41

Read - Full-Page Burst .................................... 42

Read - DQM Operation ................................. 43

Writes

Write - Single Write ....................................... 44

Write - Without Auto Precharge ................... 45

Write - With Auto Precharge ......................... 46

Alternating Bank Write Accesses ................... 47

Write - Full-Page Burst ................................... 48

Write - DQM Operation ................................ 49

FUNCTIONAL BLOCK DIAGRAM

1 Meg x 16 SDRAM

16Mb: x16

IT SDRAM

A0-A10, BA

CKE

CLK

CS#

WE#

CAS#

RAS#

DECODE

COMMAND

MODE REGISTER

ADDRESS REGISTER

CONTROL

LOGIC

CONTROLLER

REFRESH

COUNTER

ROW-

ADDRESS

LATCH

COLUMN-

ADDRESS LATCH

BURST COUNTER

2,048

ROW

DECODER

COLUMN-

ADDRESS BUFFER

ROW-

ADDRESS

MUX

BANK0

MEMORY

ARRAY

(2,048 x 256 x 16)

256 (x16)

SENSE AMPLIFIERS

I/O GATING

DQM MASK LOGIC

256

COLUMN

DECODER

256

SENSE AMPLIFIERS

I/O GATING

DQM MASK LOGIC

256 (x16)

DQML, DQMH

DATA

OUTPUT

DATA INPUT

DQ0DQ15

ROW-

ADDRESS

LATCH

ROW

DECODER

2,048

BANK1

MEMORY

ARRAY

(2,048 x 256 x 16)

16Mb: x16

IT SDRAM

PIN DESCRIPTIONS

PIN NUMBERS SYMBOL TYPE DESCRIPTION

35 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are

sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers.

34 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK

signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), ACTIVE POWER-DOWN (row ACTIVE in either bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters powerdown and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH.

18 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered

HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code.

15, 16, 17 WE#, CAS#, Input Command Inputs: RAS#, CAS# and WE# (along with CS#) define the

RAS# command being entered.

14, 36 DQML, Input Input/Output Mask: DQM is an input mask signal for write accesses and an

DQMH output enable signal for read accesses. Input data is masked when

DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle. DQML corresponds to DQ0-DQ7; DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered same state when referenced as DQM.

19 BA Input Bank Address Inputs: BA defines to which bank the ACTIVE, READ,

WRITE or PRECHARGE command is being applied. BA is also used to program the twelfth bit of the Mode Register.

21-24, 27-32, 20 A0-A10 Input Address Inputs: A0-A10 are sampled during the ACTIVE command

(row-address A0-A10) and READ/WRITE command (column-address A0A7, with A10 defining AUTO PRECHARGE) to select one location out of the 512K available in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE REGISTER command.

2, 3, 5, 6, 8, 9, DQ0- Input/ Data I/Os: Data bus.

11, 12, 39, 40, 42, DQ15 Output

43, 45, 46, 48, 49

33, 37 NC – No Connect: These pins should be left unconnected.

7, 13, 38, 44 VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immu-

nity.

4, 10, 41, 47 VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise

immunity.

1, 25 VDD Supply Power Supply: +3.3V ±0.3V.

26, 50 VSS Supply Ground.

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IT SDRAM

FUNCTIONAL DESCRIPTION

In general, the SDRAM is a dual 512K x 16 DRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16-bit banks is organized as 2,048 rows by 256 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA selects the bank, A0-A10 select the row). The address bits (A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to applying any command other than a COMMAND INHIBIT or a NOP. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied.

Once the 100µs delay has been satisfied, with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for Mode Register programming. Because the Mode Register will power up in an unknown state, it should be loaded prior to applying any operational command.

MODE REGISTER

The Mode Register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 1. The Mode Register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power.

Mode Register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use.

The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.

Burst Length

Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a fullpage burst is available for the sequential type. The fullpage burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when the burst length is set to two, by A2-A7 when the burst length is set to four and by A3A7 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.

16Mb: x16

IT SDRAM

Reserved* WB

*Should program

M11, M10 = 0, 0

to ensure compatibility

with future devices.

A6 A5 A4

Op Mode

654

0-0-Defined

Write Burst Mode

Programmed Burst Length

Single Location Access

A10

A3A8A2A1A0

382

Burst LengthCAS Latency BT

M1M2

000

001

010

011

100

101

110

111

M4M5M6

000

001

010

011

100

101

110

111

M6 - M0

Mode Register (Mx)

M3 = 0

Reserved

Full Page

Burst Type

Sequential

Interleave

Operating Mode

Standard Operation

All other states reserved

Figure 1

Mode Register Definition

Address Bus

Burst Length

CAS Latency

Reserved

M3 = 1

Reserved

Table 1

Burst Definition

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full n = A0-A7

Page

(256) (location 0-255)

NOTE: 1. For a burst length of two, A1-A7 select the block

of two burst; A0 selects the starting column within the block.

2. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block.

3. For a burst length of eight, A3-A7 select the block of eight burst; A0-A2 select the starting column within the block.

4. For a full-page burst, the full row is selected and A0-A7 select the starting column.

5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

6. For a burst length of one, A0-A7 select the unique column to be accessed, and Mode Register bit M3 is ignored.

0 0-1 0-1 1 1-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0

Cn, Cn+1, Cn+2

Cn+3, Cn+4...

…Cn-1,

Not supported

Cn…

CAS Latency

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to 1, 2 or 3 clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0, and the latency is programmed to two clocks, the DQs will start driving after T1 and the data

16Mb: x16

IT SDRAM

will be valid by T2, as shown in Figure 2. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

CLK

COMMAND

CLK

COMMAND

CLK

COMMAND

CAS Latency = 1

CAS Latency = 2

T2T1T0

Write Burst Mode

When M9 = 0, the burst length programmed via

NOPREAD

OUT

M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.

Table 2

T2T1 T3T0

NOPREAD

NOP

OUT

SPEED LATENCY = 1 LATENCY = 2 LATENCY = 3

-6 ≤ 50 ≤ 125 ≤ 166

-7 ≤ 40 ≤ 100 ≤ 143

T2T1 T3T0

NOPREAD

NOP

OUT

-8A ≤ 40 ≤ 77 ≤ 125

CAS Latency

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS CAS CAS

CAS Latency = 3

DON’T CARE

UNDEFINED

Figure 2

CAS Latency

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IT SDRAM

COMMANDS

Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear

TRUTH TABLE 1 – COMMANDS AND DQM OPERATION

(Notes: 1)

NAME (FUNCTION) CS# RAS#CAS# WE# DQ M ADDR D Qs NOTES

COMMAND INHIBIT (NOP) H X X X X X X

NO OPERATION (NOP) L H H H X X X

ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3

READ (Select bank and column and start READ burst) L H L H L/H8Bank/Col X 4

WRITE (Select bank and column and L H L L L/H8Bank/Col Valid 4 start WRITE burst)

BURST TERMINATE L H H L X X Active

PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5

AUTO REFRESH or L L L H X X X 6, 7 SELF REFRESH (Enter self refresh mode)

LOAD MODE REGISTER L L L L X Op-Code X 2

Write Enable/Output Enable ––––L – Active 8

Write Inhibit/Output High-Z ––––H – High-Z 8

following the Operation section; these tables provide current state/next state information.

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-A10 and BA define the op-code written to the Mode Register.

3. A0-A10 provide row address, and BA determines which bank is made active.

4. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA determines which bank is being read from or written to.

5. For A10 LOW, BA determines which bank is being precharged; for A10 HIGH, all banks are precharged and BA is a “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

LOAD MODE REGISTER

The Mode Register is loaded via inputs A0-A10 and BA. See Mode Register heading in Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA input selects the bank, and the address provided on inputs A0-A10 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.

READ

The READ command is used to initiate a burst read access to an active row. The value on the BA input selects the bank, and the address provided on inputs A0-A7 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs, subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value on the BA input selects the bank, and the address provided on inputs

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IT SDRAM

A0-A7 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, input BA selects the bank. Otherwise BA is treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.

AUTO PRECHARGE

AUTO PRECHARGE is a feature which performs the same individual-bank PRECHARGE function described above, but without requiring an explicit command. This is accomplished by using A10 to enable AUTO PRECHARGE in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where AUTO PRECHARGE does not apply. AUTO PRECHARGE is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command.

AUTO PRECHARGE ensures that the PRECHARGE is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet.

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IT SDRAM

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated as shown in the Operation section of this data sheet.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORERAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh

is required.

The addressing during an AUTO REFRESH command is generated by an internal refresh controller. This means that the address lines are not used to generate the refresh address, and are “Don’t Care”.

The 1 Meg x 16 SDRAM requires 2,048 AUTO REFRESH cycles every 64ms (tREF) to ensure that each row is refreshed. Distributed refresh would be achieved by providing an AUTO REFRESH command once every 31.25µs. Burst refresh could be accomplished by issuing 2,048 AUTO REFRESH commands consecutively at the minimum cycle rate of tRC.

To provide a 4K refresh scheme, the refresh rate would be doubled. Thus, 2,048 AUTO-REFRESH commands distributed every 15.625µs would allow the 1 Meg x 16 SDRAM to have a 4K refresh if required. Of the three types of refreshs options, utilizing the 2,048 cycles every 64ms (31.25µs per refresh) provides the maximum power savings.

SELF REFRESH

The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care,” with the exception of CKE, which must remain LOW.

Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh mode for a minimum period

equal to

RAS, and may remain in self refresh mode for

an indefinite period beyond that.

The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for

XSR, because time is required for the completion of

any internal refresh in progress.

Upon exiting self refresh mode, AUTO REFRESH commands may be issued every 15.625µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter.

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IT SDRAM

OPERATION

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 3).

After opening a row (issuing an ACTIVE command) a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be issued. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks rounded to 3. This is reflected in Figure 4, which covers any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other specification limits from time units to clock cycles.)

A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.

CLK

CKE

RAS#

CAS#

WE#

A0-A10

CS#

HIGH

ROW

ADDRESS

BANK 1

BANK 0

Figure 3

Activating a Specific Row

in a Specific Bank

CLK

COMMAND

T2T1 T3T0

NOPACTIVE

RCD

NOP

READ or

WRITE

DON’T CARE

Figure 4

EXAMPLE: Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK

≤≤

≤ 3

≤≤

READs

CLK

T2T1 T3T0

CAS Latency = 3

OUT

COMMAND

NOPREAD

NOP

DON’T CARE

UNDEFINED

CLK

T2T1T0

CAS Latency = 1

OUT

COMMAND

NOPREAD

CLK

T2T1 T3T0

CAS Latency = 2

OUT

COMMAND

NOPREAD

NOP

READ bursts are initiated with a READ command, as shown in Figure 5.

The starting column and bank addresses are provided with the READ command and AUTO PRECHARGE is either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, AUTO PRECHARGE is disabled.

During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 6 shows general timing for each possible CAS latency setting.

CLK

16Mb: x16

IT SDRAM

Upon completion of a burst, assuming no other commands have been initiated, the DQs will go HighZ. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue).

Data from any READ burst may be truncated with a subsequent READ command, and data from a fixedlength READ burst may be immediately followed by data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst, or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired

CKE

CS#

RAS#

CAS#

WE#

A0-A7

A8-A9

A10

HIGH

COLUMN ADDRESS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK 1

BANK 0

Figure 5

READ Command

Figure 6

CAS Latency

16Mb: x16

IT SDRAM

data element is valid, where x equals the CAS latency minus one. This is shown in Figure 7 for READ latencies of one, two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 1 Meg x 16 SDRAM uses a pipelined architec-

T2T1 T4T3 T5T0

CLK

COMMAND

ADDRESS

CLK

READ NOP NOP NOP

BANK,

COL n

CAS Latency = 1

NOP

OUT

D n + 1

OUT

T2T1 T4T3 T6T5T0

ture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed, random read accesses within a page can be performed as shown in Figure 8.

READ

X = 0 cycles

BANK, COL b

OUT

D n + 2

OUT

n + 3

OUT

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

CAS Latency = 2

NOP

OUT

D n + 1

T2T1 T4T3 T6T5T0

CLK

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK, COL n

CAS Latency = 3

NOP

OUT

NOTE: Each READ command may be to either bank. DQM is LOW.

READ

X = 1 cycle

BANK, COL b

D n + 2

READ

BANK, COL b

D n + 1

OUT

D n + 3

X = 2 cycles

D n + 2

OUT

n + 3

OUT

NOP

OUT

DON’T CARE

Figure 7

Consecutive READ Bursts

CLK

16Mb: x16

IT SDRAM

T2T1 T4T3T0

COMMAND

ADDRESS

CLK

COMMAND

ADDRESS

READ NOP

BANK, COL n

CAS Latency = 1

READ READ READ

BANK,

COL a

OUT

BANK,

COL x

BANK, COL m

OUT

T2T1 T4T3 T5T0

READ NOP

BANK, COL n

READ READ READ NOP

BANK,

COL a

CAS Latency = 2

BANK,

COL x

BANK, COL m

OUT

T2T1 T4T3 T6T5T0

CLK

COMMAND

ADDRESS

READ NOP NOP

BANK, COL n

READ

BANK,

COL a

CAS Latency = 3

NOTE: Each READ command may be to either bank. DQM is LOW.

READ READ NOP

BANK,

COL x

BANK, COL m

OUT

DON’T CARE

Figure 8

Random READ Accesses

16Mb: x16

DON’T CARE

READ NOP NOPNOP NOP

DQM

CLK

OUT

T2T1 T4T3T0

COMMAND

ADDRESS

BANK,

COL n

WRITE

DIN b

BANK,

COL b

NOTE: A CAS latency of three is used for illustration. The

READ command

may be to any bank, and the WRITE command may be to any bank.

IT SDRAM

Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a subsequent WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be the possibility that the device driving the input data would go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command.

The DQM input is used to avoid I/O contention as shown in Figures 9 and 10. The DQM signal must be asserted (HIGH) at least two clocks (DQM latency is two clocks for output buffers) prior to the WRITE

T2T1 T4T3T0

CLK

DQM

command to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z) regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 10, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.

The DQM signal must be de-asserted (DQM latency is zero clocks for input buffers) prior to the WRITE command to ensure that the written data is not masked. Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 10 shows the case where the additional NOP is needed.

COMMAND

ADDRESS

NOTE: A CAS latency of three is used for illustration. The

READ NOP NOP

BANK, COL n

command may be to any bank, and the WRITE command may be to any bank. If a burst of one is used, then DQM is not required.

Figure 9

READ to WRITE

NOP

WRITE

BANK, COL b

OUT

DIN b

READ

Figure 10

READ to WRITE with

Extra Clock Cycle

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