Micron MT48LC1M16A1 User Manual

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16Mb: x16

IT SDRAM

SYNCHRONOUS DRAM

FEATURES

• PC100 functionality

• Fully synchronous; all signals registered on positive edge of system clock

• Internal pipelined operation; column address can be changed every clock cycle

• Internal banks for hiding row access/precharge 1 Meg x 16 - 512K x 16 x 2 banks architecture with 11 row, 8 column addresses per bank

• Programmable burst lengths: 1, 2, 4, 8 or full page

• Auto Precharge Mode, includes CONCURRENT AUTO PRECHARGE

• Self Refresh and Adaptable Auto Refresh Modes

- 32ms, 2,048-cycle refresh or

- 64ms, 2,048-cycle refresh or

- 64ms, 4,096-cycle refresh

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply

• Supports CAS latency of 1, 2 and 3

• Industrial temperature range: -40°C to +85°C

OPTIONS MARKING

• Configuration 1 Meg x 16 (512K x 16 x 2 banks) 1M16A1

• Plastic Package - OCPL* 50-pin TSOP (400 mil) TG

• Timing (Cycle Time) 6ns (166 MHz) -6 7ns (143 MHz) -7 8ns (125 MHz) -8A

MT48LC1M16A1 SIT - 512K x 16 x 2 banks INDUSTRIAL TEMPERATURE

For the latest data sheet, please refer to the Micron Web site:

www.micronsemi.com/datasheets/sdramds.html

PIN ASSIGNMENT (Top View)

50-Pin TSOP

Vss

VDD

DQ0 DQ1

VssQ

DQ2 DQ3

DDQ

DQ4 DQ5

VssQ

DQ6 DQ7

DDQ

DQML

WE#

CAS# RAS#

CS#

A10

A0 A1 A2 A3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

DQ15

DQ14

VssQ

DQ13

DQ12

44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26

DDQ

DQ11 DQ10

VssQ

DQ9 DQ8

DDQ

NC DQMH CLK CKE NC

A9 A8 A7 A6 A5 A4

Vss

Note: The # symbol indicates signal is active LOW.

1 Meg x 16

Configuration 512K x 16 x 2 banks Refresh Count 2K or 4K Row Addressing 2K (A0-A10) Bank Addressing 2 (BA) Column Addressing 256 (A0-A7)

16MB (X16) SDRAM PART NUMBER

• Refresh 2K or 4K with Self Refresh Mode at 64ms S

PART NUMBER ARCHITECTURE

MT48LC1M16A1TG SIT 1 Meg x 16

• Operating Temperature

-40°C to +85°C IT

Part Number Example:

MT48LC1M16A1TG-7SIT

KEY TIMING PARAMETERS

SPEED CLOCK ACCESS TIME SETUP HOLD

CL = 3**

-6 166 MHz 5.5ns 2ns 1ns

-7 143 MHz 5.5ns 2ns 1ns

-8A 125 MHz 6ns 2ns 1ns

*Off-center parting line **CL = CAS (READ) latency

GENERAL DESCRIPTION

The 16Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 16,777,216 bits. It is internally configured as a dual 512K x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16-bit banks is organized as 2,048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA selects the bank, A0-A10 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable READ or WRITE burst lengths of 1, 2, 4 or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a self-timed row

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IT SDRAM

precharge that is initiated at the end of the burst sequence.

The 1 Meg x 16 SDRAM uses an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. Precharging one bank while accessing the alternate bank will hide the PRECHARGE cycles and provide seamless, high-speed, random-access operation.

The 1 Meg x 16 SDRAM is designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible.

SDRAMs offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic columnaddress generation, the ability to interleave between internal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.

TABLE OF CONTENTS

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IT SDRAM

Functional Block Diagram - 1 Meg x 16 ................. 3

Pin Descriptions ........................................................ 4

Functional Description ........................................ 5

Initialization ........................................................ 5

Mode Register ................................................ 5

Burst Length .............................................. 5

Burst Type ................................................. 5

CAS Latency .............................................. 7

Operating Mode ....................................... 7

Write Burst Mode ..................................... 7

Commands .............................................................. 8

Truth Table 1 (Commands and DQM Operation) .............. 8

Command Inhibit ............................................... 9

No Operation (NOP) .......................................... 9

Load Mode Register ............................................ 9

Active .................................................................. 9

Read .................................................................. 9

Write .................................................................. 9

Precharge ............................................................. 9

Auto Precharge .................................................... 9

Burst Terminate ................................................... 9

Auto Refresh ........................................................ 10

Self Refresh .......................................................... 10

Operation................................................................ 11

Bank/Row Activation ......................................... 11

Reads .................................................................. 12

Writes .................................................................. 18

Precharge ............................................................. 20

Power-Down ....................................................... 20

Clock Suspend .................................................... 21

Burst Read/Single Write ...................................... 21

Concurrent Auto Precharge ................................ 22

Truth Table 2 (CKE) ................................................... 24

Truth Table 3 (Current State, Same Bank) ....................... 25

Truth Table 4 (Current State, Different Bank) ................... 27

Absolute Maximum Ratings .................................... 29

DC Electrical Characteristics and

Operating Conditions ........................................... 29

DD Specifications and Conditions .......................... 29

Capacitance .............................................................. 30

AC Electrical Characteristics (Timing Table) .... 30

Timing Waveforms

Initialize and Load Mode Register ...................... 33

Power-Down Mode ............................................ 34

Clock Suspend Mode .......................................... 35

Auto Refresh Mode ............................................. 36

Self Refresh Mode ............................................... 37

Reads

Read - Single Read ......................................... 38

Read - Without Auto Precharge .................... 39

Read - With Auto Precharge .......................... 40

Alternating Bank Read Accesses .................... 41

Read - Full-Page Burst .................................... 42

Read - DQM Operation ................................. 43

Writes

Write - Single Write ....................................... 44

Write - Without Auto Precharge ................... 45

Write - With Auto Precharge ......................... 46

Alternating Bank Write Accesses ................... 47

Write - Full-Page Burst ................................... 48

Write - DQM Operation ................................ 49

FUNCTIONAL BLOCK DIAGRAM

1 Meg x 16 SDRAM

16Mb: x16

IT SDRAM

A0-A10, BA

CKE

CLK

CS#

WE#

CAS#

RAS#

DECODE

COMMAND

MODE REGISTER

ADDRESS REGISTER

CONTROL

LOGIC

CONTROLLER

REFRESH

COUNTER

ROW-

ADDRESS

LATCH

COLUMN-

ADDRESS LATCH

BURST COUNTER

2,048

ROW

DECODER

COLUMN-

ADDRESS BUFFER

ROW-

ADDRESS

MUX

BANK0

MEMORY

ARRAY

(2,048 x 256 x 16)

256 (x16)

SENSE AMPLIFIERS

I/O GATING

DQM MASK LOGIC

256

COLUMN

DECODER

256

SENSE AMPLIFIERS

I/O GATING

DQM MASK LOGIC

256 (x16)

DQML, DQMH

DATA

OUTPUT

DATA INPUT

DQ0DQ15

ROW-

ADDRESS

LATCH

ROW

DECODER

2,048

BANK1

MEMORY

ARRAY

(2,048 x 256 x 16)

16Mb: x16

IT SDRAM

PIN DESCRIPTIONS

PIN NUMBERS SYMBOL TYPE DESCRIPTION

35 CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are

sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers.

34 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK

signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), ACTIVE POWER-DOWN (row ACTIVE in either bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters powerdown and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down and self refresh modes, providing low standby power. CKE may be tied HIGH.

18 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered

HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code.

15, 16, 17 WE#, CAS#, Input Command Inputs: RAS#, CAS# and WE# (along with CS#) define the

RAS# command being entered.

14, 36 DQML, Input Input/Output Mask: DQM is an input mask signal for write accesses and an

DQMH output enable signal for read accesses. Input data is masked when

DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQM is sampled HIGH during a READ cycle. DQML corresponds to DQ0-DQ7; DQMH corresponds to DQ8-DQ15. DQML and DQMH are considered same state when referenced as DQM.

19 BA Input Bank Address Inputs: BA defines to which bank the ACTIVE, READ,

WRITE or PRECHARGE command is being applied. BA is also used to program the twelfth bit of the Mode Register.

21-24, 27-32, 20 A0-A10 Input Address Inputs: A0-A10 are sampled during the ACTIVE command

(row-address A0-A10) and READ/WRITE command (column-address A0A7, with A10 defining AUTO PRECHARGE) to select one location out of the 512K available in the respective bank. A10 is sampled during a PRECHARGE command to determine if all banks are to be precharged (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE REGISTER command.

2, 3, 5, 6, 8, 9, DQ0- Input/ Data I/Os: Data bus.

11, 12, 39, 40, 42, DQ15 Output

43, 45, 46, 48, 49

33, 37 NC – No Connect: These pins should be left unconnected.

7, 13, 38, 44 VDDQ Supply DQ Power: Provide isolated power to DQs for improved noise immu-

nity.

4, 10, 41, 47 VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise

immunity.

1, 25 VDD Supply Power Supply: +3.3V ±0.3V.

26, 50 VSS Supply Ground.

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IT SDRAM

FUNCTIONAL DESCRIPTION

In general, the SDRAM is a dual 512K x 16 DRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16-bit banks is organized as 2,048 rows by 256 columns by 16 bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA selects the bank, A0-A10 select the row). The address bits (A0-A7) registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

Prior to normal operation, the SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Once power is applied to VDD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to applying any command other than a COMMAND INHIBIT or a NOP. Starting at some point during this 100µs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands should be applied.

Once the 100µs delay has been satisfied, with at least one COMMAND INHIBIT or NOP command having been applied, a PRECHARGE command should be applied. All banks must then be precharged, thereby placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed. After the AUTO REFRESH cycles are complete, the SDRAM is ready for Mode Register programming. Because the Mode Register will power up in an unknown state, it should be loaded prior to applying any operational command.

MODE REGISTER

The Mode Register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency, an operating mode and a write burst mode, as shown in Figure 1. The Mode Register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is programmed again or the device loses power.

Mode Register bits M0-M2 specify the burst length, M3 specifies the type of burst (sequential or interleaved), M4-M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode, and M10 and M11 are reserved for future use.

The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.

Burst Length

Read and write accesses to the SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a fullpage burst is available for the sequential type. The fullpage burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-A7 when the burst length is set to two, by A2-A7 when the burst length is set to four and by A3A7 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.

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IT SDRAM

Reserved* WB

*Should program

M11, M10 = 0, 0

to ensure compatibility

with future devices.

A6 A5 A4

Op Mode

654

0-0-Defined

Write Burst Mode

Programmed Burst Length

Single Location Access

A10

A3A8A2A1A0

382

Burst LengthCAS Latency BT

M1M2

000

001

010

011

100

101

110

111

M4M5M6

000

001

010

011

100

101

110

111

M6 - M0

Mode Register (Mx)

M3 = 0

Reserved

Full Page

Burst Type

Sequential

Interleave

Operating Mode

Standard Operation

All other states reserved

Figure 1

Mode Register Definition

Address Bus

Burst Length

CAS Latency

Reserved

M3 = 1

Reserved

Table 1

Burst Definition

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full n = A0-A7

Page

(256) (location 0-255)

NOTE: 1. For a burst length of two, A1-A7 select the block

of two burst; A0 selects the starting column within the block.

2. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block.

3. For a burst length of eight, A3-A7 select the block of eight burst; A0-A2 select the starting column within the block.

4. For a full-page burst, the full row is selected and A0-A7 select the starting column.

5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

6. For a burst length of one, A0-A7 select the unique column to be accessed, and Mode Register bit M3 is ignored.

0 0-1 0-1 1 1-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0

Cn, Cn+1, Cn+2

Cn+3, Cn+4...

…Cn-1,

Not supported

Cn…

CAS Latency

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to 1, 2 or 3 clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0, and the latency is programmed to two clocks, the DQs will start driving after T1 and the data

16Mb: x16

IT SDRAM

will be valid by T2, as shown in Figure 2. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to both READ and WRITE bursts.

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

CLK

COMMAND

CLK

COMMAND

CLK

COMMAND

CAS Latency = 1

CAS Latency = 2

T2T1T0

Write Burst Mode

When M9 = 0, the burst length programmed via

NOPREAD

OUT

M0-M2 applies to both READ and WRITE bursts; when M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.

Table 2

T2T1 T3T0

NOPREAD

NOP

OUT

SPEED LATENCY = 1 LATENCY = 2 LATENCY = 3

-6 ≤ 50 ≤ 125 ≤ 166

-7 ≤ 40 ≤ 100 ≤ 143

T2T1 T3T0

NOPREAD

NOP

OUT

-8A ≤ 40 ≤ 77 ≤ 125

CAS Latency

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS CAS CAS

CAS Latency = 3

DON’T CARE

UNDEFINED

Figure 2

CAS Latency

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IT SDRAM

COMMANDS

Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear

TRUTH TABLE 1 – COMMANDS AND DQM OPERATION

(Notes: 1)

NAME (FUNCTION) CS# RAS#CAS# WE# DQ M ADDR D Qs NOTES

COMMAND INHIBIT (NOP) H X X X X X X

NO OPERATION (NOP) L H H H X X X

ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3

READ (Select bank and column and start READ burst) L H L H L/H8Bank/Col X 4

WRITE (Select bank and column and L H L L L/H8Bank/Col Valid 4 start WRITE burst)

BURST TERMINATE L H H L X X Active

PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5

AUTO REFRESH or L L L H X X X 6, 7 SELF REFRESH (Enter self refresh mode)

LOAD MODE REGISTER L L L L X Op-Code X 2

Write Enable/Output Enable ––––L – Active 8

Write Inhibit/Output High-Z ––––H – High-Z 8

following the Operation section; these tables provide current state/next state information.

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-A10 and BA define the op-code written to the Mode Register.

3. A0-A10 provide row address, and BA determines which bank is made active.

4. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA determines which bank is being read from or written to.

5. For A10 LOW, BA determines which bank is being precharged; for A10 HIGH, all banks are precharged and BA is a “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands from being executed by the SDRAM, regardless of whether the CLK signal is enabled. The SDRAM is effectively deselected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to an SDRAM which is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

LOAD MODE REGISTER

The Mode Register is loaded via inputs A0-A10 and BA. See Mode Register heading in Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA input selects the bank, and the address provided on inputs A0-A10 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.

READ

The READ command is used to initiate a burst read access to an active row. The value on the BA input selects the bank, and the address provided on inputs A0-A7 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the READ burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Read data appears on the DQs, subject to the logic level on the DQM inputs two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value on the BA input selects the bank, and the address provided on inputs

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IT SDRAM

A0-A7 selects the starting column location. The value on input A10 determines whether or not AUTO PRECHARGE is used. If AUTO PRECHARGE is selected, the row being accessed will be precharged at the end of the WRITE burst; if AUTO PRECHARGE is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, input BA selects the bank. Otherwise BA is treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.

AUTO PRECHARGE

AUTO PRECHARGE is a feature which performs the same individual-bank PRECHARGE function described above, but without requiring an explicit command. This is accomplished by using A10 to enable AUTO PRECHARGE in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst, except in the full-page burst mode, where AUTO PRECHARGE does not apply. AUTO PRECHARGE is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command.

AUTO PRECHARGE ensures that the PRECHARGE is initiated at the earliest valid stage within a burst. The user must not issue another command to the same bank until the precharge time (tRP) is completed. This is determined as if an explicit PRECHARGE command was issued at the earliest possible time, as described for each burst type in the Operation section of this data sheet.

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IT SDRAM

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated as shown in the Operation section of this data sheet.

AUTO REFRESH

AUTO REFRESH is used during normal operation of the SDRAM and is analogous to CAS#-BEFORERAS# (CBR) REFRESH in conventional DRAMs. This command is nonpersistent, so it must be issued each time a refresh

is required.

The addressing during an AUTO REFRESH command is generated by an internal refresh controller. This means that the address lines are not used to generate the refresh address, and are “Don’t Care”.

The 1 Meg x 16 SDRAM requires 2,048 AUTO REFRESH cycles every 64ms (tREF) to ensure that each row is refreshed. Distributed refresh would be achieved by providing an AUTO REFRESH command once every 31.25µs. Burst refresh could be accomplished by issuing 2,048 AUTO REFRESH commands consecutively at the minimum cycle rate of tRC.

To provide a 4K refresh scheme, the refresh rate would be doubled. Thus, 2,048 AUTO-REFRESH commands distributed every 15.625µs would allow the 1 Meg x 16 SDRAM to have a 4K refresh if required. Of the three types of refreshs options, utilizing the 2,048 cycles every 64ms (31.25µs per refresh) provides the maximum power savings.

SELF REFRESH

The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). Once the SELF REFRESH command is registered, all the inputs to the SDRAM become “Don’t Care,” with the exception of CKE, which must remain LOW.

Once self refresh mode is engaged, the SDRAM provides its own internal clocking, causing it to perform its own auto refresh cycles. The SDRAM must remain in self refresh mode for a minimum period

equal to

RAS, and may remain in self refresh mode for

an indefinite period beyond that.

The procedure for exiting self refresh requires a sequence of commands. First, CLK must be stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) prior to CKE going back HIGH. Once CKE is HIGH, the SDRAM must have NOP commands issued (a minimum of two clocks) for

XSR, because time is required for the completion of

any internal refresh in progress.

Upon exiting self refresh mode, AUTO REFRESH commands may be issued every 15.625µs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter.

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IT SDRAM

OPERATION

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Figure 3).

After opening a row (issuing an ACTIVE command) a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be issued. For example, a tRCD specification of 20ns with a 125 MHz clock (8ns period) results in 2.5 clocks rounded to 3. This is reflected in Figure 4, which covers any case where 2 < tRCD (MIN)/tCK ≤ 3. (The same procedure is used to convert other specification limits from time units to clock cycles.)

A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.

CLK

CKE

RAS#

CAS#

WE#

A0-A10

CS#

HIGH

ROW

ADDRESS

BANK 1

BANK 0

Figure 3

Activating a Specific Row

in a Specific Bank

CLK

COMMAND

T2T1 T3T0

NOPACTIVE

RCD

NOP

READ or

WRITE

DON’T CARE

Figure 4

EXAMPLE: Meeting tRCD (MIN) when 2 < tRCD (MIN)/tCK

≤≤

≤ 3

≤≤

READs

CLK

T2T1 T3T0

CAS Latency = 3

OUT

COMMAND

NOPREAD

NOP

DON’T CARE

UNDEFINED

CLK

T2T1T0

CAS Latency = 1

OUT

COMMAND

NOPREAD

CLK

T2T1 T3T0

CAS Latency = 2

OUT

COMMAND

NOPREAD

NOP

READ bursts are initiated with a READ command, as shown in Figure 5.

The starting column and bank addresses are provided with the READ command and AUTO PRECHARGE is either enabled or disabled for that burst access. If AUTO PRECHARGE is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, AUTO PRECHARGE is disabled.

During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 6 shows general timing for each possible CAS latency setting.

CLK

16Mb: x16

IT SDRAM

Upon completion of a burst, assuming no other commands have been initiated, the DQs will go HighZ. A full-page burst will continue until terminated (at the end of the page it will wrap to column 0 and continue).

Data from any READ burst may be truncated with a subsequent READ command, and data from a fixedlength READ burst may be immediately followed by data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst, or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles before the clock edge at which the last desired

CKE

CS#

RAS#

CAS#

WE#

A0-A7

A8-A9

A10

HIGH

COLUMN ADDRESS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK 1

BANK 0

Figure 5

READ Command

Figure 6

CAS Latency

16Mb: x16

IT SDRAM

data element is valid, where x equals the CAS latency minus one. This is shown in Figure 7 for READ latencies of one, two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. The 1 Meg x 16 SDRAM uses a pipelined architec-

T2T1 T4T3 T5T0

CLK

COMMAND

ADDRESS

CLK

READ NOP NOP NOP

BANK,

COL n

CAS Latency = 1

NOP

OUT

D n + 1

OUT

T2T1 T4T3 T6T5T0

ture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed, random read accesses within a page can be performed as shown in Figure 8.

READ

X = 0 cycles

BANK, COL b

OUT

D n + 2

OUT

n + 3

OUT

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK,

COL n

CAS Latency = 2

NOP

OUT

D n + 1

T2T1 T4T3 T6T5T0

CLK

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK, COL n

CAS Latency = 3

NOP

OUT

NOTE: Each READ command may be to either bank. DQM is LOW.

READ

X = 1 cycle

BANK, COL b

D n + 2

READ

BANK, COL b

D n + 1

OUT

D n + 3

X = 2 cycles

D n + 2

OUT

n + 3

OUT

NOP

OUT

DON’T CARE

Figure 7

Consecutive READ Bursts

CLK

16Mb: x16

IT SDRAM

T2T1 T4T3T0

COMMAND

ADDRESS

CLK

COMMAND

ADDRESS

READ NOP

BANK, COL n

CAS Latency = 1

READ READ READ

BANK,

COL a

OUT

BANK,

COL x

BANK, COL m

OUT

T2T1 T4T3 T5T0

READ NOP

BANK, COL n

READ READ READ NOP

BANK,

COL a

CAS Latency = 2

BANK,

COL x

BANK, COL m

OUT

T2T1 T4T3 T6T5T0

CLK

COMMAND

ADDRESS

READ NOP NOP

BANK, COL n

READ

BANK,

COL a

CAS Latency = 3

NOTE: Each READ command may be to either bank. DQM is LOW.

READ READ NOP

BANK,

COL x

BANK, COL m

OUT

DON’T CARE

Figure 8

Random READ Accesses

16Mb: x16

DON’T CARE

READ NOP NOPNOP NOP

DQM

CLK

OUT

T2T1 T4T3T0

COMMAND

ADDRESS

BANK,

COL n

WRITE

DIN b

BANK,

COL b

NOTE: A CAS latency of three is used for illustration. The

READ command

may be to any bank, and the WRITE command may be to any bank.

IT SDRAM

Data from any READ burst may be truncated with a subsequent WRITE command, and data from a fixed-length READ burst may be immediately followed by data from a subsequent WRITE command (subject to bus turnaround limitations). The WRITE burst may be initiated on the clock edge immediately following the last (or last desired) data element from the READ burst, provided that I/O contention can be avoided. In a given system design, there may be the possibility that the device driving the input data would go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command.

The DQM input is used to avoid I/O contention as shown in Figures 9 and 10. The DQM signal must be asserted (HIGH) at least two clocks (DQM latency is two clocks for output buffers) prior to the WRITE

T2T1 T4T3T0

CLK

DQM

command to suppress data-out from the READ. Once the WRITE command is registered, the DQs will go High-Z (or remain High-Z) regardless of the state of the DQM signal, provided the DQM was active on the clock just prior to the WRITE command that truncated the READ command. If not, the second WRITE will be an invalid WRITE. For example, if DQM was LOW during T4 in Figure 10, then the WRITEs at T5 and T7 would be valid, while the WRITE at T6 would be invalid.

The DQM signal must be de-asserted (DQM latency is zero clocks for input buffers) prior to the WRITE command to ensure that the written data is not masked. Figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a NOP cycle, and Figure 10 shows the case where the additional NOP is needed.

COMMAND

ADDRESS

NOTE: A CAS latency of three is used for illustration. The

READ NOP NOP

BANK, COL n

command may be to any bank, and the WRITE command may be to any bank. If a burst of one is used, then DQM is not required.

Figure 9

READ to WRITE

NOP

WRITE

BANK, COL b

OUT

DIN b

READ

Figure 10

READ to WRITE with

Extra Clock Cycle

16Mb: x16

IT SDRAM

A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that AUTO PRECHARGE was not activated) and a full-page burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 11 for each possible CAS

T2T1 T4T3 T6T5T0

CLK

COMMAND

ADDRESS

READ NOP NOP NOP NOP

BANK a,

COL n

CAS Latency = 1

NOP

OUT

n + 1

latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data element(s).

In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same

ACTIVE

BANK a,

ROW

OUT

D n + 2

PRECHARGE

X = 0 cycles

BANK

(a or all)

OUT

n + 3

CLK

COMMAND

ADDRESS

BANK a,

COL n

CLK

COMMAND

ADDRESS

BANK a,

COL n

NOTE: DQM is LOW.

T2T1 T4T3 T6T5T0

READ NOP NOP NOP NOPNOP

CAS Latency = 2

T2T1 T4T3 T6T5T0

READ NOP NOP NOP NOPNOP

CAS Latency = 3

n + 3

OUT

ACTIVE

BANK a,

ROW

PRECHARGE

X = 1 cycle

BANK

(a or all)

OUT

n + 1

n + 2

X = 2 cycles

D n + 2

OUT

D n + 3

OUT

ACTIVE

BANK a,

ROW

OUT

PRECHARGE

BANK

(a or all)

OUT

n + 1

DON’T CARE

Figure 11

READ to PRECHARGE

16Mb: x16

IT SDRAM

operation that would result from the same fixedlength burst with AUTO PRECHARGE. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.

Full-page READ bursts can be truncated with the

BURST TERMINATE command, and fixed-length

T2T1 T4T3 T6T5T0

CLK

COMMAND

ADDRESS

CLK

READ NOP NOP NOP

BANK,

COL n

CAS Latency = 1

NOP

OUT

n + 1

T2T1 T4T3 T6T5T0

READ bursts may be truncated with a BURST TERMINATE command, provided that AUTO PRECHARGE was not activated. The BURST TERMINATE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 12 for each possible CAS latency; data element n + 3 is the last desired data element of a longer burst.

D n + 2

OUT

BURST

TERMINATE

X = 0 cycles

OUT

D n + 3

NOP

COMMAND

ADDRESS

CLK

COMMAND

ADDRESS

NOTE: DQM is LOW.

OUT

n + 1

BURST

TERMINATE

X = 1 cycle

OUT

D n + 2

n + 3

OUT

READ NOP NOP NOP

BANK,

COL n

CAS Latency = 2

NOP

OUT

T2T1 T4T3 T6T5T0

OUT

BURST

TERMINATE

OUT

n + 1

X = 2 cycles

OUT

D n + 2

READ NOP NOP NOP NOP

BANK,

COL n

CAS Latency = 3

NOP

Figure 12

Terminating a READ Burst

NOP

n + 3

OUT

NOP

DON’T CARE

WRITEs

CLK

T2T1 T3T0

COMMAND

ADDRESS

NOP NOPWRITE

n + 1

NOP

BANK,

COL n

NOTE: Burst length = 2. DQM is LOW.

WRITE bursts are initiated with a WRITE com-

mand, as shown in Figure 13.

The starting column and bank addresses are provided with the WRITE command and AUTO PRECHARGE is either enabled or disabled for that access. If AUTO PRECHARGE is enabled, the row being accessed is precharged at the completion of the burst. For the generic WRITE commands used in the following illustrations, AUTO PRECHARGE is disabled.

During WRITE bursts, the first valid data-in element will be registered coincident with the WRITE command. Subsequent data elements will be registered on each successive positive clock edge. Upon completion of a fixed-length burst, assuming no other commands have been initiated, the DQs will remain High-Z, and any additional input data will be ignored (see Figure

14). A full-page burst will continue until terminated. (At the end of the page it will wrap to column 0 and continue.)

Data for any WRITE burst may be truncated with a subsequent WRITE command, and data for a fixedlength WRITE burst may be immediately followed by data for a subsequent WRITE command. The new WRITE command can be issued on any clock following the previous WRITE command, and the data provided

16Mb: x16

IT SDRAM

coincident with the new command applies to the new command. An example is shown in Figure 15. Data n + 1 is either the last of a burst of two, or the last desired of a longer burst. The 1 Meg x 16 SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command. Full-speed, random write accesses within a page can be performed as shown in Figure 16.

CLK

CKE

CS#

RAS#

CAS#

WE#

A0-A7

A8-A9

A10

HIGH

COLUMN

ADDRESS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK 1

BANK 0

Figure 13

WRITE Command

WRITE Burst

CLK

COMMAND

ADDRESS

NOTE: DQM is LOW.

command may be to any bank.

WRITE to WRITE

Figure 14

BANK, COL n

Figure 15

T2T1T0

NOPWRITE WRITE

BANK,

COL b

n + 1

Each WRITE

DON’T CARE

16Mb: x16

DQM

CLK

T2T1 T4T3T0

COMMAND

ADDRESS

BANK a,

COL

NOPWRITE

PRECHARGE

NOPNOP

DIN

n + 1

ACTIVE

DON’T CARE

BANK

(

or all)

NOTE: DQM could remain LOW in this example if the WRITE burst is a

fixed length of two. Future SDRAMs will require a

WR of at least

two clocks.

BANK a,

ROW

DQM

COMMAND

ADDRESS

BANK a,

COL

NOPWRITE

PRECHARGE

NOP

n + 1

ACTIVE

BANK

(

or all)

BANK a,

ROW

NOP

WR = 1 CLK (tCK tWR)

WR = 2 CLK (tCK < tWR)

IT SDRAM

Data for any WRITE burst may be truncated with a subsequent READ command, and data for a fixedlength WRITE burst may be immediately followed by a subsequent READ command. Once the READ command is registered, the data inputs will be ignored, and WRITEs will not be executed. An example is shown in Figure 17. Data n + 1 is either the last of a burst of two, or the last desired of a longer burst.

Data for a fixed-length WRITE burst may be followed by, or truncated with, a PRECHARGE command to the same bank (provided that AUTO PRECHARGE was not activated), and a full-page WRITE burst may be truncated with a PRECHARGE command to the same bank. The PRECHARGE command should be

issued

WR after the clock edge at which the last desired

T2T1 T3T0

CLK

COMMAND

WRITE

WRITE WRITE

input data element is registered. In addition, when truncating a WRITE burst, the DQM signal must be used to mask input data for the clock edge prior to, and the clock edge coincident with, the PRECHARGE command. An example is shown in Figure 18. Data n + 1 is either the last of a burst of two or the last desired of a longer burst. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.

In the case of a fixed-length burst being executed to completion, a PRECHARGE command issued at the optimum time (as described above) provides the same operation that would result from the same fixedlength burst with AUTO PRECHARGE. The disadvantage of the PRECHARGE command is that it requires that the command and address buses be available at the appropriate time to issue the command; the advantage of the PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.

ADDRESS

COMMAND

ADDRESS

BANK,

COL n

NOTE: Each WRITE command may be to any bank.

DIN

BANK, COL a

DIN

BANK,

COL x

BANK,

COL m

DQM is LOW.

Figure 16

Random WRITE Cycles

T2T1 T3T0

CLK

NOPWRITE

BANK, COL n

n + 1

DIN

NOTE: The WRITE command may be to any bank, and the READ command may

be to any bank. DQM is LOW. CAS latency = 2 for illustration.

READ NOP NOP

BANK, COL b

T4 T5

NOP

DOUT

b + 1

OUT

Figure 17

WRITE to READ

Figure 18

WRITE to PRECHARGE

16Mb: x16

RAS

RCD

All banks idle

Input buffers gated off

Exit POWERDOWN mode

()(

)

()(

)

()(

)

CKS

< t

CKS

COMMAND

NOP ACTIVE

Enter POWERDOWN mode

NOP

CLK

CKE

()(

)

()(

)

DON’T CARE

IT SDRAM

Fixed-length or full-page WRITE bursts can be truncated with the BURST TERMINATE command. When truncating a WRITE burst, the input data applied coincident with the BURST TERMINATE command will be ignored. The last data written (provided that DQM is LOW at that time) will be the input data applied one clock previous to the BURST TERMINATE command. This is shown in Figure 19, where data n is the last desired data element of a longer burst.

T2T1T0

CLK

COMMAND

ADDRESS

NOTE: DQMs are low

WRITE

BANK, COL n

DIN

BURST

TERMINATE

Command

(Address)

(Data)

Figure 19

Terminating a WRITE Burst

CLK

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks (see Figure 20). The bank(s) will be available

for a subsequent row access some specified time (

RP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, input BA selects the bank. When all banks are to be precharged, input BA is treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank.

POWER-DOWN

POWER-DOWN occurs if CKE is registered LOW coincident with a NOP or COMMAND INHIBIT, when no accesses are in progress (see Figure 21). If POWERDOWN occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CKE, for maximum power savings while in standby. The device may not remain in the powerdown state longer than the refresh period (64ms) since no refresh operations are performed in this mode.

The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE HIGH at the desired clock edge (meeting

CKS).

CKE

HIGH

CS#

RAS#

CAS#

WE#

A0-A9

Figure 21

A10

Figure 20

PRECHARGE Command

BANK 0 and 1

BANK 0 or 1

BANK 1

BANK 0

POWER-DOWN

DON’T CARE

CLK

DOUT

T2T1 T4T3 T6T5T0

COMMAND

ADDRESS

READ NOP NOP NOP

BANK, COL n

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and

DQM is LOW.

CKE

INTERNAL

CLOCK

NOP

CLOCK SUSPEND

The clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic.

For each positive clock edge on which CKE is sampled LOW, the next internal positive clock edge is suspended. Any command or data present on the input pins at the time of a suspended internal clock edge are ignored; any data present on the DQ pins will remain driven; and burst counters are not incremented as long as the clock is suspended (see examples in Figures 22 and 23).

T2T1 T4T3 T5T0

CLK

CKE

16Mb: x16

IT SDRAM

Clock suspend mode is exited by registering CKE HIGH; the internal clock and related operation will resume on the subsequent positive clock edge.

BURST READ/SINGLE WRITE

The burst read/single write mode is entered by programming the write burst mode bit (M9) in the Mode Register to a logic 1. In this mode, all WRITE commands result in the access of a single column location (burst of one) regardless of the programmed burst length. READ commands access columns according to the programmed burst length and sequence, just as in the normal mode of operation (M9 = 0).

INTERNAL

CLOCK

COMMAND

ADDRESS

NOP

WRITE

BANK,

COL n

n + 1

NOPNOP

n + 2

NOTE: For this example, burst length = 4 or greater, and DQM

is LOW.

Figure 22

Clock Suspend During WRITE Burst

Figure 23

Clock Suspend During READ Burst

CONCURRENT AUTO PRECHARGE

An access command (READ or WRITE) to another bank while an access command with AUTO PRECHARGE enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. Micron SDRAMs support CONCURRENT AUTO PRECHARGE. Four cases where CONCURRENT AUTO PRECHARGE occurs are defined below.

READ with AUTO PRECHARGE

1. Interrupted by a READ (with or without AUTO

16Mb: x16

IT SDRAM

PRECHARGE): A READ to bank m will interrupt a READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24).

2. Interrupted by a WRITE (with or without AUTO PRECHARGE): A WRITE to bank m will interrupt a READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).

T2T1 T4T3 T6T5T0

CLK

COMMAND

Internal States

ADDRESS

NOTE: DQM is LOW.

BANK n

BANK m

READ - AP

BANK n

Page Active READ with Burst of 4 Interrupt Burst, Precharge

Page Active READ with Burst of 4

BANK n,

COL a

CAS Latency = 3 (BANK n)

READ - AP

BANK m

BANK m,

COL d

CAS Latency = 3 (BANK m)

NOP

RP - BANK n

OUT

NOP NOPNOPNOP

OUT

D a + 1

OUT

Figure 24

READ with AUTO PRECHARGE Interrupted by a READ

T2T1 T4T3 T6T5T0

CLK

NOP

WRITE - AP

BANK m

RP -

BANK

NOPNOPNOPNOP

Internal States

COMMAND

BANK n

BANK m

READ - AP

BANK n

Page

READ with Burst of 4 Interrupt Burst, Precharge

Active

Page Active WRITE with Burst of 4

Idle

NOP

WR -

RP - BANK m

Precharge

OUT

d + 1

Idle

BANK

Write-Back

DQM

BANK n,

COL a

CAS Latency = 3 (BANK n)

ADDRESS

NOTE: 1. DQM is HIGH at T2 to prevent D

OUT

-a+1 from contending with DIN-d at T4.

BANK m,

COL d

OUT

d + 1

d + 2

d + 3

DON’T CARE

Figure 25

READ with AUTO PRECHARGE Interrupted by a WRITE

WRITE with AUTO PRECHARGE

3. Interrupted by a READ (with or without AUTO PRECHARGE): A READ to bank m will interrupt a WRITE on bank n when registered, with the dataout appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26).

16Mb: x16

IT SDRAM

4. Interrupted by a WRITE (with or without AUTO PRECHARGE): A WRITE to bank m will interrupt a WRITE on bank n when registered. The PRECHARGE to bank n will begin after begins when the WRITE to bank m is registered. The last valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank m (Figure 27).

WR is met, where tWR

T2T1 T4T3 T6T5T0

CLK

COMMAND

BANK n

Internal States

BANK m

ADDRESS

NOTE: 1. DQM is LOW.

WRITE - AP

BANK n

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

Page Active READ with Burst of 4

BANK n,

COL a

a + 1

READ - AP

BANK m

WR - BANK n

BANK m,

COL d

CAS Latency = 3 (BANK m)

NOPNOPNOPNOP

RP - BANK n

NOP NOP

OUT

Figure 26

WRITE with AUTO PRECHARGE Interrupted by a READ

T2T1 T4T3 T6T5T0

CLK

COMMAND

WRITE - AP

BANK n

NOP

WRITE - AP

BANK m

NOPNOPNOPNOP

RP - BANK m

OUT

d + 1

NOP

BANK n

Internal States

BANK m

ADDRESS

NOTE: 1. DQM is LOW.

Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge

WR - BANK n

Page Active WRITE with Burst of 4

BANK n,

COL a

a + 1

a + 2

BANK m,

COL d

d + 1

RP - BANK n

d + 2

WR - BANK m

Write-Back

d + 3

DON’T CARE

Figure 27

WRITE with AUTO PRECHARGE Interrupted by a WRITE

TRUTH TABLE 2 – CKE

(Notes: 1-4)

16Mb: x16

IT SDRAM

CKE

n-1

CKE

CURRENT STATE COMMAND

ACTION

L L Power-Down X Maintain Power-Down

Self Refresh X Maintain Self Refresh

Clock Suspend X Maintain Clock Suspend

L H Power-Down COMMAND INHIBIT or NOP Exit Power-Down 5

Self Refresh COMMAND INHIBIT or NOP Exit Self Refresh 6

Clock Suspend X Exit Clock Suspend 7

H L All Banks Idle COMMAND INHIBIT or NOP Power-Down Entry

All Banks Idle AUTO REFRESH Self Refresh Entry

Reading or Writing VALID Clock Suspend Entry

H H See Truth Table 3

NOTE: 1. CKE

2. Current state is the state of the SDRAM immediately prior to clock edge n.

3. COMMANDn is the command registered at clock edge n and ACTIONn is a result of COMMANDn.

4. All states and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided

6. Exiting SELF REFRESH at clock edge n will put the device in the all banks idle state once tXSR is met. COMMAND

7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock

is the logic state of CKE at clock edge n; CKE

that tCKS is met).

INHIBIT or NOP commands should be issued on any clock edges occurring during the tXSR period. A minimum of two NOP commands must be provided during

edge n + 1.

XSR period.

was the state of CKE at the previous clock edge.

n-1

NOTES

16Mb: x16

IT SDRAM

TRUTH TABLE 3 – CURRENT STATE BANK n - COMMAND TO BANK n

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)

L H H H NO OPERATION (NOP/Continue previous operation)

L L H H ACTIVE (Select and activate row)

Idle L L L H AUTO REFRESH 7

LLLLLOAD MODE REGISTER 7

L L H L PRECHARGE 11

L H L H READ (Select column and start READ burst) 10

Row Active L H L L WRITE (Select column and start WRITE burst) 10

L L H L PRECHARGE (Deactivate row in bank or banks) 8

Read L H L H READ (Select column and start new READ burst) 10

(Auto L H L L WRITE (Select column and start WRITE burst) 10

Precharge L L H L PRECHARGE (Truncate READ burst, start PRECHARGE) 8

Disabled) L H H L BURST TERMINATE 9

Write L H L H READ (Select column and start READ burst) 10

(Auto L H L L WRITE (Select column and start new WRITE burst) 10

Precharge L L H L PRECHARGE (Truncate WRITE burst, start PRECHARGE) 8

Disabled) L H H L BURST TERMINATE 9

NOTE: 1. This table applies when CKE

met (if the previous state was self refresh).

2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged and tRP has been met.

Row Active: A row in the bank has been activated and tRCD has been met. No data bursts/accesses and no

Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated

or been terminated.

Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated

or been terminated.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP commands, or allowable commands to the other bank, should be issued on any clock edge occuring during these states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to Truth Table 4.

Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met,

the bank will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met,

the bank will be in the row active state.

Read w/Auto

Precharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled and ends when tRP

has been met. Once tRP is met, the bank will be in the idle state.

Write w/Auto

Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends when

RP has been met. Once tRP is met, the bank will be in the idle state.

was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been

n-1

16Mb: x16

IT SDRAM

NOTE (continued):

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands must be applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when

met, the SDRAM will be in the all banks idle state.

Accessing Mode

met. Once tMRD is met, the SDRAM will be in the all banks idle state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is

met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.

10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with AUTO PRECHARGE enabled and READs or WRITEs with AUTO PRECHARGE disabled.

11. Does not affect the state of the bank and acts as a NOP to that bank.

RC is met. Once tRC is

MRD has been

16Mb: x16

IT SDRAM

TRUTH TABLE 4 – CURRENT STATE BANK n - COMMAND TO BANK m

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION) NOTES

Any H X X X COMMAND INHIBIT (NOP/Continue previous operation)

L H H H NO OPERATION (NOP/Continue previous operation)

Idle XXXXAny command otherwise allowed to bank m

Row Activating, L L H H ACTIVE (Select and activate row)

Active or L H L H READ (Select column and start READ burst) 7

Precharging L H L L WRITE (Select column and start WRITE burst) 7

L L H L PRECHARGE

Read L L H H ACTIVE (Select and activate row)

(Auto L H L H READ (Select column and start new READ burst) 7, 10

Precharge L H L L WRITE (Select column and start WRITE burst) 7, 11

Disabled) L L H L PRECHARGE 9

Write L L H H ACTIVE (Select and activate row)

(Auto L H L H READ (Select column and start READ burst) 7, 12

Precharge L H L L WRITE (Select column and start new WRITE burst) 7, 13

Disabled) L L H L PRECHARGE 9

Read L L H H ACTIVE (Select and activate row)

(With Auto L H L H READ (Select column and start new READ burst) 7, 8, 14

Precharge) L H L L WRITE (Select column and start WRITE burst) 7, 8, 15

L L H L PRECHARGE 9

Write L L H H ACTIVE (Select and activate row)

(With Auto L H L H READ (Select column and start READ burst) 7, 8, 16

Precharge) L H L L WRITE (Select column and start new WRITE burst) 7, 8, 17

L L H L PRECHARGE 9

NOTE: 1. This table applies when CKE

met (if the previous state was self refresh).

2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged and tRP has been met.

Row Active: A row in the bank has been activated and tRCD has been met. No data bursts/accesses and no

Read: A READ burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated

Write: A WRITE burst has been initiated, with AUTO PRECHARGE disabled, and has not yet terminated

Read w/Auto

Precharge Enabled: Starts with registration of a READ command with AUTO PRECHARGE enabled and ends when tRP

Write w/Auto

Precharge Enabled: Starts with registration of a WRITE command with AUTO PRECHARGE enabled and ends when

was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSR has been

n-1

or been terminated.

has been met. Once tRP is met, the bank will be in the idle state.

RP has been met. Once tRP is met, the bank will be in the idle state.

16Mb: x16

IT SDRAM

NOTE (continued):

4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with AUTO PRECHARGE enabled and READs or WRITEs with AUTO PRECHARGE disabled.

8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO PRECHARGE command when its burst has been interrupted by bank m’s burst.

9. Burst in bank n continues as initiated.

10. For a READ without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the READ on bank n, CAS latency later (Figure 7).

11. For a READ without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the WRITE command to prevent bus contention.

12. For a WRITE without AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.

13. For a WRITE without AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.

14. For a READ with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is registered (Figure 24).

15. For a READ with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).

16. For a WRITE with AUTO PRECHARGE interrupted by a READ (with or without AUTO PRECHARGE), the READ to bank m will interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the READ to bank m is registered. The last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m (Figure 26).

17. For a WRITE with AUTO PRECHARGE interrupted by a WRITE (with or without AUTO PRECHARGE), the WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after tWR is met, where tWR begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior to the WRITE to bank m (Figure 27).

16Mb: x16

IT SDRAM

ABSOLUTE MAXIMUM RATINGS*

Voltage on VDD, VDDQ Supply

Relative to VSS ................................ -1V to +4.6V

Voltage on Inputs, NC or I/O Pins

Relative to V Operating Temperature, T

Storage Temperature (plastic) .......... -55°C to +150°C

Power Dissipation .................................................. 1W

SS ................................ -1V to +4.6V

(ambient) -40°C to +85°C

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1, 6) (-40°C ≤ TA ≤ +85°C; VDD, VDDQ = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL MIN M AX UNITS NOTES

SUPPLY VOLTAGE VDD, VDDQ 3 3.6 V

INPUT HIGH VOLTAGE: Logic 1; All inputs VIH 2.2 VDD + 0.3 V 22

INPUT LOW VOLTAGE: Logic 0; All inputs VIL -0.3 0.8 V 22

INPUT LEAKAGE CURRENT: Any input 0V ≤ VIN ≤ VDD II -5 5 µA (All other pins not under test = 0V)

OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V ≤ VOUT ≤ VDDQIOZ -10 10 µA

OUTPUT LEVELS: VOH 2.4 – V Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) VOL – 0.4 V

IDD SPECIFICATIONS AND CONDITIONS

(Notes: 1, 6, 11, 13) (-40°C ≤ TA ≤ +85°C; VDD, VDDQ = +3.3V ±0.3V)

PARAMETER/CONDITION SYMBOL -6 -7 -8A UNITS NOTES

OPERATING CURRENT: Active Mode; IDD1 145 140 135 mA 3, 18, Burst = 2; READ or WRITE; tRC = tRC (MIN); 19, 26 CAS latency = 3

STANDBY CURRENT: Power-Down Mode; IDD2 222mA26 CKE = LOW; All banks idle

STANDBY CURRENT: Active Mode; CS# = HIGH; IDD3 45 40 35 mA 3, 12, CKE = HIGH; All banks active after tRCD met; 19, 26 No accesses in progress

OPERATING CURRENT: Burst Mode; Continuous burst; IDD4 140 130 100 mA 3, 18, READ or WRITE; All banks active, CAS latency = 3 19, 26

AUTO REFRESH CURRENT: tRC = 15.625µs; CAS latency = 3; IDD5 45 40 35 m A 3, 12, CS# = HIGH; CKE = HIGH 18, 19,

SELF REFRESH CURRENT: CKE ≤ 0.2V IDD6 111mA4

MAX

16Mb: x16

IT SDRAM

CAPACITANCE

PARAMETER SYMBOL MIN MAX UNITS NOTES

Input Capacitance: CLK CI1 2.5 4.0 p F 2

Input Capacitance: All other input-only pins CI2 2.5 5.0 p F 2

Input/Output Capacitance: DQs CIO 4.0 6.5 pF 2

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 5, 6, 8, 9, 11) (-40°C ≤ TA ≤ +85°C)

AC CHARACTERISTICS -6 -7 -8A PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

Access time from CLK (pos. edge) CL = 3

CL = 2

CL = 1 Address hold time Address setup time CLK high level width CLK low level width Clock cycle time CL = 3

CL = 2

CL = 1 CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time CL = 3

CL = 2

CL = 1 Data-out low-impedance time Data-out hold time ACTIVE to PRECHARGE command AUTO REFRESH, ACTIVE command period AUTO REFRESH period ACTIVE to READ or WRITE delay Refresh period - 2,048 or 4,096 rows PRECHARGE command period ACTIVE bank A to ACTIVE bank B command Transition time WRITE recovery time

Exit SELF REFRESH to ACTIVE command

AC 5.5 5.5 6 ns

AC 8 8.5 9 ns 22

AC 18 22 22 ns 22

AH 1 1 1 n s

AS 2 2 2 ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK 6 7 8 ns 23

CK 8 10 13 ns 22, 23

CK 20 25 25 ns 23

CKH 1 1 1 ns

CKS 2 2 2 ns

CMH 1 1 1 ns

CMS 2 2 2 ns

DH 1 1 1 n s

DS 2 2 2 ns

HZ 5.5 5.5 6 ns 10

HZ 6 8.5 9 ns 10

HZ 18 22 22 ns 10

LZ 1 1 1 ns

OH 1.5 1.5 1.5 ns

RAS 42 120,000 42 120,000 48 120,000 ns

RC 60 70 80 ns 22

RCAR 66 70 80 ns

RCD 18 20 24 ns 22

REF 64 64 64 ms

RP 18 21 24 ns 22

RRD 12 14 16 ns

T 0.3 1.2 0.3 1.2 0.3 10 ns 7

WR 1 + 4ns 1 + 3ns 1 + 2ns

CK 24

10 10 10 ns 25

XSR 80 80 80 ns 20

AC FUNCTIONAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 11) (-40°C ≤ TA ≤ +85°C)

16Mb: x16

IT SDRAM

PARAMETER SYMBOL -6 -7 -8A UNITS NOTES

READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode

CCD 1 1 1

CKED 1 1 1

PED 1 1 1

CK 17

CK 14

CK 14 DQM to input data delay tDQD000tCK 17 DQM to data mask during WRITEs tDQM 0 0 0 DQM to data high-impedance during READs tDQZ 2 2 2 WRITE command to input data delay tDWD 0 0 0 Data-in to ACTIVE command CL = 3

CL = 2

CL = 1 Data-in to PRECHARGE Last data-in to burst STOP command Last data-in to new READ/WRITE command Last data-in to PRECHARGE command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from PRECHARGE command CL = 3

CL = 2

CL = 1

DAL 5 5 5

DAL 4 4 4

DAL 3 3 3

DPL 2 2 2

BDL000tCK 17

CDL111tCK 17

RDL111tCK 16, 21

MRD 2 2 2

ROH 3 3 3

ROH 2 2 2

ROH 1 1 1

CK 17

CK 15, 21

CK 16

CK 26

CK 17

NOTES

1. All voltages referenced to VSS.

2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, tA = 25°C.

DD is dependent on output loading and cycle

3. I rates. Specified values are obtained with minimum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.

5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (-40°C ≤ TA ≤ +85°C) is ensured.

6. An initial pause of 100µs is required after powerup, followed by two AUTO REFRESH commands, before proper device operation is ensured. (V

and VDDQ must be powered up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded.

7. AC characteristics assume tT = 1ns.

8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner.

9. Outputs measured at 1.5V with equivalent load:

30pF

10.tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet

OH before going High-Z.

11. AC timing and IDD tests have VIL = 0V and VIH = 3V with timing referenced to 1.5V crossover point.

16Mb: x16

IT SDRAM

12.Other input signals are allowed to transition no more than once in any two-clock period and are otherwise at valid VIH or VIL levels.

DD specifications are tested after the device is

13.I properly initialized.

14.Timing actually specified by specified as a reference only at minimum cycle rate.

15.Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate.

16.Timing actually specified by

17.Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter.

18.The I

DD current will decrease as the CAS latency is

reduced. This is due to the fact that the maximum cycle rate is slower as the CAS latency is reduced.

19.Address transitions average one transition every two-clock period.

20. CLK must be toggled a minimum of two times during this period.

21. Based on tCK = 166 MHz for -6, 143 MHz for -7 and 125 MHz for -8A.

22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 3ns. The pulse width cannot be greater than one third of the cycle rate.

23.The clock frequency must remain constant during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate.

24.Auto precharge mode only.

25.Precharge mode only.

26.tCK = 6ns for -6, 7ns for -7, 8ns for -8A.

CKS; clock(s)

WR.

INITIALIZE AND LOAD MODE REGISTER

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM

ADDRESS

T0 T1 Tn + 1 To + 1 Tp + 1 Tp + 2 Tp + 3

()(

)

CKH

CKS

()(

)

()(

)

CMH

()(

)

NOP

()(

)

()(

)

()(

)

()(

)

()(

)

High-Z

()(

)

PRECHARGE

T=100µs

(MIN)

CMS

BANK(S)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

AUTO

REFRESH

Power-up: VDD and CLK stable.

Precharge all banks.

AUTO REFRESH

RCAR

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

NOP

AUTO

REFRESH

AUTO REFRESH

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

LOAD MODE

CODE

MRD

NOP

Program Mode Register.

ACTIVENOP NOPNOP

BANK,

ROW

2, 3

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

CK (1) 20 25 25 ns

CKH 1 1 1 ns

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CKS 2 2 2 ns

CMH111ns

CMS 2 2 2 ns

MRD222tCK

RC 60 70 80 n s

RCAR 66 70 80 ns

RP 18 21 24 n s

*CAS latency indicated in parentheses.

NOTE: 1. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

2. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.

3. Outputs are guaranteed High-Z after command is issued.

-6 -7 -8A

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM

ADDRESS

Precharge all active banks.

POWER-DOWN MODE

T0 T1 T2 Tn + 1 Tn + 2

CKH

CKS

CMH

CMS

PRECHARGE NOP NOP ACTIVENOP

BANK(S)

High-Z

Two clock cycles

CKS

Input buffers gated off while in

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

CKS

power-down mode. All banks idle, enter power-down mode.

Exit power-down mode.

All banks idle.

BANK,

ROW

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CK (1) 20 25 25 ns

CKH 1 1 1 ns

CKS 2 2 2 ns

CMH111ns

CMS 2 2 2 ns

*CAS latency indicated in parentheses.

NOTE: 1. Violating refresh requirements during power-down may result in loss of data.

2. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

-6 -7 -8A

DON’T CARE

UNDEFINED

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM

A0-A9

A10

CLOCK SUSPEND MODE

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9

CKS

CMS

COLUMN m

(A0 - A7)

BANK

CKH

CMH

CMS

CMH

CKStCKH

OUT

m + 1

NOPNOP NOP NOPNOPREAD WRITE

COLUMN e

(A0 - A7)

BANK

DIN e

NOP

DIN e + 1

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AC (3) 5.5 5.5 6 ns

AC (2) 8 8.5 9 ns

AC (1) 18 22 22 ns

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

CK (1) 20 25 25 ns

CKH 1 1 1 ns

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CKS 2 2 2 ns

CMH111ns

CMS 2 2 2 ns

DH111ns

DS222ns

HZ (3) 5.5 5.5 6 ns

HZ (2) 6 8.5 9 ns

HZ (1) 18 22 22 ns

LZ111ns

OH 1.5 1.5 1.5 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled.

2. A8 and A9 = “Don’t Care.”

3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

-6 -7 -8A

AUTO REFRESH MODE

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM

ADDRESS

T0 T1 T2 Tn + 1 To + 1

CKH

CKS

CMH

CMS

NOP

BANK(S)

High-Z

AUTO

REFRESH

RCAR

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

AUTO

REFRESH

()(

)

()(

)

()(

)

()(

)

NOPNOP

NOPNOPPRECHARGE

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

ACTIVE

BANK,

ROW

Precharge all

active banks.

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

CK (1) 20 25 25 ns

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CKH 1 1 1 ns

CKS 2 2 2 ns

CMH111ns

CMS 2 2 2 ns

RC 60 70 80 n s

RCAR 66 70 80 ns

RP 18 21 24 n s

*CAS latency indicated in parentheses.

NOTE: 1. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

-6 -7 -8A

DON’T CARE

UNDEFINED

SELF REFRESH MODE

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM

ADDRESS

T0 T1 T2 Tn + 1 To + 1 To + 2

CKH

CKS

CMH

CMS

PRECHARGE NOP NOP

CKS

AUTO

REFRESH

> t

RAS

BANK(S)

High-Z

Precharge all active banks.

Enter self

refresh mode.

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

XSR

()(

)

()(

)

()(

)

()(

)

CKS

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

Exit self refresh mode.

(Restart refresh time base.)

CLK stable prior to exiting

self refresh mode.

AUTO

REFRESH

DON’T CARE

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

CK (1) 20 25 25 ns

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CKH 1 1 1 ns

CKS 2 2 2 ns

CMH111ns

CMS 2 2 2 ns

RAS 42 120,000 42 120,000 48 120,000 ns

RP 18 21 24 n s

XS R 80 80 80 n s

*CAS latency indicated in parentheses.

NOTE: 1. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

-6 -7 -8A

UNDEFINED

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM /

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

SINGLE READ – WITHOUT AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8

CKS

CMS

ACTIVE NOP READ ACTIVE NOP

ROW

BANK

CKH

CMH

RCD

RAS

CMS

COLUMN m

DISABLE AUTO PRECHARGE

BANK

CMH

CAS Latency

PRECHARGE

ALL BANKS

SINGLE BANKS

BANK(S)

NOPNOP

DOUT m

NOP

ROW

BANK

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AC (3) 5.5 5.5 6 ns

AC (2) 8 8.5 9 ns

AC (1) 18 22 22 ns

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

CK (1) 20 25 25 ns

CKH 1 1 1 ns

CKS 2 2 2 ns

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CMH111ns

CMS 2 2 2 ns

HZ (3) 5.5 5.5 6 ns

HZ (2) 6 8.5 9 ns

HZ (1) 18 22 22 ns

LZ111ns

OH 1.5 1.5 1.5 ns

RAS 42 120,000 42 120,000 48 120,000 ns

RC 60 70 80 n s

R CD 18 20 24 n s

RP 18 21 24 n s

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.

2. A8, A9 = “Don’t Care.”

-6 -7 -8A

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM

A0-A9

A10

READ – WITHOUT AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8

CKS

CMS

ROW

BANK

CKH

CMH

RCD CAS Latency

RAS

CMS

COLUMN m

DISABLE AUTO PRECHARGE

CMH

(A0 - A7)

BANK BANK(S) BANK

NOPNOP NOPACTIVE NOP READ NOP ACTIVE

OUT

m+1

PRECHARGE

BANK 0 and 1

BANK 0 or 1

OUT

m+2D

OUT

m+3

ROW

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AC (3) 5.5 5.5 6 ns

AC (2) 8 8.5 9 ns

AC (1) 18 22 22 ns

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

CK (1) 20 25 25 ns

CKH 1 1 1 ns

CKS 2 2 2 ns

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CMH111ns

CMS 2 2 2 ns

HZ (3) 5.5 5.5 6 ns

HZ (2) 6 8.5 9 ns

HZ (1) 18 22 22 ns

LZ111ns

OH 1.5 1.5 1.5 ns

RAS 42 120,000 42 120,000 48 120,000 ns

RC 60 70 80 n s

R CD 18 20 24 n s

RP 18 21 24 n s

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.

2. A8 and A9 = “Don’t Care.”

3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

-6 -7 -8A

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM

A0-A9

A10

READ – WITH AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8

CKS

CMS

ROW

BANK

CKH

CMH

RCD CAS Latency

RAS

CMS

COLUMN

(A0 - A7)

ENABLE AUTO PRECHARGE

CMH

BANK

NOPNOP NOPACTIVE NOP READ NOP ACTIVENOP

OUT

DOUT m + 2DOUT m + 1

DOUTm + 3

ROW

BANK

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AC (3) 5.5 5.5 6 ns

AC (2) 8 8.5 9 ns

AC (1) 18 22 22 ns

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

CK (1) 20 25 25 ns

CKH 1 1 1 ns

CKS 2 2 2 ns

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CMH111ns

CMS 2 2 2 ns

HZ (3) 5.5 5.5 6 ns

HZ (2) 6 8.5 9 ns

HZ (1) 18 22 22 ns

LZ111ns

OH 1.5 1.5 1.5 ns

RAS 42 120,000 42 120,000 48 120,000 ns

RC 60 70 80 n s

R CD 18 20 24 n s

RP 18 21 24 n s

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a “manual” PRECHARGE.

2. A8 and A9 = “Don’t Care.”

3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

-6 -7 -8A

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM

A0-A9

A10

ALTERNATING BANK READ ACCESSES

T0 T1 T2 T3 T4 T5 T6 T7 T8

CKS

CMS

ROW

BANK 0 BANK 0 BANK 1 BANK 1

CKH

CMH

RCD - BANK 0

RAS - BANK 0

RC - BANK 0

RRD

CMS

COLUMN m

ENABLE AUTO PRECHARGE

CMH

(A0 - A7)

CAS Latency - BANK 0

NOP NOPACTIVE NOP READ NOP ACTIVE

ACTIVE

ROW

OUT

RCD - BANK 1

ENABLE AUTO PRECHARGE

OUT

m + 1

READ

COLUMN b

(A0 - A7)

OUT

m + 2D

CAS Latency - BANK 1

OUT

RP - BANK 0

m + 3

ROW

BANK 0

OUT

RCD - BANK 0

DON’T CARE

UNDEFINED

TIMING PARAMETERS

-6 -7 - 8A

SYMBOL* MI N MAX MIN M AX M IN M AX UNITS

AC (3) 5.5 5.5 6 ns

AC (2) 8 8.5 9 ns

AC (1) 1 8 2 2 2 2 ns

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 1 3 n s

CK (1) 20 25 2 5 n s

CKH 1 1 1 ns

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CKS 2 2 2 ns

CMH 1 1 1 ns

CMS 2 2 2 ns

LZ111ns

OH 1.5 1.5 1.5 ns

RAS 42 120,000 42 120,000 48 120,000 ns

RC 60 70 80 ns

RCD 18 20 24 ns

RP 18 21 24 ns

RRD 12 14 16 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.

2. A8 and A9 = “Don’t Care.”

3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

-6 -7 -8A

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM

A0-A9

A10

READ – FULL-PAGE BURST

T0 T1 T2 T3 T4 T5 T6 Tn + 1 Tn + 2 Tn + 3 Tn + 4

CKS

CMS

ROW

BANK

CKH

CMH

NOPNOP NOPACTIVE NOP READ NOP BURST TERMNOP NOP

CMH

CMS

COLUMN m

(A0 - A7)

BANK

OUT

m+1

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

OUT

m+2

()(

)

OUT

m-1

OUT

NOP

OUT

256 locations within same row.

m+1

RCD

CAS Latency

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AC (3) 5.5 5.5 6 ns

AC (2) 8 8.5 9 ns

AC (1) 18 22 22 ns

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

CK (1) 20 25 25 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the CAS latency = 2.

2. A8 and A9 = “Don’t Care.”

3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

4. Page left open; no tRP.

Full page completed.

Full-page burst does not self-terminate.

Can use BURST TERMINATE command.

DON’T CARE

UNDEFINED

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CKH 1 1 1 ns

CKS 2 2 2 ns

CMH111ns

CMS 2 2 2 ns

HZ (3) 5.5 5.5 6 ns

HZ (2) 6 8.5 9 ns

HZ (1) 18 22 22 ns

LZ111ns

OH 1.5 1.5 1.5 ns

R CD 18 20 24 n s

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM

A0-A9

A10

READ – DQM OPERATION

T0 T1 T2 T3 T4 T5 T6 T7 T8

CKS

CMStCMH

ROW

BANK

CKH

RCD

CMS

COLUMN m

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

CMH

(A0 - A7)

BANK

CAS Latency

NOPNOP NOPACTIVE NOP READ NOPNOP NOP

OUT

m + 2

OUT

m + 3D

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AC (3) 5.5 5.5 6 ns

AC (2) 8 8.5 9 ns

AC (1) 18 22 22 ns

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

CK (1) 20 25 25 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.

2. A8 and A9 = “Don’t Care.”

3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CKH 1 1 1 ns

CKS 2 2 2 ns

CMH111ns

CMS 2 2 2 ns

HZ (3) 5.5 5.5 6 ns

HZ (2) 6 8.5 9 ns

HZ (1) 18 22 22 ns

LZ111ns

OH 1.5 1.5 1.5 ns

R CD 18 20 24 n s

DON’T CARE

UNDEFINED

-6 -7 -8A

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM /

DQML, DQMH

A0-A9, A11

A10

BA0, BA1

SINGLE WRITE – WITHOUT AUTO PRECHARGE

T0 T1 T2 T4T3 T5 T6

CKS

CMS

ACTIVE NOP WRITE NOP PRECHARGE ACTIVE

ROW

BANK

CKH

CMH

CMS

CMH

COLUMN m

DISABLE AUTO PRECHARGE

BANK BANK BANK

ALL BANKS

SINGLE BANK

NOP

DIN m

RCD

RAS

ROW

DON’T CARE

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

CK (1) 20 25 25 ns

CKH 1 1 1 ns

CKS 2 2 2 ns

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CMH111ns

CMS 2 2 2 ns

DH111ns

DS222ns

RAS 42 120,000 42 120,000 48 120,000 ns

RC 60 70 80 n s

R CD 18 20 24 n s

RP 18 21 24 n s

WR 10 10 10 n s

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a “manual” PRECHARGE.

2. 10ns is required between <DIN m> and the PRECHARGE command, regardless of frequency, to meet tWR.

3. A8, A9 = “Don’t Care.”

-6 -7 -8A

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM

A0-A9

A10

BANK 0 and 1

BANK 0 or 1

WRITE – WITHOUT AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8

CKS

CMH

CMS

ROW

BANK

CKH

RCD

RAS

NOPNOP NOPACTIVE NOP WRITE NOPPRECHARGE ACTIVE

CMH

CMS

COLUMN

(A0 - A7)

DISABLE AUTO PRECHARGE

BANK BANK(S) BANK

DIN m

DIN m + 1 DIN m + 2 DIN m + 3

ROW

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

CK (1) 20 25 25 ns

CKH 1 1 1 ns

CKS 2 2 2 ns

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CMH111ns

CMS 2 2 2 ns

DH111ns

DS222ns

RAS 42 120,000 42 120,000 48 120,000 ns

RC 60 70 80 n s

R CD 18 20 24 n s

RP 18 21 24 n s

WR 10 10 10 n s

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by “manual” PRECHARGE.

2. A8 and A9 = “Don’t Care.”

3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

4. Faster frequencies will require two clocks (when tWR > tCK).

-6 -7 -8A

DON’T CARE

UNDEFINED

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM

A0-A9

A10

WRITE – WITH AUTO PRECHARGE

T0 T1 T2 T3 T4 T5 T6 T7 T8

CKS

CMS

ROW

BANK

CKH

CMH

RCD

RAS

NOPNOP NOPACTIVE NOP WRITE NOPNOP ACTIVE

CMH

CMS

COLUMN

(A0 - A7)

ENABLE AUTO PRECHARGE

BANK BANK

DIN m

m + 1 D

m + 2 D

m + 3

ROW

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

CK (1) 20 25 25 ns

CKH 1 1 1 ns

CKS 2 2 2 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4.

2. A8 and A9 = “Don’t Care.”

3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

4. Faster frequencies will require two clocks (when

WR > tCK).

DON’T CARE

UNDEFINED

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CMH111ns

CMS 2 2 2 ns

DH111ns

DS222ns

RAS 42 120,000 42 120,000 48 120,000 ns

RC 60 70 80 n s

R CD 18 20 24 n s

RP 18 21 24 n s

WR 1 + 4ns 1 + 3ns 1 + 2ns

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM

A0-A9

A10

COLUMN b

(A0 - A7)

BANK 1

DIN b

DIN b + 1 DIN b + 2

RP - BANK 0

ALTERNATING BANK WRITE ACCESSES

T0 T1 T2 T3 T4 T5 T6 T7 T8

CKS

CMS

CMH

ROW

BANK 0 BANK 0 BANK 1

CKH

RCD - BANK 0

RAS - BANK 0

RC - BANK 0

RRD

CMS

CMH

COLUMN m

(A0 - A7)

ENABLE AUTO PRECHARGE

DIN m

NOP NOPACTIVE NOP WRITE NOP ACTIVE

DIN m + 1 DIN m + 2 DIN m + 3

ACTIVE WRITE

ROW

ENABLE AUTO PRECHARGE

ROW

RCD - BANK 1

WR - BANK 0

ROW

BANK 0

RCD - BANK 0

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

CK (1) 20 25 25 ns

CKH 1 1 1 ns

CKS 2 2 2 ns

CMH111ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4.

2. A8 and A9 = “Don’t Care.”

3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

4. Faster frequencies will require two clocks (when

WR > tCK).

DON’T CARE

UNDEFINED

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CMS 2 2 2 ns

DH111ns

DS222ns

RAS 42 120,000 42 120,000 48 120,000 ns

RC 60 70 80 n s

R CD 18 20 24 n s

RP 18 21 24 n s

R RD 12 14 16 n s

WR 1 + 4ns 1 + 3ns 1 + 2ns

WRITE – FULL-PAGE BURST

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM

A0-A9

A10

T0 T1 T2 T3 T4 T5 Tn + 1 Tn + 2 Tn + 3

CKS

CMStCMH

ROW

BANK

CKH

RCD

CMS

COLUMN m

(A0 - A7)

CMH

BANK

DIN m

NOPNOP NOPACTIVE NOP WRITE BURST TERMNOP NOP

DIN m + 1 DIN m + 2 DIN m + 3

256 locations within

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

()(

)

DIN m - 1

()(

)

same row.

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

CK (1) 20 25 25 ns

*CAS latency indicated in parentheses.

NOTE: 1. A8 and A9 = “Don’t Care.”

2. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

3. Page left open; no tRP.

Full page completed.

Full-page burst does not

self-terminate. Can use

BURST TERMINATE command.

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CKH 1 1 1 ns

CKS 2 2 2 ns

CMH111ns

CMS 2 2 2 ns

DH111ns

DS222ns

R CD 18 20 24 n s

DON’T CARE

UNDEFINED

16Mb: x16

IT SDRAM

CLK

CKE

COMMAND

DQM

A0-A9

A10

DIN m + 3

WRITE – DQM OPERATION

T0 T1 T2 T3 T4 T5 T6 T7

CKH

CKS

CMH

CMS

ROW

BANK

CMH

CMS

COLUMN m

(A0 - A7)

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

DIN m

NOPNOP NOPACTIVE NOP WRITE NOPNOP

DIN m + 2

RCD

TIMING PARAMETERS

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

AH111ns

AS222ns

CH 2.5 2.75 3 ns

CL 2.5 2.75 3 ns

CK (3) 6 7 8 ns

CK (2) 8 10 13 ns

CK (1) 20 25 25 ns

*CAS latency indicated in parentheses.

NOTE: 1. For this example, the burst length = 4.

2. A8 and A9 = “Don’t Care.”

3. DQM represents DQML and DQMH. DQML controls the lower byte, and DQMH controls the upper byte.

DON’T CARE

UNDEFINED

-6 -7 -8A

SYMBOL* MIN MAX MIN MAX MIN MAX UNITS

CKH 1 1 1 ns

CKS 2 2 2 ns

CMH111ns

CMS 2 2 2 ns

DH111ns

DS222ns

R CD 18 20 24 n s

16Mb: x16

IT SDRAM

50-PIN PLASTIC TSOP (400 mil)

C-4

21.04

20.88

0.88

0.10 (2X)

2.80

10.21

10.11

125

0.80

PIN #1 ID

TYP

R 1.00 (2X)

NOTE: 1. All dimensions in millimeters

R 0.75 (2X)

MAX

or typical where noted.

MIN

0.45

0.30

1.2

11.86

11.66

0.10

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.01" per side.

0.25

GAGE PLANE

0.60

0.40

SEE DETAIL A

0.18

0.13

0.80 TYP

0.25

0.05

DETAIL A

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark of Micron Technology, Inc.

Micron MT48LC1M16A1 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual