MICRON MT46V4M32V1FK-5, MT46V4M32V1LG-33, MT46V4M32V1LG-4, MT46V4M32V1LG-5, MT46V4M32LG-4 Datasheet

...

128Mb: x32

DDR SDRAM

ADVANCE

‡

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PUROPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.

DOUBLE DATA RATE (DDR) SDRAM

MT46V4M32 - 1 Meg x 32 x 4 banks

For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/dramds

PIN ASSIGNMENT (TOP VIEW)

FEATURES

•VDD = +2.5V ±0.125V, VDDQ = +2.5V ±0.125V

• Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture

• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle

• Reduced and matched output drive options

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; centeraligned with data for WRITEs

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask (DM) for masking write data

• Programmable burst lengths: 2, 4, 8, or full page

• 32ms, 4,096-cycle auto refresh

• Auto precharge option

• Auto Refresh and Self Refresh Modes

• 2.5V I/O (SSTL_2 compatible)

• DQS per byte on the FBGA package

• 1.8V VDDQ option for FBGA package

•tRAS lockout

OPTIONS MARKING

• Configuration 4 Meg x 32 (1 Meg x 32 x 4 banks) 4M32

• IO Voltage

2.5V VDDQ None

1.8V VDDQV1

• Plastic Packages 100-pin TQFP (0.65mm lead pitch) LG 12mm x 12mm FBGA FK

• Timing - Cycle Time 300 MHz @ CL = 5 -33

250 MHz @ CL = 4 -4

200 MHz @ CL = 3 -5

Note: 1. -4 and -33 speed grades are only available in the FBGA package

DQ2

SSQ

DQ1

DQ0

VDDQ

DQS

NC \ RFU

SSQ

DNUNCNCNCNC

DDQVSS

DQ31

DQ30

SSQ

DQ29

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

31 3233 3435 36 38 3940 4142 4337 45 4647 4849 5044

10099 9897 96 9594 939291 90 89 8887 86 858483 82 81

DQ28 V

DDQ

DQ27 DQ26 V

SSQ

DQ25 DQ24 V

DDQ

DQ15 DQ14 V

SSQ

DQ13 DQ12 V

DDQ

VDD DQ11 DQ10 V

SSQ

DQ9 DQ8 V

DDQ

REF

DM3 DM1 CK CK# CKE NC/MCL A8/AP

A0A1A2

A10

A11

NCNCNCNCNCNCNC

A4A5A6

DQ3

DDQ

DQ4 DQ5

SSQ

DQ6 DQ7

DDQ

DQ16 DQ17

SSQ

DQ18 DQ19 V

DDQ

VSS DQ20 DQ21

SSQ

DQ22 DQ23 V

DDQ

DM0 DM2

WE# CAS# RAS#

CS# BA0 BA1

100-Pin TQFP

4 Meg x 32

Configuration 1 Meg x 32 x 4 banks Refresh Count 4K

Row Addressing 4K (A0-A11)

Bank Addressing 4 (BA0, BA1)

Column Addressing 256 (A0-A7)

128Mb (x32) DDR SDRAM PART NUMBER

PART NUMBER ARCHITECTURE

MT46V4M32LG 4 Meg x 32

Part Number Example:

MT46V4M32V1FK-33

KEY TIMING PARAMETERS

SPEED CLOCK RATE DATA-OUT ACCESS DQS-DQ

GRADE C L = 5

CL = 41CL = 31WINDOW2WINDOW SKEW

-33 300 MHz 250 MHz - 0.685ns ±0.6ns +0.40ns

-4 - 250 MHz 200 MHz 0.950ns ±0.7ns +0.45ns

-5 - - 200 MHz 1.400ns ±0.7ns +0.45ns

1. CL = CAS (Read) Latency

2. Minimum clock rate @ max CL

128Mb: x32

DDR SDRAM

ADVANCE

GENERAL DESCRIPTION

The 128Mb (x32) DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728- bits. It is internally configured as a quadbank DRAM.

The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n- prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM effectively consists of a single 2n-bit wide, one-clockcycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs.

The 128Mb DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and

continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access.

The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, 8, or full page locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access.

As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.

An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class I compatible.

NOTE: 1. The functionality and the timing specifications

discussed in this data sheet are for the DLL-enabled mode of operation.

2. Throughout the data sheet, the various figures and text refer to DQs as “DQ.” The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise.

128Mb: x32

DDR SDRAM

ADVANCE

TABLE OF CONTENTS

Functional Block Diagram - 4 Meg x 32 ..................... 4

Pin Descriptions .......................................................... 5

Functional Description ............................................... 7

Initialization ........................................................... 7

Mode Register ................................................... 7

Burst Length ................................................. 8

Burst Type .................................................... 9

Read Latency ............................................... 9

Operating Mode .......................................... 9

Extended Mode Register ................................. 10

DLL Enable/Disable .................................. 10

Commands ................................................................... 1 1

Truth Table 1 (Commands) ............................................ 11

Truth Table 1A (DM Operation) ...................................... 11

Deselect................................................................... 12

No Operation (NOP) .............................................. 12

Load Mode Register ............................................... 12

Active ....................................................................... 12

Read ....................................................................... 12

Write ....................................................................... 12

Precharge ................................................................ 12

Auto Precharge ....................................................... 12

Burst Terminate ..................................................... 12

Auto Refresh ........................................................... 13

Self Refresh ............................................................. 1 3

Operation ..................................................................... 14

Bank/Row Activation ............................................. 14

Reads ....................................................................... 15

Read Burst ......................................................... 16

Consecutive Read Bursts ................................ 17

Nonconsecutive Read Bursts ......................... 1 8

Random Read Accesses ................................... 19

Terminating a Read Burst ............................... 21

Read to Write ..................................................... 22

Read to Precharge ............................................ 23

Writes ....................................................................... 24

Write Burst ......................................................... 25

Consecutive Write to Write ............................... 26

Nonconsecutive Write to Write ........................ 27

Random Write Cycles ...................................... 2 8

Write to Read - Uninterrupting ...................... 29

Write to Read - Interrupting ........................... 30

Write to Read - Odd, Interrupting .................. 31

Write to Precharge - Uninterrupting ............. 32

Write to Precharge - Interrupting .................. 33

Write to Precharge - Odd, Interrupting ......... 34

Precharge ................................................................ 35

Power-Down ........................................................... 35

Truth Table 2 (CKE) ...................................................... 3 6

Truth Table 3 (Current State, Same Bank) ........................ 37

Truth Table 4 (Current State, Different Bank) .................. 39

Operating Conditions

Absolute Maximum Ratings ....................................... 41

DC Electrical Characteristics and Operating

Conditions ............................................................... 41

AC Input Operating Conditions ................................ 41

Clock Input Operating Conditions ........................... 42

DC Electrical Characteristics and Operating

Conditions, 1.8V Option ....................................... 4 3

AC Input Operating Conditions, 1.8V Option ......... 43

Clock Input Operating Conditions, 1.8V Option .... 43

Capacitance .................................................................. 44

DD Specifications and Conditions ................................ 4 4

Electrical Characteristics and Recommended

AC Operating Conditions ..................................... 45

Notes ............................................................................. 46

Derating Data Valid Window ..................................... 47

Voltage and Timing Waveforms

Impedance Match Output.................................... 50

Reduced Output Drive Characteristics .............. 51

Output Timing - tDQSQ and tQH ......................... 52

Output Timing - tAC and tDQSCK ....................... 54

Input Timing .......................................................... 54

Input Voltage .......................................................... 55

Initialize and Load Mode Registers ..................... 56

Power-Down Mode ................................................ 57

Auto Refresh Mode ................................................ 58

Self Refresh Mode .................................................. 59

Reads

Bank Read - Without Auto Precharge ............ 60

Bank Read - With Auto Precharge .................. 61

Writes

Bank Write - Without Auto Precharge ........... 62

Bank Write - With Auto Precharge ................. 63

Write - DM Operation ...................................... 64

100-pin TQFP dimensions .......................................... 65

FBGA Package .............................................................. 66

128Mb: x32

DDR SDRAM

ADVANCE

FUNCTIONAL BLOCK DIAGRAM

4 Meg x 32

RAS#

CAS#

ROW-

ADDRESS

MUX

CS#

WE#

CK#

CONTROL

LOGIC

COLUMNADDRESS COUNTER/

LATCH

MODE REGISTERS

COMMAND

DECODE

A0-A11,

BA0, BA1

CKE

ADDRESS REGISTER

256

(x64)

8,192

I/O GATING

DM MASK LOGIC

COLUMN DECODER

BANK0

MEMORY

ARRAY

(4096 x 256 x 64)

BANK0

ROW-

ADDRESS

LATCH

DECODER

4096

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

BANK1

BANK2

BANK3

REFRESH

COUNTER

CA0

INPUT

REGISTERS

RCVRS

clk out

DATA

DQS

MASK

DATA

CLK

clk in

DRVRS

MUX

DQS

GENERATOR

DQ0 DQ31, DM0 DM3

DQS

READ

LATCH

WRITE

FIFO

DRIVERS

CLK

DLL

128Mb: x32

DDR SDRAM

ADVANCE

PIN DESCRIPTIONS

TQFP PIN NUMBERS SYMBOL TYPE DESCRIPTION

55, 54

CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQs and DQS) is referenced to the crossings of CK and CK#.

CKE Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the

internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied.

CS# Input Chip Select: CS# enables (registered LOW) and disables (registered

HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code.

27, 26, 25

RAS#, CAS#, Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

WE# command being entered.

23, 56, 24, 57

DM0-DM3 Input Input Data Mask: DM is an input mask signal for write data. Input

data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins.

29, 30

BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an

ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

31-34, 47-51, 45, 36, 37

A0-A11 Input Address Inputs: Provide the row address for ACTIVE commands, and

the column address and auto precharge bit (A8) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A8 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A8 LOW, bank selected by BA0, BA1) or all banks (A8 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command.

97, 98, 100, 1, 3, 4, 6, 7 DQ0-7 I/O Data Input/Output:

60, 61, 63, 64, 68, 69, 71, 72 DQ8-15 I/O Data Input/Output:

9, 10, 12, 13, 17, 18, 20, 21 DQ16-23 I/O Data Input/Output:

74, 75, 77, 78, 80, 81, 83, 84 DQ24-31 I/O Data Input/Output:

94 DQS I/O Data Strobe: Output with read data, input with write data. DQS is

edge-aligned with read data, centered in write data. It is used to capture data.

(continued on next page)

128Mb: x32

DDR SDRAM

ADVANCE

38, 39, 40, 41, 42, 43, 44 NC – No Connect: These pins should be left unconnected.

87, 88, 90

91 DNU – Do Not Use: Must float to minimize noise.

93 NC/RFU Reserved for Future Use 52 NC (MCL)

No Connect: Not internally connected. Must Connect LOW (for compatibility with SGRAM devices).

2, 8, 14, 22, 59, 67, 73, VDDQ Supply DQ Power Supply: +2.5V ±0.125V. Isolated on the die for

79, 86, 95 improved noise immunity. 1.8V option

5, 11, 19, 62, 70, 76, VSSQ Supply DQ Ground. Isolated on the die for improved noise immunity.

82, 92, 99

15, 35, 65, 96 VDD Supply Power Supply: +2.5V ±0.125V.

16, 46, 66, 85 VSS Supply Ground.

58 VREF Supply SSTL_2 reference voltage.

PIN DESCRIPTIONS (continued)

TQFP PIN NUMBERS SYMBOL TYPE DESCRIPTION

NOTE: 1. NC pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins

deemed to be of importance.

FBGA BALLOUT

DQS0 DM0 VSSQ

DQ21 DQ10

DQ15DQ16

DQ26V

VDDQVDDQDQ4

DQ3

DM2 DM1DQS2 DQS1

DQ22 DQ8

NC V

QDQ1

DQ6

DQ2A2DQ0

CS#

VDDQ

DQ31

VDDQ DQ30

DQ29

DSF/MCL

DQ24DQ7

DQ28 VSSQ DM3 DQS3

DQ27

DQ5

123456789101112

Q DQ25

VDDQV

VSSQV

A11

A3 A4

A9 A5 CK#

CKE

VSSQ

RFU

CAS#

DQ17 VSSQ DQ14VDDQ

RAS#

DQ19 DQ18 V

VSS/θ

VDDQ

DQ20

DQ23

WE#

BA0

BA1

VSSQ

Q DQ13 DQ12

Q DQ11

Q DQ9

REF

A1 A6 A7 A8/AP

NCNC

RFUV

A10

NOTE: 1. This package uses 4 DQS lines

128Mb: x32

DDR SDRAM

ADVANCE

FUNCTIONAL DESCRIPTION

The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. The 128Mb DDR SDRAM is internally configured as a quad-bank DRAM.

The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n- prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.

Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access.

Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.

Initialization

DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD and VDDQ simultaneously, and then to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied any time after VDDQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to ensure that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to applying an executable command.

Once the 200µs delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be satisfied.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) is recommended by JEDEC specification but is not required by the Micron device. Following these requirements, the DDR SDRAM is ready for normal operation once a value has been written in to the DRAM and it has been refreshed correctly. Read accesses to the DRAM prior to it being written in to the DRAM must be assumed to be unknown and unrepeatable.

MODE REGISTER

The mode register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 1. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing).

Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.

Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A11 specify the operating mode.

128Mb: x32

DDR SDRAM

ADVANCE

Figure 1

Mode Register Definition

Burst Length

Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Full page burst is supported in sequential mode only.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely se-

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst LengthCAS Latency BT0* 0*

A6 A5 A4

A3A8A2A1A0

Mode Register (Mx)

Address Bus

654

38210

M6-M0

Operating Mode

A10A11BA1

BA0

1213

* M13 and M12 (BA0 and BA1)

must be 0, 0 to select the

base mode register (vs. the

extended mode register).

M9M10M11

Order of Accesses Within a Burst

Burst Starting Column

Length Address Type = Sequential Type = Interleaved

0 0-1 0-1 1 1-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full

n = A0 - A7, Cn, Cn+1, Cn+2

Page

A0 = 0 Cn+3, Cn+4...

Not supported

(256)

…Cn-1,

Cn…

n = A0 - A7, Cn, Cn-1, Cn-2

A0 = 1 Cn-3, Cn-4...

Not supported

…Cn+1,

Cn…

Table 1

Burst Definition

NOTE: 1. For a burst length of two, A1-A7 select the block

of two burst; A0 selects the starting column within the block.

2. For a burst length of four, A2-A7 select the block of four burst; A0-A1 select the starting column within the block.

3. For a burst length of eight, A3-A7 select the block of eight burst; A0-A2 select the starting column within the block.

4. For a full-page burst, the full row is selected and A0-A7 select the starting column. A0 also selects the direction of the burst (incrementing if A0 = 0, decrementing if A0 = 1).

5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

128Mb: x32

DDR SDRAM

ADVANCE

lected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 1.

Figure 2

CAS Latency

Read Latency

The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, 3, 4 or 5 clocks, as shown in Figure 2.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 2 indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A11 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER

CK#

COMMAND

DQS

CL = 2

READ NOP NOP NOP

Burst Length = 4 in the cases shown Shown with nominal tAC and nominal tDSDQ

CK#

COMMAND

DQS

CL = 3

T0 T1 T2 T2n T3 T3n

T0 T1 T2 T3 T3n

DON’T CARETRANSITIONING DATA

Table 2

CAS Latency

ALLOWABLE OPERATING

FREQUENCY (MHz)

SPEED CL = 5 CL = 4 CL = 3

-33 ≤ 300 ≤ 250 −

-4 −≤ 250 ≤ 200

-5 −−≤ 200

128Mb: x32

DDR SDRAM

ADVANCE

Figure 3

Extended Mode Register Definition

SET command with bits A7 and A9-A11 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode.

All other combinations of values for A7-A11 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

EXTENDED MODE REGISTER

The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable. These functions are controlled via the bits shown in Figure 3. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. Although not required by the Micron device, the enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. Although not required by Micron, JEDEC recommends a LOAD MODE REGISTER command be issued to the mode register (BA0/BA1 both LOW) to reset the DLL.

Output Drive Strength

The reduced drive strength for all outputs are specified to be SSTL2, Class I. The x32 supports both reduced and matched impedance drive strengths. This option is intended for the support of the lighter load and/or point-topoint environments. The selection of the reduced drive strength will alter the DQs and DQSs from SSTL2, Class I drive strength to a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive strength.

DLL

Enable

Disable

DLL

011

A6 A5 A4

A3A8A2A1A0

Extended Mode Register (Ex)

Address Bus

654

382

Drive Strength

Reserved

Half

Reserved

Matched

A10

A11

BA0

BA1

NOTE: 1. E13 and E12 (BA0 and BA1) must be 1, 0 to select the Extended Mode Register (vs. the base Mode Register).

2. Reserved for future use. Set values to 0.

DSDS

RFU

DLL Enable/Disable

The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued. The DLL must be reset any time the clock frequency is changed followed by 200 clock cycles.

128Mb: x32

DDR SDRAM

ADVANCE

appear following the Operation section; these tables provide current state/next state information.

Commands

Truth Table 1 provides a quick reference of available commands. This is followed by a verbal description of each command. Two additional Truth Tables

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 provide the opcode to be written to the selected mode register.

3. BA0-BA1 provide bank address and A0-A11provide row address.

4. BA0-BA1 provide bank address; A0-A7provide column address; A8 HIGH enables the auto precharge feature (nonpersistent), and A8 LOW disables the auto precharge feature.

5. A8 LOW: BA0-BA1 determine which bank is precharged. A8 HIGH: all banks are precharged and BA0-BA1 are “Don’t Care.”

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.

7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.

8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts.

9. DESELECT and NOP are functionally interchangeable.

10. Used to mask write data; provided coincident with the corresponding data.

TRUTH TABLE 1 – COMMANDS

(Note: 1)

NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES

DESELECT (NOP) H X X X X 9

NO OPERATION (NOP) L H H H X 9

ACTIVE (Select bank and activate row) L L H H Bank/Row 3

READ (Select bank and column, and start READ burst) L H L H Bank/Col 4

WRITE (Select bank and column, and start WRITE burst) L H L L Bank/Col 4

BURST TERMINATE L H H L X 8

PRECHARGE (Deactivate row in bank or banks) L L H L Code 5

AUTO REFRESH or SELF REFRESH L L L H X 6, 7 (Enter self refresh mode)

LOAD MODE REGISTER L L L L Op-Code 2

TRUTH TABLE 1A – DM OPERATION

NAME (FUNCTION) DM DQs NOTES

Write Enable L Valid 10

Write Inhibit HX 10

128Mb: x32

DDR SDRAM

ADVANCE

DESELECT

The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to perform a NOP (CS# LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

LOAD MODE REGISTER

The mode registers are loaded via inputs A0-A11. See mode register descriptions in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until

MRD is met.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active (or open) for accesses until a PRECHARGE command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.

READ

The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A7 selects the starting column location. The value on input A8 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses.

WRITE

The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A7 selects the starting column location. The value on input A8 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQs is written to the memory array

subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access a specified time (tRP) after the PRECHARGE command is issued. Input A8 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as “Don’t Care.” Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging.

AUTO PRECHARGE

Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A8 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command.

Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This “earliest valid stage” is determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating tRAS

min

, as described for each burst type in the Operation section of this data sheet. The user must not issue another command to the same bank until the precharge time (tRP) is completed.

BURST TERMINATE

The BURST TERMINATE command is used to truncate READ bursts (with auto precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated, as shown in the Operation section of this data sheet.

128Mb: x32

DDR SDRAM

ADVANCE

AUTO REFRESH

AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS#-BEFORERAS# (CBR) REFRESH in FPM/EDO DRAMs. This command is nonpersistent, so it must be issued each time a refresh is required.

The addressing is generated by the internal refresh controller. This makes the address bits a “Don’t Care” during an AUTO REFRESH command. The 128 Mb x32 DDR SDRAM requires AUTO REFRESH cycles at an average interval of 7.8µs (maximum).

To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 18 × 7.8µs (140.4µs). This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between updates. This is a JEDEC requirement that is NOT required for Micron’s 128Mb x32 DDR device.

SELF REFRESH

The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are “Don’t Care” during SELF REFRESH.

The procedure for exiting self refresh requires a sequence of commands. First, CK must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both refresh and DLL requirements is to apply NOPs for 200 clock cycles before applying any other command.

128Mb: x32

DDR SDRAM

ADVANCE

Operations

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated, as shown in Figure 4.

After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 15ns with a 166 MHz clock (6ns period) results in 2.5 clocks rounded to 3. This is reflected in Figure 5, which covers any case where 2 < tRCD (MIN)/tCK ≤ 3. (Figure 5 also shows the same case for tRCD; the same procedure is used to convert other specification limits from time units to clock cycles).

A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been “closed” (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by

RRD.

Figure 5

Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK

≤≤

≤ 3

Figure 4

Activating a Specific Row in

a Specific Bank

CS#

WE#

CAS#

RAS#

CKE

A0-A11

RA = Row Address BA = Bank Address

HIGH

BA0,1

CK#

COMMAND

BA0, BA1

ACT ACT

NOP

RRD

RCD

CK#

Bank x Bank y

A0-A11

Row Row

NOP

RD/WR

NOP

Bank y

Col

NOP

T0 T1 T2 T3 T4 T5 T6 T7

DON T CARE

NOP

128Mb: x32

DDR SDRAM

ADVANCE

READs

READ bursts are initiated with a READ command, as shown in Figure 6.

The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. For the generic READ commands used in the following illustrations, auto precharge is disabled.

During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid nominally at the next positive or negative clock edge (i.e., at the next crossing of CK and CK#). Figure 7 shows general timing for each possible CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coincident with the last dataout element is known as the read postamble.

Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A detailed explanation of tDQSQ (valid dataout skew), tQH (data-out window hold), the valid data window are depicted in Figure 27. A detailed explanation of tDQSCK (DQS transition skew to CK) and tAC (data-out transition skew to CK) is depicted in Figure

28.

Data from any READ burst may be concatenated with or truncated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles after the first READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). This is shown in Figure 8. A READ command can be initiated on any clock cycle following a previous READ command. Nonconsecutive read data is shown for illustration in Figure 9. Full-speed random read accesses within a page (or pages) can be performed as shown in Figure 10.

Figure 6

READ Command

CS#

WE#

CAS#

RAS#

CKE

A0-A7

BA0,1

HIGH

EN AP

DIS AP

A9, A10, A11

CK#

CA = Column Address BA = Bank Address EN AP = Enable Auto Precharge DIS AP = Disable Auto Precharge

DON T CARE

128Mb: x32

DDR SDRAM

ADVANCE

Figure 7

READ Burst

CK#

COMMAND

READ NOP NOP NOP NOP NOP

ADDRESS

Bank a,

Col n

READ NOP NOP NOP NOP NOP

Bank a,

Col n

CL = 2

NOTE: 1. DO n = data-out from column n.

2. Burst length = 4.

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Shown with nominal tAC, tDQSCK, and tDQSQ.

CK#

COMMAND

ADDRESS

DQS

CL = 3

DQS

T0 T1 T2 T3 T3n T4 T5

T0 T1 T2 T3T2n T3n T4 T5

DON T CARE TRANSITIONING DATA

128Mb: x32

DDR SDRAM

ADVANCE

Figure 8

Consecutive READ Bursts

CK#

COMMAND

READ NOP READ NOP NOP NOP

ADDRESS

Bank,

Col n

Bank,

Col b

COMMAND

READ NOP READ NOP NOP NOP

ADDRESS

Bank,

Col n

Bank,

Col b

CL = 2

CK#

COMMAND

ADDRESS

DQS

CL = 3

DQS

T0 T1 T2 T3T2n T3n T4 T5T4n T5n

T0 T1 T2 T3 T3n T4 T5T4n T5n

NOTE: 1. DO n (or b) = data-out from column n (or column b).

2. Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.

5. Shown with nominal

AC, tDQSCK, and tDQSQ.

6. Example applies only when READ commands are issued to same device.

DON T CARE TRANSITIONING DATA

128Mb: x32

DDR SDRAM

ADVANCE

Figure 9

Nonconsecutive READ Bursts

CK#

COMMAND

READ NOP NOP NOP NOP NOP

ADDRESS

Bank,

Col n

READ

Bank,

Col b

COMMAND

ADDRESS

CL = 2

CK#

COMMAND

ADDRESS

DQS

CL = 3

DQS

T0 T1 T2 T3T2n T3n T4 T5 T5n T6

NOTE: 1. DO n (or b) = data-out from column n (or column b).

2. Burst length = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first).

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b.

5. Shown with nominal

AC, tDQSCK, and tDQSQ.

6. Example applies when READ commands are issued to different devices or nonconsecutive READs.

READ NOP NOP NOP NOP NOP

Bank,

Col n

READ

Bank,

Col b

T0 T1 T2 T3 T3n T4 T5 T5n T6

DON T CARE TRANSITIONING DATA

128Mb: x32

DDR SDRAM

ADVANCE

Figure 10

Random READ Accesses

CK#

COMMAND

READ READ READ NOP NOP

ADDRESS

Bank,

Col n

Bank,

Col x

Bank,

Col b

Bank,

Col x

Bank,

Col b

READ

Bank,

Col g

COMMAND

ADDRESS

CL = 2

CK#

COMMAND

ADDRESS

DQS

CL = 3

DQS

x’

n’

b’

x’

n’

b’

T0 T1 T2 T3T2n T3n T4 T5T4n T5n

NOTE: 1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g).

2. Burst length = 2 or 4 or 8 (if 4 or 8, the following burst interrupts the previous).

3. n’ or x’ or b’ or g’ indicates the next data-out following DO n or DO x or DO b or DO g, respectively.

4. READs are to an active row in any bank.

5. Shown with nominal

AC, tDQSCK, and tDQSQ.

READ READ READ NOP NOP

Bank,

Col n

READ

Bank,

Col g

T0 T1 T2 T3 T3n T4 T5T4n T5n

DON T CARE TRANSITIONING DATA

128Mb: x32

DDR SDRAM

ADVANCE

Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 11. The BURST TERMINATE latency is equal to the READ (CAS) latency, i.e., the BURST TERMINATE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture).

Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in Figure

12. The tDQSS (MIN) case is shown; the tDQSS (MAX) case has a longer bus idle time. (tDQSS [MIN] and

DQSS [MAX] are defined in the section on WRITEs.)

A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank provided that auto precharge was not activated. The PRECHARGE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). This is shown in Figure 13. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met. Note that part of the row precharge time is hidden during the access of the last data elements.

READs (continued)

+ 46 hidden pages

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