MICRON MT46V16M8-5 Datasheet

1

128Mb: x8DDR400 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx8DDR400.p65 – Rev. A (1/30/02-B) ©2002, Micron Technology, Inc.

128Mb: x8

DDR400 SDRAM Addendum

‡

THIS DATA SHEET CONTAINS THE PRESENT DESCRIPTION OF A PRODUCT IN DEFINITION WITH NO FORMAL DESIGN IN PROGRESS.

PREVIEW

‡

KEY TIMING PARAMETERS

SPEED CLOCK RATE DATA-OUT ACCESS DQS-DQ

GRADE CL = 3

1

WINDOW2WINDOW SKEW

-5 200 MHz 2.15ns ±0.50ns +0.35ns

NOTE: 1. CL = CAS (Read) Latency

2. With a 50/50 clock duty cycle

Architecture 16 Meg x 8

Configuration 4 Meg x 8 x 4 banks
Refresh Count 4K
Row Addressing 4K (A0–A11)
Bank Addressing 4 (BA0, BA1)
Column Addressing 1K (A0–A9)

DOUBLE DATA RATE
(DDR) SDRAM

MT46V16M8 – 4 Meg x 8 x 4 banks

For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/dramds

FEATURES

• 200 MHz Clock, 400 Mb/s/p data rate

•VDD = +2.65V ±0.10V

•VDDQ = +2.65V ±0.10V

• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture

• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center­aligned with data for WRITEs

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Data mask (DM) for masking write data

• Programmable burst lengths: 2, 4, or 8

• Concurrent Auto Precharge option supported

• Auto Refresh and Self Refresh Modes

•tRAS lockout (tRAP = tRCD)

OPTIONS PART NUMBER

• Configuration
16 Meg x 8 (4 Meg x 8 x 4 banks) 16M8

• Plastic Package
66-Pin TSOP TG
(400mil with 0.65mm pin pitch)

• Timing - Cycle Time

5ns @ CL = 3

(1)

-5

• Self Refresh
Standard none

NOTE: 1. Supports modules with 3-4-4 timing

CONFIGURATION

GENERAL DESCRIPTION

The DDR400 SDRAM is a high-speed CMOS, dy­namic random-access memory that operates at a fre­quency of 200 MHz (

t

CK=5ns) with a peak data transfer
rate of 400Mb/s. DDR400 continues to use the JEDEC
standard SSTL_2 interface and the 2n-prefetch archi­tecture.

The standard DDR200/DDR266 data sheets also
pertain to the DDR400 device and should be refer­enced for a complete description of DDR SDRAM func­tionality and operating modes. However, to meet the
faster DDR400 operating frequencies, some of the AC
timing parameters, DC levels and operating tempera­tures are slightly tighter. This addendum data sheet
will concentrate on the key differences required to sup­port the enhanced speeds.
The Micron 128Mb data sheet provides full specifica­tions and functionality unless specified herein.

2

128Mb: x8DDR400 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx8DDR400.p65 – Rev. A (1/30/02-B) ©2002, Micron Technology, Inc.

128Mb: x8

DDR400 SDRAM Addendum

PREVIEW

66-PIN TSOP PACKAGE PIN ASSIGNMENT

66-PIN TSOP PACKAGE DIMENSION

SEE DETAIL A

0.10

0.65 TYP

0.71

10.16 ±0.08

0.15

0.50 ±0.10

PIN #1 ID

DETAIL A

22.22 ± 0.08

0.32 ± .075 TYP

+0.03

-0.02

+0.10

-0.05

1.20 MAX

0.10

0.25

11.76 ±0.10

0.80 TYP

0.10 (2X)

GAGE PLANE

(TOP VIEW)

NOTE: 1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm
per side.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33

66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34

V

SS

DQ7

V

SS

Q
NC

DQ6

V

DD

Q
NC

DQ5

V

SS

Q
NC

DQ4

V

DD

Q
NC
NC
V

SS

Q

DQS

DNU

V

REF

V

SS

DM
CK#
CK
CKE
NC
NC

A11
A9
A8
A7
A6
A5
A4

V

SS

x8

V

DD

DQ0

V

DD

Q

NC

DQ1

V

SS

Q

NC

DQ2

V

DD

Q

NC

DQ3

V

SS

Q
NC
NC

V

DD

Q
NC
NC

V

DD

DNU

NC

WE#
CAS#
RAS#

CS#

NC

BA0
BA1

A10/AP

A0

A1

A2

A3

V

DD

x8

3

128Mb: x8DDR400 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mbx8DDR400.p65 – Rev. A (1/30/02-B) ©2002, Micron Technology, Inc.

128Mb: x8

DDR400 SDRAM Addendum

PREVIEW

PIN DESCRIPTIONS

PIN NUMBERS SYMBOL TYPE DESCRIPTION

45, 46 CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.

44 CKE Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the

internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER-DOWN
entry and exit, and for SELF REFRESH entry. CKE is asynchronous
for SELF REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK#, and CKE) are disabled during
POWER-DOWN. Input buffers (excluding CKE) are disabled
during SELF REFRESH. CKE is an SSTL_2 input but will detect an
LVCMOS LOW level after VDD is applied.

24 CS# Input Chip Select: CS# enables (registered LOW) and disables (regis-

tered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part
of the command code.

23, 22, 21 RAS#, CAS#, Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

WE# command being entered.

47 DM Input Input Data Mask: DM is an input mask signal for write data. Input

data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins.

26, 27 BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an

ACTIVE, READ, WRITE, or PRECHARGE command is being applied.

29-32 A0, A1, A2 Input Address Inputs: Provide the row address for ACTIVE commands, and
32, 35, 36 A3, A4, A5 the column address and auto precharge bit (A10) for READ/WRITE
36, 38, 39 A6, A7, A8 commands, to select one location out of the memory array in the
40, 29, 41 A9, A10, A11 respective bank. A10 sampled during a PRECHARGE command

determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET command. BA0
and BA1 define which mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER command.

2, 5, 8 DQ0-2 I/O Data Input/Output.

11, 56, 59 DQ3-5

62, 65 DQ6-7

51 DQS I/O Data Strobe: Output with read data, input with write data. DQS is

edge-aligned with read data, centered in write data. It is used to
capture data.

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