MICRON MT28S4M16LCTG-10, MT28S4M16LCTG-12 Datasheet

4 MEG x 16

SYNCFLASH MEMORY

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

SYNCFLASH

MEMORY

FEATURES

• 100 MHz SDRAM-compatible read timing

• Fully synchronous; all signals registered on positive edge of system clock

• Internal pipelined operation; column address can be changed every clock cycle

• Internal banks for hiding row access

• Programmable burst lengths: 1, 2, 4, 8, or full page (READ)

• LVTTL-compatible inputs and outputs

• Single +3.3V ±0.3V power supply – Additional VHH hardware protect mode (RP#)

• Four-bank architecture supports true concurrent operations with zero latency:

Read from any bank while performing a PROGRAM or ERASE operation to any other bank

• Deep power-down mode: 300µA maximum

• Cross-compatible Flash memory command set

• Industry-standard, SDRAM-compatible pinouts – Pins 36 and 40 are no connects for SDRAM

OPTIONS MARKING

• Configuration 4 Meg x 16 (1 Meg x 16 x 4 banks) 4M16

• Read Timing (Cycle Time) 10ns (100 MHz) -10 12ns (83 MHz) -12

• Package 54-pin OCPL1 TSOP II (400 mil) TG

• Operating Temperature Range Commercial Temperature (0ºC to +70ºC) None

NOTE: 1. Off-center parting line

Part Number Example:

MT28S4M16LCTG-10

PIN ASSIGNMENT (Top View)

MT28S4M16LC

1 Meg x 16 x 4 banks

54-Pin TSOP II

NOTE: The # symbol indicates signal is active LOW.

DQ0

DQ1 DQ2

DQ3 DQ4

DQ5 DQ6

DQ7

DQML

WE# CAS# RAS#

CS#

BA0 BA1

A10

A0 A1 A2 A3

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28

DQ15

DQ14 DQ13

DQ12 DQ11

DQ10 DQ9

DQ8

RP# DQMH CLK CKE V

A11 A9 A8 A7 A6 A5 A4

GENERAL DESCRIPTION

This SyncFlash® data sheet is divided into two major sections. The SDRAM Interface Functional Description details compatibility with the SDRAM memory, and the Flash Memory Functional Description specifies the symmetrical-sectored flash architecture functional commands.

KEY TIMING PARAMETERS

SPEED CLOCK ACCESS TIME SETUP HOLD

GRADE FREQUENCY CL = 2* CL = 3* TIME TIME

-10 100 MHz – 7ns 3ns 2ns

-10 66 MH z 9ns – 3ns 2ns

-12 83 MH z – 9ns 3ns 2ns

-12 66 MH z 10ns – 3ns 2ns

*CL = CAS (READ) latency

The MT28S4M16LC is a nonvolatile, electrically sector-erasable (Flash), programmable memory containing 67,108,864 bits organized as 4,194,304 words (16 bits). SyncFlash memory is ideal for 3.3V-only platforms that require both hardware and software protection modes. Additional hardware protection modes are

4 MEG x 16

SYNCFLASH MEMORY

GENERAL DESCRIPTION (continued)

also available when VHH is applied to the RP# pin. Programming or erasing the device is done with a 3.3V VCCP voltage, while all other operations are performed with a 3.3V VCC. The device is fabricated with Micron’s advanced CMOS floating-gate process.

The MT28S4M16LC is organized into 16 independently erasable blocks. To ensure that critical firmware is protected from accidental erasure or overwrite, the MT28S4M16LC features sixteen 256K-word hardwareand software-lockable blocks.

The MT28S4M16LC four-bank architecture supports true concurrent operations. A read access to any bank can occur simultaneously with a background PROGRAM or ERASE operation to any other bank.

The SyncFlash memory has a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read accesses to the memory are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ command. The address bits registered coincident with the ACTIVE command are used to select the bank and

row to be accessed. The address bits registered coincident with the READ command are used to select the starting column location for the burst access.

The SyncFlash memory provides for programmable read burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option.

The 4 Meg x 16 SyncFlash memory uses an internal pipelined architecture to achieve high-speed operation.

The 4 Meg x 16 SyncFlash memory is designed to operate in 3.3V, low-power memory systems. A deep power-down mode is provided, along with a powersaving standby mode. All inputs and outputs are LVTTL-compatible.

SyncFlash memory offers substantial advances in Flash operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation and the capability to randomly change column addresses on each clock cycle during a burst access.

Please refer to Micron’s Web site (www.micron.com/

flash) for the latest data sheet.

4 MEG x 16

SYNCFLASH MEMORY

TABLE OF CONTENTS

Functional Block Diagram – 4 Meg x 16 ............... 4

Pin Descriptions ...................................................... 5

SDRAM Interface Functional Description .......... 7

Initialization ...................................................... 7

Mode Register ............................................... 7

Burst Length ............................................ 7

Burst Type ............................................... 7

CAS Latency ............................................ 9

Operating Mode ...................................... 9

Write Burst Mode .................................... 9

Commands ........................................................ 10

Truth Table 1 (Commands and DQM Operation) ....... 10

Truth Table 2 (Commands Sequences) ....................... 11

Command Inhibit ........................................ 13

No Operation (NOP) .................................... 13

Load Mode Register ...................................... 13

Active ............................................................ 13

Read .............................................................. 13

Write ............................................................. 13

Active Terminate .......................................... 13

Burst Terminate ............................................ 13

Load Command Register ............................. 13

Operation .......................................................... 14

Bank/Row Activation .................................. 14

Reads ............................................................ 15

Writes ........................................................... 20

Active Terminate .......................................... 20

Power-Down ................................................ 20

Clock Suspend ............................................. 20

Burst Read/Single Write ............................... 21

Truth Table 3 (CKE) .................................................. 21

Truth Table 4 (Current State, Same Bank) .................. 22

Truth Table 5 (Current State, Different Bank) ............. 23

Flash Memory Functional Description ............... 24

Command Interface .................................... 24

Memory Architecture ................................... 24

Protected Blocks ........................................... 24

Command Execution Logic (CEL) ............... 25

Internal State Machine (ISM) ...................... 25

ISM Status Register ...................................... 25

Output (READ) Operations .............................. 25

Memory Array ............................................. 25

Status Register .............................................. 25

Device Configuration Registers ................... 25

Input Operations .............................................. 26

Memory Array ............................................. 26

Command Execution ........................................ 26

Status Register .............................................. 27

Device Configuration .................................. 27

Program Sequence ....................................... 27

Erase Sequence ............................................. 27

Program and Erase NVMode Register ......... 27

Block Protect/Unprotect Sequence .............. 27

Device Protect Sequence .............................. 28

Reset/Deep Power-Down Mode ....................... 28

Error Handling .................................................. 28

PROGRAM/ERASE Cycle Endurance ................ 28

Absolute Maximum Ratings .................................. 35

DC Electrical Characteristics

and Operating Conditions ................................... 35

ICC Specifications and Conditions .......................... 36

Capacitance ............................................................ 36

Electrical Characteristics and Recommended

Operating Conditions (Timing Table) ............. 37

AC Functional Characteristics ............................. 38

Notes ...................................................................... 39

Timing Waveforms

Initialize and Load Mode Register ..................... 40

Clock Suspend Mode ......................................... 41

Reads

Read .............................................................. 42

Alternating Bank Read Accesses ................... 43

Read – Full-Page Burst ................................. 44

Read – DQM Operation .............................. 45

Program

Program/Erase

(Bank a followed by READ to bank b).. 46

Program/Erase

(Bank a followed by READ to bank a).. 47

4 Meg x 16 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

4 MEG x 16

SYNCFLASH MEMORY

FUNCTIONAL BLOCK DIAGRAM

4 Meg x 16

RAS#

CAS#

ROW-

ADDRESS

MUX

CLK

CS#

WE#

CKE

COLUMNADDRESS COUNTER/

LATCH

A0–A11,

BA0, BA1

DQML, DQMH

ADDRESS REGISTER

256

(x16)

4,096

I/O GATING DQM MASK LOGIC READ DATA LATCH

WRITE DRIVERS

COLUMN DECODER

BANK 0

MEMORY

ARRAY

(4,096 x 256 x 16)

BANK 0

ROW-

ADDRESS

LATCH

DECODER

High Voltage Switch/Pump

4,096

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–DQ15

BANK 1

BANK 2

BANK 3

2 2

COMMAND EXECUTION

LOGIC

MODE REGISTER

COMMAND

DECODE

STATE MACHINE

STATUS REG.

NVMODE REGISTER

DATA

INPUT

DATA

OUTPUT

RP#

VCCP

ID REG.

4 MEG x 16

SYNCFLASH MEMORY

PIN DESCRIPTIONS

54-PIN TSOP

NUMBERS

SYMBOL

TYPE DESCRIPTION

38 CLK Input Clock: CLK is driven by the system clock. All SyncFlash memory input

signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers.

37 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK

signal. Deactivating the clock provides STANDBY operation or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down modes, providing low standby power. CKE may be tied HIGH in systems where power-down modes (other than RP# deep power-down) are not required.

19 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered

HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code.

18, 17, 16 RAS#, Input Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

CAS#, command being entered.

WE#

15, 39 DQML, Input Input/Output Mask: DQM is an input mask signal for write accesses

DQMH and an output enable signal for read accesses. Input data is masked

when DQM is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (after a two-clock latency) when DQM is sampled HIGH during a READ cycle. DQML corresponds to DQ0–DQ7 and DQMH corresponds to DQ8–DQ15. DQML and DQMH are considered same state when referenced as DQM.

23-26, 29-34, A0–A11 Input Address Inputs: A0–A11 are sampled during the ACTIVE command

22, 35 (row-address A0–A11) and READ/WRITE command (column-address

A0–A7) to select one location in the respective bank. The address inputs provide the Op-Code during LOAD MODE REGISTER command and the operation code during a LOAD COMMAND REGISTER command.

40 RP# Input Initialize/Power-Down: Upon initial device power-up, a 100µs delay

after RP# has transitioned from LOW to HIGH is required for internal device initialization, prior to issuing an executable command. RP# clears the status register, sets the internal state machine (ISM) to the array read mode, and places the device in the deep power-down mode when LOW. All inputs, including CS#, are “Don’t Care” and all outputs are High-Z. When RP# = VHH, all protection modes are ignored during PROGRAM and ERASE. Also allows the device protect bit to be set to “1” (protected) and allows the block protect bits at locations 0 and 15 to be set to “0” (unprotected) when brought to VHH. RP# must be held HIGH during all other modes of operation.

(continued on next page)

4 MEG x 16

SYNCFLASH MEMORY

20, 21 BA0, Input Bank Address Input(s): BA0, BA1 define to which bank the command

BA1 is being applied. See Truth Tables 1 and 2.

2, 4, 5, 7, 8, 10, DQ0- I/O Data I/O: Data bus. 11,13, 42, 44, 45, DQ15 47, 48, 50, 51, 53

3, 9, 43, 49 VCCQ Supply DQ Power: Provide isolated power to DQs for improved noise

immunity.

6, 12, 46, 52 VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved noise

immunity.

1, 14, 27 VCC Supply Power Supply: 3.3V ±0.3V.

28, 41, 54 VSS Supply Ground.

36 VCCP Supply Program/Erase Supply Voltage: VCCP must be tied externally to VCC. The

VCCP pin sources current during device initialization, PROGRAM and ERASE operations.

PIN DESCRIPTIONS (continued)

54-PIN TSOP

NUMBERS

SYMBOL

TYPE DESCRIPTION

4 MEG x 16

SYNCFLASH MEMORY

SDRAM

SDRAM INTERFACE FUNCTIONAL DESCRIPTION

In general, the 64Mb SyncFlash memory (1 Meg x 16 x 4 banks) is configured as a quad-bank, nonvolatile SDRAM that operates at 3.3V and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits.

Read accesses to the SyncFlash memory are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank, A0–A11 select the row). The address bits registered coincident with the READ command are used to select the starting column location for the burst access (BA0 and BA1 select the bank, A0–A7 select the column).

Prior to normal operation, the SyncFlash memory must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation.

Initialization

SyncFlash memory must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. After power is applied to VCC, VCCQ, and VCCP (simultaneously), and the clock is stable, RP# must be brought from LOW to HIGH. A 100µs delay is required after RP# transitions HIGH in order to complete internal device initialization.

The SyncFlash memory is now in the array read mode and ready for mode register programming or an executable command. After initial programming of the nvmode register, the contents are automatically loaded into the mode register during initialization and the device will power up in the programmed state.

MODE REGISTER

The mode register is used to define the specific mode of operation of the SyncFlash memory. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure 1. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is reprogrammed. The contents of the mode register may be copied into the nvmode reg-

ister; the mode register settings automatically load the mode register during initialization. Details on erase nvmode register and program nvmode register command sequences are found in the Command Execution section of the Flash Memory Functional Description.

Mode register bits M0–M2 specify the burst length, M3 specifies the burst type (sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the write burst mode in an SDRAM (M9 = 1 by default), and M10 and M11 are reserved for future use.

The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.

BURST LENGTH

Read accesses to the SyncFlash memory are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ command. Burst lengths of 1, 2, 4, or 8 locations are available for both sequential and interleaved burst types, and a full-page burst is available for the sequential type. The full-page burst is used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

When a READ command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1–A7 when the burst length is set to two, by A2–A7 when the burst length is set to four, and by A3–A7 when the burst length is set to eight. The remaining (least significant) address bit(s) are used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached.

BURST TYPE

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 1.

4 MEG x 16

SYNCFLASH MEMORY

SDRAM

Figure 1

Mode Register Definition

Table 1

Burst Definition

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

0 0-1 0-1 1 1-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full

n = A0–A7 Cn, Cn+1, Cn+2

Page Cn+3, Cn+4... Not supported

256 (location 0-255) …Cn-1,

Cn...

NOTE: 1. For a burst length of two, A1–A7 select the block-

of-two burst; A0 selects the starting column within the block.

2. For a burst length of four, A2–A7 select the blockof-four burst; A0–A1 select the starting column within the block.

3. For a burst length of eight, A3–A7 select the block-of-eight burst; A0–A2 select the starting column within the block.

4. For a full-page burst, the full row is selected and A0–A7 select the starting column.

5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

6. For a burst length of one, A0–A7 select the unique column to be accessed, and mode register bit M3 is ignored.

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

0-0-Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst LengthCAS Latency BT

A3A8A2A1A0

Mode Register (Mx)

Address Bus

654

382

M6-M0

Op Mode

A10

A11

Reserved* WB

Write Burst Mode

Reserved

Single Location Access

*Program

M11, M10 = 0, 0

to ensure compatibility

with future devices.

4 MEG x 16

SYNCFLASH MEMORY

SDRAM

CAS LATENCY

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two, or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by

Figure 2

CAS Latency

Table 2

CAS Latency

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS CAS CAS

SPEED LATENCY = 1 LATENCY = 2 LATENCY = 3

-10 ≤33 ≤66 ≤100

-12 ≤33 ≤66 ≤83

clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1) and, provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0, and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Table 2 below indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

OPERATING MODE

The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to READ bursts.

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

WRITE BURST MODE

WRITE bursts are not supported with the MT28S4M16LC. By default, M9 is set to “1” and write accesses are single-location (nonburst) accesses.

CLK

T2T1 T3T0

CAS Latency = 3

OUT

COMMAND

NOPREAD

NOP

DON’T CARE

UNDEFINED

CLK

T2T1T0

CAS Latency = 1

OUT

COMMAND

NOPREAD

CLK

T2T1 T3T0

CAS Latency = 2

OUT

COMMAND

NOPREAD

NOP

4 MEG x 16

SYNCFLASH MEMORY

SDRAM

COMMANDS

Truth Table 1 provides a quick reference of available commands for SDRAM-compatible operation. This is followed by a written description of each command. Additional truth tables appear later.

TRUTH TABLE 1 SDRAM-COMPATIBLE INTERFACE COMMANDS AND DQM OPERATION

(Notes: 1)

NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQs NOTES

COMMAND INHIBIT (NOP) H X X X X X X NO OPERATION (NOP) L H H H X X X ACTIVE (Select bank and activate row) L L H H X Bank/Row X 2 READ (Select bank, column and start READ burst) L H L H X Bank/Col X 3 WRITE (Select bank, column and start WRITE) L H L L X Bank/Col Valid 3, 4 BURST TERMINATE L H H L X X Active ACTIVE TERMINATE L L H L X X X 5 LOAD COMMAND REGISTER L L L H X ComCode X 6, 7 LOAD MODE REGISTER L L L L X OpCode X 8 Write Enable/Output Enable – – – – L – Active 9 Write Inhibit/Output High-Z – – – – H – High-Z 9

NOTE: 1. CKE is HIGH for all commands shown.

2. A0–A11 provide row address, and BA0 and BA1 determine which bank is made active.

3. A0–A7 provide column address, and BA0 and BA1 determine which bank is being read from or written to.

4. A program setup command sequence (see Truth Table 2) must be completed prior to executing a WRITE.

5. ACTIVE TERMINATE is functionally equivalent to the SDRAM PRECHARGE command, however PRECHARGE (deactivate row in bank or banks) is not required for SyncFlash memory. A10 LOW: BA0 and BA1 determine the bank being active terminated. A10 HIGH: All banks active terminated and BA0 and BA1 are “Don’t Care.”

6. A0–A7 define the ComCode, and A8–A11 are “Don’t Care” for this operation. See Truth Table 2.

7. LOAD COMMAND REGISTER (LCR) replaces the SDRAM AUTO REFRESH or SELF REFRESH command, which is not required for SyncFlash memory. LCR is the first cycle for Flash memory command sequences. See Truth Table 2.

8. A0–A11 define the OpCode written to the mode register. The mode register can be dynamically loaded each cycle, provided tMRD is satisfied. The contents of the nvmode register are automatically loaded into the mode register during device initialization.

9. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

4 Meg x 16 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

4 MEG x 16

SYNCFLASH MEMORY

SDRAM

COMMANDS

Truth Table 2 provides a quick reference of available commands for flash memory interface operation. A written description of each command is found in the Flash Memory Functional Description section.

TRUTH TABLE 2 FLASH MEMORY COMMAND SEQUENCES

(Notes: 1, 2, 3, 4, 5; see notes on the next page.)

FIRST CYCLE SECOND CYCLE THIRD CYCLE

BANK BANK BANK

OPERATION CMD ADDR6ADDR DQ RP# CMD7ADDR ADDR DQ RP# CMD ADDR ADDR DQ8RP# NOTES

READ DEVICE CONFIGURATION LCR 90h Bank X H ACTIVE Row Bank X H READ CA Bank X H 9, 10 READ STATUS REGISTER LCR 70h X X H ACTIVE X X X H READ X X X H CLEAR STATUS REGISTER LCR 50h X X H ERASE SETUP/CONFIRM LCR 20h Bank X H ACTIVE Row Bank X H WRITE X Bank D0h H/VHH11, 12, 13 PROGRAM SETUP/PROGRAM LCR 40h Bank X H ACTIVE Row Bank X H WRITE Col Bank DINH/VHH11, 12, 13 PROTECT BLOCK/CONFIRM LCR 60h Bank X H ACTIVE Row Bank X H WRITE X Bank 01h H/V

11, 12,

13, 14 PROTECT DEVICE/CONFIRM LCR 60h Bank X H ACTIVE X Bank X H WRITE X Bank F1h VHH11, 12 UNPROTECT BLOCKS/CONFIRM LCR 60h Bank X H ACTIVE X Bank X H WRITE X Bank D0h H/V

11, 12,

13, 15 ERASE NVMODE REGISTER LCR 30h Bank X H ACTIVE X Bank X H WRITE X Bank C0h H 11, 12 PROGRAM NVMODE REGISTER LCR A0h Bank X H ACTIVE X Bank X H WRITE X Bank X H 11, 12

4 MEG x 16

SYNCFLASH MEMORY

SDRAM

NOTE: 1. CMD = Command: Decoded from CS#, RAS#, CAS#, and WE# inputs.

2. NOP/COMMAND INHIBIT commands may be issued throughout any operation command sequence.

3. After a PROGRAM or ERASE operation is registered to the ISM and prior to completion of the ISM operation, a READ to any location in the bank under ISM control will output the contents of the row activated prior to the LCR/active/write sequence (see Note 7).

4. In order to meet the tRCD specification, the appropriate number of NOP/COMMAND INHIBIT commands must be issued between ACTIVE and READ/WRITE commands.

5. The ERASE, PROGRAM, PROTECT, UNPROTECT operations are self-timed. The status register may be polled to monitor these operations.

6. A8–A11 are “Don’t Care.”

7. A row will not be opened when ACTIVE is preceded by LCR. ACTIVE is considered a NOP.

8. Data Inputs: DQ8–DQ15 are “Don’t Care.” Data Outputs: All unused bits are driven LOW.

9. The block address is required during ACTIVE and READ cycles for the block protect bit location. The first row in a block should be specified, acceptable values include 000h, 400h, 800h, and C00h. Bank address is “Don’t Care” for manufacturer compatibility ID, device ID, and device protect bit location.

10. CA = Configuration Address: 000h – Manufacturer compatibility ID (2Ch) 001h – Device ID (D3h) x02h – Block protect bit, where x = 0, 4, 8, or Ch 003h – Device protect bit

11. The proper command sequence (LCR/active/write) is needed to initiate an ERASE, PROGRAM, PROTECT, UNPROTECT

operation.

12. The bank address must match for the three command cycles (LCR/ACTIVE/WRITE) to initiate an ERASE, PROGRAM,

PROTECT, UNPROTECT operation.

13. If the device protect bit is set, then an ERASE, PROGRAM, PROTECT, UNPROTECT operation can still be initiated by

bringing RP# to VHH prior to the WRITE command cycle and holding it at VHH until the operation is completed.

14. The A10, A11 row address and BA0, BA1 bank address select the block to be protected; A0–A9 are “Don’t Care.”

15. If the device protect bit is not set, RP# = VIH unprotects all sixteen 256K-word erasable blocks, except for blocks 0 and

15. When RP# = VHH, all sixteen 256K-word erasable blocks (including block 0 and 15) will be unprotected, and the device protect bit will be ignored. If the device protect bit is set and RP# = VIH, the block protect bits cannot be modified.

4 MEG x 16

SYNCFLASH MEMORY

SDRAM

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands from being executed by the SyncFlash memory, regardless of whether the CLK signal is enabled. The SyncFlash memory is effectively deselected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to a SyncFlash memory that is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

LOAD MODE REGISTER

The mode register is loaded via inputs A0–A11 and BA0 and BA1. See mode register heading in Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tMRD is met. The data in the nvmode register is automatically loaded into the mode register upon power-up initialization and is the default mode setting unless dynamically changed with the LOAD MODE REGISTER command.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A11 selects the row. This row remains active for accesses until the next ACTIVE command, power-down or RESET.

READ

The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A7 selects the starting column location. Read data appears on the DQs subject to the logic level on the DQM input two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data.

WRITE

The WRITE command is used to initiate a singlelocation write access. A WRITE command must be preceded by LRC/ACTIVE. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A7 selects the column location.

Input data appearing on the DQs is written to the memory array, subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that word/column location. A WRITE command with DQM HIGH is considered a NOP.

ACTIVE TERMINATE

ACTIVE TERMINATE, which replaces the SDRAM PRECHARGE command, is not required for SyncFlash memory, but is functionally equivalent to the SDRAM PRECHARGE command. ACTIVE TERMINATE can be issued to terminate a BURST READ in progress and may or may not be bank specific.

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ command prior to the BURST TERMINATE command will be truncated as shown in the Operation section of this data sheet. BURST TERMINATE is not bank specific.

LOAD COMMAND REGISTER (LCR)

The LOAD COMMAND REGISTER (LCR) command is used to initiate flash memory control commands to the command execution logic (CEL). The CEL receives and interprets commands to the device. These commands control the operation of the ISM and the read path (i.e., memory array, ID register, or status register). However, there are restrictions on what commands are allowed in this condition. See the Command Execution section of Flash Memory Functional Description for more details.

4 MEG x 16

SYNCFLASH MEMORY

SDRAM

Figure 3

Activating a Specific Row in a

Specific Bank

CLK

T2T1 T3T0

COMMAND

NOPACTIVE READ or WRITE

NOP

RCD

DON’T CARE

Figure 4

Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK £ 3

Operation

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued to a bank within the SyncFlash memory, a row in that bank must be “opened.” (Note: A row will not be activated for LCR/active/read or LCR/active write command sequences, see the Flash Memory Architecture section for additional information). This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated.

After opening a row (issuing an ACTIVE command), a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 30ns with a 90 MHz clock (11.11ns period) results in 2.7 clocks rounded to 3. This is reflected in Figure 4, which covers any case where 2 < tRCD (MIN)/

CK ≤ 3 . (The same procedure is used to convert other

specification limits from time units to clock cycles).

A subsequent ACTIVE command to a different row in the same bank can be issued without having to close a previous active row, provided the minimum time interval between successive ACTIVE commands to the same bank is defined by tRC.

A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by

RRD.

CS#

WE#

CAS#

RAS#

CKE

CLK

A0–A10

ROW

ADDRESS

HIGH

BA0, BA1

BANK

ADDRESS

4 MEG x 16

SYNCFLASH MEMORY

SDRAM

READs

READ bursts are initiated with a READ command, as shown in Figure 5.

The starting column and bank addresses are provided with the READ command.

During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent data-out element will be valid by the next positive clock edge. Figure 6 shows general timing for one, two, and three CAS latency settings.

Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A full-page burst will continue until terminated. (At the end of the page, it will wrap to column 0 and continue.)

Data from any READ burst may be truncated with a subsequent READ command, and data from a fixedlength READ burst may be immediately followed by data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst, or the last desired data element of a longer burst that is being truncated.

Figure 5

READ Command

Figure 6

CAS Latency

The new READ command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in Figure 7 for CAS latencies of one, two, and three; data element n + 3 is either the last of a burst of four, or the last desired of a longer burst. The SyncFlash memory uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a previous READ command. Full-speed, random read accesses within a page can be performed as shown in Figure 8, or each subsequent READ may be performed to a different bank.

Data from any READ burst may be truncated with a

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN

ADDRESS

A0–A7

BA0, BA1

BANK

ADDRESS

HIGH

CLK

T2T1 T3T0

CAS Latency = 3

OUT

COMMAND

NOPREAD

NOP

DON’T CARE

UNDEFINED

CLK

T2T1T0

CAS Latency = 1

OUT

COMMAND

NOPREAD

CLK

T2T1 T3T0

CAS Latency = 2

OUT

COMMAND

NOPREAD

NOP

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MICRON MT28S4M16LCTG-10, MT28S4M16LCTG-12 Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual