MICRON MT28S2M32B1LCTG-7E, MT28S2M32B1LCFG-75ET, MT28S2M32B1LCFG-7E, MT28S2M32B1LCTG-75, MT28S4M16B1LCTG-75 Datasheet

...

ADVANCE

‡

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

64Mb: x16, x32

SYNCFLASH MEMORY

SYNCFLASH

MEMORY

FEATURES

• PC133 SDRAM-compatible read timing

• Fully synchronous; all signals registered on positive edge of system clock

• Internal pipelined operation; column address can be changed every clock cycle

• Internal banks for hiding row access

• Programmable burst lengths:

1, 2 , 4, 8, or full page (read) 1, 2, 4, or 8 (write)

• LVTTL-compatible inputs and outputs

• Single 3.0V–3.6V power supply

Additional VHH hardware protect mode (RP#)

• Supports CAS latency of 1, 2, and 3

• Four-bank architecture supports true concurrent operation with zero latency

Read any bank while programming or erasing any other bank

• Deep power-down mode: 50µA (MAX)

• Cross-compatible Flash memory command set

OPTIONS MARKING

• Configuration 4 Meg x 16 (1 Meg x 16 x 4 banks) 4M16 2 Meg x 32 (512K x 32 x 4 banks) 2M32

• Read Timing (Cycle Time)

5.4ns @ CL3 (143 MHz) -7E

5.4ns @ CL3 (133 MHz) -75

• Packages 86-pin OCPL2 TSOP (400 mil) TG 90-ball FBGA FG

• Operating Temperature Range Commercial (0ºC to +70ºC) None Extended (-40ºC to +85ºC) ET

NOTE: 1. Contact factory for availability.

2. Off-center parting line.

Part Number Example:

MT28S4M16B1LCTG-7E

PIN ASSIGNMENT (Top View)

MT28S4M16B1LC – 1 Meg x 16 x 4 banks MT28S2M32B1LC – 512K x 32 x 4 banks

86-Pin TSOP

NOTE: 1. The # symbol indicates signal is active LOW.

2. FBGA ball assignment is on the next page.

KEY TIMING PARAMETERS

ACCESS

SPEED CLOCK TIME SETUP HOLD

GRADE FREQUENCY CL = 2* CL = 3* TIME TIME

-7E 143 MHz 5.4ns 1.5ns 0.8ns

-7E 133 MHz 5.4ns 1.5ns 0.8ns

-75 133 MHz 5.4ns 1.5ns 0.8ns

-75 100 MHz 6ns 1.5ns 0.8ns

VCC

DQ0

CCQ

DQ1 DQ2

SSQ

DQ3 DQ4

CCQ

DQ5 DQ6

SSQ

DQ7

DQM0

WE# CAS# RAS#

CS#

NC BA0 BA1

A10

DQM2

RP#

DQ16

SSQ

DQ17 DQ18

CCQ

DQ19 DQ20

SSQ

DQ21 DQ22

CCQ

DQ23

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

DQ15

SSQ

DQ14 DQ13

CCQ

DQ12 DQ11

SSQ

DQ10 DQ9

CCQ

DQ8

NC V

DQM1 DNU

NC CLK CKE

A9 A8 A7 A6 A5 A4 A3

DQM3 V

VCCP

DQ31

CCQ

DQ30 DQ29

SSQ

DQ28 DQ27

CCQ

DQ26 DQ25

SSQ

DQ24

VCC

DQ0

CCQ

DQ1 DQ2

SSQ

DQ3 DQ4

CCQ

DQ5 DQ6

SSQ

DQ7

DQM0

WE# CAS# RAS#

CS#

NC BA0 BA1

A10

MCL

RP#

DNU

SSQ

DNU DNU

CCQ

DNU DNU

SSQ

DNU DNU

CCQ

DNU

VSS

DQ15

SSQ

DQ14 DQ13

CCQ

DQ12 DQ11

SSQ

DQ10 DQ9

CCQ

DQ8

DQM1

CLK CKE

A11 A8 A7 A6 A5 A4 A3

MCL V

VCCP

DNU

CCQ

DNU DNU

SSQ

DNU DNU

CCQ

DNU DNU

SSQ

DNU

x32 x16

x32x16

* CL = CAS (READ) Latency

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

90-Ball FBGA – 4 Meg x 16

90-Ball FBGA – 2 Meg x 32

FBGA BALL ASSIGNMENT (Top View)

123 789

DNU

SSQ

VccQ

CLK

DQM1

VccQ

SSQ

DQ11

DQ13

DNU

VccQ

DNU

MCL

CKE

RP#

DQ8

DQ10

DQ12

VccQ

DQ15

VSS

VSSQ

DNU

VccP

A11

Vss

DQ9

DQ14

SSQ

Vss

DNU

VccQ

VssQ

Vcc

RAS#

DQM0

SSQ

VccQ

DQ4

DQ2

DNU

SSQ

DNU

MCL

BA1

CS#

WE#

DQ7

DQ5

DQ3

SSQ

DQ0

Vcc

VccQ

DNU

A10

BA0

CAS#

Vcc

DQ6

DQ1

VccQ

Vcc

123 789

DQ26

DQ28

SSQ

VccQ

CLK

DQM1

VccQ

SSQ

DQ11

DQ13

DQ24

VccQ

DQ27

DQ29

DQ31

DQM3

CKE

RP#

DQ8

DQ10

DQ12

VccQ

DQ15

VSS

VSSQ

DQ25

DQ30

VccP

DNU

Vss

DQ9

DQ14

SSQ

Vss

DQ21

DQ19

VccQ

VssQ

Vcc

RAS#

DQM0

SSQ

VccQ

DQ4

DQ2

DQ23

SSQ

DQ20

DQ18

DQ16

DQM2

BA1

CS#

WE#

DQ7

DQ5

DQ3

SSQ

DQ0

Vcc

VccQ

DQ22

DQ17

A10

BA0

CAS#

Vcc

DQ6

DQ1

VccQ

Vcc

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

GENERAL DESCRIPTION

This 64Mb SyncFlash® data sheet is divided into two major sections. The SDRAM Interface Functional Description details compatibility with the SDRAM memory, and the Flash Memory Functional Description specifies the symmetrical-sectored Flash architecture and functional commands.

Micron’s 64Mb SyncFlash devices are nonvolatile, electrically sector-erasable (Flash), programmable read-only memory containing 67,108,864 bits. Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Each of the x32’s 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32 bits.

The 64Mb devices are organized into 16 independently erasable blocks. To ensure that critical firmware is protected from accidental erasure or overwrite, the devices feature sixteen (x32: 128K-Dword; x16: 256Kword) hardware and software-lockable blocks.

A four-bank architecture supports true concurrent operations. A read access to any bank can occur simultaneously with a background PROGRAM or ERASE operation to any other bank.

SyncFlash memory has a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Read accesses to the memory are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ command. The address bits registered coincident with the ACTIVE command are used to select the bank and row

to be accessed. The address bits registered coincident with the READ command are used to select the starting column location for the burst access.

The 64Mb devices provide for programmable read burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. The x16 device features an 8-word internal write buffer and the x32 features an 8-Dword internal write buffer that support mode register programmed burst write compatibility of 1, 2, 4, or 8 locations.

SyncFlash memory uses an internal pipelined architecture to achieve high-speed operation.

The 64Mb devices are designed to operate in 3.3V, low-power memory systems. A deep power-down mode is provided, along with a power-saving standby mode. All inputs and outputs are LVTTL-compatible.

SyncFlash memory offers substantial advances in Flash operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation and the capability to randomly change column addresses on each clock cycle during a burst access.

All Flash operations are performed using either a hardware command sequence (HCS) or a software command sequence (SCS). HCS operations are used by memory controllers with native SyncFlash support. Standard SDRAM controllers can use SCS to perform Flash operations.

Please refer to Micron’s Web site (www.micron.com/

flash) for the latest data sheet.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

TABLE OF CONTENTS

Functional Block Diagram – 4 Meg x 16 ............... 5

– 2 Meg x 32 ............... 6

Pin and Ball Descriptions ....................................... 7

SDRAM Interface Functional Description ....... 10

Initialization ...................................................... 10

Mode Register .............................................. 10

Burst Length ............................................ 10

Burst Type ............................................... 12

CAS Latency ............................................ 12

Operating Mode ..................................... 12

Write Burst Mode ................................... 12

Commands ........................................................ 13

Truth Table 1 (Commands and DQM Operation) ........ 13

Truth Table 2a (Harware Command

Sequences [HCS]) .................................................

Truth Table 2b (Software Command

Sequences [SCS]) ..................................................

Command Inhibit ........................................ 18

No Operation (NOP) ................................... 18

Load Mode Register ..................................... 18

Active ............................................................ 18

Read ............................................................. 18

Write ............................................................ 18

Active Terminate .......................................... 18

Burst Terminate ............................................ 18

Load Command Register ............................. 18

Operation .......................................................... 19

Bank/Row Activation .................................. 19

Reads ............................................................ 20

Write Bursts .................................................. 25

Active Terminate .......................................... 25

Power-Down ................................................ 25

Clock Suspend ............................................. 25

Burst Read/Single Write ............................... 26

Truth Table 3 (CKE) .................................................. 27

Truth Table 4 (Current State, Same Bank) .................. 28

Truth Table 5 (Current State, Different Bank) ............. 29

Flash Memory Functional Description ............ 30

Flash Command Sequences .............................. 30

Hardware Command Sequence (HCS) ....... 30

Software Command Sequence (SCS) .......... 30

Memory Architecture ........................................ 31

Protected Blocks ........................................... 31

Command Execution Logic (CEL) ............... 31

Internal State Machine (ISM) ...................... 31

ISM Status Register ...................................... 31

Output (READ) Operations .............................. 32

Memory Array ............................................. 33

Status Register .............................................. 33

Device Configuration Register ..................... 33

Input Operations .............................................. 33

Memory Array ............................................. 33

Command Execution ........................................ 33

Status Register .............................................. 33

Device Configuration .................................. 34

Program Sequence ....................................... 34

Erase Sequence ............................................. 34

Program and Erase NVMode Register ......... 34

Block Protect/Unprotect Sequence .............. 35

Device Protect Sequence .............................. 35

Chip Initialize Sequence .............................. 35

Disable LCR Sequence .................................. 36

Reset/Deep Power-Down Mode ....................... 36

Error Handling .................................................. 36

Program/Erase Cycle Endurance ....................... 36

Absolute Maximum Ratings ............................. 45

DC Electrical Characteristics

and Operating Conditions .......................... 45

ICC Specifications and Conditions .................... 46

Capacitance ....................................................... 46

Electrical Characteristics and Recommended

AC Operating Conditions (Timing Table) .. 47

AC Functional Characteristics .......................... 48

Timing Waveforms

Initialize and Load Mode Register

RP# .............................................................. 49

FCS .............................................................. 50

Clock Suspend Mode ........................................ 51

Reads

Read ............................................................. 52

Alternating Bank Read Accesses .................. 53

Full-Page Burst ............................................. 54

DQM Operation .......................................... 55

Program/Erase

Bank a followed by READ to bank a .......... 56

Bank a followed by READ to bank b .......... 57

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

FUNCTIONAL BLOCK DIAGRAM

4 Meg x 16

RAS#

CAS#

CLK

CS#

WE#

CKE

COLUMN-

ADDRESS

COUNTER/

LATCH

A0–A11,

BA0, BA1

DQM0–

DQM1

ADDRESS

256

4,096

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK 0

MEMORY

ARRAY

(4,096 x 256 x 16)

BANK 0

ROW-

ADDRESS

LATCH

DECODER

High Voltage

Switch/Pump

4,096

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–

DQ15

BANK 1

BANK 2

BANK 3

2 2

COMMAND

EXECUTION

LOGIC

MODE REGISTER

COMMAND

DECODE

STATE MACHINE

STATUS REG.

NVMODE

DATA

INPUT

DATA

OUTPUT

RP#

ID REG.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

RAS#

CAS#

CLK

CS#

WE#

CKE

COLUMN-

ADDRESS

COUNTER/

LATCH

A0–A10,

BA0, BA1

DQM0–

DQM3

ADDRESS

256

8,192

I/O GATING

DQM MASK LOGIC

READ DATA LATCH

WRITE DRIVERS

COLUMN

DECODER

BANK 0

MEMORY

ARRAY

(2,048 x 256 x 32)

BANK 0

ROW-

ADDRESS

LATCH

DECODER

High Voltage

Switch/Pump

2,048

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

DQ0–

DQ31

BANK 1

BANK 2

BANK 3

4 4

COMMAND

EXECUTION

LOGIC

MODE REGISTER

COMMAND

DECODE

STATE MACHINE

STATUS REG.

NVMODE

DATA

INPUT

DATA

OUTPUT

RP#

ID REG.

FUNCTIONAL BLOCK DIAGRAM

2 Meg x 32

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

(continued on next page)

PIN AND BALL DESCRIPTIONS

TSOP PIN FBGA BALL

NUMBERS NUMBERS SYMBOL TYPE DESCRIPTION

68 J1 CLK Input Clock: CLK is driven by the system clock. All SyncFlash memory

input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers.

67 J2 CKE Input Clock Enable: CKE activates (HIGH) and deactivates (LOW) the

CLK signal. Deactivating the clock provides STANDBY operation or CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except after the device enters power-down modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CLK, are disabled during power-down modes, providing low standby power. CKE may be tied HIGH in systems where power-down modes (other than RP# deep power-down) are not required.

20 J8 CS# Input Chip Select: CS# enables (registered LOW) and disables

(registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code.

19, 18, 17 J9, K7, K8 RAS#, Input Command Inputs: RAS#, CAS#, and WE# (along with CS#)

CAS#, WE# define the command being entered.

16, 71 K9, K1 x16: DQM0, Input Input/Output Mask: DQM is an input mask signal for write

DQM1 accesses and an output enable signal for read accesses. Input

data is masked when DQM is sampled HIGH during a WRITE

16, 71, 28, K9, K1, F8, x32: DQM0 cycle. The output buffers are placed in a High-Z state (after a

59 F2 –DQM3 two-clock latency) when DQM is sampled HIGH during a READ

cycle. For x16, DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15. For x32, DQM0 corresponds to DQ0–DQ7, DQM1 corresponds to DQ8–DQ15, DQM2 corresponds to DQ16–DQ23, DQM3 corresonds to DQ24–DQ31. DQM0–DQM3 are in the same state when referenced as DQM.

25–27, G8, G9, F7, A0–A11 Input Address Inputs: A0–A11 are sampled during the ACTIVE

60–66, 24, F3, G1, G2, command (row address A0–A11 [x16]; A0–A10 [x32]) and

70 G3, H1, H2, READ/WRITE command (column-address A0–A7) to select one

J3, K3, G7 location in the respective bank. The address inputs provide the

op-code during a LOAD MODE REGISTER command and the com-code during an LCR command. For x16: A11 is pin 66 (J3), and A9 is pin 70 (K3).

22, 23 J7, H8 BA0, BA1 Input Bank Address Input(s): BA0, BA1 define to which bank the

ACTIVE, READ, or WRITE command is being applied.

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

PIN AND BALL DESCRIPTIONS (continued)

TSOP PIN FBGA BALL

NUMBERS NUMBERS SYMBOL TYPE DESCRIPTION

30 K2 RP# Input Initialize/Power-Down: Upon initial device power-up, a 100µs

delay after RP# has transitioned from LOW to HIGH is required for internal device initialization, prior to issuing an executable command. RP# clears the status register, sets the internal state machine (ISM) to the array read mode, and places the device in the deep power-down mode when LOW. All inputs, including CS#, are “Don’t Care” and all outputs are High-Z. When RP# = VHH, all protection modes are ignored during PROGRAM and ERASE. This input also allows the device protect bit to be set to “1” (protected) and allows the block protect bits at locations 0 and 15 to be set to “0” (unprotected). RP# must be held HIGH during all other modes of operation.

2, 4, 5, 7, R8, N7, R9, DQ0–DQ15 x16: I/O Data I/O: Data bus.

8, 10, 11, N8, P9, M8, 13, 74, 76, M7, L8, L2, 77, 79, 80, M3, M2, P1, 82, 83, 85, N2, R1, N3,

2, 4, 5, 7, R8, N7, R9, DQ0–DQ31 x32: I/O Data I/O: Data bus.

8, 10, 11, N8, P9, M8, 13, 74, 76, M7, L8, L2, 77, 79, 80, M3, M2, P1, 82, 83, 85, N2, R1, N3, 31, 33, 34, R2, E8, D7, 36, 37, 39, D8, B9, C8, 40, 42, 45, A9, C7, A8, 47, 48, 50, A2, C3, A1, 51, 53, 54, C2, B1, D2,

56 D3, E2

3, 9, 35, B2, B7, C9, VCCQ Supply DQ Power: Provide isolated power to DQs for improved noise

41, 49, D9, E1, L1, immunity.

55, 75, 81 M9, P2, P7,

6, 12, 32, B3, B8, C1, VSSQ Supply DQ Ground: Provide isolated ground to DQs for improved 38, 46, 52, D1, E9, L9, noise immunity.

78, 84 M1, N1, P3,

1, 15, 29, A7, F9, L7, VCC Supply Power Supply: 3.0V–3.6V.

43 R7

44, 58, 72, A3, F1, L3, VSS Supply Ground.

86 R3

(continued on next page)

64Mb: x16, x32

SYNCFLASH MEMORY

ADVANCE

PIN AND BALL DESCRIPTIONS (continued)

TSOP PIN FBGA BALL

NUMBERS NUMBERS SYMBOL TYPE DESCRIPTION

57 H3 VCCP Supply Program/Erase Supply Voltage: VCCP must be tied externally to

VCC. The VCCP pin sources current during device initialization, PROGRAM, and ERASE operations.

14, 21, 69, E3, E7, H7, NC – No Connect: These pins may be driven or left unconnected.

73 H9

31, 33, 34, E8, D7, D8, x16: DNU – Do Not Use. 36, 37, 39, B9, C8, A9, 40, 42, 45, C7, A8, A2, 47, 48, 50, C3, A1, C2, 51, 53, 54, B1, D2, D3,

56 E2 70 K3 x32: DNU

28, 59 F8, F2 x16: MCL – Must connect to Vss.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

SDRAM INTERFACE FUNCTIONAL DESCRIPTION

In general, the 64Mb SyncFlash memory devices (1 Meg x 16 x 4 banks, 512K x 32 x 4 banks) are configured as a quad-bank, nonvolatile SDRAM that operate at 3.0V–3.6V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256 columns by 16 bits. Each of the x32’s 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32 bits.

Read accesses to the SyncFlash memory are identical to SDR SDRAM operation. Burst accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, followed by a READ command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0 and BA1 select the bank; x32: A0–A10, x16: A0–A11 select the row). The address bits (A0–A7) registered coincident with the READ command are used to select the starting column location for the burst access.

All non-READ operations are controlled with either an HCS or an SCS. Both the HCS and an SCS interface can be used to initiate any of the internal program, erase, initialization, or status operations. The term Flash command sequence (FCS) refers to either HCS or SCS operation.

Prior to normal operation, the SyncFlash memory must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation.

Initialization

The device power-up procedure can be defined two ways. The first is a hardware initiated power-up, where power is applied to VCC, VCCQ, and VCCP (simultaneously). Then, with the clock stable, RP# must be brought from LOW to HIGH. After RP# transitions HIGH, the power-up initialization process will complete within 100µs. The second procedure is defined as a software initiated power-up. In this case the initialization is performed using the INITIALIZE DEVICE FCS operation. When the INITIALIZE DEVICE command is used, the RP# pin does not require the LOW-to-HIGH transition typically required for initialization. After the INITIALIZE DEVICE command has been issued, the power-up initialization process will complete within 100µs.

Early completion of either initialization procedure can be detected by polling SR7 in the status register. After initialization, the SyncFlash device is in standby

mode and ready for mode register programming or an executable command. After initial programming of the nvmode register, the contents are automatically loaded into the mode register during initialization and the device will power-up in the programmed state. Note that when VCC is greater than 2.7V, either of the initialization procedures can be issued.

MODE REGISTER

The mode register is used to define the specific mode of operation of the SyncFlash memory. This definition includes the selection of a burst length, a burst type, a CAS latency, and an operating mode, as shown in Figure 1. The mode register is programmed via the LOAD MODE REGISTER command and will retain the stored information until it is reprogrammed. The nvmode register settings are transferred into the mode register during initialization. The contents of the mode register may be copied into the nvmode register with a PROGRAM NVMODE REGISTER command. Details on erase nvmode register and program nvmode register command sequences are found in the Command Execution section of the Flash Memory Functional Description.

Mode register bits M0–M2 specify the burst length, M3 specifies the burst type (sequential or interleaved), M4–M6 specify the CAS latency, M7 and M8 specify the operating mode, M9 specifies the WRITE burst mode, and M10 and M11 are reserved for future use.

The mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation.

BURST LENGTH

Read and write accesses to the SyncFlash memory are burst oriented, with the burst length being programmable, as shown in Figure 1. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 1, 2, 4, or 8 locations are available for both the sequential and the interleaved burst types (read or write), and a full-page burst is available for the sequential type (read only). The full-page burst can be used in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

Figure 1

Mode Register Definition

Table 1

Burst Definition

Burst Starting Column Order of Accesses Within a Burst

Length Address Type = Sequential Type = Interleaved

0 0-1 0-1 1 1-0 1-0

A1 A0

0 0 0-1-2-3 0-1-2-3

0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0

A2 A1 A0

0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Full

n = A0–A7 Cn, Cn+1, Cn+2

Page Cn+3, Cn+4... Not supported

256 (location 0-255) …Cn-1,

Cn...

NOTE: 1. For a burst length of two, A1–A7 select the block-

of-two burst; A0 selects the starting column within the block.

2. For a burst length of four, A2–A7 select the blockof-four burst; A0–A1 select the starting column within the block.

3. For a burst length of eight, A3–A7 select the block-of-eight burst; A0–A2 select the starting column within the block.

4. For a full-page burst, the full row is selected and A0–A7 select the starting column.

5. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

6. For a burst length of one, A0–A7 select the unique column to be accessed, and mode register bit M3 is ignored.

7. Burst write (x32: 1, 2, 4, or 8 Dwords, x16: 1, 2, 4, or 8 words) is supported (not full page).

8. The contents of the mode register can be read using the READ DEVICE CONFIGURATION command (004h).

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

0-0-Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst LengthCAS Latency BT

A3A8A2

Mode Register (Mx)

Address Bus

654

382

M6-M0

Op Mode

A10

Reserved*

Write Burst Mode

Programmed Burst Length

Single Location Access

*Program M11, M10 = “0, 0” to ensure compatibility with future devices.

A11

When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1–A7 when the burst length is set to two, by A2–A7 when the burst length is set to four, and by A3– A7 when the burst length is set to eight. The remaining (least significant) address bit(s) are used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached.

NOTE: 1. A11 and M11 are supported only by 4 Meg x 16 configuration.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

Figure 2

CAS Latency

CLK

T2T1 T3T0

CAS Latency = 3

OUT

COMMAND

NOPREAD

NOP

DON’T CARE

UNDEFINED

CLK

T2T1T0

CAS Latency = 1

OUT

COMMAND

NOPREAD

CLK

T2T1 T3T0

CAS Latency = 2

OUT

COMMAND

NOPREAD

NOP

Table 2

CAS Latency

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS CAS CAS

SPEED LATENCY = 1 LATENCY = 2 LATENCY = 3

-7E

133

143

-75

100

133

BURST TYPE

Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table 1.

CAS LATENCY

The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to one, two, or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQs will start driving as a result of the clock edge one cycle earlier (n + m - 1), and provided that the relevant access times are met, the data will be valid by clock edge n + m. For example, assuming that

the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQs will start driving after T1 and the data will be valid by T2, as shown in Figure 2. Table 2 indicates the operating frequencies at which each CAS latency setting can be used.

Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

OPERATING MODE

The normal operating mode is selected by setting M7 and M8 to zero; the other combinations of values for M7 and M8 are reserved for future use and/or test modes. The programmed burst length applies to READ and WRITE bursts (full-page burst WRITE not supported).

Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.

WRITE BURST MODE

When M9 = 0, the burst length programmed via M0–M2 applies to both read and write bursts; however, if full-page burst length is selected in conjunction with M9 = 0, the burst write length is 8 words for the x16 and 8-Dwords for the x32 (not full page). When M9 = 1, the programmed burst length applies to READ bursts, but write accesses are single-location (nonburst) accesses.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

COMMANDS

Truth Table 1 provides a quick reference of available commands for SDRAM-compatible operation. This is followed by a written description of each command. Additional truth tables appear later.

TRUTH TABLE 1 SDRAM-COMPATIBLE INTERFACE COMMANDS AND DQM OPERATION

(Notes: 1)

NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQs NOTES

COMMAND INHIBIT (NOP) H XXXX X X NO OPERATION (NOP) L H H H X X X ACTIVE (Select bank and activate row) L L H H X Bank/Row X 2 READ (Select bank, column and start READ burst) L H L H X Bank/Col X 3 WRITE (Select bank, column and start WRITE) L H L L X Bank/Col Valid 3, 4 BURST TERMINATE L H H L X X Active ACTIVE TERMINATE L L H L X X X 5 LOAD COMMAND REGISTER L L L H X Com-Code X 6, 7 LOAD MODE REGISTER LLLLXOp-Code X 8 Write Enable/Output Enable ––––L – Active 9 Write Inhibit/Output High-Z ––––H – High-Z 9

NOTE: 1. CKE is HIGH for all commands shown.

2. x32: A0–A10, x16: A0–A11 provide row address, and BA0 and BA1 determine which bank is made active.

3. A0–A7 provide column address, and BA0 and BA1 determine which bank is being read from or written to.

4. A PROGRAM SETUP command sequence (see Truth Table 2a) must be completed prior to executing a WRITE.

5. ACTIVE TERMINATE is functionally equivalent to the SDRAM PRECHARGE command; however, PRECHARGE (deactivate row in bank or banks) is not required for SyncFlash memory. A10 LOW: BA0 and BA1 determine the bank to be active terminated. A10 HIGH: All banks are active terminated and BA0 and BA1 are “Don’t Care.”

6. A0–A7 define the com-code, and A8–A11 are “Don’t Care” for this operation. See Truth Table 2a.

7. LOAD COMMAND REGISTER (LCR) replaces the SDRAM auto refresh or self refresh mode, which is not required for SyncFlash memory. LCR is the first cycle for Flash memory hardware command sequences (HCS). See Truth Table 2a. After the hardware LCR function is disabled, SyncFlash will treat SDRAM REFRESH or AUTO REFRESH commands as NOPs. A software command sequence (SCS) is available to perform all operations described in Truth Table 2b.

8. A0–A10 define the op-code written to the mode register. The mode register can be dynamically loaded each cycle, provided tMRD is satisfied. The default mode register value is stored in the nvmode register. The contents of the nvmode register are automatically loaded into the mode register during device initialization.

9. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

64Mb: x16, x32 SyncFlash Micron Technology, Inc., reserves the right to change products or specifications without notice.

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

COMMANDS

The following Truth Tables provide a quick reference of available commands for Flash memory interface operation. A written description of each command is found in the Flash Memory Functional Description section.

TRUTH TABLE 2a – HARDWARE COMMAND SEQUENCES (HCS)

(Notes: 1–5; see notes on page 17)

FIRST CYCLE SECOND CYCLE THIRD CYCLE

BANK BANK BANK

OPERATION CMD ADDR6ADDR DQ RP# CMD7ADDR ADDR DQ RP# CMD ADDR ADDR DQ8RP#9NOTES

READ DEVICE CONFIGURATION LCR 90h Bank X H ACTIVE CA

ROW

Bank X H READ CA

COL

Bank X H 11, 12 READ STATUS REGISTER LCR 70h X X H ACTIVE X X X H READ X X X H CLEAR STATUS REGISTER LCR 50h X X H ERASE SETUP/CONFIRM LCR 20h Bank X H ACTIVE Row Bank X H WRITE X Bank D0h H/VHH12, 13, 14 PROGRAM SETUP/CONFIRM LCR 40h Bank X H ACTIVE Row Bank X H WRITE Col Bank D

H/VHH12, 13,

14, 15

PROTECT BLOCK/CONFIRM LCR 60h Bank X H ACTIVE Row

Bank X H WRITE X Bank LBDa(IN) H/VHH12, 13,

15, 16 PROTECT DEVICE/CONFIRM LCR 60h Bank X H ACTIVE X Bank X H WRITE X Bank LBDa(IN)VHH12, 13, 16 UNPROTECT BLOCKS/CONFIRM LCR 60h Bank X H ACTIVE X Bank X H WRITE X Bank LBDb(

) H/VHH12, 13,

14, 15, 16 UNPROTECT DEVICE/CONFIRM LCR 60h Bank X H ACTIVE X Bank X H WRITE X Bank LBDb(IN)VHH12, 13, 16 ERASE NVMODE REGISTER LCR 30h Bank X H ACTIVE X Bank X H WRITE X Bank C0h H 12, 13 PROGRAM NVMODE REGISTER LCR A0h Bank L X H ACTIVE X Bank L X H WRITE X Bank L X H 12, 13,

17, 18

DISABLE HARDWARE LCR LCR A0h Bank U X H ACTIVE X Bank U X H WRITE X Bank U X H 12, 13,

17, 18, 19 CHIP INITIALIZE LCR 68h Bank X H ACTIVE X Bank X H WRITE X Bank C0h H 12, 13

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

TRUTH TABLE 2b – SOFTWARE COMMAND SEQUENCES (SCS)

(Notes: 1, 2, 4, 5; see notes on page 17)

(continued on next page)

OPERATION FIRST SECOND THIRD FOURTH FIFTH SIXTH SEVENTH EIGHTH

CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE

READ DEVICE CONFIGURATION

Command Active Write Active Read ADDR = 88h 90h CA ROW CACOL Bank Address = X X Bank

Bank

DQ = XXXX RP# = H H H H

READ STATUS REGISTER

Command Active Write Active Read ADDR = 88h 70h X X Bank Address = X X X X DQ = X X X X RP# = H H H H

CLEAR STATUS REGISTER

Command Active Write ADDR = 88h 50h Bank Address = X X DQ = X X RP# = H H

ERASE SETUP/CONFIRM

Command Active Write Active Write Active Write Active Write ADDR = X 55h 55h 2Ah 80h 20h Row X Bank Address = X Bank

Bank

D Q = X X X 55 h X A0h X D0h RP# = H H H H H H H H/ VHH

PROGRAM SETUP/CONFIRM

Command Active Write Active Write Active Write Active Write ADDR = X 55h 55h 2Ah 80h 40h Row Col Bank Address = X Bank

Bank

DQ = X X X 55h X A0h X DIN RP#9 = HHHHHHHH/VHH

PROTECT BLOCK/CONFIRM

Command Active Write Active Write Active Write Active Write ADDR = X 55h 55h 2Ah 80h 60h Row

Bank Address = X Bank

Bank

DQ = X X X 55 X A0h X LBDa(IN)

RP#9 = HHHHHHHH/VHH

PROTECT DEVICE/CONFIRM

Command Active Write Active Write Active Write Active Write ADDR = X 55h 55h 2Ah 80h 60h X X Bank Address = X Bank

Bank

DQ = X X X 55h X A0h X LBDa(IN)

RP#9 = HHHHHHHVHH

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

TRUTH TABLE 2b – SOFTWARE COMMAND SEQUENCES (SCS) (continued)

(Notes: 1, 2, 4, 5; see notes on page 17)

OPERATION FIRST SECOND THIRD FOURTH FIFTH SIXTH SEVENTH EIGHTH

CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE CYCLE

UNPROTECT BLOCKS/CONFIRM

10, 16

Command Active Write Active Write Active Write Active Write ADDR = X 55 h 5 5h 2Ah 80h 60h X X Bank Address = X Bank

Bank

DQ = X X X 55h X A0h X LBDb(IN)

RP#5 = HHHHHHHVHH

UNPROTECT DEVICE/CONFIRM

Command Active Write Active Write Active Write Active Write ADDR = X 55 h 5 5h 2Ah 80h 60h X X Bank Address = X Bank

Bank

DQ = X X X 55h X A0h X LBDb(IN)

RP#5 = HHHHHHHH/VHH

ERASE NVMODE REGISTER

Command Active Write Active Write Active Write Active Write ADDR = X 55 h 5 5h 2Ah 80h 30h X X Bank Address = X Bank

Bank

DQ = X X X 55h X A0h X C0h RP# = H H H H H H H H

PROGRAM NVMODE REGISTER

Command Active Write Active Write Active Write Active Write ADDR = X 55 h 5 5h 2Ah 80h A0h X X Bank Address = X Bank L

Bank L

DQ = X X X 55h X A0h X X RP# = H H H H H H H H

DISABLE HARDWARE LCR

Command Active Write Active Write Active Write Active Write ADDR = X 55 55h 2Ah 80h A0h X X Bank Address = X Bank U

Bank U

Bank U12Bank U

12,18

Bank U

12,18

Bank U

12,18

DQ = X X X 55h X A0h X X RP# = H H H H H H H H

CHIP INITIALIZE

Command Active Write Active Write Active Write Active Write ADDR = X 55 h 5 5h 2Ah 80h 68h X X Bank Address = X Bank

Bank

DQ = X X X 55h X A0h X C0h RP# = H H H H H H H H

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

NOTE: 1. CMD = Command: decoded from CS#, RAS#, CAS#, and WE# inputs.

2. NOP/COMMAND INHIBIT/BURST TERMINATE/ACTIVE TERMINATE commands can be issued throughout the HCS or SCS. Additionally, LOAD COMMAND REGISTER may be issued throughout the SCS.

3. After a PROGRAM or ERASE operation is registered to the ISM and prior to completion of the ISM operation, a READ to any location in the bank under ISM control will output the contents of the row activated prior to the LCR/active/write sequence (see Note 14).

4. To meet the tRCD specification, the appropriate number of NOP/COMMAND INHIBIT commands must be issued between ACTIVE and READ/WRITE commands.

5. The ERASE, PROGRAM, PROTECT, and UNPROTECT operations are self-timed. The status register may be polled to monitor these operations.

6. x32: A8–A10, x16: A8–A11 are “Don’t Care.”

7. A row will not be opened when ACTIVE is preceded by LCR. ACTIVE is considered a NOP.

8. x32 Data Inputs, DQ8–DQ31 are “Don’t Care” except for DIN, where all DQ31–DQ0 are driven. x16 Data Inputs, DQ8–DQ15 are "Don’t Care" except for DIN, where all DQ15–DQ0 are driven. Data Outputs: All unused bits are driven LOW.

9. VHH = 7.0V–8.5V

10. Address must be any row address in the block desired to be protected

11. CAROW, CACOL = Configuration address This value changes depending on the bit location being accessed

CAROW = X02h for block protect bit, which corresponds to the block row address: x32: X = 0, 2, 4, or 6h

x16: X = 0, 4, 8, or Ch

For all other bits CAROW = XXXh (“Don’t Care”)

CACOL = Values shown below

00h = Manufacturer compatibility ID = 2Ch 01h = Device ID MT28S4M16B1 = D5h

Device ID MT28S2M32B1 = D4h 02h = Block protect bit (BPB) 03h = Device protect bit (DPB) 04h = Mode register 05h = Hardware load command register (LCR) bit

06h/07h = Reserved for future use

12. BA = Bank address must match for all the cycles, except for manufacturer ID/device ID/device protect where it is xxh.

13. The proper command sequence (LCR/active/write) is needed to initiate an ERASE, PROGRAM, PROTECT, or UNPROTECT operation.

14. If the device protect bit is not set, RP# = VIH unprotects all sixteen ( x32: 128K-Dword, x16: 256K-word ) erasable blocks, except for blocks 0 and 15. When RP# = VHH, all sixteen ( x32: 128K-Dword, x16: 256K-word) erasable blocks (including blocks 0 and 15) will be unprotected, and the device protect bit will be ignored. If the device protect bit is set and RP# = VIH, the block protect bits cannot be modified.

15. If the device protect bit is set, then an ERASE, PROGRAM, PROTECT, or UNPROTECT operation can still be initiated by bringing RP# to VHH prior to the WRITE command cycle and holding it at VHH until the operation is completed.

16. LBDa = Lock bit data

01h = Set block protect bit F1h = Set device protect bit If the DPB is not set, RP# = VIH; all blocks can be set If the DPB is set, RP# = VIH; BPBs cannot be modified

RP# = VHH; all BPBs can be modified

To set DPB, RP# = VHH is a must

RP# = VHH; all blocks including 0 and 15 are unprotected (reset); DPB does not matter

LBDb = Lock bit data

D0h = Clear block and device protect bits If the DPB is not set, RP# = VIH; all blocks except 0 and 15 are unprotected (reset) If the DPB is set, RP# = VIH; block protect bits cannot be modified

RP# = VHH; all blocks including 0, 15, and DPB are unprotected (reset)

17. Bank L: [BA1,BA0] = [0,0] or [0,1] Bank U: [BA1 BA0] = [1,0] or [1,1]

18. If [BA1, BA0] = [0,0] or [0,1], then WRITE NVMODE REGISTER operation is performed. If [BA1, BA0] = [1,0] or [1,1], then DISABLE HARDWARE LCR operation is performed.

19. Hardware LCR is preset to “1.” Hardware LCR bit is a one time programmable bit and cannot be reset to “1” after programmed to “0.”

ADVANCE

64Mb: x16, x32

SYNCFLASH MEMORY

SDRAM

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new commands from being executed by the SyncFlash memory, regardless of whether the CLK signal is enabled. The SyncFlash memory is effectively deselected. Operations already in progress are not affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to perform a NOP to a SyncFlash memory that is selected (CS# is LOW). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.

LOAD MODE REGISTER

The mode register is loaded via inputs A0–A10. See the mode register heading in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until

MRD is met. The data in the nvmode register is automatically loaded into the mode register upon powerup initialization and is the default mode setting unless dynamically changed with the LOAD MODE REGISTER command.

ACTIVE

The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs (x32: A0–A10, x16: A0–A11) selects the row. This row remains active for accesses until the next ACTIVE command, power-down or reset.

READ

The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A7 selects the starting column location. Read data appears on the DQs subject to the logic level on the DQM input two clocks earlier. If a given DQM signal was registered HIGH, the corresponding DQs will be High-Z two clocks later; if the DQM signal was registered LOW, the DQs will provide valid data.

WRITE

The WRITE command is used to initiate a burst write access. A WRITE command must be preceded by LCR/ ACTIVE. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0–A7 selects the column location.

Input data appearing on the DQs is written to the memory array, subject to the DQM input logic level appearing coincident with the data. If a given DQM signal is registered LOW, the corresponding data will be written to memory; if the DQM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that word/column location. A WRITE command with DQM HIGH is considered a NOP.

ACTIVE TERMINATE

ACTIVE TERMINATE, which replaces the SDRAM PRECHARGE command, is not required for SyncFlash memory, but is functionally equivalent to the SDRAM PRECHARGE command. ACTIVE TERMINATE can be issued to terminate a BURST READ in progress and may or may not be bank specific.

BURST TERMINATE

The BURST TERMINATE command is used to truncate either fixed-length or full-page bursts. The most recently registered READ or WRITE command prior to the BURST TERMINATE command will be truncated as shown in the Operation section of this data sheet. BURST TERMINATE is not bank specific.

LOAD COMMAND REGISTER (HCS ONLY)

The LOAD COMMAND REGISTER command in the HCS is used to initiate Flash memory control commands to the command execution logic (CEL). The CEL receives and interprets commands to the device. These commands control the operation of the internal state machine and the read path (i.e., memory array, ID register or status register). However, there are restrictions on what commands are allowed in this condition. See the Command Execution section of Flash Memory Functional Description for more details.

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Specifications and Main Features

Frequently Asked Questions

User Manual