MICRON MT28F642D18FN-805TET, MT28F642D20FN-704BET, MT28F642D18FN-804TET, MT28F642D18FN-704BET, MT28F642D18FN-704TET Datasheet
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1
4 Meg x 16 Async/Page/Burst Flash Memory ©2002, Micron Technology, Inc.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
‡
‡
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.
FLASH MEMORY
MT28F642D18
MT28F642D20
Low Voltage, Extended Temperature
0.18µm Process Technology
PIN ASSIGNMENT
59-Ball FBGA
FEATURES
• Single device supports asynchronous, page, and
burst operations
• Flexible dual-bank architecture
Support for true concurrent operation with zero
latency
Read bank a during program bank b and vice
versa
Read bank a during erase bank b and vice versa
• Basic configuration:
One hundred and thirty-five erasable blocks
Bank a (16Mb for data storage)
Bank b (48Mb for program storage)
•V
CC, VCCQ, VPP voltages
1.70V (MIN), 1.90V (MAX) VCC, VCCQ
(MT28F642D18 only)
1.80V (MIN), 2.20V (MAX) VCC, and
2.25V (MAX) VCCQ (MT28F642D20 only)
1.80V (TYP) VPP (in-system PROGRAM/ERASE)
12V ±5% (HV) VPP tolerant (factory programming
compatibility)
• Random access time: 70ns @ 1.80V VCC
1
• Burst Mode read access
MAX clock rate: 54 MHz (tCLK = 18.5ns)
Burst latency: 70ns @ 1.80V VCC and 54 MHz
t
ACLK: 15ns @ 1.80V VCC and 54 MHz
• Page Mode read access
1
Four-/eight-word page
Interpage read access: 70ns @ 1.80V
Intrapage read access: 30ns @ 1.80V
• Low power consumption (VCC = 2.20V)
Asynchronous Read < 15mA
Interpage Read < 15mA
Intrapage Read < 5mA
Continuous Burst Read < 10mA
WRITE < 55mA (MAX)
ERASE < 45mA (MAX)
Standby < 50µA (MAX)
Automatic power save (APS) feature
Deep power-down < 25µA (MAX)
• Enhanced write and erase suspend options
• Accelerated programming algorithm (APA) in-
system and in-factory
• Dual 64-bit chip protection registers for security
purposes
NOTE: See page 7 for Ball Description Table.
See page 50 for mechanical drawing.
• Cross-compatible command support
Extended command set
Common flash interface
• PROGRAM/ERASE cycle
100,000 WRITE/ERASE cycles per block
OPTIONS MARKING
• Timing
80ns access -80
70ns access -70
• Frequency
40 MHz 4
54 MHz 5
• Boot Block Configuration
Top T
Bottom B
• Package
59-ball FBGA (8 x 7 ball grid) FN
• Operating Temperature Range
Extended (-40ºC to +85ºC) ET
Part Number Example:
MT28F642D20FN-804 TET
A
B
C
D
E
F
G
1 2 3 4 5 6 7 8
Top View
(Ball Down)
A11
A12
A13
A15
V
CC
Q
V
SS
DQ7
A18
A17
A19
WP#
DQ1
DQ9
V
CC
Q
V
PP
RST#
WE#
DQ12
DQ2
DQ10
DQ3
V
SS
A20
A21
WAIT#
DQ6
DQ13
DQ5
A4
A3
A2
A1
A0
OE#
V
SS
Q
A6
A5
A7
CE#
DQ0
DQ8
A8
A9
A10
A14
DQ15
DQ14
V
SS
Q
V
CC
CLK
ADV#
A16
DQ4
DQ11
V
CC
NOTE: 1. Data based on MT28F642D20 device.
2
4 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ©2002, Micron Technology, Inc.
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
GENERAL DESCRIPTION
The MT28F642D20 and MT28F642D18 are highperformance, high-density, nonvolatile memory solutions that can significantly improve system
performance. This new architecture features a twomemory-bank configuration that supports dual-bank
operation with no latency.
A high-performance bus interface allows a fast burst
or page mode data transfer; a conventional asynchronous bus interface is provided as well.
The devices allow soft protection for blocks, as readonly, by configuring soft protection registers with dedicated command sequences. For security purposes, two
64-bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM). Two on-chip status registers, one for
each of the two memory partitions, can be used to monitor the WSM status and to determine the progress of
the program/erase task.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation software packages.
These devices are manufactured using 0.18µm process technology.
Please refer to the Micron Web site (www.micron.com/
flash) for the latest data sheet.
ARCHITECTURE AND MEMORY
ORGANIZATION
The Flash devices contain two separate banks of
memory (bank a and bank b) for simultaneous READ
and WRITE operations, which are available in the following bank segmentation configurations:
• Bank a comprises one-fourth of the memory and
contains 8 x 4K-word parameter blocks and
31 x 32K-word blocks.
• Bank b represents three-fourths of the memory, is
equally sectored, and contains 96 x 32K-word
blocks.
Figures 2 and 3 show the bottom and top memory
organizations.
DEVICE MARKING
Due to the size of the package, Micron’s standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to the Micron part
numbers in Table 1.
Table 1
Cross Reference for Abbreviated Device Marks
PRODUCT SAMPLE MECHANICAL
PART NUMBER MARKING MARKING SAMPLE MARKING
MT28F642D20FN-705 TET FW906 FX906 FY906
MT28F642D20FN-705 BET FW905 FX905 FY905
MT28F642D20FN-804 TET FW907 FX907 FY907
MT28F642D20FN-804 BET FW908 FX908 FY908
MT28F642D18FN-705 TET FW909 FX909 FY909
MT28F642D18FN-705 BET FW910 FX910 FY910
MT28F642D18FN-804 TET FW911 FX911 FY911
MT28F642D18FN-804 BET FW912 FX912 FY912
3
4 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ©2002, Micron Technology, Inc.
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
PART NUMBERING INFORMATION
Micron’s low-power devices are available with sev-
eral different combinations of features (see Figure 1).
Table 2
Valid Part Number Combinations
1
BOOT BLOCK BURST OPERATING
ACCESS STARTING FREQUENCY TEMPERATURE
PART NUMBER TIME (ns) ADDRESS (M H z) RANGE
MT28F642D20FN-705 TET 70 Top 54 -40oC to +85oC
MT28F642D20FN-705 BET 70 Bottom 54 -40oC to +85oC
MT28F642D20FN-804 TET 80 Top 40 -40oC to +85oC
MT28F642D20FN-804 BET 80 Bottom 40 -40oC to +85oC
MT28F642D18FN-705 TET 70 Top 54 -40oC to +85oC
MT28F642D18FN-705 BET 70 Bottom 54 -40oC to +85oC
MT28F642D18FN-804 TET 80 Top 40 -40oC to +85oC
MT28F642D18FN-804 BET 80 Bottom 40 -40
o
C to +85oC
MT 28F 642 D20 FN-80 4 B ET
Micron Technology
Flash Family
28F = Dual-Supply Flash
Density/Organization/Banks
642 = 64Mb (4,096K x 16)
bank a = 1/4; bank b = 3/4
Access Time
-70 = 70ns
-80 = 80ns
Read Mode Operation
D = Asynchronous/Page/Burst Read
Package Code
FN = 59-ball FBGA (8 x 7 grid)
Operating Temperature Range
ET = Extended (-40ºC to +85ºC)
Burst Mode Frequency
4 = 40 MHz
5 = 54 MHz
Boot Block Starting Address
B = Bottom boot
T = Top boot
Operating Voltage Range
18 = 1.70V–1.90V
20 = 1.80V–2.20V V
CC
20 = 1.80V–2.25V VCCQ
Figure 1
Part Number Chart
Valid combinations of features and their corresponding part numbers are listed in Table 2.
NOTE: 1. For part number combinations not listed in this table, please contact your Micron
representative.
4
4 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ©2002, Micron Technology, Inc.
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
FUNCTIONAL BLOCK DIAGRAM
Address
Input
Buffer
BSM
X DEC
Y/Z DEC
Data Input
Buffer
Output
Multiplexer
Address
CNT WSM
Output
Buffer
Status
Reg.
WSM
Program/
Erase
Pump Voltage
Generators
Address Latch
DQ0–DQ15
DQ0–DQ15
CSM
RST#
ADV#
WAIT#
CLK
CE#
X DEC
Y/Z DEC
WE#
OE#
I/O Logic
A0–A21
Address
Multiplexer
Bank 2 Blocks
Y/Z Gating/Sensing
Data
Register
Bank 1 Blocks
Y/Z Gating/Sensing
ID Reg.
RCR
Block Lock
Device ID
Manufacturer’s ID
OTP
Query
PR Lock
Query/OTP
PR Lock
5
4 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ©2002, Micron Technology, Inc.
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
Figure 2
Bottom Boot Block Device
Bank b = 48Mb
Block Block Size Address Range
(K-bytes/ (x16)
K-words)
134 64/32 3F8000h–3FFFFFh
133 64/32 3F0000h–3F7FFFh
132 64/32 3E8000h–3EFFFFh
131 64/32 3E0000h–3E7FFFh
130 64/32 3D8000h–3DFFFFh
129 64/32 3D0000h–3D7FFFh
128 64/32 3C8000h–3CFFFFh
127 64/32 3C0000h–3C7FFFh
126 64/32 3B8000h–3BFFFFh
125 64/32 3B0000h–3B7FFFh
124 64/32 3A8000h–3AFFFFh
123 64/32 3A0000h–3A7FFFh
122 64/32 398000h–39FFFFh
121 64/32 390000h–397FFFh
120 64/32 388000h–38FFFFh
119 64/32 380000h–387FFFh
118 64/32 378000h–37FFFFh
117 64/32 370000h–377FFFh
116 64/32 368000h–36FFFFh
115 64/32 360000h–367FFFh
114 64/32 358000h–35FFFFh
113 64/32 350000h–357FFFh
112 64/32 348000h–34FFFFh
111 64/32 340000h–347FFFh
110 64/32 338000h–33FFFFh
109 64/32 330000h–337FFFh
108 64/32 328000h–32FFFFh
107 64/32 320000h–327FFFh
106 64/32 318000h–31FFFFh
105 64/32 310000h–317FFFh
104 64/32 308000h–30FFFFh
103 64/32 300000h–307FFFh
102 64/32 2F8000h–2FFFFFh
101 64/32 2F0000h–2F7FFFh
100 64/32 2E8000h–2EFFFFh
99 64/32 2E0000h–2E7FFFh
98 64/32 2D8000h–2DFFFFh
97 64/32 2D0000h–2D7FFFh
96 64/32 2C8000h–2CFFFFh
95 64/32 2C0000h–2C7FFFh
94 64/32 2B8000h–2BFFFFh
93 64/32 2B0000h–2B7FFFh
92 64/32 2A8000h–2AFFFFh
91 64/32 2A0000h–2A7FFFh
90 64/32 298000h–29FFFFh
89 64/32 290000h–297FFFh
88 64/32 288000h–28FFFFh
87 64/32 280000h–287FFFh
Bank b = 48Mb
Block Block Size Address Range
(K-bytes/ (x16)
K-words)
Bank a = 16Mb
Block Block Size Address Range
(K-bytes/ (x16)
K-words)
38 64/32 0F8000h–0FFFFFh
37 64/32 0F0000h–0F7FFFh
36 64/32 0E8000h–0EFFFFh
35 64/32 0E0000h–0E7FFFh
34 64/32 0D8000h–0DFFFFh
33 64/32 0D0000h–0D7FFFh
32 64/32 0C8000h–0CFFFFh
31 64/32 0C0000h–0C7FFFh
30 64/32 0B8000h–0BFFFFh
29 64/32 0B0000h–0B7FFFh
28 64/32 0A8000h–0AFFFFh
27 64/32 0A0000h–0A7FFFh
26 64/32 098000h–09FFFFh
25 64/32 090000h–097FFFh
24 64/32 088000h–08FFFFh
23 64/32 080000h–087FFFh
22 64/32 078000h–07FFFFh
21 64/32 070000h–077FFFh
20 64/32 068000h–06FFFFh
19 64/32 060000h–067FFFh
18 64/32 058000h–05FFFFh
17 64/32 050000h–057FFFh
16 64/32 048000h–04FFFFh
15 64/32 040000h–047FFFh
14 64/32 038000h–03FFFFh
13 64/32 030000h–037FFFh
12 64/32 028000h–02FFFFh
11 64/32 020000h–027FFFh
10 64/32 018000h–01FFFFh
9 64/32 010000h–017FFFh
8 64/32 008000h–00FFFFh
7 8/4 007000h–007FFFh
6 8/4 006000h–006FFFh
5 8/4 005000h–005FFFh
4 8/4 004000h–004FFFh
3 8/4 003000h–003FFFh
2 8/4 002000h–002FFFh
1 8/4 001000h–001FFFh
0 8/4 000000h–00FFFh
86 64/32 278000h–27FFFFh
85 64/32 270000h–277FFFh
84 64/32 268000h–26FFFFh
83 64/32 260000h–267FFFh
82 64/32 258000h–25FFFFh
81 64/32 250000h–257FFFh
80 64/32 248000h–24FFFFh
79 64/32 240000h–247FFFh
78 64/32 238000h–23FFFFh
77 64/32 230000h–237FFFh
76 64/32 228000h–22FFFFh
75 64/32 220000h–227FFFh
74 64/32 218000h–21FFFFh
73 64/32 210000h–217FFFh
72 64/32 208000h–20FFFFh
71 64/32 200000h–207FFFh
70 64/32 1F8000h–1FFFFFh
69 64/32 1F0000h–1F7FFFh
68 64/32 1E8000h–1EFFFFh
67 64/32 1E0000h–1E7FFFh
66 64/32 1D8000h–1DFFFFh
65 64/32 1D0000h–1D7FFFh
64 64/32 1C8000h–1CFFFFh
63 64/32 1C0000h–1C7FFFh
62 64/32 1B8000h–1BFFFFh
61 64/32 1B0000h–1B7FFFh
60 64/32 1A8000h–1AFFFFh
59 64/32 1A0000h–1A7FFFh
58 64/32 198000h–19FFFFh
57 64/32 190000h–197FFFh
56 64/32 188000h–18FFFFh
55 64/32 180000h–187FFFh
54 64/32 178000h–17FFFFh
53 64/32 170000h–177FFFh
52 64/32 168000h–16FFFFh
51 64/32 160000h–167FFFh
50 64/32 158000h–15FFFFh
49 64/32 150000h–157FFFh
48 64/32 148000h–14FFFFh
47 64/32 140000h–147FFFh
46 64/32 138000h–13FFFFh
45 64/32 130000h–137FFFh
44 64/32 128000h–12FFFFh
43 64/32 120000h–127FFFh
42 64/32 118000h–11FFFFh
41 64/32 110000h–117FFFh
40 64/32 108000h–10FFFFh
39 64/32 100000h–107FFFh
6
4 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ©2002, Micron Technology, Inc.
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
Figure 3
Top Boot Block Device
Bank b = 48Mb
Block Block Size Address Range
(K-bytes/ (x16)
K-words)
95 64/32 2F8000h–2FFFFFh
94 64/32 2F0000h–2F7FFFh
93 64/32 2E8000h–2EFFFFh
92 64/32 2E0000h–2E7FFFh
91 64/32 2D8000h–2DFFFFh
90 64/32 2D0000h–2D7FFFh
89 64/32 2C8000h–2CFFFFh
88 64/32 2C0000h–2C7FFFh
87 64/32 2B8000h–2BFFFFh
86 64/32 2B0000h–2B7FFFh
85 64/32 2A8000h–2AFFFFh
84 64/32 2A0000h–2A7FFFh
83 64/32 298000h–29FFFFh
82 64/32 290000h–297FFFh
81 64/32 288000h–28FFFFh
80 64/32 280000h–287FFFh
79 64/32 278000h–27FFFFh
78 64/32 270000h–277FFFh
77 64/32 268000h–26FFFFh
76 64/32 260000h–267FFFh
75 64/32 258000h–25FFFFh
74 64/32 250000h–257FFFh
73 64/32 248000h–24FFFFh
72 64/32 240000h–247FFFh
71 64/32 238000h–23FFFFh
70 64/32 230000h–237FFFh
69 64/32 228000h–22FFFFh
68 64/32 220000h–227FFFh
67 64/32 218000h–21FFFFh
66 64/32 210000h–217FFFh
65 64/32 208000h–20FFFFh
64 64/32 200000h–207FFFh
63 64/32 1F8000h–1FFFFFh
62 64/32 1F0000h–1F7FFFh
61 64/32 1E8000h–1EFFFFh
60 64/32 1E0000h–1E7FFFh
59 64/32 1D8000h–1DFFFFh
58 64/32 1D0000h–1D7FFFh
57 64/32 1C8000h–1CFFFFh
56 64/32 1C0000h–1C7FFFh
55 64/32 1B8000h–1BFFFFh
54 64/32 1B0000h–1B7FFFh
53 64/32 1A8000h–1AFFFFh
52 64/32 1A0000h–1A7FFFh
51 64/32 198000h–19FFFFh
50 64/32 190000h–197FFFh
49 64/32 188000h–18FFFFh
48 64/32 180000h–187FFFh
Bank b = 48Mb
Block Block Size Address Range
(K-bytes/ (x16)
K-words)
Bank a = 16Mb
Block Block Size Address Range
(K-bytes/ (x16)
K-words)
134 8/4 3FF000h–3FFFFFh
133 8/4 3FE000h–3FEFFFh
132 8/4 3FD000h–3FDFFFh
131 8/4 3FC000h–3FCFFFh
130 8/4 3FB000h–3FBFFFh
129 8/4 3FA000h–3FAFFFh
128 8/4 3F9000h–3F9FFFh
127 8/4 3F8000h–3F8FFFh
126 64/32 3F0000h–3F7FFFh
125 64/32 3E8000h–3EFFFFh
124 64/32 3E0000h–3E7FFFh
123 64/32 3D8000h–3DFFFFh
122 64/32 3D0000h–3D7FFFh
121 64/32 3C8000h–3CFFFFh
120 64/32 3C0000h–3C7FFFh
119 64/32 3B8000h–3BFFFFh
118 64/32 3B0000h–3B7FFFh
117 64/32 3A8000h–3AFFFFh
116 64/32 3A0000h–3A7FFFh
115 64/32 398000h–39FFFFh
114 64/32 390000h–397FFFh
113 64/32 388000h–38FFFFh
112 64/32 380000h–387FFFh
111 64/32 378000h–37FFFFh
110 64/32 370000h–377FFFh
109 64/32 368000h–36FFFFh
108 64/32 360000h–367FFFh
107 64/32 358000h–35FFFFh
106 64/32 350000h–357FFFh
105 64/32 348000h–34FFFFh
104 64/32 340000h–347FFFh
103 64/32 338000h–33FFFFh
102 64/32 330000h–337FFFh
101 64/32 328000h–32FFFFh
100 64/32 320000h–327FFFh
99 64/32 318000h–31FFFFh
98 64/32 310000h–317FFFh
97 64/32 308000h–30FFFFh
96 64/32 300000h–307FFFh
47 64/32 178000h–17FFFFh
46 64/32 170000h–177FFFh
45 64/32 168000h–16FFFFh
44 64/32 160000h–167FFFh
43 64/32 158000h–15FFFFh
42 64/32 150000h–157FFFh
41 64/32 148000h–14FFFFh
40 64/32 140000h–147FFFh
39 64/32 138000h–13FFFFh
38 64/32 130000h–137FFFh
37 64/32 128000h–12FFFFh
36 64/32 120000h–127FFFh
35 64/32 118000h–11FFFFh
34 64/32 110000h–117FFFh
33 64/32 108000h–10FFFFh
32 64/32 100000h–107FFFh
31 64/32 0F8000h–0FFFFFh
30 64/32 0F0000h–0F7FFFh
29 64/32 0E8000h–0EFFFFh
28 64/32 0E0000h–0E7FFFh
27 64/32 0D8000h–0DFFFFh
26 64/32 0D0000h–0D7FFFh
25 64/32 0C8000h–0CFFFFh
24 64/32 0C0000h–0C7FFFh
23 64/32 0B8000h–0BFFFFh
22 64/32 0B0000h–0B7FFFh
21 64/32 0A8000h–0AFFFFh
20 64/32 0A0000h–0A7FFFh
19 64/32 098000h–09FFFFh
18 64/32 090000h–097FFFh
17 64/32 088000h–08FFFFh
16 64/32 080000h–087FFFh
15 64/32 078000h–07FFFFh
14 64/32 070000h–077FFFh
13 64/32 068000h–06FFFFh
12 64/32 060000h–067FFFh
11 64/32 058000h–05FFFFh
10 64/32 050000h–057FFFh
9 64/32 048000h–04FFFFh
8 64/32 040000h–047FFFh
7 64/32 038000h–03FFFFh
6 64/32 030000h–037FFFh
5 64/32 028000h–02FFFFh
4 64/32 020000h–027FFFh
3 64/32 018000h–01FFFFh
2 64/32 010000h–017FFFh
1 64/32 008000h–00FFFFh
0 64/32 000000h–007FFFh
7
4 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ©2002, Micron Technology, Inc.
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
BALL DESCRIPTIONS
59-BALL FBGA
NUMBERS SYMBOL TYPE DESCRIPTION
E8, D8, C8, B8, A0–A21 Input Address Inputs: Inputs for the addresses during READ and WRITE
A8, B7, A7, C7, operations. Addresses are internally latched during READ and WRITE
A2, B2, C2, A1, cycles.
B1, C1, D2, D1,
D4, B6, A6, C6,
B3, C3
B4 CLK Input Clock: Synchronizes the Flash memory to the system operating
frequency during synchronous burst mode READ operations. When
configured for synchronous burst mode READs, address is latched on
the first rising (or falling, depending upon the read configuration
register setting) CLK edge when ADV# is active or upon a rising ADV#
edge, whichever occurs first. CLK is ignored during asynchronous
access READ and WRITE operations and during READ PAGE ACCESS
operations.
1
C4 ADV# Input Address Valid: Indicates that a valid address is present on the address
inputs. Addresses are latched on the rising edge of ADV# during READ
and WRITE operations. ADV# may be tied active during asynchronous
READ and WRITE operations.
1
A5 VPP Input Program/Erase Enable: [0.9V–2.20V or 11.4V–12.6V] Operates as input
at logic levels to control complete device protection. Provides factory
programming compatibility when driven to 11.4V–12.6V.
E7 CE# Input Chip Enable: Activates the device when LOW. When CE# is HIGH, the
device is disabled and goes into standby power mode.
F8 OE# Input Output Enable: Enables the output buffers when LOW. When OE# is
HIGH, the output buffers are disabled.
C5 WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is
LOW, the cycle is either a WRITE to the command state machine (CSM)
or to the memory array.
B5 RST# Input Reset: When RST# is a logic LOW, the device is in reset mode, which
drives the outputs to High-Z and resets the write state machine (WSM).
When RST# is at logic HIGH, the device is in standard operation. When
RST# transitions from logic LOW to logic HIGH, the device resets all
blocks to locked and defaults to the read array mode.
D6 WP# Input Write Protect: Controls the lock down function of the flexible locking
feature.
F7, E6, E5, G5, DQ0–DQ15 Input/ Data Inputs/Outputs: Inputs array data on the second CE# and WE#
E4, G3, E3, G1, Output cycle during PROGRAM command. Inputs commands to the
G7, F6, F5, F4, command user interface when CE# and WE# are active. DQ0–DQ15
D5, F3, F2, E2 output data when CE# and OE# are active.
D3 WAIT# Output Wait: Provides data valid feedback during continuous burst read
access. The signal is gated by OE# and CE#. This signal is always kept at
a valid logic level.
NOTE: 1. The CLK and ADV# inputs can be tied to VSS if the device is always operating in asynchronous or page mode. The WAIT#
signal can be ignored when operating in asynchronous or page mode, as it is always held at logic “1” or “0,” depending
on the RCR8 setting (see Table 9).
(continued on next page)
8
4 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ©2002, Micron Technology, Inc.
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
BALL DESCRIPTIONS (continued)
59-BALL FBGA
NUMBERS SYMBOL TYPE DESCRIPTION
A4, G4 VCC Supply Device Power Supply: [1.70V–1.90V (MT28F642D18) or 1.80V–2.20V
(MT28F642D20)] Supplies power for device operation.
E1, G6 V
CCQ Supply I/O Power Supply: [1.70V–1.90V (MT28F642D18) or 1.80V–2.25V
(MT28F642D20)] Supplies power for input/output buffers.
G2, G8 VSSQ Supply I/O Ground. Do not float any ground ball.
A3, F1 VSS Supply Do not float any ground ball.
D7 – – Contact ball is not physically present.
9
4 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ©2002, Micron Technology, Inc.
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
COMMAND STATE MACHINE (CSM)
Commands are issued to the command state machine (CSM) using standard microprocessor write timings. The CSM acts as an interface between external
microprocessors and the internal write state machine
(WSM). The available commands are listed in Table 3,
their definitions are given in Table 4, and their descriptions in Table 5. Program and erase algorithms are automated by an on-chip WSM. Table 6 shows the CSM
transition states. Once a valid PROGRAM/ERASE command is entered, the WSM executes the appropriate
algorithm. The algorithm generates the necessary timing signals to control the device internally and accomplish the requested operation. A command is valid only
if the exact sequence of WRITEs is completed. After the
WSM completes its task, the WSM status bit (SR7) is set
to a logic HIGH level (1) (see Table 8), allowing the CSM
to respond to the full command set again.
OPERATIONS
Device operations are selected by entering a standard JEDEC 8-bit command code with conventional microprocessor timings into an on-chip CSM through I/Os
DQ0–DQ7. The number of bus cycles required to activate a command is typically one or two. The first operation is always a WRITE. Control signals CE#, ADV#, and
WE# must be at a logic LOW level (VIL), and OE# and RST#
must be at logic HIGH (VIH). The second operation, when
needed, can be a WRITE or a READ depending upon the
command. During a READ operation, control signals
CE#, ADV#, and OE# must be at a logic LOW level (VIL),
and WE# and RST# must be at logic HIGH (V
IH).
Table 7 illustrates the bus operations for all the
modes: write, read, reset, standby, and output disable.
When the device is powered up, internal reset circuitry initializes the chip to a read array mode of operation. Changing the mode of operation requires that a
command code be entered into the CSM. For each of
the memory partitions, an on-chip status register is
available. These two registers enable the progress of
various operations that take place on a memory bank
to be monitored. Either of the two status registers is
interrogated by entering a READ STATUS REGISTER
command onto the CSM (cycle 1), specifying an address within the memory partition boundary, and reading the register data on I/Os DQ0–DQ7 (cycle 2). Status
register bits SR0–SR7 correspond to DQ0–DQ7 (see
Table 8).
COMMAND DEFINITION
Once a specific command code has been entered,
the WSM executes an internal algorithm, generating
the necessary timing signals to program, erase, and
verify data. See Table 4 for the CSM command definitions and data for each of the bus cycles.
Table 3
Command State Machine Codes For Device Mode Selection
COMMAND DQ0–DQ7 CODE ON DEVICE MODE
10h Accelerated programming algorithm (APA)
20h Block erase setup
40h Program setup
50h Clear status register
60h Protection configuration setup
60h Set read configuration register
70h Read status register
90h Read protection configuration register
98h Read query
B0h Program/erase suspend
C0h Protection register program/lock
D0h Program/erase resume – erase confirm
D1h Check block erase confirm
FFh Read array
10
4 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ©2002, Micron Technology, Inc.
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
Table 4
Command Definitions
FIRST BUS CYCLE SECOND BUS CYCLE
COMMAND OPERATION ADDRESS1DATA OPERATION ADDRESS1DATA
READ ARRAY WRITE WA FFh
READ PROTECTION CONFIGURATION REGISTER WRITE IA 90h READ IA ID
READ STATUS REGISTER WRITE BA 70h READ X SRD
CLEAR STATUS REGISTER WRITE BA 50h
READ QUERY WRITE QA 98h READ QA QD
BLOCK ERASE SETUP WRITE BA 20h WRITE BA D0h
PROGRAM SETUP WRITE WA 40h WRITE WA WD
ACCELERATED PROGRAMMING ALGORITHM (APA) WRITE WA 10h WRITE WA WD
PROGRAM/ERASE SUSPEND WRITE BA B0h
PROGRAM/ERASE RESUME – ERASE CONFIRM WRITE BA D0h
LOCK BLOCK WRITE BA 60h WRITE BA 01h
UNLOCK BLOCK WRITE BA 60h WRITE BA D0h
LOCK DOWN BLOCK WRITE BA 60h WRITE BA 2Fh
CHECK BLOCK ERASE WRITE BA 20h WRITE BA D1h
PROTECTION REGISTER PROGRAM WRITE PA C0h WRITE PA PD
PROTECTION REGISTER LOCK WRITE LPA C0h WRITE LPA FFFDh
SET READ CONFIGURATION REGISTER WRITE RCD 60h WRITE RCD 03h
STATUS REGISTER
The status register allows the user to determine
whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored
by toggling OE# and CE# and reading the resulting
status code on I/Os DQ0–DQ7. The high-order I/Os
(DQ8–DQ15) are set to 00h internally, so only the loworder I/Os (DQ0–DQ7) need to be interpreted. Address
lines select the status register pertinent to the selected
memory partition.
Register data is updated and latched on the falling
edge of ADV# or the rising (falling) edge of CLK when
ADV# is LOW during synchronous burst mode, or on
the falling edge of OE# or CE#, whichever occurs last.
Latching the data prevents errors from occurring if the
register input changes during status register monitoring.
The status register provides a reading of the internal state of the WSM to the external microprocessor.
During periods when the WSM is active, the status register can be polled to determine the WSM status. Table
8 defines the status register bits.
After monitoring the status register during a PROGRAM/ERASE operation, the data appearing on
DQ0–DQ7 remains as status register data until a new
command is issued to the CSM. To return the device to
other modes of operation, a new command must be
issued to the CSM.
COMMAND STATE MACHINE
OPERATIONS
The CSM decodes instructions for the commands
listed in Table 3. The 8-bit command code is input to
the device on DQ0–DQ7 (see Table 3 for CSM codes
and Table 4 for command definitions). During a PROGRAM or ERASE cycle, the CSM informs the WSM that a
PROGRAM or ERASE cycle has been requested.
NOTE: 1. WA: Word address of memory location to be
written, or read
IA: Identification code address
BA: Address within the block
ID: Identification code data
SRD: Data read from the status register
QA: Query code address
QD: Query code data
WD: Data to be written at the location WA
PA: Protection register address
PD: Data to be written at the location PA
LPA: Lock protection register address
RCD: Data to be written in the read configuration
register
X: “Don’t Care”
11
4 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ©2002, Micron Technology, Inc.
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
Table 5
Command Descriptions
CODE DEVICE MODE BUS CYCLE DESCRIPTION
10h APA First Prepares the CSM for an ACCELERATED PROGRAM ALGORITHM
(APA) command.
20h Erase Setup First Prepares the CSM for the ERASE command. If the next command is
not a CHECK BLOCK ERASE or ERASE CONFIRM command, the
command will be ignored, and the bank will go to the read status
mode and wait for another command.
40h Program Setup First A two-cycle command: The first cycle prepares for a PROGRAM
operation, and the second cycle latches addresses and data and
initiates the WSM to execute the program algorithm. The Flash
outputs status register data on the rising edge of ADV#, or on the
rising clock edge when ADV# is LOW during synchronous burst
mode, or on the falling edge of OE# or CE#, whichever occurs first.
50h Clear Status First The WSM can set the block lock status (SR1), VPP status (SR3),
Register program status (SR4), and erase status (SR5) bits in the status register
to “1,” but it cannot clear them to “0.” Issuing this command clears
those bits to “0.”
60h Protection First Prepares the CSM for changes to the block locking status. If the next
Configuration command is not BLOCK UNLOCK, BLOCK LOCK, or BLOCK LOCK
Setup DOWN, the command will be ignored, and the device will go to the
read status mode.
Set Read First Puts the device into the set read configuration mode so that it will
Configuration be possible to set the option bits related to burst read mode.
Register
70h Read Status First Places the device into a read status register mode. Reading the
Register device will output the contents of the status register for the
addressed bank. The device will automatically enter this mode for
the addressed bank after a PROGRAM or ERASE operation has been
initiated.
90h Read Protection First Puts the device into the read protection configuration mode so that
Configuration reading the device will output the manufacturer/device codes, block
lock status, protection register, or protection register lock status.
98h Read Query First Puts the device into the read query mode so that reading the device
will output common flash interface information.
B0h Program Suspend First Issuing this command will suspend the currently executing
PROGRAM/ERASE/CHECK BLOCK ERASE operation. The status register
Erase Suspend will indicate when the operation has been successfully suspended by
setting either the program suspend (SR2) or erase suspend (SR6) bit,
Check Block and the WSM status bit (SR7) to a “1” (ready). The WSM will
Erase Suspend continue to idle in the suspend state, regardless of the state of all
input control signals except RST#, which will immediately shut down
the WSM and the remainder of the chip if RST# is driven to VIL.
(continued on next page)
12
4 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ©2002, Micron Technology, Inc.
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
Table 5
Command Descriptions (continued)
CODE DEVICE MODE BUS CYCLE DESCRIPTION
C0h Program Device First Writes a specific code into the device protection register.
Protection Register
Lock Device First Locks the device protection register; data can no longer be changed.
Protection Register
D0h Erase Confirm Second If the previous command was an ERASE SETUP command, then the
CSM will close the address and data latches, and it will begin erasing
the block indicated on the address balls. During programming/erase,
the device will respond only to the READ STATUS REGISTER,
PROGRAM SUSPEND, or ERASE SUSPEND command. It will output
status register data on the rising edge of ADV#, or on the rising clock
edge when ADV# is LOW during synchronous burst mode, or on the
falling edge of OE# or CE#, whichever occurs last.
Program/Erase/ First If a PROGRAM, ERASE or CHECK BLOCK ERASE operation was
Check Block Erase previously suspended, this command will resume the operation.
Resume
FFh Read Array First During read array mode, array data will be output on the data bus.
01h Lock Block Second If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM will latch the address and lock the block indicated on the
address bus.
03 h Read Configuration Second If the previous command was SET READ CONFIGURATION REGISTER,
Register Data the configuration bits presented on the address bus will be stored
into the read configuration register.
2Fh Lock Down Second If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM will latch the address and lock down the block indicated on
the address bus.
D0h Unlock Block Second If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM will latch the address and unlock the block indicated on the
address bus. If the block had been previously set to lock down, this
operation will have no effect.
D1h Check Block Second If the previous command was ERASE SETUP, the CSM will close the
Erase Confirm address latches and check to see that the block is completely erased.
00h Invalid/Reserved Unassigned command that should not be used.
13
4 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ©2002, Micron Technology, Inc.
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
READ PROTECTION CONFIGURATION DATA
The read protection configuration mode outputs
five types of information: the manufacturer/device
identifier, the block locking status, the read configuration register, the protection register, and PR lock status. Two bus cycles are required for this operation: the
chip identification data is read by entering the command code 90h on DQ0–DQ7 and the identification
code address on the address lines. Control signals CE#,
ADV#, and OE# must be at a logic LOW level (VIL), and
WE# and RST# must be at a logic HIGH level (V
IH) to
read data from the protection configuration register.
Data is available on DQ0–DQ15. After data is read from
the protection configuration register, the READ ARRAY
command, FFh, must be issued to the bank containing
address 00h prior to issuing other commands. See Table
13 for further details.
READ QUERY
The read query mode outputs common flash interface (CFI) data when the device is read (see Table 15).
Two bus cycles are required for this operation. It is
possible to access the query by writing the read query
command code 98h on DQ0–DQ7 to the bank containing address 0h. Control signals CE#, ADV#, and OE#
must be at a logic LOW level (V
IL) and WE# and RST#
must be at a logic HIGH level (VIH) to read data from the
query. The CFI data structure contains information
such as block size, density, command set, and electrical specifications. To return to read array mode, write
the read array command code FFh on DQ0–DQ7.
READ STATUS REGISTER
The status register is read by entering the command
code 70h on DQ0–DQ7. Two bus cycles are required for
this operation: one to enter the command code and a
second to read the status register. The addresses for
both cycles must be in the same partition. In a READ
cycle, the address is latched on the rising edge of the
ADV# signal. Register data is updated and latched on
the falling edge of ADV# or the rising (falling) CLK when
ADV# is LOW during burst mode, or on the falling edge
of OE# or CE#, whichever occurs last.
During a PROGRAM cycle, the WSM controls the
program sequences and the CSM responds to a PROGRAM SUSPEND command only.
During an ERASE cycle, the CSM responds to an
ERASE SUSPEND command only. When the WSM has
completed its task, the WSM status bit (SR7) is set to a
logic HIGH level and the CSM responds to the full command set. The CSM stays in the current command state
until the microprocessor issues another command.
The WSM successfully initiates an ERASE or PROGRAM operation only when V
PP is within its correct volt-
age range.
CLEAR STATUS REGISTER
The internal circuitry can set, but not clear, the block
lock status bit (SR1), the VPP status bit (SR3), the program status bit (SR4), and the erase status bit (SR5) of
the status register. The CLEAR STATUS REGISTER command (50h) allows the external microprocessor to clear
these status bits and synchronize to the internal operations. When the status bits are cleared, the device
returns to the read array mode.
READ OPERATIONS
The following READ operations are available: READ
ARRAY, READ PROTECTION CONFIGURATION REGISTER, READ QUERY and READ STATUS REGISTER.
READ ARRAY
The array is read by entering the command code
FFh on DQ0–DQ7. Control signals CE#, ADV#, and OE#
must be at a logic LOW level (VIL) and WE# and RST#
must be at a logic HIGH level (VIH) to read data from the
array. Data is available on DQ0–DQ15. Any valid address within any of the blocks selects that address and
allows data to be read from that address. Upon initial
power-up or device reset, the device defaults to the
read array mode.
14
4 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ©2002, Micron Technology, Inc.
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
Table 6
Command State Machine Transition Table
(continued on the next page)
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15
4 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ©2002, Micron Technology, Inc.
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
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Command State Machine Transition Table (continued)
(continued on the next page)
16
4 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28F642D18_3.p65 – Rev. 3, Pub. 8/02 ©2002, Micron Technology, Inc.
4 MEG x 16
ASYNC/PAGE/BURST FLASH MEMORY
ADVANCE
Table 6
Command State Machine Transition Table (continued)
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sutats
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