MICRON MT28F321P20FG-80T, MT28F321P20FG-80TET, MT28F321P20FG-90B, MT28F321P20FG-90BET, MT28F321P20FG-90T Datasheet

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PRELIMINARY

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PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S

PRODUCTION DATA SHEET SPECIFICATIONS.

FLASH MEMORY

MT28F321P20 MT28F321P18

Low Voltage, Extended Temperature

0.18µm Process Technology

BALL ASSIGNMENT

48-Ball FBGA

FEATURES

• Flexible dual-bank architecture Support for true concurrent operation with zero

latency

Read bank a during program bank b and vice

versa

Read bank a during erase bank b and vice versa

• Basic configuration: Seventy-one erasable blocks Bank a (4Mb for data storage) Bank b (28Mb for program storage)

•VCC, VCCQ, VPP voltages*

1.70V (MIN), 1.90V (MAX) VCC, VCCQ

(MT28F321P18)

1.80V (MIN), 2.20V (MAX) VCC, VCCQ

(MT28F321P20)

0.9V (MIN) VPP (in-system PROGRAM/ERASE) 12V ±5% (HV) VPP tolerant (factory

programming compatibility)

• Random access time: 70ns and 80ns @ 1.80V VCC*

• Page Mode read access* Eight-word page Interpage read access: 70ns/80ns @ 1.80V Intrapage read access: 30ns @ 1.80V

• Low power consumption (VCC = 2.20V) Asynchronous READ < 15mA Standby < 50µA

Automatic power save (APS) feature

• Enhanced write and erase suspend options ERASE-SUSPEND-to-READ within same bank PROGRAM-SUSPEND-to-READ within same bank ERASE-SUSPEND-to-PROGRAM within same bank

• Dual 64-bit chip protection registers for security

purposes

• Cross-compatible command support Extended command set Common flash interface

• PROGRAM/ERASE cycle 100,000 WRITE/ERASE cycles per block

* Data based on MT28F321P20 device.

NOTE: See page 7 for Ball Description Table.

See page 33 for mechanical drawing.

1 2 3 4 5 6 7 8

Top View

(Ball Down)

A13

A14

A15

A16

A19

A17

DQ8

DQ9

DQ10

WP#

A18

A20

DQ2

DQ3

WE#

DQ5

DQ6

DQ13

OE#

CE#

DQ0

DQ1

A11

A10

A12

DQ14

DQ15

DQ7

RST#

DQ11

DQ12

DQ4

OPTIONS MARKING

• Timing 70ns access -70 80ns access -80 90ns access -90

• Boot Block Configuration Top T Bottom B

• Package 48-ball FBGA (6 x 8 ball grid) FG

• Operating Temperature Range Extended (-40ºC to +85ºC) ET

Part Number Example:

MT28F321P20FG-70 TET

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GENERAL DESCRIPTION

The MT28F321P20 and MT28F321P18 are highperformance, high-density, nonvolatile memory solutions that can significantly improve system performance. This new architecture features a two-memorybank configuration that supports background operation with no latency.

A high-performance bus interface allows a fast page mode, data transfer; a conventional asynchronous bus interface is provided as well.

The devices allow soft protection for blocks, as read only, by configuring soft protection registers with dedicated command sequences. For security purposes, two 64-bit chip protection registers are provided.

The embedded WORD WRITE and BLOCK ERASE functions are fully automated by an on-chip write state machine (WSM). Two on-chip status registers, one for each of the two memory partitions, can be used to monitor the WSM status and to determine the progress of the program/erase task.

The erase/program suspend functionality allows compatibility with existing EEPROM emulation software packages.

The device is manufactured using 0.18µm process technology.

Please refer to Micron’s Web site (www.micron.com/

flash) for the latest data sheet.

ARCHITECTURE AND MEMORY ORGANIZATION

The Flash devices contain two separate banks of memory (bank a and bank b) for simultaneous READ and WRITE operations.

The Flash memory devices are available in the following bank segmentation configuration:

• Bank a comprises one-eighth of the memory and contains 8 x 4K-word parameter blocks; the remainder of bank a is split into 7 x 32Kword blocks.

• Bank b represents seven-eighths of the memory, is equally sectored, and contains 48 x 32K-word blocks.

Figures 2 and 3 show the bottom and top memory

organizations.

DEVICE MARKING

Due to the size of the package, Micron’s standard part number is not printed on the top of each device. Instead, an abbreviated device mark comprised of a five-digit alphanumeric code is used. The abbreviated device marks are cross referenced to Micron part numbers in Table 1.

Table 1

Cross Reference for Abbreviated Device Marks

PRODUCT SAMPLE MECHANICAL

PART NUMBER MARKING MARKING SAMPLE MARKING

MT28F321P20FG-70 BET FW818 FX818 FY818 MT28F321P20FG-70 TET FW819 FX819 FY819 MT28F321P20FG-80 BET FW810 FX810 FY810 MT28F321P20FG-80 TET FW811 FX811 FY811 MT28F321P18FG-90 BET FW820 FX820 FY820 MT28F321P18FG-90 TET FW821 FX821 FY821

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PRELIMINARY

PART NUMBERING INFORMATION

Micron’s low-power devices are available with sev-

eral different combinations of features (see Figure 1).

Table 2

Valid Part Number Combinations

BOOT BLOCK OPERATING

ACCESS STARTING TEMPERATURE

PART NUMBER TIME (ns) ADDRESS RANGE

MT28F321P20FG-70 BET 70 Bottom -40oC to +85oC MT28F321P20FG-70 TET 70 Top -40oC to +85oC MT28F321P20FG-80 BET 80 Bottom -40oC to +85oC MT28F321P20FG-80 TET 80 Top -40oC to +85oC MT28F321P18FG-90 BET 90 Bottom -40oC to +85oC MT28F321P18FG-90 TET 90 Top -40

C to +85oC

MT 28F 321 P20FG-70 T ET

Micron Technology

Flash Family

28F = Dual-Supply Flash

Density/Organization/Banks

321 = 32Mb (2,048K x 16) bank a = 1/8; bank b = 7/8

Access Time

-70 = 70ns

-80 = 80ns

-90 = 90ns

Read Mode Operation

P = Asynchronous/Page Read

Package Code

FG = 48-ball FBGA (6 x 8 grid)

Operating Temperature Range

ET = Extended (-40ºC to +85ºC)

Boot Block Starting Address

B = Bottom boot T = Top boot

Operating Voltage Range

18 = 1.70V–1.90V 20 = 1.80V–2.20V

Figure 1

Part Number Chart

Valid combinations of features and their corresponding part numbers are listed in Table 2.

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FUNCTIONAL BLOCK DIAGRAM

Address

Input

Buffer

X DEC

Y/Z DEC

Data Input

Buffer

Output

Multiplexer

Address

CNT WSM

Output

Buffer

Status

Reg.

WSM

Program/

Erase

Pump Voltage

Generators

Address Latch

DQ0–DQ15

CSM

RST#

CE#

X DEC

Y/Z DEC

WE#

OE#

I/O Logic

A0–A20

Address

Multiplexer

Bank 2 Blocks

Y/Z Gating/Sensing

Data

Bank 1 Blocks

Y/Z Gating/Sensing

ID Reg.

RCR

Block Lock

Device ID

Manufacturer’s ID

OTP

Query

PR Lock

Query/OTP

PR Lock

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Figure 2

Bottom Boot Block Device

Bank b = 28Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

70 64/32 1F8000h-1FFFFFh 69 64/32 1F0000h-1F7FFFh 68 64/32 1E8000h-1EFFFFh 67 64/32 1E0000h-1E7FFFh 66 64/32 1D8000h-1DFFFFh 65 64/32 1D0000h-1D7FFFh 64 64/32 1C8000h-1CFFFFh 63 64/32 1C0000h-1C7FFFh 62 64/32 1B8000h-1BFFFFh 61 64/32 1B0000h-1B7FFFh 60 64/32 1A8000h-1AFFFFh 59 64/32 1A0000h-1A7FFFh 58 64/32 198000h-19FFFFh 57 64/32 190000h-197FFFh 56 64/32 188000h-18FFFFh 55 64/32 180000h-187FFFh 54 64/32 178000h-17FFFFh 53 64/32 170000h-177FFFh 52 64/32 168000h-16FFFFh 51 64/32 160000h-167FFFh 50 64/32 158000h-15FFFFh 49 64/32 150000h-157FFFh 48 64/32 148000h-14FFFFh 47 64/32 140000h-147FFFh 46 64/32 138000h-13FFFFh 45 64/32 130000h-137FFFh 44 64/32 128000h-12FFFFh 43 64/32 120000h-127FFFh 42 64/32 118000h-11FFFFh 41 64/32 110000h-117FFFh 40 64/32 108000h-10FFFFh 39 64/32 100000h-107FFFh 38 64/32 0F8000h-0FFFFFh 37 64/32 0F0000h-0F7FFFh 36 64/32 0E8000h-0EFFFFh 35 64/32 0E0000h-0E7FFFh 34 64/32 0D8000h-0DFFFFh 33 64/32 0D0000h-0D7FFFh 32 64/32 0C8000h-0CFFFFh 31 64/32 0C0000h-0C7FFFh 30 64/32 0B8000h-0BFFFFh 29 64/32 0B0000h-0B7FFFh 28 64/32 0A8000h-0AFFFFh 27 64/32 0A0000h-0A7FFFh 26 64/32 098000h-097FFFh 25 64/32 090000h-097FFFh 24 64/32 088000h-087FFFh 23 64/32 080000h-087FFFh 22 64/32 078000h-07FFFFh 21 64/32 070000h-077FFFh 20 64/32 068000h-067FFFh 19 64/32 060000h-067FFFh 18 64/32 058000h-05FFFFh 17 64/32 050000h-057FFFh 16 64/32 048000h-04FFFFh 15 64/32 040000h-047FFFh

Bank a = 4Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

14 64/32 038000h-03FFFFh 13 64/32 030000h-037FFFh 12 64/32 028000h-02FFFFh 11 64/32 020000h-027FFFh 10 64/32 018000h-01FFFFh

9 64/32 010000h-017FFFh 8 64/32 008000h-00FFFFh 7 8/4 007000h-007FFFh 6 8/4 006000h-006FFFh 5 8/4 005000h-005FFFh 4 8/4 004000h-004FFFh 3 8/4 003000h-003FFFh 2 8/4 002000h-002FFFh 1 8/4 001000h-001FFFh 0 8/4 000000h-000FFFh

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Figure 3

Top Boot Block Device

Bank b = 28Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

55 64/32 1B8000h-1BFFFFh 54 64/32 1B0000h-1B7FFFh 53 64/32 1A8000h-1AFFFFh 52 64/32 1A0000h-1A7FFFh 51 64/32 198000h-19FFFFh 50 64/32 190000h-197FFFh 49 64/32 188000h-18FFFFh 48 64/32 180000h-187FFFh 47 64/32 178000h-17FFFFh 46 64/32 170000h-177FFFh 45 64/32 168000h-16FFFFh 44 64/32 160000h-167FFFh 43 64/32 158000h-15FFFFh 42 64/32 150000h-157FFFh 41 64/32 148000h-14FFFFh 40 64/32 140000h-147FFFh 39 64/32 138000h-13FFFFh 38 64/32 130000h-137FFFh 37 64/32 128000h-12FFFFh 36 64/32 120000h-127FFFh 35 64/32 118000h-11FFFFh 34 64/32 110000h-117FFFh 33 64/32 108000h-10FFFFh 32 64/32 100000h-107FFFh 31 64/32 0F8000h-0FFFFFh 30 64/32 0F0000h-0F7FFFh 29 64/32 0E8000h-0EFFFFh 28 64/32 0E0000h-0E7FFFh 27 64/32 0D8000h-0DFFFFh 26 64/32 0D0000h-0D7FFFh 25 64/32 0C8000h-0CFFFFh 24 64/32 0C0000h-0C7FFFh 23 64/32 0B8000h-0BFFFFh 22 64/32 0B0000h-0B7FFFh 21 64/32 0A8000h-0AFFFFh 20 64/32 0A0000h-0A7FFFh 19 64/32 098000h-09FFFFh 18 64/32 090000h-097FFFh 17 64/32 088000h-08FFFFh 16 64/32 080000h-087FFFh 15 64/32 078000h-07FFFFh 14 64/32 070000h-077FFFh 13 64/32 068000h-06FFFFh 12 64/32 060000h-067FFFh 11 64/32 058000h-05FFFFh 10 64/32 050000h-057FFFh

9 64/32 048000h-04FFFFh 8 64/32 040000h-047FFFh 7 64/32 038000h-03FFFFh 6 64/32 030000h-037FFFh 5 64/32 028000h-02FFFFh 4 64/32 020000h-027FFFh 3 64/32 018000h-01FFFFh 2 64/32 010000h-017FFFh 1 64/32 008000h-00FFFFh 0 64/32 000000h-007FFFh

Bank a = 4Mb

Block Block Size Address Range

(K-bytes/K-words) (x16)

70 8/4 1FF000h-1FFFFFh 69 8/4 1FE000h-1FEFFFh 68 8/4 1FD000h-1FDFFFh 67 8/4 1FC000h-1FCFFFh 66 8/4 1FB000h-1FBFFFh 65 8/4 1FA000h-1FAFFFh 64 8/4 1F9000h-1F9FFFh 63 8/4 1F8000h-1F8FFFh 62 64/32 1F0000h-1F7FFFh 61 64/32 1E8000h-1EFFFFh 60 64/32 1E0000h-1E7FFFh 59 64/32 1D8000h-1DFFFFh 58 64/32 1D0000h-1D7FFFh 57 64/32 1C8000h-1CFFFFh 56 64/32 1C0000h-1C7FFFh

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BALL DESCRIPTIONS

48-BALL FBGA

NUMBERS SYMBOL TYPE DESCRIPTION

D8, C8, B8, C7, A0–A20 Input Address Inputs: Inputs for the address during READ and WRITE A8, B7, C6, A7, operations. Addresses are internally latched during READ and WRITE A3, C3, B2, A2, cycles. C2, A1, B1, C1, D1, B6, B5, A6,

D7 CE# Input Chip Enable: Activates the device when LOW. When CE# is HIGH, the

device is disabled and goes into standby power mode.

F8 OE# Input Output Enable: Enables the output buffer when LOW. When OE# is

HIGH, the output buffers are disabled.

B3 WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If WE# is

LOW, the cycle is either a WRITE to the command state machine (CSM) or to the memory array.

B4 RST# Input Reset: When RST# is a logic LOW, the device is in reset mode, which

drives the outputs to High-Z and resets the write state machine (WSM). When RST# is at logic HIGH, the device is in standard operation. When RST# transitions from logic LOW to logic HIGH, the device resets all blocks to locked and defaults to the read array mode.

A5 WP# Input Write Protect: Controls the lock down function of the flexible locking

feature.

A4 VPP Input Program/Erase Enable: [0.9V–2.2V or 11.4V–12.6V] Operates as input

at logic levels to control complete device protection. Provides factory programming compatibility when driven to 11.4V–12.6V.

E7, F7, D5, B5, DQ0–DQ15 Input/ Data Inputs/Outputs: Input array data on the second CE# and WE# F4, D3, E3, F2, Output cycle during PROGRAM command. Input commands to the

D6, 36, F6, D4, command user interface when CE# and WE# are active. DQ0–DQ15

E4, F3, D2, E2 output data when CE# and OE# are active.

E8, F1 VSS Supply Do not float any ground ball.

F5 VCC Supply Device Power Supply: [1.70V–1.90V (MT28F321P18) or 1.80V–2.20V

(MT28F321P20)] Supplies power for device operation.

E1 VCCQ Supply I/O Power Supply: [1.70V–1.90V (MT28F321P18) or 1.80V–2.20V

(MT28F321P20)] Supplies power for input/output buffers.

C4 NC – Internally not connected.

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COMMAND STATE MACHINE (CSM)

Commands are issued to the command state machine (CSM) using standard microprocessor write timings. The CSM acts as an interface between external microprocessors and the internal WSM. The available commands are listed in Table 3, their definitions are given in Table 4, and their descriptions in Table 5. Program and erase algorithms are automated by an on-chip WSM. For more specific information about the CSM transition states, see Micron technical note TN-28-33, “Command State Machine Description and Command Definition.”

Once a valid PROGRAM/ERASE command is entered, the WSM executes the appropriate algorithm, which generates the necessary timing signals to control the device internally and accomplish the requested operation. A command is valid only if the exact sequence of WRITEs is completed. After the WSM completes its task, the WSM status bit (SR7) (see Table 7) is set to a logic HIGH level (1), allowing the CSM to respond to the full command set again.

OPERATIONS

Device operations are selected by entering a standard JEDEC 8-bit command code with conventional microprocessor timings into an on-chip CSM through I/Os DQ0–DQ7. The number of bus cycles required to activate a command is typically one or two. The first operation is always a WRITE. Control signals CE# and WE# must be at a logic LOW level (VIL), and OE# and RST# must be at logic HIGH (VIH). The second operation, when needed, can be a WRITE or a READ depending upon the command. During a READ operation, control signals CE# and OE# must be at a logic LOW

level (VIL), and WE# and RST# must be at logic HIGH (VIH).

Table 6 shows the bus operations for all the modes:

write, read, reset, standby, and output disable.

When the device is powered up, internal reset circuitry initializes the chip to a read array mode of operation. Changing the mode of operation requires that a command code be entered into the CSM. For each one of the two memory partitions, an on-chip status register is available. These two registers allow the progress of the various operations that can take place on a memory bank to be monitored. One of the two status registers is interrogated by entering a READ STATUS REGISTER command onto the CSM (cycle 1), specifying an address within the memory partition boundary, and reading the register data on I/Os DQ0–DQ7 (cycle 2). Status register bits SR0-SR7 correspond to DQ0–DQ7 (see Table 7).

COMMAND DEFINITION

Once a specific command code has been entered, the WSM executes an internal algorithm, generating the necessary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and data for each of the bus cycles.

STATUS REGISTER

The status register allows the user to determine whether the state of a PROGRAM/ERASE operation is pending or complete. The status register is monitored by toggling OE# and CE#, and reading the resulting status code on I/Os DQ0–DQ7. The high-order I/Os (DQ8–DQ15) are set to 00h internally, so only the low-

Table 3

Command State Machine Codes For Device Mode Selection

COMMAND DQ0–DQ7 CODE ON DEVICE MODE

40h/10h Program setup/alternate program setup

20h Block erase setup 50h Clear status register 60h Protection configuration setup 70h Read status register 90h Read protection configuration register 98h Read query B0h Program/erase suspend C0h Protection register program/lock

D0h Program/erase resume – erase confirm

FFh Read array

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PRELIMINARY

order I/Os (DQ0–DQ7) need to be interpreted. Address lines select the status register pertinent to the selected memory partition.

Register data is updated and latched on the falling edge of OE# or CE#, whichever occurs last. Latching the data prevents errors from occurring if the register input changes during a status register read.

The status register provides the internal state of the WSM to the external microprocessor. During periods when the WSM is active, the status register can be polled to determine the WSM status. Table 7 defines the status register bits.

After monitoring the status register during a PROGRAM/ERASE operation, the data appearing on DQ0–DQ7 remains as status register data until a new command is issued to the CSM. To return the device to other modes of operation, a new command must be issued to the CSM.

CSM OPERATIONS

The CSM decodes instructions for read array, read protection configuration register, read query, read status register, clear status register, program, erase, erase suspend, erase resume, program suspend, program resume, lock block, unlock block, and lock down block, chip protection program, and set read configuration register. The 8-bit command code is input to the device on DQ0–DQ7 (see Table 3 for CSM codes and Table 4 for command definitions). During a PROGRAM or ERASE cycle, the CSM informs the WSM that a PROGRAM or ERASE cycle has been requested.

During a PROGRAM cycle, the WSM controls the program sequences and the CSM responds to a PROGRAM SUSPEND command only.

During an ERASE cycle, the CSM responds to an ERASE SUSPEND command only. When the WSM has completed its task, the WSM status bit (SR7) is set to a logic HIGH level and the CSM responds to the full com-

Table 4

Command Definitions

FIRST BUS CYCLE SECOND BUS CYCLE

COMMAND OPERATION ADDRESS

DATA OPERATION ADDRESS1DATA

READ ARRAY WRITE WA FFh READ PROTECTION CONFIGURATION REGISTER WRITE IA 90h READ IA ID READ STATUS REGISTER WRITE B A 70h READ X SRD CLEAR STATUS REGISTER WRITE B A 50h READ QUERY WRITE Q A 98h READ Q A Q D BLOCK ERASE SETUP WRITE B A 20h WRITE B A D0h PROGRAM SETUP/ALTERNATE PROGRAM SETUP WRITE WA 40h/10h WRITE WA W D PROGRAM/ERASE SUSPEND WRITE B A B0h PROGRAM/ERASE RESUME - ERASE CONFIRM WRITE BA D0h LOCK BLOCK WRITE BA 60h WRITE B A 01h UNLOCK BLOCK WRITE B A 60h WRITE B A D0h LOCK DOWN BLOCK WRITE B A 60h WRITE B A 2Fh PROTECTION REGISTER PROGRAM WRITE PA C0h WRITE PA PD PROTECTION REGISTER LOCK WRITE LPA C0h WRITE LPA FFFDh

NOTE: 1. BA: Address within the block

IA: Identification code address ID: Identification code data LPA: Lock protection register address PA: Protection register address PD: Data to be written at the location PA QA: Query code address QD: Query code data SRD: Data read from the status register WA: Word address of memory location to be written, or read WD: Data to be written at the location WA X: “Don’t Care”

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(continued on the next page)

Table 5

Command Descriptions

CODE DEVICE MODE BUS CYCLE DESCRIPTION

10h Alt. Program Setup First Operates the same as a PROGRAM SETUP command.

20h Erase Setup First Prepares the CSM for an ERASE CONFIRM command. If the next

command is not an ERASE CONFIRM command, the command will be ignored, and the bank will go to read status mode and wait for another command.

40h Program Setup First A two-cycle command: The first cycle prepares for a PROGRAM

operation, and the second cycle latches addresses and data and initiates the WSM to execute the program algorithm. The Flash device outputs status register data on the falling edge of OE# or CE#, whichever occurs first.

50h Clear Status First The WSM can set the block lock status (SR3), program status (SR4),

clear them to “0.” Issuing this command clears those bits to “0.”

60h Protection First Prepares the CSM for changes to the block locking status. If the next

Configuration command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK Setup DOWN, the command will be ignored, and the device will go to read

status mode.

70h Read Status First Places the device into read status register mode. Reading the device

The device will automatically enter this mode for the addressed bank after a PROGRAM or ERASE operation has been initiated.

90h Read Protection First Puts the device into the read protection configuration mode so that

Configuration reading the device will output the manufacturer/device codes or

block lock status.

98h Read Query First Puts the device into the read query mode so that reading the device

will output common flash interface information.

B0h Program/Erase First Suspends the currently executing PROGRAM/ERASE operation. The

Suspend status register will indicate when the operation has been successfully

suspended by setting either the program suspend (SR2) or erase suspend (SR6), and the WSM status bit (SR7) to a “1” (ready). The WSM will continue to idle in the suspend state, regardless of the state of all input control signals except RST#, which will immediately shut down the WSM and the remainder of the chip if RST# is driven to VIL.

C0h Program Device First Writes a specific code into the device protection register.

Protection Register

Lock Device First Locks the device protection register; data can no longer be changed. Protection Register

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Table 5

Command Descriptions (continued)

CODE DEVICE MODE BUS CYCLE DESCRIPTION

D0h Erase Confirm Second If the previous command was an ERASE SETUP command, then the

CSM will close the address and data latches, and it will begin erasing the block indicated on the address balls. During programming/erase, the device will respond only to the READ STATUS REGISTER, PROGRAM SUSPEND, or ERASE SUSPEND commands and will output status register data on the falling edge of OE# or CE#, whichever occurs last.

Program/Erase First If a PROGRAM or ERASE operation was previously suspended, this Resume command will resume the operation.

FFh Read Array First During the array mode, array data will be output on the data bus.

01h Lock Block Second If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM will latch the address and lock the block indicated on the address bus.

2Fh Lock Down Second If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM will latch the address and lock down the block indicated on the address bus.

D0h Unlock Block Second If the previous command was PROTECTION CONFIGURATION SETUP,

the CSM will latch the address and unlock the block indicated on the address bus. If the block had been previously set to lock down, this operation will have no effect.

00h Invalid /Reserved Unassigned command that should not be used.

mand set. The CSM stays in the current command state until the microprocessor issues another command.

The WSM successfully initiates an ERASE or PROGRAM operation only when VPP is within its correct voltage range.

CLEAR STATUS REGISTER

The internal circuitry can set, but not clear, the block lock status bit (SR1), the VPP status bit (SR3), the program status bit (SR4), and the erase status bit (SR5) of the status register. The CLEAR STATUS REGISTER command (50h) allows the external microprocessor to clear these status bits and synchronize to the internal operations. When the status bits are cleared, the device returns to the read array mode.

READ OPERATIONS

The following READ operations are available: READ ARRAY, READ PROTECTION CONFIGURATION REGISTER, READ QUERY and READ STATUS REGISTER.

READ ARRAY

The array is read by entering the command code FFh on DQ0–DQ7. Control signals CE# and OE# must

be at a logic LOW level (VIL), and WE# and RST# must be at logic HIGH level (VIH) to read data from the array. Data is available on DQ0–DQ15. Any valid address within any of the blocks selects that address and allows data to be read from that address. Upon initial powerup or device reset, the device defaults to the read array mode.

READ PROTECTION CONFIGURATION DATA

The chip identification mode outputs three types of information: the manufacturer/device identifier, the block locking status, and the protection register. Two bus cycles are required for this operation: the chip identification data is read by entering the command code 90h on DQ0–DQ7 to the bank containing address 00h and the identification code address on the address lines. Control signals CE# and OE# must be at a logic LOW level (VIL), and WE# and RST# must be at a logic HIGH level (VIH) to read data from the protection configuration register. Data is available on DQ0–DQ15. After data is read from the protection configuration register, the READ ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. See Table 9 for further details.

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