MICRON MT28F200B3SG-8T, MT28F200B3SG-8TET, MT28F200B5WG-8TET, MT28F200B5WG-8BET, MT28F200B5SG-8BET Datasheet

1

2Mb Smart 5 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F50.p65 – Rev. 1/00 ©2000, Micron Technology, Inc.

2Mb

SMART 5 BOOT BLOCK FLASH MEMORY

FLASH MEMORY MT28F002B5

MT28F200B5

5V Only, Dual Supply (Smart 5)

FEATURES

•Five erase blocks:
16KB/8K-word boot block (protected)
Two 8KB/4K-word parameter blocks
Two main memory blocks

•Smart 5 technology (B5):
5V ±10% VCC
5V ±10% VPP application/production

programming

12V ±5% VPP compatibility production

programming

•Address access times: 60ns, 80ns

•100,000 ERASE cycles

•Industry-standard pinouts

•Inputs and outputs are fully TTL-compatible

•Automated write and erase algorithm

•Two-cycle WRITE/ERASE sequence

•Byte- or word-wide READ and WRITE
(MT28F200B5, 128K x 16/256K x 8)

•Byte-wide READ and WRITE only
(MT28F002B5, 256K x 8)

•TSOP and SOP packaging options

OPTIONS MARKING

•Timing

60ns access -6
80ns access -8
80ns access -8 ET

•Configurations

256K x 8 MT28F002B5
128K x 16/256K x 8 MT28F200B5

•Boot Block Starting Word Address

Top (1FFFFH) T
Bottom (00000H) B

•Operating Temperature Range

Commercial (0°C to +70°C) None
Extended (-40°C to +85°C) ET

•Packages

Plastic 44-pin SOP (600 mil) SG
Plastic 48-pin TSOP Type 1 WG

(12mm x 20mm)

Plastic 40-pin TSOP VG

(10mm x 20mm)

Part Number Example:

MT28F200B5SG-8 T

GENERAL DESCRIPTION

The MT28F002B5 (x8) and MT28F200B5 (x16/x8)
are nonvolatile, electrically block-erasable (flash), pro­grammable, read-only memories containing 2,097,152
bits organized as 262,144 bytes (8 bits) or 131,072
words (16 bits). Writing or erasing the device is done
with a 5V VPP voltage, while all operations are per­formed with a 5V VCC. Due to process technology
advances, 5V VPP is optimal for application and produc­tion programming. For backward compatibility with
SmartVoltage technology, 12V VPP is supported for a
maximum of 100 cycles and may be connected for up
to 100 cumulative hours. These devices are fabricated
with Micron’s advanced CMOS floating-gate process.

The MT28F002B5 and MT28F200B5 are organized
into five separately erasable blocks. To ensure that
critical firmware is protected from accidental erasure or
overwrite, the devices feature a hardware-protected
boot block. Writing or erasing the boot block requires
either applying a super-voltage to the RP# pin or driv­ing WP# HIGH in addition to executing the normal
write or erase sequences. This block may be used to store
code implemented in low-level system recovery. The
remaining blocks vary in density and are written and
erased with no additional security measures.

Please refer to Micron’s Web site (www.micron.com/

flash/htmls/datasheets.html) for the latest data sheet.

40-Pin TSOP Type I48-Pin TSOP Type I

44-Pin SOP

2

2Mb Smart 5 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F50.p65 – Rev. 1/00 ©2000, Micron Technology, Inc.

2Mb

SMART 5 BOOT BLOCK FLASH MEMORY

A15
A14
A13
A12
A11
A10

A9

A8

NC
NC

WE#

RP#

V

PP

WP#

NC
NC
NC

A7

A6

A5

A4

A3

A2

A1

A16

BYTE#
V

SS

DQ15/(A - 1)
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4

V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0

OE#
V

SS

CE#

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

VPP

WP#

NC

A7
A6
A5
A4
A3
A2
A1

A0

CE#
V

SS

OE#

DQ0
DQ8
DQ1
DQ9
DQ2

DQ10

DQ3

DQ11

RP#
WE#

A8
A9
A10
A11
A12
A13
A14
A15
A16

BYTE#
V

SS

DQ15/(A - 1)
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4

V

CC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

PIN ASSIGNMENT (Top View)

40-Pin TSOP Type I

48-Pin TSOP Type I 44-Pin SOP

ORDER NUMBER AND PART MARKING

MT28F200B5SG-6 B
MT28F200B5SG-6 T
MT28F200B5SG-8 B
MT28F200B5SG-8 T
MT28F200B5SG-8 BET
MT28F200B5SG-8 TET

ORDER NUMBER AND PART MARKING

MT28F200B5WG-6 B
MT28F200B5WG-6 T
MT28F200B5WG-8 B
MT28F200B5WG-8 T
MT28F200B5WG-8 BET
MT28F200B5WG-8 TET

ORDER NUMBER AND PART MARKING

MT28F002B5VG-6 B
MT28F002B5VG-6 T
MT28F002B5VG-8 B
MT28F002B5VG-8 T
MT28F002B5VG-8 BET
MT28F002B5VG-8 TET

A16
A15
A14
A13
A12
A11

A9
A8

WE#

RP#

V

PP

WP#

NC

A7
A6
A5
A4
A3
A2
A1

A17

V

SS

NC
NC

A10

DQ7
DQ6
DQ5
DQ4

V

CC

V

CC

NC

DQ3
DQ2
DQ1
DQ0

OE#
V

SS

CE#

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

3

2Mb Smart 5 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F50.p65 – Rev. 1/00 ©2000, Micron Technology, Inc.

2Mb

SMART 5 BOOT BLOCK FLASH MEMORY

FUNCTIONAL BLOCK DIAGRAM

16KB Boot Block

8KB Parameter Block
8KB Parameter Block

96KB Main Block

Y - Select Gates

Sense Amplifiers

Write/Erase-Bit

Compare and Verify

Addr.

Buffer/

Latch

Power

(Current)

Control

Addr.

Counter

Command
Execution

Logic

I/O

Control

Logic

V

PP

Switch/

Pump

Status

Register

Identification

Register

Y -

Decoder

128KB Main Block

X - Decoder/Block Erase Control

Output

Buffer

Input

Buffer

State

Machine

BYTE#

1

A0-A16/(A17)

CE#

OE#

WE#

RP#

V

PP

DQ15/(A - 1)

1

MUX

DQ15

8

8

7

DQ8-DQ14

1

DQ0-DQ7

16

8

18 (19)

7

(A - 1)

9

(10)

9

8

Output

Buffer

Output

Buffer

Input

Buffer

Input

Buffer

Input Data

Latch/Mux

7

A9

V

CC

WP#

NOTE 1. Does not apply to MT28F002B5.

4

2Mb Smart 5 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F50.p65 – Rev. 1/00 ©2000, Micron Technology, Inc.

2Mb

SMART 5 BOOT BLOCK FLASH MEMORY

PIN DESCRIPTIONS

44-PIN SOP 40-PIN TSOP 48-PIN TSOP

NUMBERS NUMBERS NUMBERS SYMBOL TYPE DESCRIPTION

43 9 11 WE# Input Write Enable: Determines if a given cycle is a WRITE cycle. If

WE# is LOW, the cycle is either a WRITE to the command
execution logic (CEL) or to the memory array.

2 12 14 WP# Input Write Protect: Unlocks the boot block when HIGH if VPP =

V

PPH

1 (5V) or V

PPH

2 (12V)

1

and RP# = VIH during a WRITE or
ERASE. Does not affect WRITE or ERASE operation on other
blocks.

12 22 26 CE# Input Chip Enable: Activates the device when LOW. When CE# is

HIGH, the device is disabled and goes into standby power
mode.

44 10 12 RP# Input Reset/Power-Down: When LOW, RP# clears the status register,

sets the internal state machine (ISM) to the array read mode
and places the device in deep power-down mode. All inputs,
including CE#, are “Don’t Care,” and all outputs are High-Z.
RP# unlocks the boot block and overrides the condition of
WP# when at VHH (12V), and must be held at VIH during all
other modes of operation.

14 24 28 OE# Input Output Enable: Enables data output buffers when LOW.

When OE# is HIGH, the output buffers are disabled.

33 – 47 BYTE# Input Byte Enable: If BYTE# = HIGH, the upper byte is active through

DQ8-DQ15. If BYTE# = LOW, DQ8-DQ14 are High-Z, and all
data is accessed through DQ0-DQ7. DQ15/(A - 1) becomes the
least significant address input.

11, 10, 9, 8, 21, 20, 19, 25, 24, 23, A0-A16/ Input Address Inputs: Select a unique, 16-bit word or 8-bit byte. The

7, 6, 5, 4, 18, 17, 16, 22, 21, 20, (A17) DQ15/(A - 1) input becomes the lowest order address when
42, 41, 40, 15, 14, 8, 7, 19, 18, 8, 7, BYTE# = LOW (MT28F200B5) to allow for a selection of an
39, 38, 37, 36, 6, 5, 4, 3, 6, 5, 4, 3, 2, 8-bit byte from the 262,144 available.

36, 35, 34 2, 1, 40 1, 48

31 – 45 DQ15 Input/ Data I/O: MSB of data when BYTE# = HIGH. Address Input: LSB

(A - 1) Output of address input when BYTE# = LOW during READ or WRITE

operation.

15, 17, 19, 25-28, 32-35 29, 31, 33, DQ0-DQ7 Input/ Data I/Os: Data output pins during any READ operation or
21, 24, 26, 35, 38, 40, Output data input pins during a WRITE. These pins are used to input

28, 30 42, 44 commands to the CEL.

16, 18, 20, – 30, 32, 34, DQ8-DQ14 Input/ Data I/Os: Data output pins during any READ operation or
22, 25, 27, 36, 39, 41, Output data input pins during a WRITE when BYTE# = HIGH. These

29 43 pins are High-Z when BYTE# is LOW.

11113V

PP

Supply Write/Erase Supply Voltage: From a WRITE or ERASE CONFIRM

until completion of the WRITE or ERASE, VPP must be at V

PPH

1

(5V) or V

PPH

2 (12V)

1

. VPP = “Don’t Care” during all other

operations.

23 30, 31 37 V

CC

Supply Power Supply: +5V ±10%.

13, 32 23, 39 27, 46 V

SS

Supply Ground.

3 13, 29, 37, 38 9, 10, 15-17 NC – No Connect: These pins may be driven or left unconnected.

NOTE: 1. For SmartVoltage-compatible production programming, 12V VPP is supported for a maximum of 100 cycles and may

be connected for up to 100 cumulative hours.

5

2Mb Smart 5 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F50.p65 – Rev. 1/00 ©2000, Micron Technology, Inc.

2Mb

SMART 5 BOOT BLOCK FLASH MEMORY

NOTE: 1. L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”).

2. VPPH = VPPH1 = 5V.

3. Operation must be preceded by ERASE SETUP command.

4. Operation must be preceded by WRITE SETUP command.

5. The READ ARRAY command must be issued before reading the array after writing or erasing.

6. When WP# = VIH, RP# may be at VIH or VHH.

7. VHH = 12V.

8. VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.

9. A1-A8, A10-A16 = VIL.

10. Value reflects DQ8-DQ15.

TRUTH TABLE (MT28F200B5)

1

FUNCTION RP# CE# OE# WE# WP# BYTE# A0 A9 VPPDQ0-DQ7 DQ8-DQ14 DQ15/A - 1

Standby H H X X X X X X X High-Z High-Z High-Z

RESET L X X X X X X X X High-Z High-Z High-Z

READ

READ (word mode) H L L H X H X X X Data-Out Data-Out Data-Out

READ (byte mode) H L L H X L X X X Data-Out High-Z A - 1

Output Disable H L H H X X X X X High-Z High-Z High-Z

WRITE/ERASE (EXCEPT BOOT BLOCK)

2

ERASE SETUP H L H L X X X X X 20H X X

ERASE CONFIRM

3

HL HLXXXXV

PPH

D0H X X

WRITE SETUP H L H L X X X X X 10H/40H X X

WRITE (word mode)

4

HL HLXHXXV

PPH

Data-In Data-In Data-In

WRITE (byte mode)

4

HL HLXLXXV

PPH

Data-In X A - 1

READ ARRAY

5

HL HLXXXXX FFH X X

WRITE/ERASE (BOOT BLOCK)

2, 7

ERASE SETUP H L H L X X X X X 20H X X

ERASE CONFIRM

3

V

HH

LHLXXXXV

PPH

D0H X X

ERASE CONFIRM

3, 6

HL HLHXXXV

PPH

D0H X X

WRITE SETUP H L H L X X X X X 10H/40H X X

WRITE (word mode)

4

V

HH

LHLXHXXV

PPH

Data-In Data-In Data-In

WRITE (word mode)

4, 6

HL HLHHXXV

PPH

Data-In Data-In Data-In

WRITE (byte mode)

4

V

HH

LHLXLXXV

PPH

Data-In X A - 1

WRITE (byte mode)

4, 6

HL HLHLXXV

PPH

Data-In X A - 1

READ ARRAY

5

HL HLXXXXX FFH X X

DEVICE IDENTIFICATION

8, 9

Manufacturer Compatibility H L L H X H L V

ID

X 89H 00H –

(word mode)

10

Manufacturer Compatibility H L L H X L L V

ID

X 89H High-Z X

(byte mode)

Device (word mode, top boot)

10

HL LHXHHVIDX 74H 22H –

Device (byte mode, top boot) H L L H X L H V

ID

X 74H High-Z X

Device (word mode, bottom boot)

10

HL LHXHHVIDX 75H 22H –

Device (byte mode, bottom boot) H L L H X L H V

ID

X 75H High-Z X

6

2Mb Smart 5 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F50.p65 – Rev. 1/00 ©2000, Micron Technology, Inc.

2Mb

SMART 5 BOOT BLOCK FLASH MEMORY

NOTE: 1. L = VIL, H = VIH, X = VIL or VIH.

2. VPPH = VPPH1 = 5V.

3. Operation must be preceded by ERASE SETUP command.

4. Operation must be preceded by WRITE SETUP command.

5. The READ ARRAY command must be issued before reading the array after writing or erasing.

6. When WP# = VIH, RP# may be at VIH or VHH.

7. VHH = 12V.

8. VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.

9. A1-A8, A10-A17 = VIL.

TRUTH TABLE (MT28F002B5)

1

FUNCTION RP# CE# OE# WE# WP# A0 A9 VPP DQ0-DQ7

Standby H H XXXXXXHigh-Z
RESET L XXXXXXXHigh-Z

READ

READ H L L H X X X X Data-Out
Output Disable H L H H X X X X High-Z

WRITE/ERASE (EXCEPT BOOT BLOCK)

2

ERASE SETUP H L H L X X X X 20H
ERASE CONFIRM

3

HLHLXXXVPPH D0H
WRITE SETUP H L H L X X X X 10H/40H
WRITE

4

HLHLXXXVPPH Data-In
READ ARRAY

5

HLHLXXXX FFH

WRITE/ERASE (BOOT BLOCK)

2, 7

ERASE SETUP H L H L X X X X 20H
ERASE CONFIRM

3

VHH LHLXXXVPPH D0H

ERASE CONFIRM

3, 6

HLHLHXXVPPH D0H
WRITE SETUP H L H L X X X X 10H/40H
WRITE

4

VHH LHLXXXVPPH Data-In

WRITE

4, 6

HLHLHXXVPPH Data-In
READ ARRAY

5

HLHLXXXX FFH

DEVICE IDENTIFICATION

8, 9

Manufacturer Compatibility H L L H X L VID X 89H
Device (top boot) H L L H X H VID X 7CH
Device (bottom boot) H L L H X H VID X 7DH

7

2Mb Smart 5 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F50.p65 – Rev. 1/00 ©2000, Micron Technology, Inc.

2Mb

SMART 5 BOOT BLOCK FLASH MEMORY

FUNCTIONAL DESCRIPTION

The MT28F002B5 and MT28F200B5 flash memory
incorporate a number of features ideally suited for
system firmware. The memory array is segmented into
individual erase blocks. Each block may be erased
without affecting data stored in other blocks. These
memory blocks are read, written and erased with com­mands to the command execution logic (CEL). The CEL
controls the operation of the internal state machine
(ISM), which completely controls all WRITE, BLOCK
ERASE and VERIFY operations. The ISM protects each
memory location from over-erasure and optimizes each
memory location for maximum data retention. In addi­tion, the ISM greatly simplifies the control necessary
for writing the device in-system or in an external
programmer.

The Functional Description provides detailed infor­mation on the operation of the MT28F002B5 and
MT28F200B5 and is organized into these sections:

• Overview

• Memory Architecture

• Output (READ) Operations

• Input Operations

• Command Set

• ISM Status Register

• Command Execution

• Error Handling

• WRITE/ERASE Cycle Endurance

• Power Usage

• Power-Up

OVERVIEW

SMART 5 TECHNOLOGY (B5)

Smart 5 technology allows maximum flexibility for
in-system READ, WRITE and ERASE operations. For 5V­only systems, WRITE and ERASE operations may be
executed with a VPP voltage of 5V. Due to process
technology advances, 5V VPP is optimal for application
and production programming. For backward compat­ibility with SmartVoltage technology, 12V VPP is sup­ported for a maximum of 100 cycles and may be
connected for up to 100 cumulative hours. However,
no performance increase will be realized. For any opera­tion, VCC may be at 5V.

FIVE INDEPENDENTLY ERASABLE MEMORY
BLOCKS

The MT28F002B5 and MT28F200B5 are organized
into five independently erasable memory blocks that
allow portions of the memory to be erased without
affecting the rest of the memory data. A special boot
block is hardware-protected against inadvertent era­sure or writing by requiring either a super-voltage on

the RP# pin or driving the WP# pin HIGH. One of these
two conditions must exist along with the V

PP voltage

(5V or 12V) on the VPP pin before a WRITE or ERASE will
be performed on the boot block. The remaining blocks
require that only the VPP voltage be present on the VPP
pin before writing or erasing.

HARDWARE-PROTECTED BOOT BLOCK

This block of the memory array can be erased or
written only when the RP# pin is taken to VHH or when
the WP# pin is brought HIGH. This provides additional
security for the core firmware during in-system firm­ware updates should an unintentional power fluctua­tion or system reset occur. The MT28F002B5 and
MT28F200B5 are available with the boot block starting
at the bottom of the address space (“B” suffix) or the top
of the address space (“T” suffix).

SELECTABLE BUS SIZE (MT28F200B5 ONLY)

The MT28F200B5 allows selection of an 8-bit (256K
x 8) or 16-bit (128K x 16) data bus for reading and
writing the memory. The BYTE# pin is used to select the
bus width. In the x16 configuration, control data is read
or written only on the lower eight bits (DQ0-DQ7).

Data written to the memory array utilizes all active
data pins for the selected configuration. When the x8
configuration is selected, data is written in byte form;
when the x16 configuration is selected, data is written
in word form.

INTERNAL STATE MACHINE (ISM)

BLOCK ERASE and BYTE/WORD WRITE timing are
simplified with an ISM that controls all erase and write
algorithms in the memory array. The ISM ensures
protection against overerasure and optimizes write
margin to each cell.

During WRITE operations, the ISM automatically
increments and monitors WRITE attempts, verifies write
margin on each memory cell and updates the ISM status
register. When BLOCK ERASE is performed, the ISM
automatically overwrites the entire addressed block
(eliminates overerasure), increments and monitors
ERASE attempts, and sets bits in the ISM status register.

ISM STATUS REGISTER

The ISM status register allows an external processor
to monitor the status of the ISM during WRITE and
ERASE operations. Two bits of the 8-bit status register
are set and cleared entirely by the ISM. These bits
indicate whether the ISM is busy with a WRITE or
ERASE task and when an ERASE has been suspended.
Additional error information is set in three other bits:
V

PP status, write status and erase status.

8

2Mb Smart 5 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F50.p65 – Rev. 1/00 ©2000, Micron Technology, Inc.

2Mb

SMART 5 BOOT BLOCK FLASH MEMORY

Figure 1

Memory Address Maps

Top Boot

MT28F002B5/200B5xx-xxT

Bottom Boot

MT28F002B5/200B5xx-xxB

1FFFFH

1E000H
1DFFFH

1D000H

1CFFFH

1C000H

1BFFFH

10000H

0FFFFH

00000H

16KB Boot Block

8KB Parameter Block

8KB Parameter Block

96KB Main Block

128KB Main Block

WORD ADDRESS

3FFFFH

3C000H

3BFFFH

3A000H

39FFFH

38000H

37FFFH

20000H

1FFFFH

00000H

BYTE ADDRESS

1FFFFH

10000H

0FFFFH

04000H

03FFFH

03000H

02FFFH

02000H

01FFFH

00000H

128KB Main Block

96KB Main Block

8KB Parameter Block

8KB Parameter Block

16KB Boot Block

WORD ADDRESS

3FFFFH

20000H

1FFFFH

08000H

07FFFH

06000H

05FFFH

04000H

03FFFH

00000H

BYTE ADDRESS

COMMAND EXECUTION LOGIC (CEL)

The CEL receives and interprets commands to the
device. These commands control the operation of the
ISM and the read path (i.e., memory array, ID register or
status register). Commands may be issued to the CEL
while the ISM is active. However, there are restrictions
on what commands are allowed in this condition. See
the Command Execution section for more detail.

DEEP POWER-DOWN MODE

To allow for maximum power conservation, the
MT28F002B5 and MT28F200B5 feature a very low cur­rent, deep power-down mode. To enter this mode, the
RP# pin is taken to VSS ±0.2V. In this mode, the current
draw is a maximum of 20µA at 5V VCC. Entering deep
power-down also clears the status register and sets the
ISM to the read array mode.

MEMORY ARCHITECTURE

The MT28F002B5 and MT28F200B5 memory array
architecture is designed to allow sections to be erased
without disturbing the rest of the array. The array is
divided into five addressable blocks that vary in size

and are independently erasable. When blocks rather
than the entire array are erased, total device endurance
is enhanced, as is system flexibility. Only the ERASE
function is block-oriented. All READ and WRITE opera­tions are done on a random-access basis.

The boot block is protected from unintentional
ERASE or WRITE with a hardware protection circuit
which requires that a super-voltage be applied to RP# or
that the WP# pin be driven HIGH before erasure is
commenced. The boot block is intended for the core
firmware required for basic system functionality. The
remaining four blocks do not require that either of
these two conditions be met before WRITE or ERASE
operations.

BOOT BLOCK

The hardware-protected boot block provides extra
security for the most sensitive portions of the firmware.
This 16KB block may only be erased or written when the
RP# pin is at the specified boot block unlock voltage
(VHH) of 12V or when the WP# pin is VIH. During a
WRITE or ERASE of the boot block, the RP# pin must be

9

2Mb Smart 5 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F50.p65 – Rev. 1/00 ©2000, Micron Technology, Inc.

2Mb

SMART 5 BOOT BLOCK FLASH MEMORY

After power-up or RESET, the device will automati­cally be in the array read mode. All commands and their
operations are covered in the Command Set and Com­mand Execution sections.

STATUS REGISTER

Performing a READ of the status register requires the
same input sequencing as a READ of the array except
that the address inputs are “Don’t Care.” The status
register contents are always output on DQ0-DQ7, re­gardless of the condition of BYTE# on the MT28F200B5.
DQ8-DQ15 are LOW when BYTE# is HIGH, and DQ8­DQ14 are High-Z when BYTE# is LOW. Data from the
status register is latched on the falling edge of OE# or
CE#, whichever occurs last. If the contents of the status
register change during a READ of the status register,
either OE# or CE# may be toggled while the other is
held LOW to update the output.

Following a WRITE or ERASE, the device automati­cally enters the status register read mode. In addition,
a READ during a WRITE or ERASE will produce the
status register contents on DQ0-DQ7. When the device
is in the erase suspend mode, a READ operation will
produce the status register contents until another com­mand is issued. In certain other modes, READ STATUS
REGISTER may be given to return to the status register
read mode. All commands and their operations are
covered in the Command Set and Command Execution
sections.

IDENTIFICATION REGISTER

A READ of the two 8-bit device identification regis­ters requires the same input sequencing as a READ of
the array. WE# must be HIGH, and OE# and CE# must
be LOW. However, ID register data is output only on
DQ0-DQ7, regardless of the condition of BYTE# on the
MT28F200B5. A0 is used to decode between the two
bytes of the device ID register; all other address inputs
are “Don’t Care.” When A0 is LOW, the manufacturer
compatibility ID is output, and when A0 is HIGH, the
device ID is output. DQ8-DQ15 are High-Z when BYTE#
is LOW. When BYTE# is HIGH, DQ8-DQ15 are 00H
when the manufacturer compatibility ID is read and
22H when the device ID is read.

To get to the identification register read mode,
READ IDENTIFICATION may be issued while the device
is in certain other modes. In addition, the identifica­tion register read mode can be reached by applying a
super-voltage (VID) to the A9 pin. Using this method,
the ID register can be read while the device is in any
mode. Once A9 is returned to VIL or VIH, the device will
return to the previous mode.

held at VHH or the WP# pin held HIGH until the ERASE
or WRITE is completed. The VPP pin must be at VPPH (5V
or 12V) when the boot block is written to or erased.

The MT28F002B5 and MT28F200B5 are available in
two configurations and top or bottom boot block. The
top boot block version supports processors of the x86
variety. The bottom boot block version is intended for
680X0 and RISC applications. Figure 1 illustrates the
memory address maps associated with these two
versions.

PARAMETER BLOCKS

The two 8KB parameter blocks store less sensitive
and more frequently changing system parameters and
also may store configuration or diagnostic coding.
These blocks are enabled for erasure when the VPP pin
is at VPPH. No super-voltage unlock or WP# control is
required.

MAIN MEMORY BLOCKS

The two remaining blocks are general-purpose
memory blocks and do not require a super-voltage on
RP# or WP# control to be erased or written. These
blocks are intended for code storage, ROM-resident
applications or operating systems that require in­system update capability.

OUTPUT (READ) OPERATIONS

The MT28F002B5 and MT28F200B5 feature three
different types of READs. Depending on the current
mode of the device, a READ operation will produce data
from the memory array, status register or device iden­tification register. In each of these three cases, the WE#,
CE# and OE# inputs are controlled in a similar manner.
Moving between modes to perform a specific READ is
covered in the Command Execution section.

MEMORY ARRAY

To read the memory array, WE# must be HIGH, and
OE# and CE# must be LOW. Valid data will be output
on the DQ pins once these conditions have been met
and a valid address is given. Valid data will remain on
the DQ pins until the address changes, or until OE# or
CE# goes HIGH, whichever occurs first. The DQ pins
will continue to output new data after each address
transition as long as OE# and CE# remain LOW.

The MT28F200B5 features selectable bus widths.
When the memory array is accessed as a 128K x 16,
BYTE# is HIGH, and data will be output on DQ0-DQ15.
To access the memory array as a 256K x 8, BYTE# must
be LOW, DQ8-DQ14 are High-Z, and all data is output
on DQ0-DQ7. The DQ15/(A - 1) pin becomes the lowest
order address input so that 262,144 locations can be
read.

10

2Mb Smart 5 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F50.p65 – Rev. 1/00 ©2000, Micron Technology, Inc.

2Mb

SMART 5 BOOT BLOCK FLASH MEMORY

INPUT OPERATIONS

The DQ pins are used either to input data to the
array or to input a command to the CEL. A command
input issues an 8-bit command to the CEL to control the
mode of operation of the device. A WRITE is used to
input data to the memory array. The following section
describes both types of inputs. More information de­scribing how to use the two types of inputs to write or
erase the device is provided in the Command Execution
section.

COMMANDS

To perform a command input, OE# must be HIGH,
and CE# and WE# must be LOW. Addresses are “Don’t
Care” but must be held stable, except during an ERASE
CONFIRM (described in a later section). The 8-bit com­mand is input on DQ0-DQ7, while DQ8-DQ15 are
“Don’t Care” on the MT28F200B5. The command is
latched on the rising edge of CE# (CE#-controlled) or
WE# (WE#-controlled), whichever occurs first. The
condition of BYTE# on the MT28F200B5 has no effect
on a command input.

MEMORY ARRAY

A WRITE to the memory array sets the desired bits to
logic 0s but cannot change a given bit to a logic 1 from
a logic 0. Setting any bits to a logic 1 requires that the
entire block be erased. To perform a WRITE, OE# must
be HIGH, CE# and WE# must be LOW, and VPP must be
set to VPPH1 or VPPH2. Writing to the boot block also
requires that the RP# pin be at VHH or WP# be HIGH. A0­A16/(A17) provide the address to be written, while the
data to be written to the array is input on the DQ pins.
The data and addresses are latched on the rising edge of
CE# (CE#-controlled) or WE# (WE#-controlled), which­ever occurs first. A WRITE must be preceded by a WRITE
SETUP command. Details on how to input data to the
array will be covered in the Write Sequence section.

Selectable bus sizing applies to WRITEs as it does to
READs on the MT28F200B5. When BYTE# is LOW (byte
mode), data is input on DQ0-DQ7, DQ8-DQ14 are
High-Z and DQ15 becomes the lowest order address
input. When BYTE# is HIGH (word mode), data is input
on DQ0-DQ15.

Table 1

Command Set

COMMAND HEX CODE DESCRIPTION

RESERVED 00H This command and all unlisted commands are invalid and should not

be called. These commands are reserved to allow for future feature
enhancements.

READ ARRAY FFH Must be issued after any other command cycle before the array can be

read. It is not necessary to issue this command after power-up or RESET.

IDENTIFY DEVICE 90H Allows the device ID and manufacturer compatibility ID to be read. A0 is

used to decode between the manufacturer compatibility ID (A0 = LOW)
and device ID (A0 = HIGH).

READ STATUS REGISTER 70H Allows the status register to be read. Please refer to Table 2 for more

information on the status register bits.
CLEAR STATUS REGISTER 50H Clears status register bits 3-5, which cannot be cleared by the ISM.
ERASE SETUP 20H The first command given in the two-cycle ERASE sequence. The ERASE will

not be completed unless followed by ERASE CONFIRM.
ERASE CONFIRM/RESUME D0H The second command given in the two-cycle ERASE sequence. Must follow

an ERASE SETUP command to be valid. Also used during an ERASE

SUSPEND to resume the ERASE.
WRITE SETUP 40H or The first command given in the two-cycle WRITE sequence. The write

10H data and address are given in the following cycle to complete the WRITE.

ERASE SUSPEND B0H Requests a halt of the ERASE and puts the device into the erase suspend

mode. When the device is in this mode, only READ STATUS REGISTER,

READ ARRAY and ERASE RESUME commands may be executed.