MICRON MT28F400B3SG-8T, MT28F400B3SG-8TET, MT28F400B3SG-8B, MT28F400B3WG-8TET, MT28F400B3WG-8B Datasheet

1

4Mb Smart 3 Boot Block Flash Memory
F45_3.p65 – Rev. 3, Pub. 12/01 ©2001, Micron Technology, Inc.

4Mb

SMART 3 BOOT BLOCK FLASH MEMORY

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

GENERAL DESCRIPTION

The MT28F004B3 (x8) and MT28F400B3 (x16/x8)
are nonvolatile, electrically block-erasable (flash), pro­grammable memory devices containing 4,194,304 bits
organized as 262,144 words (16 bits) or 524,288 bytes (8
bits). Writing or erasing the device is done with either a

3.3V or 5V VPP voltage, while all operations are performed
with a 3.3V VCC. Due to process technology advances,
5V VPP is optimal for application and production pro­gramming. These devices are fabricated with Micron’s
advanced 0.18µm CMOS floating-gate process.

The MT28F004B3 and MT28F400B3 are organized
into seven separately erasable blocks. To ensure that
critical firmware is protected from accidental erasure or
overwrite, the devices feature a hardware-protected
boot block. Writing or erasing the boot block requires
either applying a super-voltage to the RP# pin or driv­ing WP# HIGH in addition to executing the normal write
or erase sequences. This block may be used to store
code implemented in low-level system recovery. The
remaining blocks vary in density and are written and
erased with no additional security measures.

Refer to Micron’s Web site (www.micron.com/flash)
for the latest data sheet.

FLASH MEMORY

MT28F004B3
MT28F400B3

3V Only, Dual Supply (Smart 3)

FEATURES

• Seven erase blocks:
16KB/8K-word boot block (protected)
Two 8KB/4K-word parameter blocks
Four main memory blocks

• Smart 3 technology (B3):

3.3V ±0.3V VCC

3.3V ±0.3V VPP application programming
5V ±10% VPP application/production programming

1

• Compatible with 0.3µm Smart 3 device

• Advanced 0.18µm CMOS floating-gate process

• Address access time: 80ns

• 100,000 ERASE cycles

• Industry-standard pinouts

• Inputs and outputs are fully TTL-compatible

• Automated write and erase algorithm

• Two-cycle WRITE/ERASE sequence

• Byte- or word-wide READ and WRITE
(MT28F400B3, 256K x 16/512K x 8)

• Byte-wide READ and WRITE only
(MT28F004B3, 512K x 8)

• TSOP and SOP packaging options

OPTIONS MARKING

• Timing

80ns access -8

• Configurations

512K x 8 MT28F004B3
256K x 16/512K x 8 MT28F400B3

• Boot Block Starting Word Address

Top (3FFFFh) T
Bottom (00000h) B

• Operating Temperature Range

Commercial (0ºC to +70ºC) None
Extended (-40ºC to +85ºC) ET

• Packages

44-pin SOP (MT28F400B3) SG
48-pin TSOP Type I (MT28F400B3) WG
40-pin TSOP Type I (MT28F004B3) VG

NOTE: 1. This generation of devices does not support 12V VPP

compatibility production programming; however, 5V VPP
application production programming can be used with no
loss of performance.

Part Number Example:

MT28F400B3SG-8 T

40-Pin TSOP Type I 48-Pin TSOP Type I

44-Pin SOP

2

4Mb Smart 3 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F45_3.p65 – Rev. 3, Pub. 12/01 ©2001, Micron Technology, Inc.

4Mb

SMART 3 BOOT BLOCK FLASH MEMORY

PIN ASSIGNMENT (Top View)

40-PIN TSOP TYPE I

48-PIN TSOP TYPE I 44-PIN SOP

ORDER NUMBER AND PART MARKING

MT28F400B3SG-8 B
MT28F400B3SG-8 T
MT28F400B3SG-8 BET
MT28F400B3SG-8 TET

ORDER NUMBER AND PART MARKING

MT28F400B3WG-8 B
MT28F400B3WG-8 T
MT28F400B3WG-8 BET
MT28F400B3WG-8 TET

ORDER NUMBER AND PART MARKING

MT28F004B3VG-8 B
MT28F004B3VG-8 T
MT28F004B3VG-8 BET
MT28F004B3VG-8 TET

A15
A14
A13
A12
A11
A10

A9
A8

NC
NC

WE#

RP#

V

PP

WP#

NC
NC

A17

A7
A6
A5
A4
A3
A2
A1

A16

BYTE#
V

SS

DQ15/(A-1)
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4

V

CC

DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0

OE#
V

SS

CE#

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

V

PP

WP#

A17

A7
A6
A5
A4
A3
A2
A1
A0

CE#

V

SS

OE#

DQ0
DQ8
DQ1
DQ9
DQ2

DQ10

DQ3

DQ11

RP#
WE#

A8
A9
A10
A11
A12
A13
A14
A15
A16

BYTE#
V

SS

DQ15/(A-1)
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4

V

CC

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22

44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23

A16
A15
A14
A13
A12
A11

A9
A8

WE#

RP#

V

PP

WP#

A18

A7
A6
A5
A4
A3
A2
A1

A17

V

SS

NC
NC

A10

DQ7
DQ6
DQ5
DQ4

V

CC

V

CC

NC

DQ3
DQ2
DQ1
DQ0

OE#
V

SS

CE#

A0

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

3

4Mb Smart 3 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F45_3.p65 – Rev. 3, Pub. 12/01 ©2001, Micron Technology, Inc.

4Mb

SMART 3 BOOT BLOCK FLASH MEMORY

FUNCTIONAL BLOCK DIAGRAM

16KB Boot Block

8KB Parameter Block
8KB Parameter Block

96KB Main Block

128KB Main Block

128KB Main Block

Y - Select Gates

Sense Amplifiers

Write/Erase-Bit

Compare and Verify

Addr.

Buffer/

Latch

Power

(Current)

Control

Addr.

Counter

Command
Execution

Logic

I/O

Control

Logic

V

PP

Switch/

Pump

Status

Register

Identification

Register

Y -

Decoder

128KB Main Block

X - Decoder/Block Erase Control

Output

Buffer

Input

Buffer

State

Machine

BYTE#

1

A0–A17/(A18)

CE#

OE#

WE#

RP#

V

PP

DQ15/(A - 1)

1

MUX

DQ15

8

8

7

DQ8–DQ14

1

DQ0–DQ7

16

8

18 (19)

7

A-1

9

(10)

9

8

Output

Buffer

Output

Buffer

Input

Buffer

Input

Buffer

Input Data
Latch/Mux

7

A9

V

CC

WP#

NOTE: 1. Does not apply to MT28F004B3.

4

4Mb Smart 3 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F45_3.p65 – Rev. 3, Pub. 12/01 ©2001, Micron Technology, Inc.

4Mb

SMART 3 BOOT BLOCK FLASH MEMORY

PIN DESCRIPTIONS

44-PIN SOP 40-PIN TSOP 48-PIN TSOP

NUMBERS NUMBERS NUMBERS SYMBOL TYPE DESCRIPTION

43 9 11 WE# Input Write Enable: Determines if a given cycle is a WRITE

cycle. If WE# is LOW, the cycle is either a WRITE to the
command execution logic (CEL) or to the memory array.

2 12 14 WP# Input Write Protect: Unlocks the boot block when HIGH if VPP

= VPPH1 (3.3V) or VPPH2 (5V) and RP# = VIH during a
WRITE or ERASE. Does not affect WRITE or ERASE
operation on other blocks.

12 22 26 CE# Input Chip Enable: Activates the device when LOW. When

CE# is HIGH, the device is disabled and goes into
standby power mode.

44 10 12 RP# Input Reset/Power-Down: When LOW, RP# clears the status

register, sets the internal state machine (ISM) to the
array read mode and places the device in deep power­down mode. All inputs, including CE#, are “Don’t
Care,” and all outputs are High-Z. RP# unlocks the boot
block and overrides the condition of WP# when at VHH
(12V), and must be held at VIH during all other modes
of operation.

14 24 28 OE# Input Output Enable: Enables data output buffers when

LOW. When OE# is HIGH, the output buffers are
disabled.

33 – 47 BYTE# Input Byte Enable: If BYTE# = HIGH, the upper byte is active

through DQ8–DQ15. If BYTE# = LOW, DQ8–DQ14 are
High-Z, and all data is accessed through DQ0–DQ7.
DQ15/(A-1) becomes the least significant address input.

11, 10, 9, 8, 21, 20, 19, 25, 24, 23, A0–A17/ Input Address Inputs: Select a unique, 16-bit word or 8-bit

7, 6, 5, 4, 18, 17, 16, 22, 21, 20, (A18) byte. The DQ15/(A-1) input becomes the lowest order
42, 41, 40, 15, 14, 8, 7, 19, 18, 8, 7, address when BYTE# = LOW (MT28F400B3) to allow for
39, 38, 37, 36, 6, 5, 4, 3, 6, 5, 4, 3, 2, a selection of an 8-bit byte from the 524,288 available.

36, 35, 34, 3 2, 1, 40, 13 1, 48, 17

31 – 45 DQ15/ Input/ Data I/O: MSB of data when BYTE# = HIGH. Address

(A-1) Output Input: LSB of address input when BYTE# = LOW during

READ or WRITE operation.

15, 17, 19, 25-28, 32-35 29, 31, 33, DQ0–DQ7 Input/ Data I/Os: Data output pins during any READ operation
21, 24, 26, 35, 38, 40, Output or data input pins during a WRITE. These pins are used

28, 30 42, 44 to inputcommands to the CEL.

16, 18, 20, – 30, 32, 34, DQ8–DQ14 Input/ Data I/Os: Data output pins during any READ operation
22, 25, 27, 36, 39, 41, Output or data input pins during a WRITE when BYTE# = HIGH.

29 43 These pins are High-Z when BYTE# is LOW.

11113VPP Supply Write/Erase Supply Voltage: From a WRITE or ERASE

CONFIRM until completion of the WRITE or ERASE, VPP
must be at VPPH1 (3.3V) or VPPH2 (5V). VPP = “Don’t Care”
during all other operations.

23 30, 31 37 VCC Supply Power Supply: +3.3V ±0.3V.

13, 32 23, 39 27, 46 VSS Supply Ground.

– 29, 37, 38 9, 10, 15, 16 NC – No Connect: These pins may be driven or left

unconnected.

5

4Mb Smart 3 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F45_3.p65 – Rev. 3, Pub. 12/01 ©2001, Micron Technology, Inc.

4Mb

SMART 3 BOOT BLOCK FLASH MEMORY

NOTE: 1. L = VIL (LOW), H = VIH (HIGH), X = VIL or VIH (“Don’t Care”).

2. VPPH = VPPH1 (3.3V) or VPPH2 (5V).

3. Operation must be preceded by ERASE SETUP command.

4. Operation must be preceded by WRITE SETUP command.

5. The READ ARRAY command must be issued before reading the array after writing or erasing.

6. When WP# = VIH, RP# may be at VIH or VHH.

7. VHH = 12V.

8. VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.

9. A1–A8, A10–A17 = VIL.

10. Value reflects DQ8–DQ15.

TRUTH TABLE (MT28F400B3)

1

FUNCTION RP# CE# OE# WE# WP# BYTE# A0 A9 VPPDQ0–DQ7 DQ8–DQ14 DQ15/A-1

Standby H H X X X X X X X High-Z High-Z High-Z
RESET L X X X X X X X X High-Z High-Z High-Z

READ

READ (word mode) H L L H X H X X X Data-Out Data-Out Data-Out
READ (byte mode) H L L H X L X X X Data-Out High-Z A-1
Output Disable H L H H X X X X X High-Z High-Z High-Z

WRITE/ERASE (EXCEPT BOOT BLOCK)

2

ERASE SETUP H L H L X X X X X 20h X X
ERASE CONFIRM

3

HLHLXXXXV

PPH

D0h X X
WRITE SETUP H L H L X X X X X 10h/40h X X
WRITE (word mode)

4

HLHLXHXXV

PPH

Data-In Data-In Data-In

WRITE (byte mode)

4

HLHLXLXXV

PPH

Data-In X A-1

READ ARRAY

5

HLHLXXXXX FFh X X

WRITE/ERASE (BOOT BLOCK)

2, 7

ERASE SETUP H L H L X X X X X 20h X X
ERASE CONFIRM

3

V

HH

LHLXXXXV

PPH

D0h X X
ERASE CONFIRM

3, 6

HLHLHXXXV

PPH

D0h X X
WRITE SETUP H L H L X X X X X 10h/40h X X
WRITE (word mode)

4

V

HH

LHLXHXXV

PPH

Data-In Data-In Data-In

WRITE (word mode)

4, 6

HLHLHHXXV

PPH

Data-In Data-In Data-In

WRITE (byte mode)

4

V

HH

LHLXLXXV

PPH

Data-In X A-1

WRITE (byte mode)

4, 6

HLHLHLXXV

PPH

Data-In X A-1

READ ARRAY

5

HLHLXXXXX FFh X X

DEVICE IDENTIFICATION

8, 9

Manufacturer Compatibility H L L H X H L V

ID

X 89h 00h –

(word mode)

10

Manufacturer Compatibility H L L H X L L V

ID

X 89h High-Z X

(byte mode)
Device (word mode, top boot)

10

HL LHXHHVIDX 70h 44h –

Device (byte mode, top boot) H L L H X L H V

ID

X 70h High-Z X

Device (word mode, bottom boot)

10

HL LHXHHVIDX 71h 44h –

Device (byte mode, bottom boot) H L L H X L H V

ID

X 71h High-Z X

6

4Mb Smart 3 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F45_3.p65 – Rev. 3, Pub. 12/01 ©2001, Micron Technology, Inc.

4Mb

SMART 3 BOOT BLOCK FLASH MEMORY

NOTE: 1. L = VIL, H = VIH, X = VIL or VIH.

2. VPPH = VPPH1 = 3.3V or VPPH2 = 5V.

3. Operation must be preceded by ERASE SETUP command.

4. Operation must be preceded by WRITE SETUP command.

5. The READ ARRAY command must be issued before reading the array after writing or erasing.

6. When WP# = VIH, RP# may be at VIH or VHH.

7. VHH = 12V.

8. VID = 12V; may also be read by issuing the IDENTIFY DEVICE command.

9. A1–A8, A10–A18 = VIL.

TRUTH TABLE (MT28F004B3)

1

FUNCTION RP# CE# OE# WE# WP# A0 A9 VPP DQ0–DQ7

Standby H H XXXXXXHigh-Z
RESET L X XXXXXXHigh-Z

READ

READ H L L H X X X X Data-Out
Output Disable H L H H X X X X High-Z

WRITE/ERASE (EXCEPT BOOT BLOCK)

2

ERASE SETUP H L H L X X X X 20h
ERASE CONFIRM

3

HLHLXXXVPPH D0h
WRITE SETUP H L H L X X X X 10h/40h
WRITE

4

HLHLXXXVPPH Data-In
READ ARRAY

5

HLHLXXXX FFh

WRITE/ERASE (BOOT BLOCK)

2, 7

ERASE SETUP H L H L X X X X 20h
ERASE CONFIRM

3

VHH LHLXXXVPPH D0h

ERASE CONFIRM

3, 6

HLHLHXXVPPH D0h
WRITE SETUP H L H L X X X X 10h/40h
WRITE

4

VHH LHLXXXVPPH Data-In

WRITE

4, 6

HLHLHXXVPPH Data-In
READ ARRAY

5

HLHLXXXX FFh

DEVICE IDENTIFICATION

8, 9

Manufacturer Compatibility H L L H X L VID X 89h
Device (top boot) H L L H X H VID X 78h
Device (bottom boot) H L L H X H VID X 79h

7

4Mb Smart 3 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F45_3.p65 – Rev. 3, Pub. 12/01 ©2001, Micron Technology, Inc.

4Mb

SMART 3 BOOT BLOCK FLASH MEMORY

FUNCTIONAL DESCRIPTION

The MT28F004B3 and MT28F400B3 Flash devices in­corporate a number of features ideally suited for system
firmware. The memory array is segmented into indi­vidual erase blocks. Each block may be erased without
affecting data stored in other blocks. These memory
blocks are read, written and erased with commands to
the command execution logic (CEL). The CEL controls
the operation of the internal state machine (ISM), which
completely controls all WRITE, BLOCK ERASE and VERIFY
operations. The ISM protects each memory location from
over-erasure and optimizes each memory location for
maximum data retention. In addition, the ISM greatly
simplifies the control necessary for writing the device in­system or in an external programmer.

The Functional Description provides detailed infor­mation on the operation of the MT28F004B3 and
MT28F400B3 and is organized into these sections:

• Overview

• Memory Architecture

• Output (READ) Operations

• Input Operations

• Command Set

• ISM Status Register

• Command Execution

• Error Handling

• WRITE/ERASE Cycle Endurance

• Power Usage

• Power-Up

OVERVIEW

SMART 3 TECHNOLOGY (B3)

Smart 3 technology allows maximum flexibility for in­system READ, WRITE and ERASE operations. WRITE and
ERASE operations may be executed with a VPP voltage of

3.3V or 5V. Due to process technology advances, 5V VPP is
optimal for application and production programming.

SEVEN INDEPENDENTLY ERASABLE MEMORY
BLOCKS

The MT28F004B3 and MT28F400B3 are organized into
seven independently erasable memory blocks that allow
portions of the memory to be erased without affecting the
rest of the memory data. A special boot block is hard­ware-protected against inadvertent erasure or writing by
requiring either a super-voltage on the RP# pin or driving
the WP# pin HIGH. One of these two conditions must
exist along with the VPP voltage (3.3V or 5V) on the VPP pin
before a WRITE or ERASE is performed on the boot block.
The remaining blocks require only the VPP voltage be
present on the VPP pin before writing or erasing.

HARDWARE-PROTECTED BOOT BLOCK

This block of the memory array can be erased or
written only when the RP# pin is taken to VHH or when the
WP# pin is brought HIGH. This provides additional secu­rity for the core firmware during in-system firmware
updates should an unintentional power fluctuation or
system reset occur. The MT28F004B3 and MT28F400B3
are available with the boot block starting at the bottom of
the address space (“B” suffix) or the top of the address
space (“T” suffix).

SELECTABLE BUS SIZE (MT28F400B3 ONLY)

The MT28F400B3 allows selection of an 8-bit
(512K x 8) or 16-bit (256K x 16) data bus for reading and
writing the memory. The BYTE# pin is used to select the
bus width. In the x16 configuration, control data is read
or written only on the lower eight bits (DQ0–DQ7).

Data written to the memory array utilizes all active
data pins for the selected configuration. When the x8
configuration is selected, data is written in byte form;
when the x16 configuration is selected, data is written in
word form.

INTERNAL STATE MACHINE (ISM)

BLOCK ERASE and BYTE/WORD WRITE timing are
simplified with an ISM that controls all erase and write
algorithms in the memory array. The ISM ensures protec­tion against overerasure and optimizes write margin to
each cell.

During WRITE operations, the ISM automatically in­crements and monitors WRITE attempts, verifies write
margin on each memory cell and updates the ISM status
register. When BLOCK ERASE is performed, the ISM
automatically overwrites the entire addressed block
(eliminates overerasure), increments and monitors
ERASE attempts, and sets bits in the ISM status register.

ISM STATUS REGISTER

The ISM status register enables an external processor
to monitor the status of the ISM during WRITE and ERASE
operations. Two bits of the 8-bit status register are set and
cleared entirely by the ISM. These bits indicate whether
the ISM is busy with a WRITE or ERASE task and when an
ERASE has been suspended. Additional error informa­tion is set in three other bits: VPP status, write status and
erase status.

COMMAND EXECUTION LOGIC (CEL)

The CEL receives and interprets commands to the
device. These commands control the operation of the
ISM and the read path (i.e., memory array, ID register or
status register). Commands may be issued to the CEL
while the ISM is active. However, there are restrictions on

8

4Mb Smart 3 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F45_3.p65 – Rev. 3, Pub. 12/01 ©2001, Micron Technology, Inc.

4Mb

SMART 3 BOOT BLOCK FLASH MEMORY

Figure 1

Memory Address Maps

Top Boot

MT28F004B3/400B3xx-xxT

Bottom Boot

MT28F004B3/400B3xx-xxB

3FFFFh

3E000h
3DFFFh

3D000h

3CFFFh
3C000h
3BFFFh

30000h

2FFFFh

20000h

1FFFFh

10000h

0FFFFh

00000h

16KB Boot Block

8KB Parameter Block
8KB Parameter Block

96KB Main Block

128KB Main Block

128KB Main Block

128KB Main Block

WORD ADDRESS

7FFFFh

7C000h
7BFFFh

7A000h

79FFFh

78000h

77FFFh

60000h

5FFFFh

40000h

3FFFFh

20000h

1FFFFh

00000h

BYTE ADDRESS

3FFFFh

30000h

2FFFFh

20000h

1FFFFh

10000h

0FFFFh

04000h

03FFFh

03000h

02FFFh

02000h

01FFFh

00000h

128KB Main Block

128KB Main Block

128KB Main Block

96KB Main Block

8KB Parameter Block
8KB Parameter Block

16KB Boot Block

WORD ADDRESS

7FFFFh

60000h

5FFFFh

40000h

3FFFFh

20000h

1FFFFh

08000h

07FFFh

06000h

05FFFh

04000h

03FFFh

00000h

BYTE ADDRESS

what commands are allowed in this condition. See the
Command Execution section for more detail.

DEEP POWER-DOWN MODE

To allow for maximum power conservation, the
MT28F004B3 and MT28F400B3 feature a very low cur­rent, deep power-down mode. To enter this mode, the
RP# pin is taken to VSS ±0.2V. In this mode, the current
draw is a maximum of 8µA at 3.3V VCC. Entering deep
power-down also clears the status register and sets the
ISM to the read array mode.

MEMORY ARCHITECTURE

The MT28F004B3 and MT28F400B3 memory array
architecture is designed to allow sections to be erased
without disturbing the rest of the array. The array is
divided into seven addressable blocks that vary in size
and are independently erasable. When blocks rather than
the entire array are erased, total device endurance is
enhanced, as is system flexibility. Only the ERASE func­tion is block-oriented. All READ and WRITE operations
are done on a random-access basis.

The boot block is protected from unintentional ERASE
or WRITE with a hardware protection circuit which re-

quires that a super-voltage (VHH) be applied to RP# or that
the WP# pin be driven HIGH before erasure is com­menced. The boot block is intended for the core firmware
required for basic system functionality. The remaining
six blocks do not require either of these two conditions be
met before WRITE or ERASE operations.

BOOT BLOCK

The hardware-protected boot block provides extra
security for the most sensitive portions of the firmware.
This 16KB block may only be erased or written when the
RP# pin is at the specified boot block unlock voltage (VHH)
of 12V or when the WP# pin is VIH. During a WRITE or
ERASE of the boot block, the RP# pin must be held at VHH
or the WP# pin held HIGH until the ERASE or WRITE is
completed. The VPP pin must be at VPPH (3.3V or 5V) when
the boot block is written to or erased.

The MT28F004B3 and MT28F400B3 are available in
two configurations and top or bottom boot block. The top
boot block version supports processors of the x86 variety.
The bottom boot block version is intended for 680X0 and
RISC applications. Figure 1 illustrates the memory ad­dress maps associated with these two versions.

9

4Mb Smart 3 Boot Block Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
F45_3.p65 – Rev. 3, Pub. 12/01 ©2001, Micron Technology, Inc.

4Mb

SMART 3 BOOT BLOCK FLASH MEMORY

latched on the falling edge of OE# or CE#, whichever
occurs last. If the contents of the status register change
during a READ of the status register, either OE# or CE#
may be toggled while the other is held LOW to update the
output.

Following a WRITE or ERASE, the device automati­cally enters the status register read mode. In addition, a
READ during a WRITE or ERASE produces the status
register contents on DQ0–DQ7. When the device is in the
erase suspend mode, a READ operation produces the
status register contents until another command is is­sued. In certain other modes, READ STATUS REGIS­TER may be given to return to the status register read
mode. All commands and their operations are described
in the Command Set and Command Execution sections.

IDENTIFICATION REGISTER

A READ of the two 8-bit device identification registers
requires the same input sequencing as a READ of the
array. WE# must be HIGH, and OE# and CE# must be
LOW. However, ID register data is output only on DQ0–
DQ7, regardless of the condition of BYTE# on the
MT28F400B3. A0 is used to decode between the two bytes
of the device ID register; all other address inputs are
“Don’t Care.” When A0 is LOW, the manufacturer com­patibility ID is output, and when A0 is HIGH, the device
ID is output. DQ8–DQ15 are High-Z when BYTE# is LOW.
When BYTE# is HIGH, DQ8–DQ15 are 00h when the
manufacturer compatibility ID is read and 44h when the
device ID is read.

To get to the identification register read mode, READ
IDENTIFICATION may be issued while the device is in
certain other modes. In addition, the identification regis­ter read mode can be reached by applying a super-volt­age (VID) to the A9 pin. Using this method, the ID register
can be read while the device is in any mode. When A9 is
returned to VIL or VIH, the device returns to the previous
mode.

INPUT OPERATIONS

The DQ pins are used either to input data to the array
or to input a command to the CEL. A command input
issues an 8-bit command to the CEL to control the mode
of operation of the device. A WRITE is used to input data
to the memory array. The following section describes
both types of inputs. More information describing how to
use the two types of inputs to write or erase the device is
provided in the Command Execution section.

COMMANDS

To perform a command input, OE# must be HIGH,
and CE# and WE# must be LOW. Addresses are “Don’t
Care” but must be held stable, except during an ERASE
CONFIRM (described in a later section). The 8-bit com-

PARAMETER BLOCKS

The two 8KB parameter blocks store less sensitive and
more frequently changing system parameters and also
may store configuration or diagnostic coding. These
blocks are enabled for erasure when the VPP pin is at VPPH.
No super-voltage unlock or WP# control is required.

MAIN MEMORY BLOCKS

The four remaining blocks are general-purpose
memory blocks and do not require a super-voltage on
RP# or WP# control to be erased or written. These blocks
are intended for code storage, ROM-resident applica­tions or operating systems that require in-system update
capability.

OUTPUT (READ) OPERATIONS

The MT28F004B3 and MT28F400B3 feature three dif­ferent types of READs. Depending on the current mode of
the device, a READ operation produces data from the
memory array, status register or device identification
register. In each of these three cases, the WE#, CE# and
OE# inputs are controlled in a similar manner. Moving
between modes to perform a specific READ is described
in the Command Execution section.

MEMORY ARRAY

To read the memory array, WE# must be HIGH, and
OE# and CE# must be LOW. Valid data is output on the
DQ pins when these conditions have been met and a
valid address is given. Valid data remains on the DQ pins
until the address changes, or until OE# or CE# goes HIGH,
whichever occurs first. The DQ pins continue to output
new data after each address transition as long as OE# and
CE# remain LOW.

The MT28F400B3 features selectable bus widths.
When the memory array is accessed as a 256K x 16, BYTE#
is HIGH, and data is output on DQ0–DQ15. To access the
memory array as a 512K x 8, BYTE# must be LOW, DQ8–
DQ14 must be High-Z, and all data must be output on
DQ0–DQ7. The DQ15/A-1 pin becomes the lowest or­der address input so that 524,288 locations can be read.

After power-up or RESET, the device is automatically
in the array read mode. All commands and their opera­tions are described in the Command Set and Command
Execution sections.

STATUS REGISTER

Performing a READ of the status register requires the
same input sequencing as a READ of the array except that
the address inputs are “Don’t Care.” The status register
contents are always output on DQ0–DQ7, regardless of
the condition of BYTE# on the MT28F400B3. DQ8–DQ15
are LOW when BYTE# is HIGH, and DQ8–DQ14 are High­Z when BYTE# is LOW. Data from the status register is