MICRON MT28C3212P2FL-11BET, MT28C3212P2FL-11T, MT28C3212P2FL-10T, MT28C3212P2FL-10B, MT28C3212P2NFL-11TET Datasheet
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1
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory ©2002, Micron Technology, Inc.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
FLASH AND SRAM
COMBO MEMORY
MT28C3212P2FL
MT28C3212P2NFL
Low Voltage, Extended Temperature
FEATURES
• Flexible dual-bank architecture
• Support for true concurrent operations with no
latency:
Read bank b during program bank a and vice versa
Read bank b during erase bank a and vice versa
• Organization: 2,048K x 16 (Flash)
128K x 16 (SRAM)
• Basic configuration:
Flash
Bank a (4Mb Flash for data storage)
– Eight 4K-word parameter blocks
– Seven 32K-word blocks
Bank b (28Mb Flash for program storage)
– Fifty-six 32K-word main blocks
SRAM
2Mb SRAM for data storage
– 128K-words
• F_VCC, VCCQ, F_VPP, S_VCC voltages
1
1.65V (MIN)/1.95V (MAX) F_VCC read voltage or
1.80V (MIN)/2.20V (MAX) F_VCC read voltage
1.65V (MIN)/1.95V (MAX) S_VCC read voltage or
1.80V (MIN)/2.20V (MAX) S_VCC read voltage
1.65V (MIN)/1.95V (MAX) VCCQ or
1.80V (MIN)/2.20V (MAX) VCCQ
1.80V (TYP) F_VPP (in-system PROGRAM/ERASE)
0.0V (MIN)/2.20V (MAX) F_VPP (in-system
PROGRAM/ERASE)
2
12V ±5% (HV) F_VPP (production programming
compatibility)
• Asynchronous access time
1
Flash access time: 100ns or 110ns @ 1.65V F_VCC
SRAM access time: 100ns @ 1.65V S_VCC
• Page Mode read access
1
Interpage read access: 100ns/110ns @ 1.65V F_VCC
Intrapage read access: 35ns/45ns @ 1.65V F_VCC
• Low power consumption
• Enhanced suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
• Read/Write SRAM during program/erase of Flash
• Dual 64-bit chip protection registers for security
purposes
• PROGRAM/ERASE cycles
100,000 WRITE/ERASE cycles per block
• Cross-compatible command set support
Extended command set
Common Flash interface (CFI) compliant
NOTE: 1. These specifications are guaranteed for operation
within either one of two voltage ranges, 1.65V–1.95V
or 1.80V–2.20V. Use only one of the two voltage
ranges for PROGRAM and ERASE operations.
2. MT28C3212P2NFL only.
OPTIONS MARKING
• Timing
100ns -10
110ns -11
• Boot Block
Top T
Bottom B
•VPP1 Range
0.9V–2.2V None
0.0V–2.2V N
• Operating Temperature Range
Commercial Temperature (0oC to +70oC) None
Extended Temperature (-40oC to +85oC) ET
• Package
66-ball FBGA (8 x 8 grid) FL
Part Number Example:
MT28C3212P2FL-10 TET
BALL ASSIGNMENT
66-Ball FBGA (Top View)
A
B
C
D
E
F
G
H
1 2 3 4 5 6 7 8 9 10 11 12
Top View
(Ball Down)
NC
NC
A14
A9
DQ11
A6
A0
A15
A10
A19
S_OE#
A7
A4
A20
A16
F_WE#
S_V
SS
F_WP#
S_LB#
A18
F_V
CC
A12
S_WE#
DQ6
S_CE2
DQ10
DQ8
A2
F_V
SS
F_VSS
DQ14
DQ4
S_V
CC
DQ2
DQ0
A1
F_OE#
V
ccQ
DQ7
DQ5
F_V
CC
DQ3
DQ1
S_CE1#
NCNCNCNCNC
A13
DQ15
DQ13
DQ12
DQ9
A3
F_CE#
NC
NC
A11
A8
NC
F_RP#
F_V
PP
S_UB#
A17
A5
2
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Table 2
Cross Reference for Abbreviated Device Marks
PRODUCT SAMPLE MECHANICAL
PART NUMBER MARKING MARKING SAMPLE MARKING
MT28C3212P2FL-10 BET FW443 FX443 FY443
MT28C3212P2FL-10 TET FW442 FX442 FY442
MT28C3212P2FL-11 BET FW444 FX444 FY444
MT28C3212P2FL-11 TET FW433 FX433 FY433
MT28C3212P2NFL-11 TET FW445 FX445 FY445
GENERAL DESCRIPTION
The MT28C3212P2FL and MT28C3212P2NFL combination Flash and SRAM memory devices provide a
compact, low-power solution for systems where PCB
real estate is at a premium. The dual-bank Flash is a
high-performance, high-density, nonvolatile memory
device with a revolutionary architecture that can significantly improve system performance.
This new architecture features:
• A two-memory-bank configuration supporting
dual-bank burst operation;
• A high-performance bus interface providing a fast
page data transfer; and
• A conventional asynchronous bus interface.
The device also provides soft protection for blocks
by configuring soft protection registers with dedicated
command sequences. For security purposes, dual 64bit chip protection registers are provided.
The embedded WORD WRITE and BLOCK ERASE
functions are fully automated by an on-chip write state
machine (WSM). The WSM simplifies these operations
and relieves the system processor of secondary tasks.
An on-chip status register, one for each bank, can be
used to monitor the WSM status to determine the
progress of a PROGRAM/ERASE command.
The erase/program suspend functionality allows
compatibility with existing EEPROM emulation software packages.
The device takes advantage of a dedicated power
source for the Flash device (F_VCC) and a dedicated
power source for the SRAM device (S_VCC), both at
1.65V–1.95V or 1.80V–2.20V for optimized power consumption and improved noise immunity. The
MT28C3212P2FL and MT28C3212P2NFL devices sup-
port two VPP voltage ranges, VPP1 and VPP2. VPP1 is an incircuit voltage of 0.9V–2.2V (MT28C3212P2FL) or 0.0V–
2.2V (MT28C3212P2NFL). VPP2 is the production compatibility voltage of 12V ±5%. The 12V ±5% VPP2 is supported for a maximum of 100 cycles and 10 cumulative
hours. See Table 1.
The MT28C3212P2FL and MT28C3212P2NFL devices contain an asynchronous 2Mb SRAM organized
as 128K-words by 16 bits. These devices are fabricated
using an advanced CMOS process and high-speed/
ultra-low-power circuit technology.
The MT28C3212P2FL and MT28C3212P2NFL devices are packaged in a 66-ball FBGA package with
0.80mm pitch.
DEVICE MARKING
Due to the size of the package, Micron’s standard
part number is not printed on the top of each device.
Instead, an abbreviated device mark comprised of a
five-digit alphanumeric code is used. The abbreviated
device marks are cross referenced to Micron part numbers in Table 2.
Table 1
VPP Voltage Ranges
VOLTAGE RANGE
DEVICE VPP1 VPP2
MT28C3212P2FL 0.9V–2.2V 11.4V–12.6V
MT28C3212P2NFL 0.0V–2.2V 11.4V–12.6V
3
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
PART NUMBERING INFORMATION
Micron’s low-power devices are available with sev-
eral different combinations of features (see Figure 1).
Table 3
Valid Part Number Combinations
BOOT BLOCK OPERATING
V
PP1 ACCESS STARTING TEMPERATURE
PART NUMBER RANGE TIME (ns) ADDRESS RANGE
MT28C3212P2FL-10 BET 0.9V–2.2V 100 Bottom -40oC to +85oC
MT28C3212P2FL-10 TET 0.9V–2.2V 100 Top -40oC to +85oC
MT28C3212P2FL-11 BET 0.9V–2.2V 110 Bottom -40oC to +85oC
MT28C3212P2FL-11 TET 0.9V–2.2V 110 Top -40oC to +85oC
MT28C3212P2NFL-11 TET 0.0V–2.2V 110 Top -40
o
C to +85oC
MT 28C 321 2 P 2 N FL-11 T ET
Micron Technology
Flash Family
28C = Dual-Supply Flash/SRAM Combo
Density/Organization/Banks
321 = 32Mb (2,048K x 16)
bank a = 1/8; bank b = 7/8
SRAM Density
2 = 2Mb SRAM (128K x 16)
Access Time
-10 = 100ns
-11 = 110ns
Read Mode Operation
P = Asynchronous/Page Read
Package Code
FL = 66-ball FBGA (8 x 8 grid)
Operating Temperature Range
None = Commercial (0ºC to +70ºC)
ET = Extended (-40ºC to +85ºC)
V
PP1
Range
None = 0.9V–2.2V
N = 0.0V–2.2V
Boot Block Starting Address
B = Bottom boot
T = Top boot
Operating Voltage Range
2 = 1.65V–1.95V or 1.80V–2.20V
Figure 1
Part Number Chart
Valid combinations of features and their corresponding part numbers are listed in Table 3.
4
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
BLOCK DIAGRAM
F_V
PP
S_OE#
S_CE2
S_CE1#
S_WE#
DQ0
–
DQ15
A17
–
A20
A0
–
A16
F_RP#
F_CE#
F_OE#
F_WE#
F_V
CC
F_WP#
F_V
SS
FLASH
SRAM
S_V
SS
S_UB#
S_LB#
2,048K x 16
128K x 16
Bank a
Bank b
S_V
CC
VCCQ
FLASH FUNCTIONAL BLOCK DIAGRAM
Address
Input
Buffer
X DEC
Y/Z DEC
Data Input
Buffer
Output
Multiplexer
Address
CNT/WSM
Output
Buffer
Status
Reg.
WSM
Program/
Erase
Pump Voltage
Generators
Address Latch
DQ0-DQ15
DQ0–DQ15
CSM
F_RST#
F_CE#
X DEC
Y/Z DEC
F_WE#
F_OE#
I/O Logic
A0–A20
Address
Multiplexer
Bank 2 Blocks
Y/Z Gating/Sensing
Data
Register
Bank 1 Blocks
Y/Z Gating/Sensing
ID Reg.
RCR
Block Lock
Device ID
Manufacturer’s ID
OTP
Query
PR Lock
Query/OTP
PR Lock
5
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
BALL DESCRIPTIONS
66-BALL FBGA
NUMBERS SYMBOL TYPE DESCRIPTION
A3, A4, A5, A6, A0–A20 Input Address Inputs: Inputs for the addresses during READ and WRITE
A7, A8, B3, B4, operations. Addresses are internally latched during READ and WRITE
B5, B6, E5, G3, cycles. Flash: A0–A20; SRAM: A0–A16.
G4, G5, G6, G7,
G8, G9, H4, H5,
H6
H7 F_CE# Input Flash Chip Enable: Activates the device when LOW. When CE# is HIGH,
the device is disabled and goes into standby power mode.
H9 F_OE# Input Flash Output Enable: Enables Flash output buffers when LOW. When
F_OE# is HIGH, the output buffers are disabled.
C3 F_WE# Input Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle.
F_WE# is active LOW.
D4 F_RP# Input Reset. When F_RP# is a logic LOW, the device is in reset, which drives
the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH,
the device is in standard operation. When F_RP# transitions from logic
LOW to logic HIGH, the device resets all blocks to locked and defaults to
the read array mode.
E3 F_WP# Input Flash Write Protect. Controls the lock down function of the flexible
locking feature.
G10 S_CE1# Input SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level
deselects the SRAM and reduces the power consumption to standby
levels.
D8 S_CE2 Input SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level
deselects the SRAM and reduces the power consumption to standby
levels.
F5 S_OE# Input SRAM Output Enable: Enables SRAM output buffers when LOW. When
S_OE# is HIGH, the output buffers are disabled.
B8 S_WE# Input SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle.
S_WE# is active LOW.
F3 S_LB# Input SRAM Lower Byte: When LOW, it selects the SRAM address lower byte
(DQ0–DQ7).
F4 S_UB# Input SRAM Upper Byte: When LOW, it selects the SRAM address upper byte
(DQ8–DQ15).
B7, B9, B10, DQ0–DQ15 Input/ Data Inputs/Outputs: Input array data on the second CE# and WE#
C7, C8, C9, Output cycle during PROGRAM command. Input commands to the command
C10, D7, E6, user interface when CE# and WE# are active. Output data when CE#
E8, E9, E10, and OE# are active.
F7, F8, F9, F10
(continued on next page)
6
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
BALL DESCRIPTIONS (continued)
66-BALL FBGA
NUMBERS SYMBOL TYPE DESCRIPTION
E4 F_VPP Input/ Flash Program/Erase Power Supply: [0.9V–2.2V or 11.4V–12.6V].
Supply Operates as input at logic levels to control complete device protection.
Provides backward compatibility for factory programming when driven
to 11.4V–12.6V. A lower F_VPP voltage range (0.0V–2.2V) is available on
the MT28C3212P2NFL device.
D10, H3 F_VCC Supply Flash Power Supply: [1.65V–1.95V or 1.80V–2.20V]. Supplies power for
device operation.
A9, H8 F_VSS Supply Flash Specific Ground: Do not float any ground pin.
D9 S_VCC Supply SRAM Power Supply: [1.65V–1.95V or 1.80V–2.20V]. Supplies power for
device operation.
D3 S_VSS Supply SRAM Specific Ground: Do not float any ground pin.
A10 VCCQ Supply I/O Power Supply: [1.65–1.95V or 1.80V–2.20V]. This input should be tied
directly to VCC.
A1, A2, A11, NC – No Connect: Lead is not internally connected; it may be driven or
A12, C4, H1, floated.
H2, H10, H11,
H12
7
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
NOTE: 1. Two devices may not drive the memory bus at the same time.
2. Allowable flash read modes include read array, read query, read configuration, and read status.
3. Outputs are dependent on a separate device controlling bus outputs.
4. Modes of the Flash and SRAM can be interleaved so that while one is disabled, the other controls outputs.
5. SRAM is enabled and/or disabled with the logical function: S_CE1# or S_CE2.
6. Simultaneous operations can exist, as long as the operations are interleaved such that only one device attempts to
control the bus outputs at a time.
7. Data output on lower byte only; upper byte High-Z.
8. Data output on upper byte only; lower byte High-Z.
9. Data input on lower byte only.
10. Data input on upper byte only.
TRUTH TABLE – FLASH
FLASH SIGNALS SRAM SIGNALS MEMORY OUPUT
MODES
F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB#
MEMORY DQ0–DQ15 NOTES
BUS CONTROL
Read H L L H SRAM must be High-Z Flash DOUT 1, 2, 3
Write H L H L Flash DIN 1
Standby H H X X Other High-Z 4
Output Disable H L H H SRAM any mode allowable Other High-Z 4, 5
Reset L X X X Other High-Z 4, 6
TRUTH TABLE – SRAM
FLASH SIGNALS SRAM SIGNALS MEMORY OUPUT
MODES
F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB#
MEMORY DQ0–DQ15 NOTES
BUS CONTROL
Read
DQ0–DQ15 L H L H L L SRAM D OUT 1, 3
DQ0–DQ7 L H L H H L SRAM DOUT LB 7
DQ8–DQ15 Flash must be High-Z L H L H L H SRAM DOUT UB 8
Write
DQ0–DQ15 L H H L L L SRAM D IN 1, 3
DQ0–DQ7 L H H L H L SRAM DIN LB 9
DQ8–DQ15 L H H L L H SRAM DIN UB 10
Standby H X X X X X Other High-Z 4
Flash any mode allowable X L X X X X Other High-Z 4
Output Disable L H X X X X Other High-Z 4
FLASH
8
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
ARCHITECTURE AND MEMORY
ORGANIZATION
The Flash memory device contains two separate
memory banks (bank a and bank b) for simultaneous
READ and WRITE operations. Bank a is 2Mb deep and
contains 8 x 4K-word parameter blocks and seven 32K-
word blocks. Bank b is 28Mb deep, is equally sectored,
and contains fifty-six 32K-word blocks.
Figures 2 and 3 show the top and bottom memory
organizations.
FLASH
9
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Figure 2
Bottom Boot Block Device
Bank b = 28Mb
Block Block Size Address Range
(K-bytes/K-words) (x16)
70 64/32 1F8000h-1FFFFFh
69 64/32 1F0000h-1F7FFFh
68 64/32 1E8000h-1EFFFFh
67 64/32 1E0000h-1E7FFFh
66 64/32 1D8000h-1DFFFFh
65 64/32 1D0000h-1D7FFFh
64 64/32 1C8000h-1CFFFFh
63 64/32 1C0000h-1C7FFFh
62 64/32 1B8000h-1BFFFFh
61 64/32 1B0000h-1B7FFFh
60 64/32 1A8000h-1AFFFFh
59 64/32 1A0000h-1A7FFFh
58 64/32 198000h-19FFFFh
57 64/32 190000h-197FFFh
56 64/32 188000h-18FFFFh
55 64/32 180000h-187FFFh
54 64/32 178000h-17FFFFh
53 64/32 170000h-177FFFh
52 64/32 168000h-16FFFFh
51 64/32 160000h-167FFFh
50 64/32 158000h-15FFFFh
49 64/32 150000h-157FFFh
48 64/32 148000h-14FFFFh
47 64/32 140000h-147FFFh
46 64/32 138000h-13FFFFh
45 64/32 130000h-137FFFh
44 64/32 128000h-12FFFFh
43 64/32 120000h-127FFFh
42 64/32 118000h-11FFFFh
41 64/32 110000h-117FFFh
40 64/32 108000h-10FFFFh
39 64/32 100000h-107FFFh
38 64/32 0F8000h-0FFFFFh
37 64/32 0F0000h-0F7FFFh
36 64/32 0E8000h-0EFFFFh
35 64/32 0E0000h-0E7FFFh
34 64/32 0D800h-0DFFFFh
33 64/32 0D0000h-0D7FFFh
32 64/32 0C8000h-0CFFFFh
31 64/32 0C0000h-0C7FFFh
30 64/32 0B8000h-0BFFFFh
29 64/32 0B0000h-0B7FFFh
28 64/32 0A8000h-0AFFFFh
27 64/32 0A0000h-0A7FFFh
26 64/32 098000h-097FFFh
25 64/32 090000h-097FFFh
24 64/32 088000h-087FFFh
23 64/32 080000h-087FFFh
22 64/32 078000h-07FFFFh
21 64/32 070000h-077FFFh
20 64/32 068000h-067FFFh
19 64/32 060000h-067FFFh
18 64/32 058000h-05FFFFh
17 64/32 050000h-057FFFh
16 64/32 048000h-04FFFFh
15 64/32 040000h-047FFFh
Bank a = 4Mb
Block Block Size Address Range
(K-bytes/K-words) (x16)
14 64/32 038000h-03FFFFh
13 64/32 030000h-037FFFh
12 64/32 028000h-02FFFFh
11 64/32 020000h-027FFFh
10 64/32 018000h-01FFFFh
9 64/32 010000h-017FFFh
8 64/32 008000h-00FFFFh
7 8/4 007000h-007FFFh
6 8/4 006000h-006FFFh
5 8/4 005000h-005FFFh
4 8/4 004000h-004FFFh
3 8/4 003000h-003FFFh
2 8/4 002000h-002FFFh
1 8/4 001000h-001FFFh
0 8/4 000000h-000FFFh
FLASH
10
2 Meg x 16 Page Flash 128K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT28C3212P2FL_2.p65 – Rev. 2, Pub. 4/02 ©2002, Micron Technology, Inc.
2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
Figure 3
Top Boot Block Device
Bank b = 28Mb
Block Block Size Address Range
(K-bytes/K-words) (x16)
55 64/32 1B8000h-1BFFFFh
54 64/32 1B0000h-1B7FFFh
53 64/32 1A8000h-1AFFFFh
52 64/32 1A0000h-1A7FFFh
51 64/32 198000h-19FFFFh
50 64/32 190000h-197FFFh
49 64/32 188000h-18FFFFh
48 64/32 180000h-187FFFh
47 64/32 178000h-17FFFFh
46 64/32 170000h-177FFFh
45 64/32 168000h-16FFFFh
44 64/32 160000h-167FFFh
43 64/32 158000h-15FFFFh
42 64/32 150000h-157FFFh
41 64/32 148000h-14FFFFh
40 64/32 140000h-147FFFh
39 64/32 138000h-13FFFFh
38 64/32 130000h-137FFFh
37 64/32 128000h-12FFFFh
36 64/32 120000h-127FFFh
35 64/32 118000h-11FFFFh
34 64/32 110000h-117FFFh
33 64/32 108000h-10FFFFh
32 64/32 100000h-107FFFh
31 64/32 0F8000h-0FFFFFh
30 64/32 0F0000h-0F7FFFh
29 64/32 0E8000h-0EFFFFh
28 64/32 0E0000h-0E7FFFh
27 64/32 0D8000h-0DFFFFh
26 64/32 0D0000h-0D7FFFh
25 64/32 0C8000h-0CFFFFh
24 64/32 0C0000h-0C7FFFh
23 64/32 0B8000h-0BFFFFh
22 64/32 0B0000h-0B7FFFh
21 64/32 0A8000h-0AFFFFh
20 64/32 0A0000h-0A7FFFh
19 64/32 098000h-09FFFFh
18 64/32 090000h-097FFFh
17 64/32 088000h-08FFFFh
16 64/32 080000h-087FFFh
15 64/32 078000h-07FFFFh
14 64/32 070000h-077FFFh
13 64/32 068000h-06FFFFh
12 64/32 060000h-067FFFh
11 64/32 058000h-05FFFFh
10 64/32 050000h-057FFFh
9 64/32 048000h-04FFFFh
8 64/32 040000h-047FFFh
7 64/32 038000h-03FFFFh
6 64/32 030000h-037FFFh
5 64/32 028000h-02FFFFh
4 64/32 020000h-027FFFh
3 64/32 018000h-01FFFFh
2 64/32 010000h-017FFFh
1 64/32 008000h-00FFFFh
0 64/32 000000h-007FFFh
Bank a = 4Mb
Block Block Size Address Range
(K-bytes/K-words) (x16)
70 8/4 1FF000h-1FFFFFh
69 8/4 1FE000h-1FEFFFh
68 8/4 1FD000h-1FDFFFh
67 8/4 1FC000h-1FCFFFh
66 8/4 1FB000h-1FBFFFh
65 8/4 1FA000h-1FAFFFh
64 8/4 1F9000h-1F9FFFh
63 8/4 1F8000h-1F8FFFh
62 64/32 1F0000h-1F7FFFh
61 64/32 1E8000h-1EFFFFh
60 64/32 1E0000h-1E7FFFh
59 64/32 1D8000h-1DFFFFh
58 64/32 1D0000h-1D7FFFh
57 64/32 1C8000h-1CFFFFh
56 64/32 1C0000h-1C7FFFh
FLASH
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2 MEG x 16 PAGE FLASH
128K x 16 SRAM COMBO MEMORY
FLASH MEMORY OPERATING MODES
COMMAND STATE MACHINE
Commands are issued to the command state machine (CSM) using standard microprocessor write timings. The CSM acts as an interface between external
microprocessors and the internal write state machine
(WSM). The available commands are listed in Table 4,
their definitions are given in Table 5 and their descriptions in Table 6. Program and erase algorithms are automated by the on-chip WSM. Table 7 shows the CSM
transition states. Once a valid PROGRAM/ERASE command is entered, the WSM executes the appropriate
algorithm, which generates the necessary timing signals to control the device internally. A command is
valid only if the exact sequence of WRITEs is completed.
After the WSM completes its task, the write state machine status (WSMS) bit (SR7) (see Table 9) is set to a
logic HIGH level (VIH), allowing the CSM to respond to
the full command set again.
OPERATIONS
Device operations are selected by entering a standard JEDEC 8-bit command code with conventional
microprocessor timings into an on-chip CSM through
I/O pins DQ0–DQ7. The number of bus cycles required
to activate a command is typically one or two. The first
operation is always a WRITE. Control pins F_CE# and
F_WE# must be at a logic LOW level (VIL), and F_OE#
and F_RP# must be at logic HIGH (VIH). The second
operation, when needed, can be a WRITE or a READ
depending upon the command. During a READ operation, control pins F_CE# and F_OE# must be at a logic
LOW level (VIL), and F_WE# and F_RP# must be at logic
HIGH (VIH).
Table 8 illustrates the bus operations for all the
modes: write, read, reset, standby, and output disable.
When the device is powered up, internal reset circuitry initializes the chip to a read array mode of operation. Changing the mode of operation requires that a
command code be entered into the CSM. For each one
of the two flash memory partitions, an on-chip status
register is available. These two registers allow the monitoring of the progress of various operations that can
take place on a memory bank. One of the two status
registers is interrogated by entering a READ STATUS
REGISTER command onto the CSM (cycle 1), specifying an address within the memory partition boundary,
and reading the register data on I/O pins DQ0–DQ7
(cycle 2). Status register bits SR0-SR7 correspond to
DQ0–DQ7 (see Table 9).
COMMAND DEFINITION
Once a specific command code has been entered,
the WSM executes an internal algorithm, generating
the necessary timing signals to program, erase, and
verify data. See Table 5 for the CSM command definitions and data for each of the bus cycles.
STATUS REGISTER
The status register allows the user to determine
whether the state of a PROGRAM/ERASE operation is
pending or complete. The status register is monitored
by toggling F_OE# and F_CE# and reading the resulting status code on I/O pins DQ0–DQ7. The high-order
I/Os (DQ8–DQ15) are set to 00h internally, so only the
Table 4
Command State Machine Codes For Device Mode Selection
COMMAND DQ0–DQ7 CODE ON DEVICE MODE
10h/40h Program setup/alternate program setup
20h Block erase setup
50h Clear status register
60h Protection configuration setup
70h Read status register
90h Read protection configuration register
98h Read query
B0 h Program/erase suspend
C0h Protection register program/lock
D0h Program/erase resume - erase confirm
FF h Read array
FLASH
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2 MEG x 16 PAGE FLASH
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low-order I/O pins (DQ0–DQ7) need to be interpreted.
Address lines select the status register pertinent to the
selected memory partition.
Register data is updated and latched on the rising
edge of F_OE# or F_CE#, whichever occurs first. The
latest falling edge of either of these two signals updates the latch within a given READ cycle. Latching the
data prevents errors from occurring if the register input
changes during a status register read.
The status register provides the internal state of the
WSM to the external microprocessor. During periods
when the WSM is active, the status register can be polled
to determine the WSM status. Table 9 defines the status register bits.
After monitoring the status register during a
PROGRAM/ERASE operation, the data appearing on
DQ0–DQ7 remains as status register data until a new
command is issued to the CSM. To return the device to
other modes of operation, a new command must be
issued to the CSM.
COMMAND STATE MACHINE OPERATIONS
The CSM decodes instructions for the commands
listed in Table 4. The 8-bit command code is input to
the device on DQ0–DQ7 (see Table 5 for command
definitions). During a PROGRAM or ERASE cycle, the
CSM informs the WSM that a PROGRAM or ERASE cycle
has been requested.
During a PROGRAM cycle, the WSM controls the
program sequences and the CSM responds to a PROGRAM SUSPEND command only.
During an ERASE cycle, the CSM responds to an
ERASE SUSPEND command only. When the WSM has
completed its task, the WSMS bit (SR7) is set to a logic
HIGH level and the CSM responds to the full command
set. The CSM stays in the current command state until
the microprocessor issues another command.
The WSM successfully initiates an ERASE or PROGRAM operation only when VPP is within its correct voltage range.
Table 5
Command Definitions
FIRST BUS CYCLE SECOND BUS CYCLE
COMMAND OPERATION ADDRESS DATA OPERATION ADDRESS DATA
READ ARRAY WRITE WA F Fh
READ PROTECTION CONFIGURATION REGISTER WRITE IA 90h READ I A ID
READ STATUS REGISTER WRITE BA 70h READ BA SRD
CLEAR STATUS REGISTER WRITE BA 50h
READ QUERY WRITE QA 98h READ QA QD
BLOCK ERASE SETUP WRITE BA 20h WRITE BA D0h
PROGRAM SETUP/ALTERNATE PROGRAM SETUP WRITE WA 40h/10h WRITE WA WD
PROGRAM/ERASE SUSPEND WRITE BA B0h
PROGRAM/ERASE RESUME - ERASE CONFIRM WRITE BA D0h
LOCK BLOCK WRITE BA 60h WRITE BA 01h
UNLOCK BLOCK WRITE BA 60h WRITE BA D0h
LOCK DOWN BLOCK WRITE BA 60h WRITE BA 2Fh
PROTECTION REGISTER PROGRAM WRITE PA C0h WRITE PA PD
PROTECTION REGISTER LOCK WRITE LPA C0h WRITE LPA FFFDh
NOTE: 1. WA: Word address of memory location to be written, or read
2. IA: Identification code address
3. BA: Address within the block
4. ID: Identification code data
5. SRD: Data read from the status register
6. QA: Query code address
7. QD: Query code data
8. WD: Data to be written at the location WA
9. PA: Protection register address
10. LPA: Lock protection register address
11. PD: Protection register data
FLASH
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2 MEG x 16 PAGE FLASH
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Table 6
Command Descriptions
CODE DEVICE MODE BUS CYCLE DESCRIPTION
10h Alt. Program Setup First Operates the same as a PROGRAM SETUP command.
20h Erase Setup First Prepares the CSM for an ERASE CONFIRM command. If the next
command is not ERASE CONFIRM, the CSM sets both SR4 and SR5 of
the status register to a “1,” places the device into read status register
mode, and waits for another command.
40h Program Setup First A two-cycle command: The first cycle prepares for a PROGRAM
operation, the second cycle latches addresses and data and initiates
the WSM to execute the program algorithm. The Flash outputs status
register data on the falling edge of F_OE# or F_CE#, whichever
occurs first.
50h Clear Status First The WSM can set the program status (SR4), and erase status (SR5) bits
Register in the status register to “1,” but it cannot clear them to “0.” Issuing
this command clears those bits to “0.”
60h Protection First Prepares the CSM for changes to the block locking status. If the next
Configuration command is not BLOCK UNLOCK, BLOCK LOCK or BLOCK LOCK
Setup DOWN, then the CSM sets both the program and erase status register
bits to indicate a command sequence error.
70h Read Status First Places the device into read status register mode. Reading the device
Register outputs the contents of the status register, regardless of the address
presented to the device. The device automatically enters this mode
after a PROGRAM or ERASE operation has been initiated.
90h Read Protection First Puts the device into the read protection configuration mode so that
Configuration reading the device outputs the manufacturer/device codes or block
lock status.
98h Read Query First Puts the device into the read query mode so that reading the device
outputs common Flash interface information.
B0h Program Suspend First Suspends the currently executing PROGRAM/ERASE operation. The
status register indicates when the operation has been successfully
Erase Suspend First suspended by setting either the program suspend (SR2) or erase
suspend (SR6) and the WSMS bit (SR7) to a “1” (ready). The WSM
continues to idle in the suspend state, regardless of the state of all
input control pins except F_RP#, which immediately shuts down the
WSM and the remainder of the chip if F_RP# is driven to VIL.
C0h Program Device First Writes a specific code into the device protection register.
Protection Register
Lock Device First Locks the device protection register; data can no longer be changed.
Protection register
(continued on the next page)
FLASH
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Table 6
Command Descriptions (continued)
CODE DEVICE MODE BUS CYCLE DESCRIPTION
D0h Erase Confirm First If the previous command was an ERASE SETUP command, then the
CSM closes the address and data latches, and it begins erasing the
block indicated on the address pins. During programming/erase, the
device responds only to the READ STATUS REGISTER, PROGRAM
SUSPEND, or ERASE SUSPEND commands and outputs status register
data on the falling edge of F_OE# or F_CE#, whichever occurs last.
Program/Erase First If a PROGRAM or ERASE operation was previously suspended, this
Resume command resumes the operation.
FFh Read Array First During the array mode, array data is output on the data bus.
01h Lock Block Second If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM latches the address and locks the block indicated on the
address bus.
2Fh Lock Down Second If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM latches the address and locks down the block indicated on
the address bus.
D0h Unlock Block Second If the previous command was PROTECTION CONFIGURATION SETUP,
the CSM latches the address and unlocks the block indicated on the
address bus. If the block had been previously set to lock down, this
operation has no effect.
00h Invalid/Reserved Unassigned command that should not be used.
FLASH
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CLEAR STATUS REGISTER
The internal circuitry can set, but not clear, the block
lock status bit (SR1), the VPP status bit (SR3), the program status bit (SR4), and the erase status bit (SR5) of
the status register. The CLEAR STATUS REGISTER command (50h) allows the external microprocessor to clear
these status bits and synchronize to the internal operations. When the status bits are cleared, the device
returns to the read array mode.
READ OPERATIONS
The following READ operations are available: READ
ARRAY, READ PROTECTION CONFIGURATION REGISTER, READ QUERY and READ STATUS REGISTER.
READ ARRAY
The array is read by entering the command code
FFh on DQ0–DQ7. Control pins F_CE# and F_OE# must
be at a logic LOW level (VIL), and F_WE# and F_RP#
must be at a logic HIGH level (VIH) to read data from the
array. Data is available on DQ0–DQ15. Any valid address within any of the blocks selects that address and
allows data to be read from that address. Upon initial
power-up, the device defaults to the read array mode.
READ CHIP PROTECTION IDENTIFICATION DATA
The chip identification mode outputs three types
of information: the manufacturer/device identifier, the
block locking status, and the protection register. Two
bus cycles are required for this operation: the chip identification data is read by entering the command code
90h on DQ0–DQ7 to the bank containing address 00h
and the identification code address on the address
lines. Control pins F_CE# and F_OE# must be at a logic
LOW level (VIL), and F_WE# and F_RP# must be at a
logic HIGH level (VIH) to read data from the protection
configuration register. Data is available on DQ0–DQ15.
After data is read from the protection configuration
register, the READ ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. See Table 11 for further details.
READ QUERY
The read query mode outputs common Flash interface (CFI) data when the device is read (see Table 15).
Two bus cycles are required for this operation. It is
possible to access the query by writing the read query
command code 98h on DQ0–DQ7. Control pins F_CE#
and F_OE# must be at a logic LOW level (VIL), and F_WE#
and F_RP# must be at a logic HIGH level (VIH) to read
data from the query. The CFI data structure contains
information such as block size, density, command set,
and electrical specifications. To return to read array
mode, write the read array command code FFh on DQ0–
DQ7.
READ STATUS REGISTER
The status register is read by entering the command
code 70h on DQ0–DQ7. Two bus cycles are required for
this operation: one to enter the command code and a
second to read the status register. In a READ cycle, the
address is latched and register data is updated on the
falling edge of F_OE# or F_CE#, whichever occurs last.
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