Micron GDDR6 User Manual
Technical Note
GDDR6: Design Guide
Introduction
GDDR6 is a high-speed synchronous dynamic random-access (SDRAM) memory designed to support applications requiring high bandwidth such as graphic cards, game
consoles, and high-performance compute systems, as well as emerging applications
that demand even higher memory bandwidth.
In addition to standard graphics GDDR6, Micron offers two additional GDDR6 devices:
GDDR6 networking (GDDR6N) and GDDR6 automotive. GDDR6N is targeted at networking and enterprise-class applications. GDDR6 automotive is targeted for automotive requirements and processes. All three Micron GDDR6 devices have been designed
and tested to meet the needs of their specific applications for bandwidth, reliability and
longevity.
This technical note is designed to help readers implement GDDR6 as an off-the-shelf
memory with established packaging, handling and testing. It outlines best practices for
signal and power integrity, as well as standard GDDR6 DRAM features, to help new system designs achieve the high data rates offered by GDDR6.
TN-ED-04: GDDR6 Design Guide
Introduction
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Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by
Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications. All
information discussed herein is provided on an "as is" basis, without warranties of any kind.
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© 2018 Micron Technology, Inc. All rights reserved.
GDDR6 Overview
TN-ED-04: GDDR6 Design Guide
GDDR6 Overview
In the DRAM evolutionary process, GDDR6 has made a significant leap in throughput
while maintaining standard packaging and assembly processes. While standard DRAM
speeds have continued to increase, development focus has been primarily on density —
often at the expense of bandwidth. GDDR has taken a different path, focusing on high
bandwidth. With DDR4 operating from 1.6 to 3.2 Gb/s, LPDDR4 up to 4.2 Gb/s, and
GDDR5N at 6 Gb/s, the increase in clock and data speeds has made it important to follow good design practices. Now, with GDDR6 speeds reaching 14 Gb/s and beyond, it is
critical to have designs that are well planned, simulated and implemented.
GDDR6 DRAM is high-speed memory designed specifically for applications requiring
high bandwidth. In addition to graphics, Micron GDDR6 is offered in networking
(GDDR6N) and automotive grades, sharing similar targets for extended reliability and
longevity. For the networking and automotive grade devices, maximum data rate and
voltage supply differ slightly from Micron graphics GDDR6 to help assure long-term reliability; all other aspects between Micron GDDR6, GDDR6N and GDDR6 automotive
are the same. All content discussed in this technical note applies equally to all GDDR6
products. 12 Gb/s will be used for examples, although higher rates may be available.
GDDR6 has 32 data pins, designed to operate as two independent x16 channels. It can
also operate as a single x32 (pseudo-channel) interface. A GDDR6 channel is point to
point, single DQ load. Designed for single rank only, with no allowances for multiple
rank configurations. Internally, the device is configured as a 16-bank DRAM and uses a
16n-prefetch architecture to achieve high-speed operation. The 16n-prefetch architecture is combined with an interface designed to transfer 8 data words per clock cycle at
the I/O pins.
Table 1: Micron GDDR and DDR4 DRAM Comparison
Clock Period (tCK) Data Rate (Gb/s)
Product
DDR4 1.25ns 0.625ns 1.6 3.2 4–16Gb 8n 8, 16
GDDR5 20ns 1.00ns 2 8 4–8Gb 8n 16
GDDR6 20ns 0.571ns 2 14 8–16Gb 16n 16
Density
Prefetch
(Burst
Length)
Number of
BanksMAX MIN MIN MAX
For more information, see the Micron GDDR6 The Next-Generation Graphics DRAM
technical note (TN-ED-03) available on micron.com.
Density
The JEDEC® standard for GDDR6 DRAM defines densities from 8Gb, 12Gb, 16Gb, 24Gb
to 32Gb. At the time of publication of this technical note, Micron supports 8Gb and
16Gb parts.
For applications that require higher density, GDDR6 can operate two devices on a single
channel (see Channel Options later in this document or the Micron GDDR6 data sheet
for details).
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Prefetch
CK
DQ,DBI_n
EDC
WCK
WCK
f (e.g. 1.5 GHz)
2f (e.g. 3 Gb/s)
2f (e.g. 3 GHz)
4f (e.g. 6 GHz)
8f (e.g. 12 Gb/s)
4f (e.g. 6 Gb/s)
CA
8f (e.g. 12 Gb/s)
EDC
(quad data rate)
(full data rate)
(half data rate)
(double data rate)
Frequency
TN-ED-04: GDDR6 Design Guide
GDDR6 Overview
Prefetch (burst length) is 16n, double that of GDDR5. GDDR5X was the first GDDR to
change to 16n prefetch, which, along with the 32-bit wide interface, meant an access
granularity of 64 bytes. GDDR6 now allows flexibility in access size by using two 16-bit
channels, each with a separate command and address. This allows each 16-bit channel
to have a 32-byte access granularity — the same as GDDR5.
Micron GDDR6N and GDDR6 automotive have been introduced with data rates of 10
Gb/s and 12 Gb/s (per pin). The JEDEC GDDR6 standard does not define AC timing parameters or clock speeds. Micron GDDR6 is initially available up to 14 Gb/s. Micron's
paper, 16 Gb/s and Beyond with Single-Ended I/O in High-Performance Graphics Memo-
ry, describes GDDR6 DRAM operation up to 16 Gb/s, and the possibility of operating
the data interface as high as 20 Gb/s (demonstrated on the interface only; the memory
array itself was not tested to this speed).
GDDR6 data frequency is 8X the input reference clock and 4X the WCK data clock frequency. WCK is provided by the host. The system should always be capable to provide
four WCK signals. (WCK per byte). Though not required by all DRAM, ability to supply
four WCK signals ensures compatibility with all GDDR6 components.
Figure 1: WCK Clocking Frequency and EDC Pin Data Rate Options (Example)
For more information on clocking speeds and options, see the Micron GDDR6 The
Next-Generation Graphics DRAM technical note (TN-ED-03) and the GDDR6N data
sheet (available upon request) on micron.com.
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Command Address
Bus Inversion
TN-ED-04: GDDR6 Design Guide
GDDR6 Overview
GDDR6 has a new “packetized” command address (CA) bus. Command and address are
combined into a single, 10-bit interface, operating at double data rate to CK. This eliminates chip select, address strobe, and write enable signals and minimizes the required
CA pin count to 12 per channel (or 16 in pseudo-channel mode). The elimination of a
CS aligns with the point-to-point nature of GDDR memory and reinforces the requirement that there is only a single (logical) device per memory interface (single DRAM or
two DRAM back-to-back in byte mode, operating as a single addressable memory).
As shown in the clock diagram, CA operates at double CK. The first half of command/
address is latched on the rising edge, and the second half of command/address is latched on the falling edge. Refer to the Command Truth Table in the product data sheet for
encoding of each command.
• DDR packetized CA bus CA[9:0] replaces the 15 command address signals used in
GDDR5.
• Command address bus inversion limits the number of CA bits driving low to 5, or 7, in
PC mode.
Data bus inversion (DBI) and command address bus inversion (CABI) are enabled in
mode register 1. Although optional, DBI and CABI are critical to high-speed signal integrity and are required for operation at full speed.
DBI is used in GDDR5 as well as DDR4, and CABI leverages address bus inversion (ABI)
from GDDR5. DBI and CABI:
• Drive fewer bits LOW (maximum of half of the bits are driven LOW, including the
DBI_n pin)
• Consume less power (only bits that are driven LOW consume power)
• Result in less noise and better data eye
• Apply to both READ and WRITE operations, which can be enabled separately
READ WRITE
If more than four bits of a byte are LOW:
— Invert output data
— Drive DBI_n pin LOW
If four or less bits of a byte lane are LOW:
— Do not invert output data
— Drive DBI_n pin HIGH
CRC Data Link Protection
GDDR6 provides data bus protection in the form of CRC. Micron GDDR6N supports
half or full data rate EDC function. At half rate, an 8-bit checksum is created per write or
read burst. The checksum uses a similar polynomial as the full data rate option to calculate two intermediate 8-bit checksums, and then compresses these two into a final 8-bit
checksum. This allows 100% fault detection coverage for random single, double and triple bit errors, and >99% fault detection for other random errors. The nature of the EDC
signal is such that it is always sourced from DRAM to controller, for both reads and
writes. Due to this, extra care is recommended during PCB design and analysis ensuring
the EDC net is evaluated for both near-end and far-end crosstalk.
If DBI_n input is LOW, write data is inverted
— Invert data internally before storage
If DBI_n input is HIGH, write data is not inverted
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Banks and Bank Grouping
Refer to Micron product data sheets for currently available speed grades and bank
grouping requirements.
Micron GDDR6 supports bank groups as defined in the JEDEC specification. Bank
groups are enabled through MR3; it is recommended that bank groups are disabled if
not required for the desired frequency of operation. Short timings are supported without bank groups. Enabling bank groups in MR3 will have no benefit, and results in a
small timing penalty by requiring use of tRRDL, tCCDL, tWTRL and tRTPL.
• GDDR6 has 16 banks.
• With bank groups enabled, organized as four bank groups, each comprised of four
sub-banks, per JEDEC.
• Maximum clock frequency with bank groups disabled is (fCKBG). Refer to product
specific data sheets for fCKBG specifications.
VPP Supply
VPP input—added with GDDR5X—is a 1.8V supply that powers the internal word line.
Adding the VPP supply facilitates the VDD transition to 1.35V and 1.25V and provides additional power savings. It is worth keeping in mind that IPP values are average currents,
and actual current draw will be narrow pulses in nature. Failure to provide sufficient
power to VPP prevents the DRAM from operating correctly.
TN-ED-04: GDDR6 Design Guide
GDDR6 Overview
V
REFC
V
REFD
POD I/O Buffers
GDDR6 has the option to use internal V
sults with good accuracy as well as allowing adjustability. V
× V
that the V
V
. External V
DDQ
input should be pulled to VSS using a zero ohm resistor.
REFC
is internally generated by the DRAM. V
REFD
is also acceptable. If internal V
REFC
. This method should provide optimum re-
REFC
has a default level of 0.7
REFC
is used, it is recommended
REFC
is now independent per data pin and
REFD
can be set to any value over a wide range. This means the DRAM controller must set the
DRAM’s V
settings to the proper value; thus, V
REFD
must be trained.
REFD
The I/O buffer is pseudo open drain (POD), as seen in the figure below. By being terminated to V
instead of half of V
DDQ
, the size and center of the signal swing can be cus-
DDQ
tom-tailored to each design’s need. POD enables reduced switching current when driving data since only zeros consume power, and additional switching current savings can
be realized with DBI enabled. An additional benefit with DBI enabled is a reduction in
switching noise resulting in a larger data-eye.
If not configured otherwise, termination and drive strength are automatically calibrated
within the selected range using the ZQ resistor. It is also possible to specify an offset or
disable the automatic calibration. It is expected that the system should perform optimally with auto calibration enabled.
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Figure 2: Signaling Schemes
SSTL POD15/POD125/POD135
TX
Z
V
REF
=
0.5 × V
DDQ
V
REF
=
0.7 × V
DDQ
V
DDQ
V
DDQ
V
DDQ
2 × R
TT
2 × R
TT
RX TX
Z
60Ω
RX
V
REF
V
DDQ
V
SSQ
V
IH
V
IL
V
REF
V
DDQ
V
SSQ
V
IH
V
IL
60Ω
40Ω
Clock Termination
GDDR6 includes the ability to apply ODT on CK_t/CK_c. The clock ODT configuration
is selected at reset initialization. Refer to Device Initialization in the product data sheet
for available modes and requirements. If ODT is not used, the clock signals should be
terminated on the PCB (similar to GDDR5), with CK_t and CK_c terminated independently (single-ended) to V
DDQ
TN-ED-04: GDDR6 Design Guide
GDDR6 Overview
.
JTAG Signals
GDDR6 includes boundary scan functionality to assist in testing. It is recommended to
take advantage of this capability if possible in the system. In addition to IO testing,
boundary scan can be used to read device temperature and V
system-wide JTAG, it might be considered to connect JTAG to test points or connector
for possible later use. If unused, the four JTAG signals are ok to float. TDO is High-Z by
default. TMS, TDI, and TCK have internal pull-ups. If pins are connected, a pull-up can
be installed on TMS to help ensure it remains inactive.
values. If there is no
REFD
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Channel Options
GDDR6 has the flexibility to operate the command and address busses in four different
configurations, allowing the device to be optimized for application-specific requirements:
• x16 mode (two independent x16 bit data channels)
• x8 mode (two devices, each with x8 channels, in a back-to-back "clamshell" configuration)
• 2-channel mode (two independent command/address busses)
• Pseudo channel (PC) mode (a single CA bus and combined x32 data bus; similar to
GDDR5 and GDDR5X)
These are configured by pin state during reset initialization (during initialization, the
pins are sampled to configure the options). The controller must meet device setup and
hold times (specified in the data sheet) prior to de-assertion of RESET_n (tATS and
t
ATH).
x16 Mode/x8 Mode (Clamshell)
GDDR6 standard mode of operation is x16 mode, providing two 16-bit channels. It is also possible to configure the device in a mode that provides two 8-bit wide channels for
clamshell configuration. This option puts each of the clamshell devices into a mode
where only half of each channel is used from each component (hence, the x8 designation).
TN-ED-04: GDDR6 Design Guide
Channel Options
• To be used for creating a clamshell (back-to-back) pair of two devices operating as a
single memory.
• Allows for a doubling of density. Two 8Gb devices appear to the controller as a single,
logical 16Gb device with two 16-bite wide channels.
• Configured by state of EDC1_A and EDC0_B, tied to VSS, at the time RESET_n is deasserted.
• One byte of each device is disabled and can be left floating (NC). Along with DQs for
the byte, DBI_n is also disabled, in High-Z state.
• Separate WCK must be provided for each byte. (WCK per word cannot be used in this
configuration)
2-Channel Mode/Pseudo Channel Mode
• 2-channel mode is the standard mode of operation for GDDR6. It is expected to return better performance in most cases.
• Configured by state of CA6_A and CA6_B at the time RESET_n is deasserted.
• The difference in CA bus pin usage between PC mode and 2-channel mode is that 8 of
the 12 CA pins (CKE_n, CA[9:4], CABI_n) are shared between both channels, while only the other four CA pins (CA[3:0]) are routed separately for each channel (similar to
GDDR5X operation).
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Figure 3: GDDR6 Pins in 2-Channel Mode
DQ[15:0],DBI[1:0]_n,EDC[1:0]
GDDR6
Bytes 0+1
Bytes 0 + 1
Control B
DQ[15:0],DBI[1:0]_n,EDC[1:0]
CKE_n,CA[9:0],CABI_n
Channel B
Channel A
Control A
CK_t/_c
CKE_n,CA[9:0],CABI_n
WCK0_t/_c,WCK1_t/_c
WCK0_t/_c,WCK1_t/_c
GDDR6
Bytes 0+1
Bytes 0 + 1
Control B
DQ[15:0],DBI[1:0]_n,EDC[1:0]
DQ[15:0],DBI[1:0]_n,EDC[1:0]
CA[3:0]
CA[3:0]
Channel B
Channel A
Control A
CK_t/_c
CKE_n,CA[9:4],CABI_n
WCK0_t/_c,WCK1_t/_c
WCK0_t/_c,WCK1_t/_c
Figure 4: GDDR6 Pins in Pseudo Channel Mode
TN-ED-04: GDDR6 Design Guide
Channel Options
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