Micro Medical SuperSpiro Service manual

Super Spiro - Service Manual
056-09 Issue. 1.0 November 1999
Contents
Microprocessor circuit Page 9 Flash disk Page 10 Serial interface Page 10 Transducer interface Page 10 Frame store Page 10 FPGA Page 11 Keypad circuit Page 11 Real time clock circuit Page 12 Sound generator circuit Page 12 Printer control circuit Page 12 Expansion Page 12 Printer driver circuit Page 12
Technical support Page 13 Fault analysis Page 14 Circuit diagrams
Micro processor circuit Page 15 FPGA circuit Page 16 Keypad circuit Page 17 Real time clock circuit Page 18 Printer circuit Page 19 Printer driver 1 Page 20 Printer driver 2 Page 21
2
Exploded Isometric View
Item 15
Item 1
Item 10
Item 16
Item 8
Item 20
Item 21
Item 22
Item 12
Item 14
Item 23
Item 13
Item 9
Item 2
Item 11
Item 18
Item 9
Item 7
Item 4
Item 6
Item 17
Item 5
Item 3
Item 19
3
Parts List
ITEM No.
1 TOP MOULDING MLD5611A 2 BACK PANEL MLD5615C 3 SIDE PANEL MLD5615B 4 DISPLAY CABLE ASSEMBLY ASS5624 5 BOTTOM MOULDING MLD5612A 6 HINGE BLOCK MLD5618 7 DISPLAY FRONT MLD5613 8 DISPLAY BACK MLD5614
9 DISPLAY HINGE ASSEMBLY ASS5601 10 PAPER COVER MLD5617 11 CSK SELF TAPPING SCREW 9mm LONG SCR5604 12 SPEAKER SPKR100 13 SPEAKER COVER MLD5620 14 CONTRAST WHEEL MLD5621 15 SCREW COVER MLD5616 16 CSK SELF TAPPING SCREW 8mm LONG SCR5602 17 CSK SELF TAPPING SCREW 13mm LONG SCR5601 18 M3 MACHINE SCREW 6mm LONG SCR0306 19 CSK SELF TAPPING SCREW 18mm LONG SCR4700 20 DISPLAY LATCH MLD5619 21 DISPLAY LATCH BUTTON MLD5622 22 PRINTER MECHANISM PTR4200 23 THERMAL PRINT HEAD TPH3000
DESCRIPTION MICRO MEDICAL PT No.
4
Super Spiro - System Overview (Fig. 1)
The Micro Medical Super Spiro is a data recording spirometer consisting of a microcomputer
unit (1) incorporating a 1/4VGA colour LCD display, data entry keypad, RS232 serial interface and all associated circuitry. It is supplied with a digital volume transducer (2), disposable mouthpieces, transducer holder (3) and mains adapter (4). The Super Spiro is powered by a universal mains adapter (4). When testing a subject the transducer is inserted into the holder which is plugged into the microcomputer unit. The digital volume transducer is used to measure the subjects expired flow and volume in accordance with the operating manual.
1
super
spiro
4
Micro
Medical
3
2
5
Transducer (Fig. 2)
The Micro Medical digital volume transducer consists of an acrylic tube with a vane positioned
between two swirl plates. The low inertia vane is attached to a stainless steel pivot, which is free to rotate on two jewelled bearings mounted at the centre of the swirl plates. As air is passed through the transducer the swirl plates create a vortex, which causes the vane to rotate in a direction dependant upon the direction of airflow. The number of rotations is proportional to the volume of air passed through the transducer and the frequency of rotation is proportional to the flow rate. The transducer housing consists of a main body that contains a pair of light emitting diodes (LED’s) and phototransistors. The transducer is fixed to the mouthpiece holder which pushes into the main body and is captured by an “O” ring seal. The LED’s produce infra red beams which are interrupted by the vane twice per revolution. This interruption is sensed by the phototransistors. The output from the collector of each phototransistor will be a square wave with a phase difference between the two of + or - 90 degrees depending upon the direction of flow. There is no routine maintenance required for the transducer other than cleaning according to the instructions in the operating manual.
Micro Medical Digital Volume Transducer
Volume proportional to the number of pulses Flow proportional to the puse frequency
Rotating
vane
Volume = k X No. of pulses
Infra red
emitter
Infra red detector
Swirl plate
Flow = k / pulse period
Jewelled
bearing
6
Disassembling the Super Spiro for Repairs
Main Unit
1. Disconnect all mains power supplies
2. Remove paper roll and paper roll housing cover, and put to one side
We recommend that you use a Philip Number Zero screwdriver for the following instruction.
3. Place the Super Spiro face down to remove the six screws (Item 19) in the lower moulding, and put the screws to one side.
4. Turn the unit face up before easing the upper and lower mouldings apart.
5. Reconnect mains power supply
6. The Super Spiro is now ready for fault finding.
Display Console
1. Remove the 4 screw covers (item 15) and dispose of.
We recommend that you use a Philip Number Zero screwdriver for the following instruction.
2. Remove the 4 screws (item 16) and put to one side.
3. Carefully remove the display front panel (item 7) and put to one side.
4. Carefully pull the display away from the display back moulding (item 8).
5. Unplug the 2 connectors from the main display.
6. The display backlight is now ready for replacement.
Display backlight replacement
DISPLAY (REAR VIEW)
CFL CONNECTOR INVERTOR BOARD
CFL UNIT
1. Place the display face down on a clean work surface
7
FIXING SCREW
I
T
KCS3224A CFL UN
2. Unplug the connector from the Invertor board situated on the back of the display.
We recommend that you use a Philip Number Zero screwdriver for the following instruction.
3. Loosen the fixing screw located on the CFL unit.
4. Slide the CFL unit to the opposite direction to the arrow mark (located on the CFL unit) and pull the unit gently up.
5. Safely dispose of the CFL unit.
6. Take a new CFL unit and position in the original place.
7. Slide the CFL unit in the direction of the arrow.
8. Tighten the fixing screw to secure the CFL unit.
9. Reconnect the connector on the CFL unit to the invertor board.
Reassembling the Superspiro after repairs
Main unit
1. Disconnect all mains power supplies
2. Position the top moulding over the bottom moulding and ensure that they both mate ensuring that the contrast wheel (item 14) is correctly located.
3. Place the Super Spiro face down and insert the six screws.
4. Turn the unit face up and connect the mains supply.
5. Turn the unit and offer up the paper roll as explained in the operating manual.
6. Replace the paper cover.
7. The Super Spiro is now ready for operation.
Display console
1. Reconnect the 2 connectors on item 4 to the plugs on the display ensuring correct polarity.
2. Position the display over the locating pillars on the display back panel (item 8).
3. Position the display front panel (item 7) over the display.
4. Secure the display using 4 screws (item 16)
5. Replace the 4 screw covers (item 15).
8
Circuit Description
The Super Spiro board was designed primarily to interface with the Micro Medical Spirometer turbine, but the interface was kept open ended so that other modules, for example, airways resistance by the interrupter method (Rint) can be attached. Furthermore, a 9 pin ‘D’ type connector was also designed in to allow other ‘customer special’ modules to be attached. Provision was given to add a mezzanine board for customer special interface circuitry to be connected.
The main features of the design are: Intel 80386EX micro controller.
2 Mbytes of DRAM (only 1 Meg is used). 512 Mbytes of Flash EPROM for programme. (256K used) 2 Mbytes of Flash EPROM as Flash disk memory. Dual frame store of 320 X 240 X 8 pixels. Second frame store can be scrolled horizontally or vertically. Frame store, key pad, Dram etc. are all controlled by single FPGA chip. Boot software can be downloaded using the JTAG port. In built printer and printer controller. Serial port for external PC communication / external printer. RJ11 interface to Micro Medical modules. The following paragraphs describe the circuits printed at the end of this manual. Signal and component names shown on the circuit diagrams are printed in bold type.
Microprocessor circuit (Drawing 056-02)
The board is controlled by an Intel 80386EX, U14, running at 25 MHz. The crystal oscillator, U15, of 50MHz drives the processor, as twice the operating frequency is required. U10 (MAX 824) controls the reset of the processor, such that it resets the processor if the supply voltage drops below 4.6V. The processor requires a high active reset line whilst the rest of the board requires a low active reset.
The start up program is stored in U20, a 512 Mbytes Flash EEPROM – TE28F160S. This is selected by the signal UCS (U14 pin 1) which is always active on start up. The reset of the chip select lines are then programmed by the boot routine.
The program memory has two major parts, the boot section and non-boot section. The boot section is secured, and can only be programmed if the link LK1 is present and VPPEN (U14 pin 110) is enabled, supplying VCC to pin 13 of U19. This section is programmed with a boot loader via the on­board socket, J9. Whilst this is happening the processor goes into suspend mode, and all its pins are then available in a long shift register. By entering a correct sequence of code, via J9, the boot loader can be programmed into U19. Once this is done, the link is removed and processor is reset and it would then run the boot loader, thus allowing further software to be downloaded. The rest of U19 is filled with kernel software that controls the flash disk as well as most I/O functions, just as the BIOS does in the PC.
U18 is 1M X 16 (2 Mbytes) DRAM which is the main RAM of the processor. Only 640 K is directly available to the processor, and 128 K is used for storing the display image temporarily (see later).
The DRAM refresh and address multiplexing is controlled by U13 – Xilinx XC4006E FPGA. The chip select for the DRAM, UC3, is mapped for 0 - $BFFFF, but $A0000 - $BFFFF is frame store memory, so UC3 is only valid if frame store is invalid. This will become clearer in the Frame Store section.
Q23, Q24 and U22A are used to switch on 5 volts to VPP of Flash EEPROM. This gives extra security against any part of the program becoming corrupted by software. However, the software can write the non-boot section, by enabling the VPP line and following the EEPOM erase/write algorithm. Chances of both these events accidentally happening are very small. Nevertheless, the boot software is completely protected by the absence of Link LK1.
9
Flash Disk (Drawing 056-02)
The flash disk, U20, behaves just like a PC floppy disk drive except that it is non-removable. Its size is 2 Mbytes with sector size of 512 bytes. The main difference is that there is a finite number (approximately 100,000) of times the sectors can be written, so an intelligent disk operating system is employed to rotate the sectors round, and delete the others when no system activity is envisaged. Delete takes few milliseconds. The Flash Disk is mapped at $C8000 - $CBFFF (16K blocks). There are 128 pages of 16K, and the pages are controlled by 8 bit latch U17, which holds the page number (higher addresses) of the Flash disk.
The board is designed to accommodate a larger 4 Mbytes device with 256 pages. The MSB of the page line (U17/19) is connected to green led. This is mainly used for testing of the
board and has no other significance.
Serial Interface (Drawing 056-02)
U4 (MAX3223) converts logic levels to RS232 levels. J3, a 9-pin female D type connector, is used as
the external RS232 port. The signal pins are such that it can make one to one connection with the PC serial port. It has the facility to use hardware handshaking lines CTS and RTS, but these are currently not used. If power supply is required from the RS232 connection, say to drive a serial to parallel converter, then fuse FS2 can be fitted to give 5V on pin 4
J3 pin connections.
1 N/C 2 TX 3 RX 4 5V* 5 GND 6 N/C 7 CTS 8 RTS 9 N/C
* If fuse connected.
Transducer Interface (Drawing 056-02)
The connector, J13, is used for connecting to Micro Medical transducers, namely Spirometer turbine, Rint and NEP transducers. It is a 6-pin interface, though for turbine, the middle 4 lines are used. 12V power is available on pin 5 and GND on pin 4. The rest of pins are multifunction, and can be configured in various ways, either as inputs, outputs or SPI bus. Pins 2 and 3 have schmitt trigger inputs connected to it, mainly for turbine operation.
Frame Store (Drawing 056-03)
Frame Stores are mapped from address $A0000 to $BFFFF (128 Kbytes). Although, the actual display is 320 X 240 pixels, the frame store is organised as 512 X 256 pixels. This organisation makes the design much simpler. The frame store memory U11 and U12 are both high speed static RAM, U11 being a fixed frame store (A) and U12 a scrolling frame store (B). They overlay on top of each other and their mode can be controlled by I/O register in the FPGA, U13. It can be organised as A on B, B on A, A only or B only. A on B means that where the A data is 0, B data is displayed. This allows a border to be displayed on fixed screen, and a waveform scrolled inside the window. During read, both the memories are multiplexed, so that its data can be read in one cycle. The display requires data as 8 bits, with r1, g1, b1, r2, g2, b2, r3, g3 as the first byte, b3, r4, g4, b4, r5, b5, g5, r5 as the second byte and so on. The data from frame store is available as pixel 1, pixel 2 etc. with each pixel being 8 bits. The FPGA has the necessary look up table to display 64 colours (bits 0 –
10
bits 5) and converts pixel data to RGB data as required by LCD. This is a complex operation and is beyond the scope of this document. It is sufficient to know that the RGB data is sent out to LCD via
J11. DISP_FRAME signal is a single line, active low pulse at the start of every frame.
DISP_LOAD is a single, active low, clock pulse at the start of every line. DISP_CLK clocks the data DISP_D0 – DISP_D7 into the display. DISP_CNTL enables the display.
U25 is a DC to DC converter to give 26.4 volts from 5V supply. This is the bias voltage for the LCD
display. It can be slightly adjusted by VR1 to give better contrast at different viewing angles. J10 is a back light connector that provides power to the back light. Q22 is used to enable the back
light. It was designed for power saving, but since the unit only operates on mains, this feature is not currently used. VR3 controls the back light intensity in some back light modules, but this feature is not in the modules currently fitted.
The frame store data can be saved quickly in the RAM that resides in the same address space, using a block transfer. This is done by first programming the CS3 line to address space $A0000 - $AFFFF. Since $B0000 - $BFFFF is now not the part of CS3, the FPGA will map it to DRAM. The whole 64K page can be transferred from $A0000 (frame store) to $B0000 (RAM). The CS3 line is then programmed for $B0000 - $BFFFF allowing $B0000 (frame store) page to be transferred to $A0000 (RAM) page. CS3 is then restored back to $A0000 - $BFFFF.
Restoring the screen is inverse of the above procedure.
FPGA (Drawing 056-03)
This device controls most of the circuitry not controlled by the processor. The program for the FPGA resides in serial EEPROM, U8, and is downloaded once on power up. The processor monitors the FPGADONE line to ensure that FPGA is programmed before commencing, otherwise, the DRAM will not be operational.
Besides DRAM, the FPGA controls the LCD display, keypad, sound chip, and most of chip select lines. These CS lines can be programmed in the processor, but this can be further qualified in the FPGA if necessary. There are some spare serial enable lines for an additional 9 pin I/O port and the mezzanine expansion board.
Keypad Circuit (Drawing 056-04)
The keypad consists of a matrix of 25 keys together with a separate paper feed key and on/off key. The matrix is read by successively pulling the columns of the matrix low, KEYOUT[0..4], and reading the state of the rows, KEYIN[0..4], to determine which key has been pressed. KEYOUT[0..4] and KEYIN[0..4] are connected directly to the FPGA (see 056-03). The diodes, D7and D8, prevent current flowing between the lines of KEYOUT[0..4] in the event of two keys on the same row being depressed simultaneously. The resistor network, RN5, bias KEYIN[0..4] to VCC. The on/off switch is used to apply the 5V from the external power supply to the circuit, VCC, and turning the unit on. When the on/off key is depressed, the pull up resistor, R3, is pulled to ground. R3, C17 and the schmitt input gate U3A form a de-bounce circuit whose output is applied to the clock input of a bi-stable latch, U2B, that is powered directly from 5V and is active all the time the power supply is plugged in. The output of the latch is applied to Q19 that in turn switches the series pass transistor, Q20, to connect 5V to VCC. The latch, U2B, is also controlled by the set and reset inputs. By taking the set input to 5V the unit will be turned on and by taking the reset input to 5V the unit will be turned off regardless of the clock input. The set input is asserted by either the real time clock alarm output, RTC_INT (see 056-05), or by the POWER_ON signal from the processor (see 056-02). The reset input is asserted or by the POWER_OFF signal from the processor.
11
Real Time Clock Circuit (Drawing 056-05)
The real time clock, U16, is set by the processor during the factory set-up and may be adjusted using the configuration module. The processor communicates with the real time clock through a bi­directional serial interface line, RCA_DATA, is clocked by RTS_CLK, and is selected by RTC_SEL. The processor (see 056-02) generates these three control lines.
Sound Generator Circuit (Drawing 056-05)
The various sounds used in the spirometry tests are generated by U7 and associated components. This device contains the addressable, pre-programmed sounds and is controlled by the lines,
SNDCNT[0..5], generated by the FPGA (see 056-03).
Printer Control Circuit (Drawing 056-06)
The printer driver uses a single chip micro-controller, U6, with on board program memory and RAM to receive serial data from the microprocessor, U14, and control the printer mechanism. The asynchronous serial lines PRNTDATA and PRNTACK are used by U14 to send and receive data to and from U6. The signal BUSY generated by U6 is used to control the flow of data from U14 and PF is generated by the paper feed key. The printer mechanism uses stepper motors to drive the print head and paper feed. Each stepper motor uses four lines, driven sequentially. The order in which the lines are driven determines the direction of rotation. The thermal print head uses eight heater elements. The stepper motors and print head signals are generated on port A and B (active high) of U6. Timing for Port A and B is derived from an adjustable oscillator comprising of U9 and associated components. Adjusting VR2 varies the oscillator frequency and consequently the period for which the thermal elements are energised. This in turn adjusts the print density. After the micro-controller is first reset, the print head is driven to the left until the end switch is activated. The end switch consists of a normally closed pair of contacts accessed at pins 1 and 2 of the printer connector J2. The end switch is detected by PD5 on the micro-controller.
Expansion (Drawing 056-05)
J8 and J12 are 10-pin header connectors that allow a mezzanine card to be fitted. This is used for
future customer special circuitry. Similarly, J14 is placed near the output plate on the right side of the unit to allow customer special signals to be connected to the mezzanine board or to the processor directly.
Printer Driver Circuits (Drawings 056-07 and 056-08)
The outputs from port A and B of U6 drives the two stepper motors and eight thermal elements through the high current transistors Q1 to Q16 in common emitter configuration. Diodes D1 to D4 are used to dissipate the inductive fly-back from the stepper motors and elements.
Power Supply
An external, dual voltage, supply provides 5.5 volts and 12 volts to socket J1 (Drawing 056-05). This power supply has a universal input, is factory sealed, and contains no user serviceable parts.
12
Technical Support
Great Britain and World Headquarters
Micro Medical Ltd PO Box 6 Rochester Kent ME1 2AZ
Telephone + 44 (0)1634 360044 Fax +44 (0)1634 360055 Web Site http://www.micromedical.com.uk Email support@micromedical.com.uk
Contact Micro Medical Ltd for the local agent in your region or country for local service:
13
Fault Analysis
The following analysis is only a guideline and should be carried out in a logical sequence. If the fault is still apparent after the following suggestions then the unit should be fault found using the circuit descriptions and circuit diagrams provided.
When the unit is turned on there is no display present
-Ensure charger is turned on at the mains.
FVC readings are low
-Remove turbine from transducer housing. Taking the turbine, move it slowly through the air and
check that the vane is not sticking.
The unit does not record any blows
-Inspect transducer housing connector for damage.
-Check that transducer housing lead is properly connected to the RJ11 socket.
-Remove turbine from transducer housing. Taking the turbine, move it slowly through the air and
check that the vane is not sticking.
-Blow into transducer housing and move transducer head cable around to check for breaks in the
cable.
14
UADS
S
B
P
N
UWR URD
0.1UF
TP25
TURB2
VCC
1110
R33 10K
VPPEN
PWR_OFF­PWR_ON­RTC_SEL­RTC_CLK
RTC_DATA
FPGADONE CS0 UCS1
UCS2 UCS3
ONLINE PRNBUSY
R8
UCS5
VCC
VCC
C63
0.1UF
TP3 GND
VCC
C62 1UF
VCC
RESET-
D[0..15]
A[1..21]
R37 10K
LK1
1 2
LINK2
TP24 GND
VCC
U14
119
RESET
125
CLK2
44
NA#
35
BS8#
34
READY
98
NMI
79
SMI#
110
P1.0/DCD0#
111
P1.1/RTS0#
113
P1.2/DTR0#
114
P1.3/DSR0#
115
P1.4/RI0#
116
P1.5/LOCK#
117
P1.6/HOLD
121
P1.7/HLDA
133
P2.0/CS0#
134
P2.1/CS1#
135
P2.2/CS2#
136
P2.3/CS3#
137
CS4
0R
R54 10K
140 142 143
80 81 87 89 91 92 93 94
101 102 103 104
100
96 99
128 122 127 139 123
106
84 86 85
82 27
28 129 107
P2.4/CS4# P2.5/RXD0 P2.6/TXD0 P2.7/CTS0#
P3.0/TMROUT0 P3.1/TMROUT1 P3.2/INT0 P3.3/INT1 P3.4/INT2 P3.5/INT3 P3.6/PWRDOWN P3.7/COMCLK
INT4/TMRCLK0 INT5/TMRGATE0 INT6/TMRCLK1 INT7/TMRGATE1
BUSY#/TMRGATE2 PEREQ/TMRCLK2 ERROR#/TMROUT2
DRQ1/RXD1 DACK1#/TXD1 DRQ0/DCD1# DACK0#/CS5# EOP#/CTS1#
DSR1#/STXCLK DTR1#/SRXCLK RTS1#/SSIOTX RI1#/SSIORX
TCK TDI TMS TRST# FLT#
FA80386EX25L
VCC
R53 470R
132
LED2 GREEN
CS6#/REFRESH#
VCC
C46
0.1UF
M/IO
SMIACT
WDTOUT
TDO
CLKOUT
ADS W/R
LBA
BHE BLE
UCS
43 32 31
D/C
29 37
RD
38
WR
4
45
A1 A2 A3 A4 A5 A6 A7 A8
A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11 D12 D13 D14 D15
C47
0.1UF
A1
46
A2
48
A3
49
A4
52
A5
53
A6
54
A7
55
A8
56
A9
57
A10
58
A11
59
A12
61
A13
62
A14
63
A15
64
A16
66
A17
67
A18
68
A19
70
A20
71
A21
73 74 76 78 130 42 40
5
D0
6
D1
7
D2
8
D3
10
D4
12
D5
13
D6
14
D7
15
D8
17
D9
19
D10
20
D11
21
D12
22
D13
23
D14
25
D15
1 2 124
26 112
C45
0.1UF
C66
0.1UF
REFRESH
C74
0.1UF
TP20 UCS
C58
0.1UF
TP11 CS0
CS4
D0 D1 D2 D3 D4 D5 D6 D7
R29 33R
CS0
C21
0.1UF
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 FA14 FA15 FA16 FA17 FA18 FA19 FA20 FA21
VCC
11
13 14 17 18
1
3 4 7 8
D[0..15]
A[1..21]
32 28 27 26 25 24 23 22 20 19 18 17 13 12 11 10
14
54 55 15
U17
G CLK
1D 2D 3D 4D 5D 6D 7D 8D
74FCT377
VCC
VPPEN
CLK25MHZ
C52
0.1UF
8 7 6 5 4 3
2
UCS0 UBHE UBLE
U20
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21
CE0 CE1 OE WE VPP
TE28F320J5100
1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
R50 100K
C61
0.1UF
TP15 CS4
2 5 6 9 12 15 16 19
BYTE
D10 D11 D12 D13 D14 D15
STS
D0 D1 D2 D3 D4 D5 D6 D7
D8 D9
RP
WP NC
NC
FA14 FA15 FA16 FA17 FA18 FA19 FA20 FA21
1 2
C50
0.1UF
33 35 38 40 44 46 49 51
34 36 39 41 45 47 50 52
31 53 16 56
29 30
VCC
U22A
SN74HC14
VSS
D0 D1 D2 D3 D4 D5 D6 D7
D8 D9 D10 D11 D12 D13 D14 D15
RESET-
C60
0.1UF
U19
25
A1
A0
24
A2
23
A3
22
A4
21
A5
20
A6
19
A7
18
A8
8
A9
7
A10
6
A11
5
A12
4
A13
3
A14
2
A15
1
A16
48
A17
17
A18
16
A19
26
UCS
28 11 13
28F400B5T80
U22D
9 8
SN74HC14
UUCS
TP16 VPP_EN
VCC
D9
5.6V
32
1
5V
Title
A3
Date: 5-Oct-1999 Sheet of File: G:\tempd\056-02.sch Drawn By:
Q24 DTC114EKA
C4
0.1UF
Super Spiro - Processor circuit
Number RevisionSize
D0
A1
D1
A2
D2
A3
D3
A4
D4
A5
D5
A6
D6
A7
D7 A8 A9
D8 A10
D9 A11
D10
A12
D11
A13
D12
A14
D13
A15
D14
A16
D15 A17 A18
BYTE CE OE
RP
WE
WP
VPP
LED1
3
GREEN
R36
1
100R
056-02 1.0
TP4 GND
29
D0
31
D1
33
D2
35
D3
38
D4
40
D5
42
D6
44
D7
30
D8
32
D9
34
D10
36
D11
39
D12
41
D13
43
D14
45
D15
47
12 14
L i
URD UWR
1
R52
2
470R
VCC
23
Q23 FMMT549
R35 10K
TP28 GND
J3
DB9
VCC
R30 10R
FS2 300mA
1 6 2 7 3 8 4 9 5
J13
1 2 3 4 5 6
RJ11
INT1 INT2
STXCLK SSIOTX
SSIORX PRNTACK
PRNTDATA
J7
MOLEX 4PIN
U22F
13 12
SN74HC14
VCC
5
C41
0.1UF
1UF
12V VCC VCC
1 2 3 4
4
2
4
C51
2
16
9
17
8
1
14
C26
0.1UF
2 4 3
C25
0.1UF
R49 3K3
C72 1nF
R20 0R
VCC
VCC
U10
VCC
WDI
GND
MAX824_EUKM
U15
VCC GND
50MHz
U4
R1 IN R2 IN
T1 OUT T2 OUT
EN
FON
C1+ C1 ­V+
MAX3223CAP
R48 3K3
C71
1nF
R51 470R
RES
RES
CLK
EN
RS232 TTL
TP21 TURB1
3 4
5 6
1
2
3
1
3
1
R1 OUT R2 OUT
T1 IN T2 IN
INVALID
FOFF
U22B
U22C
SN74HC14
LED3
RED
C2+ C2 -
V-
15 10
13 12
11
20
5 6 7
SN74HC14
3
UREADY
TP1
VCC
TX TP2RX
C24
C23
0.1UF
SND_EOM RTC_INT-
J9
1 2 3 4 5 6 7 8 9
10
HEADER 5X2
U22E
SN74HC14
15
UD[0..15]
UA[1..21]
UBHE UBLE
UWR
URD UREADY REFRESH
UCS0 UCS1 UCS2 UCS3 UCS5
INT1
INT2
CLK25MHZ
KEYIN[0..4]
KEYOUT[0..4]
VCC
R21
10K
FPGADONE
EXP[0..4]
SNDCNTL[0..5]
SEREN[0..4]
UD[0..15]
UA[1..21]
Flash Disk C8000 - CBFFF Display A0000 - BFFFF Display Reg (I/O) 200 - 20F DRAM 00000 - DFFFF SPARE
KEYIN[0..4]
KEYOUT[0..4]
U8
17
VP CEO RES
XC17512L
D
CLK
CE
14
6
VCC
R22
100K
EXP[0..4]
SNDCNTL[0..5]
SEREN[0..4]
VCC
R26
100K
VCC
TP27
TP29
TP26
VCC VEE
DISP_ CLK
MEM_D0 MEM_D1 MEM_D2 MEM_D3 MEM_D4 MEM_D5 MEM_D6 MEM_D7
DISP_ LD
DISP_ FR AME
J11
CON15
VCC
J10
1 2 3
1 3
VR3
10K
4 5
B_5B-ZR
Back Light Connector
TP22
VEE
D11
3
ZHCS750
R39
C75
680K
R40
36K
Title
Number RevisionSize
A3
Date: 5-Oct-1999 Sheet of File: G:\tempd\056-03.sch Drawn By:
+
C73
100pF
22UF/35V
Super Spiro - FPGA circuit
056-03 1.1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
VEE
26.4V
C70
0.1UF
33R 33R 33R 33R
RN6D
D0 D1 D2 D3 D4 D5 D6 D7
NC
Q22
DTC114EKA
C64
+
U21
7
4
MAX629ESA
VCC
TP23
DISP_ CNT L
13 14 15 17 18 19 20 21
1
21
L1
47UH
1 2
C44
C69
0.1UF
U13
XC4006E-3PQ160C_VIDEO
33
UD0 UD1 UD2 UD3 UD4 UD5 UD6 UD7
UA1 UA2 UA3 UA4 UA5 UA6 UA7 UA8 UA9 UA10 UA11 UA12 UA13 UA14 UA15 UA16 UA17 UA18 UA19 UA20
KEYIN0 KEYIN1 KEYIN2 KEYIN3
VCC
R34
100K
KEYIN4
KEYOUT0 KEYOUT1 KEYOUT2 KEYOUT3 KEYOUT4
2 4 8
EXP2 EXP3 EXP4
27
4K7
UD0
32
UD1
31
UD2
30
UD3
28
UD4
27
UD5
26
UD6
25
UD7
154
UA1
153
UA2
152
UA3
150
UA4
149
UA5
148
UA6
147
UA7
146
UA8
145
UA9
144
UA10
143
UA11
140
UA12
139
UA13
138
UA14
137
UA15
135
UA16
134
UA17
133
UA18
132
UA19
130
UA20
155
UBHE
156
UBLE
157
UWR
158
URD
159
READY
2
REFRESH
125
CS1
126
CS2
127
CS3
128
CS4
129
CS5
123
INT1
116
INT2
124
CLK25MHZ
113
KEYIN0
109
KEYIN1
112
KEYIN2
111
KEYIN3
115
KEYIN4
105
KEYOUT0
106
KEYOUT1
107
KEYOUT2
108
KEYOUT3
114
KEYOUT4
82
PROGRAM
117
DIN
119
CCLK
80
DONE
59
INIT
6
TDI
121
TDO
7
TCK
13
TMS
40
M0
38
M1
42
M2
EXP0
EXP1
18
36
RN9C
4K7
4K7
DISP_CNTL
DISP_LOAD
DISP_FRAME
MEMA_OE MEMA_WE
MEMB_WE
SNDCNTL0 SNDCNTL1 SNDCNTL2 SNDCNTL3 SNDCNTL4 SNDCNTL5
DISP_D0 DISP_D1 DISP_D2 DISP_D3 DISP_D4 DISP_D5 DISP_D6 DISP_D7
DISP_CLK
MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8
MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14 MEM_A15 MEM_A16
MEM_D0
MEM_D1
MEM_D2
MEM_D3
MEM_D4
MEM_D5
MEM_D6
MEM_D7
MEMA_CS
MEMB_CS MEMB_OE
DRA0 DRA1 DRA2 DRA3 DRA4 DRA5 DRA6 DRA7 DRA8 DRA9
DRRAS DRCASU DRCASL
DROE
DRWE
SEREN0 SEREN1 SEREN2 SEREN3 SEREN4
43 44 45 46 47 48 49 50
52 53 54 55
83 77 75 73 71 68 66 64 67 69 76 72 62 65 58 57 56
85 87 89 92 90 88 86 84
78 74 63
95 94 93
22 21 18 17 4 5 8 9 11 12
23 15 16 14 24
37 36 35 34 104 102 96 99 97 98 103
0.1UF
MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14 MEM_A15 MEM_A16
MEM_D0 MEM_D1 MEM_D2 MEM_D3 MEM_D4 MEM_D5 MEM_D6 MEM_D7
4 5
33R
3 6
33R
2 7
33R
1 8
33R
4 5
33R
3 6
33R
1 8
33R
2 7
33R
SEREN0 SEREN1 SEREN2 SEREN3 SEREN4 SNDCNTL0 SNDCNTL1 SNDCNTL2 SNDCNTL3 SNDCNTL4 SNDCNTL5
TP9
MEM A_ S EL
4 5
33R
1 8
33R
2 7
33R
3 6
33R
3 6
33R
4 5
33R
2 7
33R
1 8
33R
C49
C42
C53
C43
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
OE WE CS2 CS1
100K
0.1UF
D0 D1 D2 D3 D4 D5 D6 D7
D8
D9 D10 D11 D12 D13 D14 D15
Contrast
13
C48
C39
0.1UF
0.1UF
13
D0
14
D1
15
D2
17
D3
18
D4
19
D5
20
D6
21
D7
1
NC
2
UD0
3
UD1
4
UD2
5
UD3
7
UD4
8
UD5
9
UD6
10
UD7
35
UD8
36
UD9
37
UD10
38
UD11
40
UD12
41
UD13
42
UD14
43
UD15
6
VR1
-
5
+
C59
0.1UF
0.1UF
MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14 MEM_A15 MEM_A16
LCAS
TP17
­+
VCC
18 19 20 21 24 25 26 27 28 29
15 31 32 30 14
4 8
0.1UF
12 11 10
9 8 7 6
5 27 26 23 25
4 28
3 31
2 24
29 30 22
U18
KM416C1200BT-6
C33
0.1UF
U5A
1
U11
KM681000BLG-7
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9
RAS UCAS LCAS OE WE
0.1UF
VCC
TP10
MEMB_ SEL
RAS
UCAS
TP18
TP19
2 3
LM2904D
C28
0.1UF
MEM_D0 MEM_D1 MEM_D2 MEM_D3 MEM_D4 MEM_D5 MEM_D6 MEM_D7
U5B
LM2904D
C38
0.1UF
C67
C31
0.1UF
4 5 3 6 2 7 1 8
MEM_A0 MEM_A1 MEM_A2 MEM_A3 MEM_A4 MEM_A5 MEM_A6 MEM_A7 MEM_A8 MEM_A9 MEM_A10 MEM_A11 MEM_A12 MEM_A13 MEM_A14 MEM_A15 MEM_A16
C68
0.1UF
RN8D
33R 33R 33R 33R
4 5 3 6 2 7 1 8
12 11 10
9 8 7 6
5 27 26 23 25
4 28
3 31
2 24
29 30 22
RN7D
33R 33R 33R 33R
1 8 2 7 3 6 4 5
U12
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16
OE WE CS2 CS1
KM681000BLG-7
0.1UF
VCC
32
1
BKLGTEN
C65
0.1UF
47 UF /1 0 V
86
1
SHDN ISET REF POL
LX
FB
C34
0.1UF
5 3 2
7
R38
1M0
16
PWR_ON-
N
A
PWR_OFF-
47UF/16V
5V
RTC_INT-
l t
FS3
1A
C3
C19
+
0.1UF
MINIRELAY (RS345-022)
D5
3
ZHCS750
2 3
5V
R5 100K
R6 OR
32
5V
R4 100K
32
Q18 FMMT489
Q17 FMMT489
R12 8K2
R9 8K2
R10 2K0
R7 2K0
C20
0.1UF
C18
0.1UF
1
1
1 2
4 5
2
1
Q20 FMMT717
1
R11 100R
32
8
9
U3B
5 6
78 RL1
Q19DTC114EKA
4093
1
U3C
4093
C27
+
47UF/16V
10
4
VCC
13
12
C22
0.1UF
C57
+
47UF/16V
KEYOUT[0..4]
KEYIN[0..4]
8
U2B
9
S
D
Q
CLK
Q
R
4013
10
U3A
11
3
4093
5V
KEYOUT[0..4]
KEYIN[0..4]
1 2
D7
IMN10
9
esc
del
.
ON/OFF
1 2 3
1
2
3
4
F1
F2
F3
1
4
7
F4
2
5
890
F5
6
3
PAPER FEED
6
KEYOUT0 KEYOUT1 KEYOUT2
KEYOUT3
KEYOUT4
KEYIN0
KEYIN1
5V
R3 100K
5V
C17
0.1UF
KEYIN2
KEYIN3
KEYIN4
PAPERFEED-
VCC
4 5
1 8
3 6
2 7
6
5 4
RN5D
RN5A
RN5C
RN5B
R16
D8
IMN10
100K
100K
100K
100K
100K
5
4
1
2 3
8
5
7
6
10
12
13 11
J6
KEYPAD
6
14
C16
0.1UF
3
D5Q
VCC
CLK
GN D
4
7
U2A
1
S
2
Q
R
4013
147
U3D
12
13
4093
17
C15
0.1UF
11
Title
A3
Date: 5-Oct-1999 Sheet of File: G:\tempd\056-04.sch Drawn By:
Super Spiro - Keypad circuit
Number RevisionSize
1.0056-04
RTC_SEL­RTC_CLK
RTC_DATA
SNDCNTL[0..5]
VCC
R31 10K
SNDCNTL[0..5]
TP12
VCC
VCC
C56
0.1UF
C54 33PF
TP13
TP14
RTC_ D A TA
RTC_SCL K
RTC_SEL
X2
32.786KHz
1
2
3
A0
VDD
OS CI
6
5
SCL
SDA
U16 PCF8583T
OS CO
INT
VSS
3
8
7
4
D10
BAV70
VCC
SEREN[0..4]
BAT1
1
2
R32 10K
3.6V
1 3 2
C55
0.1UF
RTC_INT-
EXP[0..4]
SEREN[0..4]
SEREN4
SEREN0
SEREN1
SEREN2
SEREN3
EXP[0..4]
R2 10K
STXCLK
SSIOTX
SSIORX
C8
0.1UF
U1
3
VDD
2
DQ
1
GND
DS1821
VCC
Resettable Fuse
FS4
R44
0R
R41
0R
R45
0R
R42
0R
R46
0R
R43
0R
R47
0R
300mA
VCC
J14
DB9
1 6 2 7 3 8 4 9 5
12V
J12
1 2 3 4 5 6
Header for expansion card
7 8 9 10
HEADER 10
SND_EOM
SNDCNTL1
SNDCNTL0 SNDCNTL2 SNDCNTL3 SNDCNTL4 SNDCNTL5
TP5 SND_EN
VCC
C36
0.1UF
1
Speaker Output
2
VCC
C35
+
47UF/16V
C32
0.1UF
J5 CON3
VCC
1 2 3
Record Input
R13
R15
10K
10K
U7
ISD2532S
1
A0
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
9
A7
10
A8
23
CE
24
PD
27
P/R
25
EOM
22
OVF
26
XCLK
VCCD VCCA
VSSD VSSA
AUXIN ANAIN
ANAOUT
MICREF
AGC
28 16
12 13
14
SP+
15
SP-
11 20
21
18 17
MIC
19
C29
0.1UF
J4
Molex 2 pin R/A
C11
0.1UF
EXP0 EXP1 EXP2 EXP3 EXP4
C12
+
47 U F /16V
12V 5V
FS1 500mA
12V
VCC
J8
1 2 3 4 5
Header for expansion card
6 7 8 9 10
HEADER 10
J1 CON4
1
Power Connector
2 3 4
Resetable Fuse.
Title
Super Spiro - RTC circuit
Number RevisionSize
A3
Date: 5-Oct-1999 Sheet of File: G:\tempd\056-05.sch Drawn By:
056-05 1.0
18
5V
R23 100K
C40
820pF
U9A
1 2
4069UB
RESET-
PRNTDATA PRNTACK
PF­ONLINE-
U9B
3 4
4069UB
TP7 PRNT_DATA
U9E
11 10
4069UB U9C
5 6
4069UB
VCC
R19 10K
PAPERFEED-
C37
X1
33PF
4.0MHz R14 10K
U9D
9 8
4069UB
C30
33PF
43 42
1 2
41
32 33 34 35 36 37
39
4
3 18 23 40
R17 1K
U6
OSC1
PA7
OSC2
PA6 PA5 PA4
RST IRQ
PA3 PA2
TCAP
PA1
TCMP38PA0
PB0
PD0/RDI
PB1
PD1/TDO
PB2
PD2/MISO
PB3
PD3/MOSI
PB4
PD4/SCK
PB5
PD5/SS
PB6
PD7
PB7
PC0 PC1 PC2
NC
PC3 PC4
NC
PC5
NC
PC6
NC
PC7
NC
MC68HC05C9ACFN(44)
TP6 PRNT_CLK
C5
0.1uf
OUT0
OUT0 OUT1
OUT1 OUT2
OUT2 OUT3
OUT3 OUT4
OUT4 OUT5
OUT5 OUT6
OUT6 OUT7
OUT7
VCC
R18 10K
R1 1K
J2
5V
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
CON25
Head Motor
Paper Feed Motor
0.1UF
5 6 7 8 9 10 11 12
13 14 15 16 17 19 20 21
31 30 29 28 27 26 25 24
47UF/ 1 6 V
056-07 056-07.SCH
OUT0
IN0
OUT0
IN0
OUT1
IN1
OUT1
IN1
OUT2
IN2
OUT2
IN2
OUT3
IN3
OUT3
IN3
OUT4
IN4
OUT4
IN4
OUT5
IN5
OUT5
IN5
OUT6
IN6
OUT6
IN6
OUT7
IN7
OUT7
IN7
BUSY
TP8 PRNT_BUSY
P i n
C2
+
C1
C7
0.1UF
C6
+
4 7 U F / 1 6 V
IN0
IN0 IN1
IN1 IN2
IN2 IN3
IN3 IN4
IN4 IN5
IN5 IN6
IN6 IN7
IN7
056-08 056-08.SCH
R24 22K
R25 150K
Q21
3 2
FMMT489
1
1 3
VR2 20K
D6
ZHCS750
R27 2K2
R28 22K
23
U9F
13 12
4069UB
VCC VDD
Title
Super Spiro - Printer circuit
Number RevisionSize
A3
Date: 5-Oct-1999 Sheet of File: G:\tempd\056-06.sch Drawn By:
056-06 1.0
19
5V
D1 UMN1
Q3
32
5V
13245
Q4
FMMT489
1
D2 UMN1
32
Q1
32
FMMT489
1
Q2
32
FMMT489
1
FMMT489
1
RN1
IN0 IN1 IN2 IN3
IN4 IN5 IN6 IN7
8 7 6
8 7 6
1 2 3 45
1K0 RN2
1 2 3 45
1K0
Q5
FMMT489
1
32
FMMT489
1
C10
0.1UF
13245
Q6
32
C9
0.1UF
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
Q7
FMMT489
1
32
Q8
32
FMMT489
1
OUT6
OUT7
Title
A3
Date: 5-Oct-1999 Sheet of File: G:\tempd\056-07.sch Drawn By:
Super Spiro - Printer driver 1
Number RevisionSize
056-07 1.0
20
5V
D3 UMN1
Q11
32
5V
13245
13245
Q13
FMMT489
1
D4 UMN1
32
Q9
32
FMMT489
1
Q10
32
FMMT489
1
FMMT489
1
RN3
IN0 IN1 IN2 IN3
IN4 IN5 IN6 IN7
8 7 6
8 7 6
1 2 3 45
1K0
RN4
1 2 3 45
1K0
FMMT489
1
Q12
32
FMMT489
1
C14
0.1UF
Q14
32
C13
0.1UF
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
FMMT489
1
21
Q15
32
Q16
32
FMMT489
1
OUT6
OUT7
Title
Super Spiro - Printer driver 2
Number RevisionSize
A3
Date: 5-Oct-1999 Sheet of File: G:\tempd\056-08.sch Drawn By:
056-08 1.0
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