Micro Linear Corporation ML6695CQ Datasheet
December 1998
PRELIMINARY
ML6695
100BASE-X Fiber Physical Layer With 5-bit Interface
GENERAL DESCRIPTION
The ML6695 implements the physical layer of the Fast
Ethernet 100BASE-X standard for fiber media. The device
provides the 5-bit (or symbol) interface for interface to
upper-layer silicon. The ML6695 integrates the data
quantizer and the LED driver, allowing the use of low cost
optical PMD components.
The ML6695 includes 125MHz clock recovery/clock
generation, an LED driver, and a data quantizer (post
amplifier). The device also offers a power down mode
which results in total power consumption of less than 20mA.
The ML6695 is suitable for the current 100BASE-FX IEEE
803.2u standard defined using 1300nm optics, as well as
for the
proposed
100BASE-SX standard defined using lower
cost 820nm optics.
BLOCK DIAGRAM
TXC
CLOCK
SYNTHESIZER
FEATURES
■ 100BASE-FX physical layer with 5-bit interface
■ Optimal 100BASE-SX solution (draft standard)
■ Integrated data quantizer (post-amplifier)
■ Integrated LED driver
■ 125MHz clock generation and recovery
■ Power-down mode
LPBK
PWRDN
TSM4
TSM3
TSM2
TSM1
TSM0
SDO
RXC
RSM4
RSM3
RSM2
RSM1
RSM0
DESERIALIZER
SERIALIZER
NRZ TO NRZI
ENCODER
CLOCK & DATA
RECOVERY
NRZI TO NRZ
DECODER
LED
DRIVER
SIGNAL
DETECT
DATA QUANTIZER
(POST AMPLIFIER)
IOUT
IOUT
RTSET
V
IN+
V
IN–
CAPDCCAPB
1
ML6695
PIN CONFIGURATION
PWRDN
RSM4
RSM3
DGND1
RSM2
DVCC1
RSM1
DGND2
RSM0
RXC
DGND3
ML6695
44-Pin PLCC (Q44)
1
TSM0
TSM1
TSM2
TSM3
TSM4
6543214443424140
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
SDO
DVCC2
DGND4B
DGND4C
DGND4A
TOP VIEW
AGND1
5
CC
DV
CC
TXC
AV
DGND5B
DGND5A
2
CC
LPBK
AV
CAPB
CAPDC
AGND2
IOUT
39
38
IOUT
37
AGND3
36
RTSET
35
AVCC3A
34
AVCC3B
33
AVCC4A
32
AGND4A
31
AVCC4B
30
VIN+
29
VIN–
AGND4B
PIN DESCRIPTION
PIN NAME FUNCTION
1A
2 TSM4 Transmit data TTL inputs. TSM 0-4
3 TSM3 Transmit data TTL inputs. TSM 0-4
4 TSM2 Transmit data TTL inputs. TSM 0-4
1 Analog ground
GND
inputs accept TX data symbols
from the MII. Data appearing at
TSM 0-4 are clocked into the
ML6695 on the rising edge of
TXCLK .
inputs accept TX data symbols
from the MII. Data appearing at
TSM 0-4 are clocked into the
ML6695 on the rising edge of
TXC.
inputs accept TX data symbols
from the MII. Data appearing at
TSM 0-4 are clocked into the
ML6695 on the rising edge of
TXC.
PIN NAME FUNCTION
5 TSM1 Transmit data TTL inputs. TSM 0-4
inputs accept TX data symbols
from the MII. Data appearing at
TSM 0-4 are clocked into the
ML6695 on the rising edge of TXC.
6 TSM0 Transmit data TTL inputs. TSM 0-4
inputs accept TX data symbols
from the MII. Data appearing at
TSM 0-4 are clocked into the
ML6695 on the rising edge of TXC.
7 PWRDN Powerdown TTL input. Driving this
pin low, or floating the pin, powers
the ML6695 down to a lowcurrent, inoperative state. Driving
PWRDN high enables the
ML6695.
8 RSM4 Receive data TTL outputs. RSM 0-
4 output may be sampled
synchronously with RXC’s rising
edge.
2
PIN DESCRIPTION (Continued)
ML6695
PIN NAME FUNCTION
9 RSM3 Receive data TTL outputs. RSM 0-
4 output may be sampled
synchronously with RXC’s rising
edge.
10 DGND1 Digital ground
11 RSM2 Receive data TTL outputs. RSM 0-
4 output may be sampled
synchronously with RXC’s rising
edge.
12 D VCC1 Digital positive power supply
13 RSM1 Receive data TTL outputs. RSM 0-
4 output may be sampled
synchronously with RXC’s rising
edge.
14 DGND2 Digital ground
15 RSM0 Receive data TTL outputs. RSM 0-
4 output may be sampled
synchronously with RXC’s rising
edge.
16 RXC Recovered receive symbol clock
TTL output. This 25MHz clock is
phase-aligned with the internal
125MHz bit clock recovered from
the signal received at V
Receive data are clocked out at
RSM 0-4 on the falling edges of
this clock.
IN+/–
.
PIN NAME FUNCTION
26 CAPDC Data quantizer offset-correction
loop, offset-storage capacitor input
pin. The capacitor tied between
this pin and AVCC stores the
amplified data quantizer offset
voltage and also sets the dominant
pole in the offset-correction loop.
A 0.1µF surface mount is
recommended.
27 CAPB Data quantizer input bias bypass
capacitor input. The capacitor tied
between this pin and AVCC filters
the quantizer’s internal input bias
reference. A 0.1µF surface-mount
capacitor is recommended.
28 AGND4B Analog ground
29 VIN– Receive quantizer input. This
differential input pair receives
100BASE-FX NRZI signals from the
network opto-coupler.
30 VIN+ Receive quantizer input. This
differential input pair receives
100BASE-FX NRZI signals from the
network opto-coupler.
31 AVCC4B Analog positive power supply
32 AGND4A Analog ground
33 AVCC4A Analog positive power supply
17 DGND3 Digital ground
18 SDO Signal Detect TTL output. This
output goes high when the signal
at VIN+/- exceeds the preset
amplitude threshold.
19 D VCC2 Digital positive power supply
20 DGND4C Digital ground
21 DGND4B Digital ground
22 DGND4 Digital ground
23 DVCC5 Digital positive power supply
24 DGND5B Digital ground
25 DGND5A Digital ground
34 AVCC3B Analog positive power supply
35 AVCC3A Analog positive power supply
36 RTSET Transmit level bias resistor. For
100BASE-FX, an external 2.32kW,
1% resistor connected between
RTSET and AGND3 sets a
precision constant bias current
that gives a nominal output "on"
current of 75mA at I
37 AGND3 Analog ground
38 IOUT Transmit LED output. This pin
connects through an external 15W
resistor to AVCC when the part is
used to drive a network LED.
OUT
.
3
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