December 1998
PRELIMINARY
ML6695
100BASE-X Fiber Physical Layer With 5-bit Interface
GENERAL DESCRIPTION
The ML6695 implements the physical layer of the Fast
Ethernet 100BASE-X standard for fiber media. The device
provides the 5-bit (or symbol) interface for interface to
upper-layer silicon. The ML6695 integrates the data
quantizer and the LED driver, allowing the use of low cost
optical PMD components.
The ML6695 includes 125MHz clock recovery/clock
generation, an LED driver, and a data quantizer (post
amplifier). The device also offers a power down mode
which results in total power consumption of less than 20mA.
The ML6695 is suitable for the current 100BASE-FX IEEE
803.2u standard defined using 1300nm optics, as well as
for the
proposed
100BASE-SX standard defined using lower
cost 820nm optics.
BLOCK DIAGRAM
TXC
CLOCK
SYNTHESIZER
FEATURES
■ 100BASE-FX physical layer with 5-bit interface
■ Optimal 100BASE-SX solution (draft standard)
■ Integrated data quantizer (post-amplifier)
■ Integrated LED driver
■ 125MHz clock generation and recovery
■ Power-down mode
LPBK
PWRDN
TSM4
TSM3
TSM2
TSM1
TSM0
SDO
RXC
RSM4
RSM3
RSM2
RSM1
RSM0
DESERIALIZER
SERIALIZER
NRZ TO NRZI
ENCODER
CLOCK & DATA
RECOVERY
NRZI TO NRZ
DECODER
LED
DRIVER
SIGNAL
DETECT
DATA QUANTIZER
(POST AMPLIFIER)
IOUT
IOUT
RTSET
V
IN+
V
IN–
CAPDCCAPB
1
ML6695
PIN CONFIGURATION
PWRDN
RSM4
RSM3
DGND1
RSM2
DVCC1
RSM1
DGND2
RSM0
RXC
DGND3
ML6695
44-Pin PLCC (Q44)
1
TSM0
TSM1
TSM2
TSM3
TSM4
6543214443424140
7
8
9
10
11
12
13
14
15
16
17
18 19 20 21 22 23 24 25 26 27 28
SDO
DVCC2
DGND4B
DGND4C
DGND4A
TOP VIEW
AGND1
5
CC
DV
CC
TXC
AV
DGND5B
DGND5A
2
CC
LPBK
AV
CAPB
CAPDC
AGND2
IOUT
39
38
IOUT
37
AGND3
36
RTSET
35
AVCC3A
34
AVCC3B
33
AVCC4A
32
AGND4A
31
AVCC4B
30
VIN+
29
VIN–
AGND4B
PIN DESCRIPTION
PIN NAME FUNCTION
1A
2 TSM4 Transmit data TTL inputs. TSM 0-4
3 TSM3 Transmit data TTL inputs. TSM 0-4
4 TSM2 Transmit data TTL inputs. TSM 0-4
1 Analog ground
GND
inputs accept TX data symbols
from the MII. Data appearing at
TSM 0-4 are clocked into the
ML6695 on the rising edge of
TXCLK .
inputs accept TX data symbols
from the MII. Data appearing at
TSM 0-4 are clocked into the
ML6695 on the rising edge of
TXC.
inputs accept TX data symbols
from the MII. Data appearing at
TSM 0-4 are clocked into the
ML6695 on the rising edge of
TXC.
PIN NAME FUNCTION
5 TSM1 Transmit data TTL inputs. TSM 0-4
inputs accept TX data symbols
from the MII. Data appearing at
TSM 0-4 are clocked into the
ML6695 on the rising edge of TXC.
6 TSM0 Transmit data TTL inputs. TSM 0-4
inputs accept TX data symbols
from the MII. Data appearing at
TSM 0-4 are clocked into the
ML6695 on the rising edge of TXC.
7 PWRDN Powerdown TTL input. Driving this
pin low, or floating the pin, powers
the ML6695 down to a lowcurrent, inoperative state. Driving
PWRDN high enables the
ML6695.
8 RSM4 Receive data TTL outputs. RSM 0-
4 output may be sampled
synchronously with RXC’s rising
edge.
2
PIN DESCRIPTION (Continued)
ML6695
PIN NAME FUNCTION
9 RSM3 Receive data TTL outputs. RSM 0-
4 output may be sampled
synchronously with RXC’s rising
edge.
10 DGND1 Digital ground
11 RSM2 Receive data TTL outputs. RSM 0-
4 output may be sampled
synchronously with RXC’s rising
edge.
12 D VCC1 Digital positive power supply
13 RSM1 Receive data TTL outputs. RSM 0-
4 output may be sampled
synchronously with RXC’s rising
edge.
14 DGND2 Digital ground
15 RSM0 Receive data TTL outputs. RSM 0-
4 output may be sampled
synchronously with RXC’s rising
edge.
16 RXC Recovered receive symbol clock
TTL output. This 25MHz clock is
phase-aligned with the internal
125MHz bit clock recovered from
the signal received at V
Receive data are clocked out at
RSM 0-4 on the falling edges of
this clock.
IN+/–
.
PIN NAME FUNCTION
26 CAPDC Data quantizer offset-correction
loop, offset-storage capacitor input
pin. The capacitor tied between
this pin and AVCC stores the
amplified data quantizer offset
voltage and also sets the dominant
pole in the offset-correction loop.
A 0.1µF surface mount is
recommended.
27 CAPB Data quantizer input bias bypass
capacitor input. The capacitor tied
between this pin and AVCC filters
the quantizer’s internal input bias
reference. A 0.1µF surface-mount
capacitor is recommended.
28 AGND4B Analog ground
29 VIN– Receive quantizer input. This
differential input pair receives
100BASE-FX NRZI signals from the
network opto-coupler.
30 VIN+ Receive quantizer input. This
differential input pair receives
100BASE-FX NRZI signals from the
network opto-coupler.
31 AVCC4B Analog positive power supply
32 AGND4A Analog ground
33 AVCC4A Analog positive power supply
17 DGND3 Digital ground
18 SDO Signal Detect TTL output. This
output goes high when the signal
at VIN+/- exceeds the preset
amplitude threshold.
19 D VCC2 Digital positive power supply
20 DGND4C Digital ground
21 DGND4B Digital ground
22 DGND4 Digital ground
23 DVCC5 Digital positive power supply
24 DGND5B Digital ground
25 DGND5A Digital ground
34 AVCC3B Analog positive power supply
35 AVCC3A Analog positive power supply
36 RTSET Transmit level bias resistor. For
100BASE-FX, an external 2.32kW,
1% resistor connected between
RTSET and AGND3 sets a
precision constant bias current
that gives a nominal output "on"
current of 75mA at I
37 AGND3 Analog ground
38 IOUT Transmit LED output. This pin
connects through an external 15W
resistor to AVCC when the part is
used to drive a network LED.
OUT
.
3
ML6695
PIN DESCRIPTION (Continued)
PIN NAME FUNCTION
39 IOUT Transmit LED output. This open-
collector current output drives
NRZI waveforms into an LED.
Output current can be set
externally by choosing RTSET
value.
40 AGND2 Analog ground
41 AVCC2 Analog positive power supply
42 LPBK Loopback TTL input pin. Tying this
pin to ground places the part in
loopback mode; data at TSM0 0-4
are serialized, then sent to the
quantizer, followed by the receive
PLL for clock recovery, and finally
to the RSM<4:07> outputs.
Floating this pin or tying it to V
places the part in its normal mode
of operation.
CC
PIN NAME FUNCTION
43 AVCC1 Analog positive power supply
44 TXC Transmit clock TTL input. This
25MHz clock is phase-aligned
with the internal 125MHz TX bit
clock. Data appearing at
Tsm<4:0> are clocked into the
ML6695 on the rising edge of this
clock.
4
ABSOLUTE MAXIMUM RATINGS
ML6695
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Junction Temperature ....................................0ºC to 125ºC
Storage Temperature................................. –65ºC to 150ºC
Lead Temperature (Soldering, 10 sec) ..................... 260ºC
Thermal Resistance (qJA)
PLCC ............................................................... 53°C/W
VCC Supply Voltage Range ............................–0.3V to 6V
Input Voltage Range
Digital Inputs ........................................... –0.3V to V
VIN+, VIN-,TXC, CAPDC, CAPB ............... –0.3V to V
Output Current
IOUT, IOUT ........................................................ 90mA
All Other Outputs ............................................... 10mA
CC
CC
OPERATING CONDITIONS
Temperature Range ....................................... 0ºC to 70ºC
VCC Supply Voltage ......................................... 5V ±5%
All VCC supply pins
All GND pins
must
be within 0.1V of each other.
must
be within 0.1V of each other.
DC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 5V ±5%, TA = Operating Temperature Range (Note 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
TTL INPUTS (TSM<4:0>, LPBK, TXC, PWRDN)
V
V
I
I
TTL OUTPUTS (RSM<4:0>, RXC, SDO)
Input Low Voltage I
IL
Input High Voltage I
IH
Input Low Current V
IL
Input High Current V
IH
= –400µA –0.3 0.8 V
IL
= 100µA 2.0 VCC+0.3 V
IH
= 0.4V –200 µA
IN
= 2.4V 100 µA
IN
V
V
RECEIVER
V
ICM
V
R
IDR
V
SDA
A
HYST
I
RT
TRANSMITTER
I
LEDHIOUT
I
LEDLIOUT/IOUT
POWER SUPPLY CURRENT
I
CC
I
PD
OL
OH
ID
Output Low Voltage I
Output High Voltage I
VIN+/- input common-mode voltage VCC = 5V 2.5 V
VIN+/- differential input voltage range 3.5 1700 mV
VIN+/- differential input resistance 500 1k W
Signal detect assertion threshold peak-to-peak non-idle 8 12 mV
Input hysteresis 1.5 2 dB
RTSET input current RTSET = 2.32kW ±1% 486 540 594 µA
high output current (Note 2) RTSET = 2.32kW ±1% 67.5 75 82.5 mA
low output current RTSET = 2.32kW ±1% 0.1 mA
Supply Current, 100BASE-FX operation, Current into all VCC pins, 200 295 mA
transmitting VCC = 5.25V
Supply Current, Powerdown Mode 20 mA
= 4mA 0.4 V
OL
= –4mA 2.4
OH
signal level at VIN+/- for
SDO assertion
P-P
P-P
5
ML6695
AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 5V ±5%, TA = Operating Temperature Range (Note 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
TRANSMITTER (NOTE 8)
t
TR/F
t
TDCIOUT
I
OUT
SIGNAL DETECT
t
t
ANS
AS
SDO assert time (SDO low to high) VIN>8mV
SDO deassert time (SDO high to low) VIN<8mV
DATA INTERFACE
X
NTOL
t
TPWH
t
TPWL
t
RPWH
t
RPWL
t
TPS
TX input clock frequency tolerance 25MHz frequency –50 50 ppm
TXC pulse width HIGH 14 ns
TXC pulse width LOW 14 ns
RXC pulse width HIGH 14 ns
RXC pulse width LOW 14 ns
Setup time, TSM 0-4 data valid to 13 ns
TXC rising edge (1.4V point)
t
TPH
Hold time, TSM 0-4 data valid after 3 ns
TXC rising edge (1.4V point)
t
RCS
Time that RSM0-4 data are valid 10 ns
before RXC falling edge (1.4V point)
t
RCH
Time that RSM0-4 data are valid 10 ns
after RXC falling edge (1.4V point)
rise/fall time Note 3 2 ns
output duty cycle distortion Note 3 -0.5 0.5 ns
P-P
P-P
350 µs
100 µs
t
RPCR
t
RPCF
Note 1. Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
Note 2. Output current amplitude is I
Note 3. Using the test load shown in Figure 1, transmitting "H" symbols.
RXC 10%-90% rise time 6ns
RXC 90%-10% fall time 6ns
= 207V/RTSET.
OUT
6
FUNCTIONAL DESCRIPTION
ML6695
TRANSMIT SECTION
The ML6695 transmit section accepts parallel NRZ data
nibbles, creates a serial NRZI data stream using the
internal 125MHz clock multiplier, and provides an opencollector output IOUT to directly drive an LED. IOUT
must be connected to VCC through a 15W resistor. The
internal clock multiplier accepts an external 25MHz
clock input.
The LED driver at IOUT is a current mode switch which
develops the output light by sinking current through the
network LED into IOUT. RTSET'S value determines the
output current:
125
.
V
IOUT
140
´
W
(1)
RTSET
where IOUT is the desired output current.
RECEIVE SECTION
The ML6695 receive section includes a fiber optic
quantizer and a 125MHz receive clock recovery circuit.
The quantizer is a wide-bandwidth limiting amplifier with
=
DC offset correction. The quantizer output drives a data
comparator with a controlled slicing threshold. The
comparator provides a large-amplitude receive signal. The
clock recovery circuit extracts 125MHz receive clock
from the large-amplitude signal, and provides the clock
for the parallel data output registers. Received NRZ data
nibbles appear at the RSM outputs synchronously with
RXC falling edges. Received signals exceeding the preset
signal detect amplitude threshold for more than 5µs cause
the SDO output to go high. Received signals that fall
below the preset threshold for more than 5µs cause SDO
to go low.
OTHER MODES
The ML6695 will enter a power down mode when the
PWRDN pin is tied low. In this state the ML6695 powers
down to a low-current (less than 20mA), inoperative state.
Driving it high enables normal operation of the ML6695.
Loopback mode is entered when the LPBK is tied to
ground. In this mode, the data at TSM0-4 are serialized,
then sent to the quantizer, followed by the receive PLL for
clock recovery, and finally to the RSM0-4 outputs. Tying
LPBK to V
operation.
places the ML6695 in its normal mode of
CC
15Ω 15Ω
38 39
IOUT IOUT
ML6695
Figure 1. Test Load
7
ML6695
PHYSICAL DIMENSIONS inches (millimeters)
Package: Q44
44-Pin PLCC
0.685 - 0.695
(17.40 - 17.65)
0.650 - 0.656
(16.51 - 16.66)
1
0.042 - 0.056
(1.07 - 1.42)
0.025 - 0.045
(0.63 - 1.14)
(RADIUS)
0.042 - 0.048
(1.07 - 1.22)
12
0.050 BSC
(1.27 BSC)
0.013 - 0.021
(0.33 - 0.53)
PIN 1 ID
23
0.026 - 0.032
(0.66 - 0.81)
SEATING PLANE
ORDERING INFORMATION
PART NUMBER TEMPERATURE RANGE PACKAGE
ML6695CQ 0°C to 70°C 44-Pin PLCC (Q44)
0.650 - 0.656
34
(16.51 - 16.66)
0.165 - 0.180
(4.06 - 4.57)
0.685 - 0.695
(17.40 - 17.65)
0.148 - 0.156
(3.76 - 3.96)
0.009 - 0.011
(0.23 - 0.28)
0.100 - 0.112
(2.54 - 2.84)
0.500 BSC
(12.70 BSC)
0.590 - 0.630
(14.99 - 16.00)
Micro Linear makes no representations or warranties with respect to the accuracy, utility, or completeness of the contents
of this publication and reserves the right to make changes to specifications and product descriptions at any time without
notice. No license, express or implied, by estoppel or otherwise, to any patents or other intellectual property rights is granted
by this document. The circuits contained in this document are offered as possible applications only. Particular uses or
applications may invalidate some of the specifications and/or product descriptions contained herein. The customer is urged
to perform its own engineering review before deciding on a particular application. Micro Linear assumes no liability
whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of Micro Linear products including
liability or warranties relating to merchantability, fitness for a particular purpose, or infringement of any intellectual property
right. Micro Linear products are not designed for use in medical, life saving, or life sustaining applications.
© Micro Linear 2000. is a registered trademark of Micro Linear Corporation. All other trademarks are the
property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116;
5,281,862; 5,283,483; 5,418,502; 5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376;
5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897; 5,717,798; 5,742,151; 5,747,977; 5,754,012; 5,757,174;
5,767,653; 5,777,514; 5,793,168; 5,798,635; 5,804,950; 5,808,455; 5,811,999; 5,818,207; 5,818,669; 5,825,165; 5,825,223;
5,838,723; 5.844,378; 5,844,941. Japan: 2,598,946; 2,619,299; 2,704,176; 2,821,714. Other patents are pending.
2092 Concourse Drive
San Jose, CA 95131
Tel: (408) 433-5200
Fax: (408) 432-0295
www.microlinear.com
8
DS6695-01
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