Micro Linear Corporation ML6461CS Datasheet

February 1999
PRELIMINARY

ML6461

CCIR656 NTSC Video Encoder

GENERAL DESCRIPTION

The ML6461 is a multi-standard CCIR656 (4:2:2) video
(input) composite and S-video (outputs) encoder for NTSC
systems. It is designed to provide a low cost, single-chip
output interface for a variety of video applications
including set-top decoders, DVD players, and other YCrCb
to Y/C equipment.

The ML6461 accepts 8-bit YCrCb video in either CCIR656
or Square Pixel format and generates analog Y, C and CV
waveforms complete with Closed Caption encoding.

The ML6461 includes output analog reconstruction filters,
phase equalizer , and 6dB (2X gain) drivers. Gain scaling,
sync, and Y+C mixing are performed at the output of the
relevant 10-bit D AC, eliminating the gain mapping stages
that require additional DAC bits. The result is Y SNR and
granularity remain precisely the same as the source.

The ML6461 supports both master and sla v e timing
operations. S-Video and multiple composite signals can be
driven simultaneously into 75Ω loads.

BLOCK DIAGRAM

YCRCB0

21

YCRCB1

20

YCRCB2

19

YCRCB3

18

YCRCB4

17

YCRCB5

13

YCRCB6

12

YCRCB7

11

7

DV

CC1

LUMA

BLANKING

INPUT Y/C DEMUX & CLOCK GENERATOR

TIMING

GENERATOR

(SAV/EAV)

DGNDI

DELAY

COMPEN-

SATION

8

SAMPLER

DV

CC2

UP

CAPTIONING

14

CLOSED

15

DGND2

LUMA

RECONSTRUCTION

FILTER

(FIR)

FEATURES

■ Closed Caption VBI encoder for line 21 and 284

■ Handles SAV/EAV codes for CCIR656 Video

■ Single clock input: 27MHz CCIR656, 24.54MHz Sq. Pix.

■ Color subcarrier correction for overlay applications

■ Onboard analog 7th-order reconstruction filters and

6dB drivers with differential gain/phase of 0.5%/0.5º

■ Y, C, CV outputs drive both AC or DC coupled loads

■ Multiple 75Ω line drivers for two composite outputs,

channel modulator, and S-Video

■ 2-wire serial control bus, or selectable presets for stand-

alone operation

■ Handles Japanese NTSC signals

10 BIT

YDAC

NEGATIVE
SYNC DAC

POSITIVE

SYNC DAC

AV

CC1

1

2

AGND1

7th ORDER

ANALOG

FILTER

WITH
GROUP DELAY
EQUALIZATION

REFERENCE

GENERATOR

+

Σ

+

7th ORDER

ANALOG

FILTER

WITH
GROUP DELAY
EQUALIZATION

AV

CC2

24

25

AGND2

Y

OUT

6dB

6dB

6dB

CV

C

27

OUT

26

OUT

28

16

9

10

5

22

23

CLK

VSYNC

HSYNC

FIELD

SCLK

SDATA

PRESET1

SERIAL

INTERFACE

PRESET0

4

CHROMA

BLANKING

OVERLAY

INTERFACE

PHERR

3 6

BURST

INSERTION

COLOR

SPACE

CONVERTER

PHASE

ACCUMULATOR

UP

SAMPLER

CHROMA

BANDLIMIT

FILTER

SUBCARRIER

GENERATION

MULTIPLYING

ACCUMULATOR

Σ

SAMPLER

UP

CHROMA

RECONSTRUCTION

FILTER

(FIR)

CDAC

8

1

ML6461

PIN CONFIGURATION

AV

CC1

AGND1

PRESET0

PRESET1

FIELD

PHERR

DV

CC1

DGND1

VSYNC

HSYNC

YCRCB7

YCRCB6

YCRCB5

DV

CC2

ML6461

28-Pin SOIC (S28)

1

2

3

4

5

6

7

8

9

10

11

12

13

14

TOP VIEW

28

27

26

25

24

23

22

21

20

19

18

17

16

15

C

OUT

Y

OUT

CV

OUT

AV

CC2

AGND2

SDATA

SCLK

YCRCB0

YCRCB1

YCRCB2

YCRCB3

YCRCB4

CLK

DGND2

2

PIN DESCRIPTION

ML6461

PIN NAME FUNCTION

1AV

2 AGND1 Analog ground pin
3 PRESET0 Preset input pin for stand alone

4 PRESET1 Preset input pin for stand alone

5 FIELD T his pin can be configured as an input

6 PHERR External chroma lock input
7DV
8 DGND1 Digital ground pin
9 VSYNC Vertical sync hronization signal. Pin is

10 HSYNC Horizontal synchronization signal. Pin

CC1

CC1

Analog 5V supply pin

operation

operation

or output via the control register (bits
B8 and B9). If configured as output, it
can be programmed to give analog or
digital (even/odd) field information. If
configured as input, it can be used to
set analog fields (1 and 2) or (3 and 4).

Digital 5V supply pin

configured as input in external slave
mode and as output in master and
internal slave (CCIR656) modes.
Polarity and function are programmed
in control register in bits B10, B17,
B26, and B28.

is configured as input in external slave
mode and as output in master and
internal slave (CCIR656) modes.
Polarity and function are programmed
in control register in bits B15, B25,
B28, and B29.

PIN NAME FUNCTION

11 YCRCB7 YCRCB digital input bit 7
12 YCRCB6 YCRCB digital input bit 6
13 YCRCB5 YCRCB digital input bit 5
14 DV
15 DGND2 Digital ground pin
16 CLK System clock: 27Mhz (CCIR656 rate),

17 YCRCB4 YCRCB digital input bit 4
18 YCRCB3 YCRCB digital input bit 3
19 YCRCB2 YCRCB digital input bit 2
20 YCRCB1 YCRCB digital input bit 1
21 YCRCB0 YCRCB digital input bit 0
22 SCLK Serial control bus clock input
23 SDATA Serial control bus data input
24 AGND2 Analog ground pin
25 AV
26 CV
27 Y
28 C

CC2

CC2

OUT

OUT

OUT

Digital 5V supply pin

24.54Mhz (Square Pixel rate)

Analog 5V supply pin
Composite video output
Luma output
Chroma output

3

ML6461

ABSOLUTE MAXIMUM RATINGS

Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute

Storage Temperature .................................... –65 to 150ºC

Junction T emperature..............................................120ºC

maximum ratings are stress ratings only and functional
device operation is not implied.

OPERATING CONDITIONS

AVCC, DVCC.................................................... –0.3 to 7V

Analog and Digital Inputs/Outputs....–0.3 to AVCC + 0.3V

Input current per pin................................... –25 to 25mA

Temperature Range........................................0°C to 70°C

Operating Supply Range...............................4.5V to 5.5V

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, AVCC = DVCC = 4.5V to 5.5V, TA = Operating Temperature Range (Note 1)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

POWER PERFORMANCE

Power Dissipation 750 mW

SUPPLIES

AV
DV

I
I

DIGITAL INPUT SIGNALS

Analog Supply Voltage 4.5 5.5 V

CC

Digital Supply Current 4.5 5.5 V

CC

Analog Supply Current 125 mA

SA

Digital Supply Current Max. Programmed Clock Rates 35 mA

SD

V

V

I

I

DIGITAL OUTPUT SIGNALS

V

V

ENCODER AND DAC (Note 2)

Input Low Voltage 0.8 V

IL

Input High Voltage 2.0 V

IH

Low Level Input Current VIN = at 0.1V 1 µA

IL

High Level Input Current VIN = at DVCC – 0.1V 1 µA

IH

Input Capacitance 2pF

Low Level Output Voltage I

OL

High Level Output Voltage I

OH

Output Capacitance 50 pF

Output Amplitude Accuracy SMPTE Color Bars 2 5 %
CV Output Amplitude SMPTE Color Bars, Peak-to-Peak 0.95 1.05 V
C Output Amplitude SMPTE Color Bars, Peak-to-Peak 0.594 0.657 V
Y Analog/Digital Bandlimit Swept Multiburst 5.7 MHz
C Analog/Digital Bandlimit Swept Multiburst 1.5 MHz
Vector Phase Accuracy (Note 3) Swept Multiburst –2.5 1 2.5 º
Vector Amplitude Accuracy (Note 3) SMPTE Color Bars –2.5 2.5 %

= 2mA 0.4 V

OUT

= 100µA VCC-0.4 V

OUT

Chroma Phase Linearity NTC7 Stepped Subcarrier –2 2 º
Chroma Amplitude Linearity NTC7 Stepped Subcarrier –1 1 IRE
Differential Gain NTC7 Modulated Staircase (Note 2) 0.5 1 %
Differential Phase NTC7 Modulated Staircase (Note 2) 0.5 1 º

4

ML6461

ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

ENCODER AND DAC (Continued) (Note 2)

Luma Nonlinearity –1 1 IRE
FSC Phase Jitter (RMS) SMPTE Color Bars 1 º
Quadrature Error SMPTE Color Bars 1 º

SERIAL BUS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

INPUT

V

V

I

I
Z
C

Low Level Input Voltage 0 0.8 V

IL

High Level Input Voltage VCC – 0.8 V

IH

Low Level Input Current VIN = 0V 1.0 µA

IL

High Level Input Current VIN = DV

IH

Input Impedance f

IN

Input Capacitance 2pF

IN

SYSTEM TIMING

f

CLOCKSCLK

V

HYS

t

SPIKE

t

WAIT

Input Hysteresis 0.2 V
Spike Suppression Max Length for Zero Response 50 ns
Wait Time From STOP to START

On S

t

HD/START

t

SU/START

t

LOW

t

t

HD/DATA

t

SU/DATA

Hold Time for START On S
Setup Time for START On S
Min LOW Time On S
Min HIGH Time On S

HI

Hold Time On S
Setup Time On Fast mode 100 ns

CC

CC

= 100kHz 1 MΩ

CLK

1.0 µA

V

Frequency 100 kHz

DATA

DATA

CLK

CLK

DATA

DATA

1.3 µs

0.6 µs

1.3 µs

0.6 µs

0.6 µs

5.0 µs

Slow mode 250 ns
t
t

t

SU/STOP

Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
Note 2: All specifications include reconstruction filter and line driver.
Note 3: Normalized to burst.

Rise Time for S

LH

Fall Time for S

HL

Setup Time for STOP On S

CLK

CLK

& S

& S

DATA

DATA

DATA

30 300 ns
30 300 ns

0.6 µs

5

ML6461

FUNCTIONAL DESCRIPTION

INTRODUCTION

The ML6461 is a single-chip NTSC video encoder for
generating analog composite (CV) and S-video (Y/C)
outputs from YCrCb digital inputs. The ML6461 is a mixed
signal processor optimizing SNR and distortion by
performing subcarrier generation, sync generation,
modulation and upsampling in the digital domain, while
performing mixing, reconstruction and gain scaling in the
analog domain. In particular , the Y channel requires no
digital scaling, eliminating the need for higher precision
digital solutions. All timing is based on an external clock
source either 27MHz for CCIR656 clock rate or

24.54MHz for square pixel clock rate.
Additionally , the ML6461 allo ws the inclusion of Closed

Captioning codes in the vertical blanking interval (VBI).
Both lines 21 and 284 support Closed Captioning.

DEVICE FUNCTIONAL DESCRIPTION

Video Formats Clock DAC Closed Macrovision Reconstruction 75

Rates Caption Filter Cable

Other special functions include: programmable polarity
and relative position of sync pulses, master and slav e
modes of which includes the ability to handle ITU-R656­compliant digital TV or ITU-R/SMPTE specifications,
chroma subcarrier phase and frequency adjustments from
external source; Japanese NTSC support; 100% color bars
processing; and internal 7th order reconstruction filters
with group delay equalization and 6dB line drivers for
direct TV output.

The ML6461 can be programmed and controlled via a
two-wire serial bus or preset modes. A summary of the
features of the ML6461 are listed in Table 1.

VIDEO STANDARDS SUPPORTED

The ML6461 supports NTSC only. The video standards
and clock rates are listed in Table 2.

ΩΩ

Ω

ΩΩ

Encoder Driver

NTSC PAL CCIR656 Square

ML6460 Yes. Input: 8-Bit No Yes Yes Yes. Yes Yes Yes. 7th-order Yes.

YCrCb digital 10-bit Butterworth, with
Outputs: Y , C, DAC group delay
and CV analog equalization

ML6461 Yes. Input: 8-Bit No Yes Yes Yes. Yes No Yes. 7th-order Yes.

YCrCb digital 10-bit Butterworth, with
Outputs: Y , C, DAC group delay
and CV analog equalization

Table 1. Video Encoder Functional Selection

INPUT CLOCK RATE LINES PER FRAME HORIZONTAL LINE

NTSC CCIR656 27 MHz 525 858

NTSC Square Pixel 24.54 MHz 525 780

Table 2: Video Standards and Clock Rates

MODE VSYNC PIN HSYNC PIN FIELD PIN

Master Mode OUT OUT IN/OUT

External Slave Mode IN IN IN/OUT

Internal Slave Mode (SAV/EAV CCIR656) OUT OUT IN/OUT

Pixel

HORIZONTAL PIXELS PER

Table 3: Pin Assignments for Various Master/Slave Modes

6

FUNCTIONAL DESCRIPTION (Continued)

ML6461

VIDEO TIMING AND INPUTS

The clock source for the ML6461 can be either 27MHz
(CCIR656) or 24.54MHz (NTSC Square Pixel). The
ML6461 internal timing generator also provides necessary
horizontal and vertical syncs, video blanking, burst, and
closed caption timing. The internal clock is derived
through buffering and inverting the external CLK signal.
The inputs YCRCB<7:0>, VSYNC, and HSYNC are
registered at the rising edge of CLK and PHERR is
registered at the falling edge of CLK. All inputs must be
valid for the minimum setup time of 5ns. The outputs
VSYNC, HSYNC, and FIELD are clocked at the rising edge
of CLK and are valid 10ns following the edge of the clock.

The ML6461 can operate in master and slave modes. In
master mode, the ML6461 internally generates the vertical
reset (VSYNC pin is an output) and horizontal reset
(HSYNC pin is an output). In the slave modes, there are
two alternatives. External sla v e mode allo ws the user to
provide an external vertical reset (VSYNC pin is an input)
and an external horizontal reset (HSYNC pin is an input).
Internal slave mode (CCIR656) uses the SAV and EAV
codes to generate the vertical and horizontal resets. The
master/slave modes are selected via register program.
Table 3 provides a description of the various modes and
the assignments of the VSYNC, HSYNC, and FIELD pins.

MASTER MODE

A logical 0 in the SLAVE/MASTER bit (bit B28) will
configure the ML6461 in the master mode. Multiplexed Y ,
Cr , Cb data is streamed through the YCRCB <7:0> input
pins. VSYNC and HSYNC pins are configured as outputs
and provide vertical and horizontal sync information. The
polarity of the active edge of the HSYNC and VSYNC
pulses can be programmed through the control register via
the SENSE_HSYNC bit (bit B15) and the SENSE_VSYNC
bit (bit B10), respectively. Coincident active edges of the
horizontal and vertical syncs at the start of the line 4
indicates the beginning of an odd field, whereas, the
active edge of the vertical sync pulse when the horizontal
sync is non-active at the middle of line 266, indicates the
beginning of an even field (Figure 1). The FIELD pin can be
configured either as an input or output through the
FRAME_MODE bit (bit B8). If configured as output (B8
=0) it can be set to provide either even/odd field
information (B9 = FLD_FRM_MODE = 0) or analog field
information (B9 = 1). For the former case, a logical 1 on
the FIELD pin indicates odd fields and a logical 0 even
fields. For the latter,(on the FIELD pin), a logical 1 is held
during analog fields 1 and 2, and a logical 0 during analog
fields 3 and 4. If the FIELD pin is configured as an input
(B8 = FRAME_MODE = 1) it must be held low and high on
alternating frames and it should change state at the
beginning of vertical sync during fields 1 and 3. The
internal subcarrier oscillator is reset to make the frame —
for which FIELD pin is held 1 — correspond to analog
fields 1 and 2 (Figure 2). In master mode, a composite
blanking signal is also available thru the HSYNC pin. This
can be activated via the CBLANK bit (B29=1). The

polarity of the composite blanking signal is programmable
from the SENSE_HSYNC bit (B15). When the
SENSE_HSYNC bit is set (B15=1), the ML6461 will output
a logic 0 at the HSYNC pin during the pixels which are
blanked. Conversely, when the SENSE_HSYNC bit is
cleared (B15=0), the ML6461 will output a logic 1 at the
HSYNC pin during the pixels which are blanked.
Consequently, the YCRCB<7:0> inputs will be ignored and
a constant blanking level will be output to the analog
channels YOUT, COUT, and CVOUT. T he operation of the
VSYNC and FIELD pins are not affected by the settings of
CBLANK and SENSE_HSYNC.

SLAVE MODES

A logical 1 in the SLAVE/MASTER bit (B28) will configure
the ML6461 for slave mode. Based on what timing
information is provided, there are two slave modes:
internal and external. Composite blanking—similar to that
described in Master Mode—is also available. Note that in
the internal slave mode, vertical and horizontal sync
pulses and/or composite blanking signals are output for
monitoring purposes only. All timing is derived from SA V/
EAV codes.

Internal Slave Mode for CCIR656 with SAV/EAV codes

In this mode (B26 = SLAVE_MODE=1), all the horizontal
and vertical timing information including odd/even field
selection is embedded in the multiplexed Y, Cr , Cb data
stream input through the YCRCB <7:0> pins. VSYNC and
HSYNC pins are configured as outputs to give vertical and
horizontal sync pulses respectively. The operation of the
FIELD pin is similar to that in the master mode. Composite
blanking — similar to the one described in the master
mode — is also available. Note that in the internal slave
mode, vertical and horizontal sync pulses and / or
composite blanking signal is output for monitoring
purposes only. As mentioned above, all timing is derived
from SAV/EAV codes.

External Slave Mode

In this mode: Where (B26 = SLAVE_MODE=0), horizontal
and vertical reset pulses must be provided externally
through HSYNC and VSYNC pins which are configured as
inputs. The polarity of these pulses is programmed
through bits SENSE_HSYNC (B15) and SENSE_VSYNC
(B10). A horizontal reset pulse on the HSYNC pin can be
given either at the beginning of active video
(B25=HRESET_MODE=1) or at the beginning of horizontal
blanking (B25=HRESET_MODE=0). Once per frame, the
active edge of a vertical reset pulse coincident with the
active edge of a horizontal reset pulse initializes the
internal vertical line counter to the beginning of an odd
field at line 4. Non-coincident vertical reset pulses, for
example, the ones which fall outside of the interval (see
Figure 3) determined by the activ e edge of the horizontal
reset pulse, will be ignored. The FIELD pin, as explained
above can be configured as an input to dictate analog
fields or as an output to monitor odd/even fields or analog

7

ML6461

FUNCTIONAL DESCRIPTION (Continued)

fields (1-2) and (3-4). The ML6461 also supports a frame
based synchronization mode (B17 = FSYNC = 1) where a
vertical reset pulse unconditionally resets the vertical line

Line 3

HSYNC

Line 4

Coincident
Active Edges

counter to line 4. For proper operation only one acti ve
edge should be sent per frame. The polarity is controlled
by SENSE_VSYNC (B10).

Line 5

Line 6

VSYNC

Beginning of
an Odd Field

HSYNC

VSYNC

Line 265

Line 266

Beginning of

an Even Field

Line 267

Line 268

Line 269

Figure 1. Example of the Beginning of the Odd And Even Fields vs. HSYNC and VSYNC in Master Mode.

(SLAVE/MASTER = 0, SENSE_HSYNC = 0, SENSE_VSYNC

==

= 0)

==

8

ML6461

FIELD (1,2 and 3,4)

FIELD (ODD/EVEN)

FIELD (1,2 and 3,4)

FIELD (ODD/EVEN)

H

L

H

L

ANALOG

FIELD 1

523 524 525 1 2 3 4 5 6 7 8

EQUALIZING

PULSES

H

L

H

L

ANALOG

FIELD 2

SERRATION

PULSES

BURST PHASE

EQUALIZING

910 22

PULSES

FIELD (1,2 and 3,4)

FIELD (ODD/EVEN)

FIELD (1,2 and 3,4)

FIELD (ODD/EVEN)

261 262 263 264 265 267 268 269 270 271

H

L

H

L

ANALOG

FIELD 3

523 524 525 1 2 3 4 5 6 7 8

H

L

H

L

ANALOG

FIELD 4

266

START

OF VSYNC

BURST PHASE

272 286285

910 22

261 262 263 264 265 267 268 269 270 271

266

Figure 2. Four Fields (M) NTSC Format FIELD Pin Out

272 286285

9