Micro Linear Corporation ML6430CH, ML6431CH Datasheet
December 1998
PRELIMINARY
ML6430/ML6431*
Genlocking Sync Generator with
Digital Audio Clock for NTSC, PAL & VGA
GENERAL DESCRIPTION
The ML6430/ML6431 are multi-standard single-chip
BiCMOS video Genlock ICs for NTSC, PAL and VGA.
They are designed to provide a stable clock from an
analog video signal, and to provide timing pulses for
clamping, decoding, blanking and processing video
signals. The ML6430/ML6431 handle VCR glitches and
variations created by head switching, tape dropouts,
missing sync pulses, freeze frames, high speed playback
and camcorder gyro errors. The ML6430/ML6431 are
designed for high noise immunity, insensitivity to varying
signal amplitudes, overmodulated color carriers, and sync
glitches. Advanced analog and digital clock synthesis
techniques provide multi-standard and non-standard
operation from a single crystal or external asynchronous
clock source. Pin selectable preset modes allow operation
for most video standards in simple stand-alone mode
without the necessity of using the serial bus. For more
demanding applications, a two wire serial control bus is
available for full control of all of the ML6430/ML6431
features.
The ML6430/ML6431 are ideal for clock generation in
MPEG encoders, high performance display timing, and
video editing.
FEATURES
■ Line locked scalable horizontal pixel clock for an
arbitrary number of pixels per line
■ Standard frequencies of 12.27, 13.5, 14.75MHz, or 4Fsc
■ 4´/2´ or 2´/1´ clock outputs (54 and 27MHz, or 27 and
13.5MHz) and VGA clocks
■ Audio clocks: 32, 44.1, or 48kHz, locked to video
■ On-chip sync separator, VCO and pulse generator
■ Low clock jitter: Short Term: <200ps rms locked
■ Line to line: <600ps rms (2.2ns peak-to-peak) locked
■ Fast recovery from VCR head switch, stable for fast
shuttle speeds and pause
■ Single crystal or external frequency source
■ PAL, NTSC or VGA operation
■ 2 wire serial control bus, or selectable presets for stand
alone operation
■ RS170A compatible
* This Part Is End Of Life As Of August 1, 2000
BLOCK DIAGRAM
C
VIN/
H
SYNC
6
CV
REF
7
V
SYNC
8
XTAL
IN
11
CRYSTAL
XTAL
12
P0
31
P1
32
P2/S DATA
1
P3/S CLK
2
OUT
OSC.
SLEEP/54MHz
V
SV
CC
SYNC SEPARATOR
ANALOG PLL
DIGITAL PHASE DET.
÷M
SERIAL CONTROL
AND PRESETS
3 13 5 10 20 30
÷N
PHASE
DETECTOR
FREERUN
REF
VCO
AND FILTERING
DIGITAL PHASE
AV
CC
SIGNAL DETECT
DIGITAL PLL
MOD.
GND S GND A GND B GND D
HORIZ. PIXEL
PULSE AND AUDIO
CLOCK GENERATOR
BV
CC
MUX
DYNA. STATE MACH.
CONTROLLER
COUNTER
292194
CC
VERT. LINE
COUNTER
D
B
1X CLOCK/4X CLOCK
AUDIOCLK/PHERROUT*
ONLY AVAILABLE IN ML6431
C
SYNC
NOSIGNAL
LOCKED
H
RESET
F
RESET
S
CLAMP
/BURST
CLAMP
2X CLOCK
H
BLANK
V
BLANK
FIELD ID
*PHERROUT IS
26
14
15
23
22
28
27
19
18
25
24
17
16
1
ML6430/ML6431
PIN CONFIGURATION
ML6430
32-Pin TQFP (H32-7)
D
P1P0GND D
CC
V
SCLAMP
BCLAMP/BURST
SYNC
C
HBLANK
P2/S
DATA
P3/S
CLK
SLEEP/54MHz
VCC S
GND S
C
VIN/HSYNC
CV
REF
V
SYNC
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
9 10111213141516
A
CC
V
GND A
XTALIN
XTALOUT
FREERUN
NOSIGNAL
LOCKED
TOP VIEW
ML6431
32-Pin TQFP (H32-7)
24
23
22
21
20
19
18
17
AUDIOCLK
VBLANK
HRESET
FRESET
V
B
CC
GND B
1X CLOCK/4X CLOCK
2X CLOCK
FIELD ID
P2/S
DATA
P3/S
CLK
SLEEP/54MHz
VCC S
GND S
C
VIN/HSYNC
CV
REF
V
SYNC
D
GND A
XTALIN
CC
V
SCLAMP
FREERUN
XTALOUT
BCLAMP/BURST
C
LOCKED
NOSIGNAL
P1P0GND D
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
9 10111213141516
A
CC
V
TOP VIEW
SYNC
HBLANK
24
23
22
21
20
19
18
17
VBLANK
HRESET
FRESET
V
CC
GND B
1X CLOCK/4X CLOCK
2X CLOCK
FIELD ID
AUDIOCLK/PHERROUT
B
2
ML6430/ML6431
PIN DESCRIPTION (NOTE: ML6430 and ML6431 pin functions are identical
PIN NAME FUNCTION
1 P2/S
DATA
This is a dual function pin. If presets
are enabled, refer to Table 7. If presets
are disabled, serial bus data input.
2 P3/S
CLK
This is a dual function pin. If presets
are enabled, refer to Table 7. If presets
are disabled, serial bus clock input.
3 SLEEP/54MHz
Hardware sleep mode: when low,
disables entire chip for ultra-low
power dissipation. Sleep mode can
also be enabled/disabled via serial bus
(Register 8). 54MHz is a clock input.
This can be any 4X clock up to
70MHz used for pulse generation.
4V
S Analog supply for sync separator.
CC
5 GND S Analog ground for sync separator.
6CVIN/H
Composite video input; video input in
SYNC
typical composite video applications,
or Y input for YUV applications, or G
input for RGB applications with sync
on green. For typical VGA or other
high performance display applications, this input may be supplied with
a TTL level H
signal and the
SYNC
vertical sync input supplied with a TTL
level V
SYNC
signal.
PIN NAME FUNCTION
13 FREERUN Forces the PLL to run at a selected
standard without syncing to a video
signal. Accuracy is ±20ppm in
FREERUN with ideal crystal, otherwise
locked to video source
14 NOSIGNAL Indicates video signal activity has not
been detected at the composite input.
If NOSIGNAL = low, this condition
does not imply that lock has been
established. The NOSIGNAL pin can
be tied to FREERUN to create a local
loop in which the genlock will not try
to lock until a signal is detected at the
input.
15 LOCKED Indicates when digital PLL is locked to
incoming video signal.
16 (ML6430) AUDIOCLK
Digital audio clock output.
Programmable for 32kHz, 44.1kHz or
48kHz output.
16 (ML6431) AUDIOCLK/PHERROUT
This is a dual mode pin. Pin is selected
via serial bus (Register 7). AUDIOCLK
is an audio clock signal (see Table 9).
PHERROUT indicates whether
incoming HSYNC is ahead or behind
output HSYNC.
except
for pin 16. See below)
7CV
REF
Reference voltage for internal sync
slicer. The external capacitor is driven
by a charge pump to follow the sync
tip.
8V
SYNC
Vertical input for non-composite
sources. This input may be supplied
with a TTL level V
SYNC
signal. For
composite inputs this pin is tied high
or low.
9VCC A Analog supply pin for analog PLL.
10 GND A Analog ground for analog PLL.
11 XTAL
IN
Crystal may be parallel tuned 3.58
MHz or 4.43MHz, or may be driven
by an external oscillator at these
frequencies, or at 4x these
frequencies.
12 XTAL
OUT
Crystal drive pin. No connect if using
external oscillator or clock.
17 FIELD ID Field Flag: Odd = 1, Even = 0
18 2X CLOCK 2X oversampled PIXEL CLOCK &
Output of Digital PLL. Nominal
frequency of 27MHz
19 1X CLOCK/4X CLOCK
1X pixel clock. Nominal frequency
of 13.5MHz or 54MHz ±20ppm in
FREERUN with ideal crystal, otherwise
locked to video source. PAL 4X CLOCK
not available (no 4x4.4336MHz clock).
20 GND B Digital ground for output driver
buffers.
21 VCC B Digital supply for output driver buffers.
22 F
RESET
Frame reset; active low for one half
line at the high to low transition of
field ID. In NTSC mode, FRESET goes
low on the high-to-low transition on
the Field ID pin and at the beginning
of line 1 (see Figure 2). In PAL mode,
FRESET goes low on the high-to-low
transition on the Field ID pin and at
the end of line 310 (see Figure 3).
3
ML6430/ML6431
PIN DESCRIPTION (Continued)
PIN NAME FUNCTION
23 H
24 V
25 H
26 C
27 B
RESET
BLANK
BLANK
SYNC
CLAMP
Horizontal reset; active low for one
half pixel.
Vertical blanking, active low
Horizontal blanking, active low
Composite sync output. May be either
the raw output of sync slicer, or
regenerated signal from internal pulse
generators. If raw slicer output is
selected, then signals disappear when
input signal disappears. If regenerated
output is selected, then signal is
always present regardless of input
conditions. Preset modes produce
regenerated sync.
/BURST
This is a dual mode pin. User may
select either a back porch clamp pulse
or a burst gate pulse via the serial
control bus. Preset is B
CLAMP
pulse.
PIN NAME FUNCTION
28 S
29 VCC D Digital supply pin for digital PLL.
30 GND D Digital ground pin for digital PLL.
31 P0 This is a three-state pin: low means
32 P1 This is a three state pin. Refer to
CLAMP
Sync clamp pulse occurs just after
leading edge of sync. Duration is
typically less than 50% of sync pulse
to avoid problems with equalizers in
the vertical interval, active high.
serial bus is enabled, high or
unconnected (high Z) means presets
are active. Refer to Table 7.
Table 7. If presets are disabled pin
is ignored.
4
ML6430/ML6431
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
OPERATING CONDITIONS
Supply Range ...............................................4.5V to 5.5V
Temperature Range ....................................... 0°C to 70°C
Thermal Resistance ............................................. 80°C/W
device operation is not implied.
DC Supply Voltage (VCC A & VCC D) .............–0.3V to 7V
Analog & Digital Inputs/Outputs... –0.3V to VCC A + 0.3V
Input current per pin ............................................. ±25mA
Storage Temperature ............................... – 65°C to 150°C
Junction Temperature ..............................................125°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 4.5 to 5.5V and TA = 0° to 70°C, CIN = 0.1µF, C
PARAMETER CONDITIONS MIN TYP MAX UNITS
SUPPLY
Supply Current (Analog and Digital) 80 120 mA
Analog Supply Current VCC A = VCC D = 4.5 35 mA
Digital Supply Current Max programmed clock rates 45 mA
DIGITAL INPUTS
= 0.1µF (Note 1).
REF
Low Level Input Voltage 0 0.8 V
High Level Input Voltage VCC – 0.8 V
Low Level Input Current VIN = 0V + 0.1V 1.0 µA
High Level Input Current VIN = VCC D – 0.1V 1.0 µA
Input Capacitance 2pF
TTL INPUTS (H
V
Input Low Voltage 0.8 V
IL
V
Input High Voltage 2.0 V
IH
THREE STATE DIGITAL INPUTS
Low Level Input Voltage 0 0.8 V
High Level Input Voltage VCC – 0.8 V
Low Level Input Current VIN = 0V 50 150 µA
High Level Input Current VIN = VCC D 50 150 µA
Input Capacitance 2pF
Mid Level Input Voltage with 5V Supply 2 3 V
DIGITAL OUTPUTS
Low Level Output Voltage 0 0.5 V
SYNC
, V
SYNC
)
CC
V
High Level Output Voltage VCC – 0.5 V
C
: Output Capacitance 50 pF
LOAD
Output Disable Leakage 10 µA
5
ML6430/ML6431
GENLOCK PERFORMANCE SPECIFICATIONS
Unless otherwise noted, VIN = 1 VPP NTSC test signal for composite inputs, or 100% color bars for component (Note 1).
See Figure 1 for parameter measurement definition
PARAMETER CONDITIONS MIN TYP MAX UNITS
SYNC SEPARATION
Min Sync Amplitude 135 mV
Max Video Amplitude 3V
Clamp timing error NTC7 AC bounce signal (Note 2) 10 ns
Clamp Recovery TIme NTC7 DC bounce signal (Note 3) 16 µs
CLOCK RECOVERY
Short Term Output Jitter Rejection Input jitter = 50ns RMS –15 dB
RMS Residual Output Clock Jitter Input jitter <1ns RMS 600 ps
Peak to Peak (6s), Line to Line Jitter Input Jitter < 1ns 2.0 2.2 ns
Head Switch Recovery Time to 1ns Error 5µs step H change on or before 4 lines
line 1
Step Frequency Recovery Time to 1ns Error 1% step H frequency change on or 12 15 ms
before line 1
Missing Sync Sensitivity (Note 4) 1.0 ns
Sync Glitch Sensitivity (Note 5) 1.0 ns
4X Clock Duty Cycle C
2X Clock Duty Cycle C
1X Clock Duty Cycle C
Clock Skew — 1X to 2X C
Pulse Output Rise Time C
Pulse Output Fall Time C
Pulse Output Setup Time C
Pulse Output Hold Time C
= 50pF, f
LOAD
= 50pF, f
LOAD
= 50pF, f
LOAD
= 50pF, f
LOAD
= 50pF 2 10 ns
LOAD
= 50pF 2 10 ns
LOAD
= 50pF 20 ns
LOAD
= 50pF 20 ns
LOAD
< 60MHz 40 60 %
CLK4X
< 30MHz 48 52 %
CLK2X
< 15MHz 48 52 %
CLK1X
< 15MHz 6 ns
CLK1X
SERIAL BUS
PARAMETER CONDITIONS MIN TYP MAX UNITS
INPUT
Low Level Input Voltage 0 0.8 V
High Level Input Voltage VCC – 0.8 V
CC
Low Level Input Current VIN = 0V 1.0 mA
High Level Input Current VIN = VCC D 1.0 mA
V
Input Impedance f
= 100kHz 1 MW
CLK
Input Capacitance (CIN) 2pF
SYSTEM TIMING
S
Frequency (f
CLK
Input Hysteresis (V
Spike Suppression (t
) 100 kHz
CLOCK
) 0.2 V
HYS
) Max length for zero response 50 ns
SPIKE
Power Setup Time to Valid Data Inputs VCC Settled to Within 1% 10 ms
6
SERIAL BUS LOGIC (Continued)
PARAMETER CONDITIONS MIN TYP MAX UNITS
SYSTEM TIMING (Continued)
Wait Time From STOP to START
On S
Hold Time for START On S
Setup Time for START On S
Min LOW Time On S
Min HIGH Time On S
Hold Time On S
Setup Time On (t
DATA
(t
) 1.3 µs
WAIT
DATA (tHD/START
DATA (tSU/START
(t
CLK
LOW
(tHI) 0.6 µs
CLK
DATA (tHD/DATA
) Fast mode (Note 2) 100 ns
SU/DATA
) 1.3 µs
) 5.0 µs
) 0.6 µs
) 0.6 µs
ML6430/ML6431
Slow mode (Note 2) 250 ns
Rise Time for S
Fall Time for S
Setup Time for STOP On S
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst-case test conditions.
Note 2: Parameter is Luma dependent.
Note 3: Reclock time after bounce.
Note 4: Net phase error for single isolated missing H pulse.
Note 5: Net phase error for glitch at sync level <50ns.
COMPOSITE
REGENERATED
EQUALIZERS
SERRATIONS
CLK
& S
CLK
VIDEO IN
PIN 6
CSYNC
PIN 26
H
BLANK
PIN 25
S
CLAMP
PIN 28
BGATE
PIN 27
B
CLAMP
PIN 27
H
RESET
PIN 23
& S
DATA (tLH
DATA (tHL
DATA (tSU/STOP
t
t
HBLK
t
HBPC
t
HRW
) 30 300 ns
) 30 300 ns
) 0.6 µs
HSW
t
HEQW
t
HSERRW
t
HBLKW
t
HSTC
t
HSTCW
t
HBPGW
t
HBPCW
Figure 1. Line Rate Waveforms
NOTE: NOT TO SCALE
7
ML6430/ML6431
DEVICE DIFFERENCES
Tables 1 and 2 summarize the differences between the
ML6430 and ML6431. The pinouts of the ML6430 and the
ML6431 are the same with the exception that the ML6431
DEVICE FUNCTIONAL DESCRIPTION
Video Formats,
Timing, Clock Input Free Run VGA VCR
and Pulse Rates Crystal Mode Clock Lock
Generation
NTSC PAL CCIR601 Square 4xFSC 3.58 4.43
Pixel MHz MHz
ML6430 Yes Yes Yes Yes Yes Yes Yes Yes. Limited Yes. Limited to Yes
ML6431 Yes Yes* Yes Yes* Yes Yes Yes Yes. Faster Yes. Works Yes.
* Readjusted the center frequency for PAL square pixel with NTSC crystal to achieve greater than +/-5% range. See Table 4
has a few enhancements, (Center Frequency and Free Run
Mode, see Table 1) and added functionality (see Table 2).
transition 640x480
between free pixel clock.
run modes
1 and 2.
(Figure 4)
transition be- up to 75MHz.
tween freerun (Table 6)
modes 1and 2.
(Figure 4a)
Table 1. Summary of Functional Differences between the ML6430 and ML6431.
DEVICE MODE REGISTER DIFFERENCES PIN OUT DIFFERENCES
Register 7, Register 7, Pin 3 Pin 16
Bit 2 Bit 3
ML6430 Sleep Mode 0 0 SLEEP AUDIOCLK
Pulse Generator Mode* 1 0 54MHz** AUDIOCLK
Time Base Correction Mode
ML6431 Sleep Mode 0 0 SLEEP AUDIOCLK
Pulse Generator Mode* 1 0 54MHz** AUDIOCLK
PHERROUT Mode* X 1 Must be set HIGH PHERROUT
*For these modes the SLEEP mode can only be enable/disabled via serial bus (Register 8).
**The 54MHz clock input (pin 3) can be any 4 x Clock up to 70MHz
Table 2. Summary of Register Differences between the ML6430 and ML6431.
This function not available in the ML6430
8
FUNCTIONAL DESCRIPTION
ML6430/ML6431
DUAL PLLS
The Genlock has the following properties:
• A stable, asynchronous crystal controlled oscillator
provides the basic timing signals.
• A precision analog circuit uses the above timing
signals to generate an arbitrarily phased output whose
phase can be altered at pixel rate.
• A digital PLL loop monitors the error signal from a
digital phase detector, and generates a pixel by pixel
phase adjustment of the output.
• An intelligent state machine further enhances
performance by monitoring errors and error history and
adjusting the gains of the loop accordingly.
• A circuit automatically detects a VCR signal and
increases loop gain for proper tracking and minimum
jitter.
The digital PLL has five operating modes. In normal
operation with a stable input the controller will settle to
state 1. If errors are large and consistent, controller will
move to state 5. If error conditions are corrected,
controller will sequentially decrease the state as the errors
are reduced toward 0. If small but consistent errors persist
while controller is in state 1, then controller may move to
states 2 or 3 to help settle out errors more quickly. None
of these changes will cause a reset of pixel count, or a
discontinuity of output clocks. Operating modes are
described in greater detail below.
1. Normal: Gain is low, instantaneous phase gain is
1/32, giving a net short term jitter gain (output/input
jitter) of about -30db. Full peak to peak jitter (including
lower frequency jitter) from a white source is about 15db.
2. Slow: Gain is increased by 4x, and settling time
reduced by about the same. This mode is used as a
transition mode during normal lock sequence, or as a
modest speed up mode if errors are high.
3. Medium: Gain is increased by 8x, and settling time
reduced by about the same. This mode is used as a
transition mode during normal lock sequence, or as a
speed up mode if errors are consistently high.
4. Fast: Gain is increased by 16x. Adds frequency
adjustments to mode 5 for fast settling during hot
switches or pathological gyro errors in hand held
camcorders.
5. Phase: Only Gain is 16x for phase changes, 0 for
frequency changes. Primarily used to quickly settle
head switch phase errors without affecting loop
frequency.
PHERROUT SIGNAL
The PHERROUT pin indicates, on a line by line basis,
whether the H SYNC pulse of the analog input signal is
leading or trailing the genlock's output H SYNC pulse.
This information is used by the genlock to decide whether
to speed up or slow down the internal clock to achieve
locking of the H SYNC pulses. If PHERROUT = 0, then
the analog sync is ahead; therefore, the internal clock
will speed up in an effort to lock the H SYNC pulses. By
contrast, if PHERROUT = 1, then the analog sync is
behind; therefore, the internal clock will slow down in an
effort to lock the H SYNC pulses. Ultimately, when the
genlock is locked to the incoming analog signal,
PHERROUT will alternate approximately every line
between 0 and 1.
PHERROUT (PIN 16) DESCRIPTION
0 Speed up output timing
1 Slow down output timing
Table 3. PHERROUT Signal Description
SYNC SEPARATION
Sync separation is accomplished using peak tracking
analog amplifiers with a precision sync slicer. The closed
tracking loop is equipped with timers to discriminate true
sync pulses from noise glitches or chroma overshoots. The
use of analog sync separation techniques removes a
serious source of jitter present in most digital PLLs.
CRYSTAL SELECTION
The precision crystal source for the ML6430/ML6431 can
be supplied in one of four ways. An industry standard
3.58MHz parallel tuned NTSC color subcarrier crystal or a
4.43MHz parallel tuned PAL color subcarrier crystal may
be used. Alternately, a 14.318MHz NTSC or 17.7MHz
PAL, 4xFs, or a 3.58MHz or 4.43MHz oscillator source
may be used. Regardless of the crystal used, the ML6430/
ML6431 can lock to PAL, NTSC, Beta or MII or YUV in
either 625 or 525 standards. Table 4 provides the clock
rate accuracy for both the NTSC and PAL clock rates for
each crystal selected. Note that the range may vary
between the ML6430 and the ML6431.
LOW POWER SLEEP MODES
Sleep mode may be initiated either from the serial control
bus, or from an external pin. In both cases the entire chip
except the serial bus is shut down. For applications where
PHERROUT is used, the sleep mode can only be enabled/
disabled via serial control.
9
ML6430/ML6431
FUNCTIONAL DESCRIPTION (Continued)
CENTER FREQUENCY AND ± RANGE FOR EACH FREQUENCY
VIDEO STANDARD CLOCK RATE CLOCK RATE
3.58MHz Crystal
NTSC Square Pixel 4xClk= 49.09MHz +8.35%/ –5.19%
NTSC 601 4xClk= 54.00MHz +6.07%/ –7.18%
NTSC 4fsc 4xClk= 57.27MHz +7.15%/ –6.23%
PAL Square Pixel 4xClk= 59.00MHz +4.01%/ –9.10%
PAL 601 4xClk= 54.00MHz +6.07%/–7.18%
PAL 4fsc 4xClk= 35.47MHz +9.58%/ –4.14%
4.43MHz Crystal
NTSC Square Pixel 4xClk= 49.09MHz +8.28%/ –5.23%
NTSC 601 4xClk= 54.00MHz +7.81%/ –5.64%
NTSC 4fsc 4xClk= 57.27MHz +6.00%/ –7.18%
PAL Square Pixel 4xClk= 59.00MHz +7.27%/ –6.13%
PAL 601 4xClk= 54.00MHz +7.81%/–5.64%
PAL 4fsc 4xClk= 35.47MHz +7.05%/ –6.31%
STANDARD OF THE ML6430
ACCURACY
Table 4. NTSC/ PAL Clock Rate Range vs. Crystal Input
DISABLING AUTOMATIC VCR SIGNAL DETECTION
DEVICE DISABLE VCR SIGNAL DETECTION?
ML6430 No. Detection function is always on.
ML6431 Yes. Detection function can be disabled
or enabled via serial bus only. This
feature is enabled by default.
Table 5.
In the ML6430, the VCR detection circuit is always
enabled. This circuit detects the presence of a VCR input
signal at C
VIN
/ H
(pin 6) and automatically adjusts
SYNC
the gain settings for the digital PLL to optimize locking
performance. This circuit scans for head switching greater
than the thresholds selected by the user threshold bits (via
serial bus) and then increases the phase gain of the digital
PLL to compensate.
CENTER FREQUENCY AND ± RANGE FOR EACH FREQUENCY
VIDEO STANDARD CLOCK RATE CLOCK RATE
3.58MHz Crystal
NTSC Square Pixel 4xClk= 49.09MHz +8.35%/ –5.19%
NTSC 601 4xClk= 54.00MHz +6.07%/ –7.18%
NTSC 4fsc 4xClk= 57.27MHz +7.15%/ –6.23%
PAL Square Pixel 4xClk= 59.00MHz +7.47%/ –5.93%
PAL 601 4xClk= 54.00MHz +6.07%/–7.18%
PAL 4fsc 4xClk= 35.47MHz +7.64%/ –5.77%
4.43MHz Crystal
NTSC Square Pixel 4xClk= 49.09MHz +8.28%/ –5.23%
NTSC 601 4xClk= 54.00MHz +7.81%/ –5.64%
NTSC 4fsc 4xClk= 57.27MHz +6.00%/ –7.18%
PAL Square Pixel 4xClk= 59.00MHz +7.27%/ –6.13%
PAL 601 4xClk= 54.00MHz +7.81%/–5.64%
PAL 4fsc 4xClk= 35.47MHz +7.05%/ –6.31%
STANDARD OF THE ML6431
ACCURACY
PULSE GENERATOR MODE
54MHz Input or Any 4X Clock
The 54MHz pin (pin 3) is an input that clocks the
horizontal and vertical counters. In this mode, the
ML6430 or ML6431 is used as a pulse generator. The
input signal at can be any 4X clock; for example, 54MHz
(4 x CCIR clock rate of 13.5MHz), 49.09MHz (4 x Square
Pixel clock rate of 12.27MHz), or 57.27 MHz (4 x Fsc
clock rate of 14.31MHz for NTSC color subcarrier). This
input is limited to 70MHz.
As a pulse generator, the sync, clamp, blanking, and
clock signals are derived from the clock input at the
54MHz pin. This mode is activated by setting the
appropriate values in Register 7 via the serial bus. See
Tables 10 or 11.
USING F
FOR NTSC vs. PAL MODES
RESET
In the ML6431, the VCR detection circuit operates the
same as the ML6430 with the additional ability to disable
or enable the VCR detection circuit to optimize for low
jitter performance. This feature is enabled by default.
This feature can be disabled in the ML6431 only by
setting the appropriate values in Register 7, Bit 0 via the
serial bus interface (see Table 11). When the VCR detect
circuit is disabled, the ML6431 is optimized for low jitter
performance.
10
In NTSC mode, F
(pin 22) goes low on the high-to-
RESET
low transition of the FIELD ID pin (pin 17) and the
beginning of line 1 (see Figure 2).
In the PAL mode, F
(pin 22)goes low on the low-to-
RESET
high transition of the FIELD ID pin and the end of line
310 (see Figure 3).
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