Micro Linear Corporation ML4624CQ, ML4622CP, ML4622CS, ML4622IS, ML4624CP Datasheet
January 1997
ML4622, ML4624
Fiber Optic Data Quantizer
GENERAL DESCRIPTION
The ML4622 and ML4624 data quantizers are low noise,
wideband, bipolar monolithic ICs designed specifically for
signal recovery applications in fiberoptic receiver systems.
They contain a wideband limiting amplifier which is
capable of accepting an input signal as low as 2mV
P-P
with a 55dB dynamic range. This high level of sensitivity
is achieved by using a DC restoration feedback loop
which nulls any offset voltage produced in the limiting
amplifier.
The output stage is a high speed comparator circuit with
both TTL and ECL outputs. An enable pin is included for
added control.
The Link Detect circuit provides a Link Monitor function
with a user selectable reference voltage. This circuit
monitors the peaks of the input signal and provides a
logic level output indicating when the input falls below
an acceptable level. This output can be used to disable
the quantizer and/or drive an LED, providing a visible link
status.
ML4622/ML4624 BLOCK DIAGRAM
FEATURES
■ Data rates up to 40MHz or 80MBd
■ Can be powered by either +5V providing TTL or raised
ECL level outputs or –5.2V providing ECL levels
■ Low noise design: 25µV RMS over bandwidth
■ Adjustable Link Monitor function with hystersis
■ Wide 55dB input dynamic range
■ Low power design
■ ML4624 is pin compatible with the ML4621
APPLICATIONS
■ IEEE 802.3 10BASE-FL Receiver
■ IEEE 802.5 fiber optic token ring, 4 and 16mbps
■ Fiber Optic Data Communications and
Telecommunications Receivers
V
IN
V
IN
V
DC
V
REF
VTHADJ
CF1
CF2
BIAS
+
AMP
–
ECL
CMP
ECL+
ECL–
TTL
CMP
TTL OUT
CMP ENABLE
∫
TTL*
V
CC
V
CC
GND
REF
THRESH
GEN
LINK DETECT
C
TIMER
*ML4624 ONLY
GND TTL
TTL LINK MON
1
ML4622, ML4624
PIN CONNECTIONS
TTL LINK MON
GND
V
IN–
VIN+
V
DC
CF2
CF1
GND TTL
ML4622
16-Pin DIP or
SOIC (Narrow)
16
1
15
2
14
3
13
4
12
5
11
6
10
7
8
TOP VIEW
9
CMP ENABLE
ADJ
V
TH
V
REF
C
TIMER
V
CC
TTL OUT
ECL+
ECL–
24-Pin Narrow DIP
NC
TTL LINK MON
CMP ENABLE
V
IN
V
IN
V
DC
CF2
CF1
NC
NC
NC
NC
–
+
ML4624
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
NC
NC
C
TIMER
V
REF
VTHADJ
GND
TTL OUT
TTL
V
CC
GND TTL
ECL+
ECL–
V
V
IN
V
CF2
CF1
ML4624
28-Pin PCC
4 3 2 1 28 27 26
5
–
IN
6
+
7
NC
8
DC
9
10
11
NC
12 13 14 15 16 17 18
NC NC NC NC ECL+
TTL LINK MONCMP ENABLE
NC V
NC NCNC
CC
25
24
23
22
21
20
19
ECL– GND TTL
NC
C
TIMER
V
REF
VTHADJ
GND
TTL OUT
TTL
V
CC
2
PIN DESCRIPTION
ML4622, ML4624
NAME FUNCTION
TTL LINK MON TTL Link Monitor output. Signal is
low when the VIN+, VIN– inputs
exceed the minimum threshold,
which is set by a voltage on the
VTHADJ pin. Signal is high when the
input signal level is below the
threshold. Capable of driving a 10mA
LED indicator. This pin can be tied to
CMP ENABLE.
CMP ENABLE A low voltage at this TTL input pin
enables both the ECL and the TTL
outputs. A high TTL voltage disables
the comparator output with ECL+
high, ECL– low, and TTL OUT high.
VIN– This input pin should be capacitively
coupled to the input source or to
filtered ground. (The input resistance
is approximately 1.6kΩ.)
VIN+ This input pin should be capacitively
coupled to the input source or to
filtered ground. (The input resistance
is approximately 1.6kΩ.)
ECL– The ECL comparator negative output.
Has internal pull down resistor.
External pull downs are not required
unless driving a large capacitive
load.
ECL+ The ECL comparator positive output.
Has internal pull down resistor.
External pull downs are not required
unless driving a large capacitive
load.
GND TTL The negative supply for the TTL
comparator stage. If the TTL output is
not necessary, connect GND TTL
to VCC.
NAME FUNCTION
VCC TTL The positive supply for the TTL
comparator stage. If the TTL output is
not necessary, connect VCC TTL to
VCC. (ML4624 only)
TTL OUT TTL data output.
V
DC
CF2 A capacitor from this pin to CF1
CF1 Connect to CF2 through a capacitor.
GND Negative supply. Connect to –5.2V
VTHADJ This input pin sets the link monitor
V
REF
C
TIMER
V
CC
An external capacitor on this pin
integrates an error signal which nulls
the offset of the input amplifier. If the
DC feedback loop is not being used,
this pin should be connected to V
controls the maximum bandwidth of
the amplifier.
for ECL operation, or to ground for
TTL or raised ECL operation.
threshold.
A 2.5V reference with respect to
GND.
A capacitor from this pin to V
determines the Link Monitor
response time.
Positive supply. Connect to ground
for negative ECL operation, or to 5V
for TTL or raised ECL operation.
CC
REF
.
3