February 1998
ML4621
Data Quantizer
GENERAL DESCRIPTION
The ML4621 data quantizer is a low noise, wideband
monolithic IC designed specifically for signal recovery
applications in fiber-optic receiver systems. It contains a
two stage wideband limiting amplifier which is capable
of accepting an input signal as low as 2mV with a 55dB
dynamic range. This high level of sensitivity is achieved
by using a DC restoration feedback loop which nulls any
offset voltage produced in the limiting amplifier.
The output stage is a high speed comparator circuit with
both TTL and ECL outputs. An enable pin is included for
added control.
The minimum signal discriminator circuit provides a link
monitor function with a user selectable reference voltage.
This circuit monitors the peaks of the input signal and
provides a logic level output indicating when the input
falls below an acceptable level. This output can be used
to disable the quantizer and/or drive an LED, providing a
visible link status.
FEATURES
■ 50MHz minimum bandwidth for data rates of up to
100MBd
■ Can be powered by either 5V providing TTL level
outputs, or -5.2V providing ECL level outputs
■ Low noise design: 25µV RMS over 50MHz noise
bandwidth
■ Adjustable link monitor function
■ Wide 55dB input dynamic range
■ 10ns minimum input pulse
BLOCK DIAGRAM (Pin Configuration Shown is for PLCC Version)
6
5
8
23
22
V
IN+
V
IN–
VDC
V
REF
VTHADJ
10
CF1 V
CF2
A1
DC
Please See ML4622/ML4624 for New Designs
AMP
REF
THRESHOLD
GENERATOR
A2
FILTER
OUT+
MINIMUM
SIGNAL
DISCRIMINATOR
I
NOM
27 26 24
11 139 12 14
V
OUT–
I
SET
C
PEAK
CMP+ ECL+ ECL–CMP–
ECL
CMP
GND TTL
17 16
TTL
CMP
CMP ENABLE
ECL LINK MON
TTL LINK MON
GND
2118
V
CC
V
TTL
CC
TTL OUT
28
19
20
3
1
2
1
ML4621
PIN CONFIGURATION
ML4621
24-Pin Narrow DIP (P24N)
VIN–
VIN+
VDC
CF2
CF1
OUT
OUT
CMP+
CMP–
–
+
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
ECL LINK MON
TTL LINK MON
CMP ENABLE
V
V
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
I
NOM
I
SET
C
PEAK
V
REF
V
ADJ
TH
GND
TTL OUT
VCC TTL
GND TTL
ECL+
ECL–
V
VIN–
VIN+
VDC
CF2
CF1
OUT
NC
ML4621
28-Pin PLCC (Q28)
NC
CMP ENABLE
TTL LINK MON
ECL LINK MON
4
3
2
1
5
6
7
8
9
10
–
11
12
13
14
+
OUT
V
CMP+
15
NC
CMP–
TOP VIEW
VCCI
28
16
ECL–
NOMISET
27
26
17
18
ECL+
GND TTL
25
24
23
22
21
20
19
NC
C
PEAK
V
REF
V
ADJ
TH
GND
TTL OUT
V
TTL
CC
2
PIN DESCRIPTION (Pin Number in Parenthesis is for DIP Version)
ML4621
PIN NAME FUNCTION
1 (1) ECL LINK MON ECL link monitor output. Signal
is low when the VIN+ and VIN–
inputs exceed the minimum
threshold set by a voltage on
V
ADJ. Signal is high when
TH
input signal level is below that
threshold.
2 (2) TTL LINK MON TTL link monitor output. Same
logic function as the ECL LINK
MON. Capable of driving a
10mA LED indicator. This pin is
normally tied to CMP ENABLE.
3 (3) CMP ENABLE Low voltage at this TTL input
enables both the ECL and TTL
outputs. A high TTL voltage
disables the comparator output
with ECL+ high, ECL– low, and
TTL OUT high.
5 (4) VIN– This input should be capacitively
coupled to the input source or to
ground. (Input resistance is
approximately 8kΩ).
6 (5) VIN+ This input should be capacitively
coupled to the input source or to
ground. (Input resistance is
approximately 8kΩ).
8 (6) VDC An external capacitor on this pin
integrates an error signal which
nulls the offset of the input
amplifier. If the DC feedback
loop is not being used, this pin
should be connected to V
REF
.
9 (7) CF2 A capacitor from this pin to
ground controls the maximum
bandwidth of the amplifier to
accommodate lower operating
frequencies.
10 (8) CF1 The capacitor on this pin should
match the one on CF2.
11 (9) V
- Negative output of the amplifier,
OUT
which is normally tied to CMP–.
12 (10) V
+ Positive output of the amplifier,
OUT
which is normally tied to CMP+.
PIN NAME FUNCTION
14(12) CMP– Comparator input pin. Open base
configuration relies on the DC
bias of the amp output to set the
proper DC operating voltage.
Reestablish voltage if filtering is
used between V
– and CMP–.
OUT
16(13) ECL– ECL comparator negative output.
17(14) ECL+ ECL comparator positive outout.
18(15) GND TTL Negative supply for the TTL
comparator stage. If the TTL
output is not necessary, connect
GND TTL and VCC TTL to VCC.
19(16) VCC TTL Positive supply for the TTL
comparator stage. If the TTL
output is not necessary, connect
GND TTL and VCC TTL to VCC.
20(17) TTL OUT TTL data output (totem pole type
output stage).
21(18) GND Negative supply. Connect to –
5.2V for ECL operation, or to
source ground for TTL operation.
22(19) VTH ADJ This input sets the minimum
amplitude of the input signal
required to cause the link
monitors to go low .
23(20) V
REF
A 2.5V reference with respect to
GND.
24(21) C
PEAK
A capacitor from this pin to GND
determines the link monitor
response time.
26(22) I
SET
Current into an internal diode
connected between this pin and
GND is turned around and pulled
27(23) I
28(24) V
NOM
CC
from C
connected to I
Sets a current of approximately
125µA when connected to I
Positive supply. Connect to
. This pin is normally
PEAK
NOM
.
SET
.
source ground for ECL operation,
or to 5V for TTL operation.
13 (11) CMP+ Comparator input pin. Open base
configuration relies on the DC
bias of the amp output to set
proper DC operating voltage.
Reestablish voltage if filtering is
used between V
+ and CMP+.
OUT
3
ML4621
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
VCC – GND ................................................–0.3V to 7.0V
V
TTL – GND TTL ...................................–0.3V to 7.0V
CC
GND ............................................... –0.3V to VCC + 0.3V
Junction T emperature..............................................150°C
Storage Temperature Range ..................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .....................260°C
Thermal Resistance (θJA)
24 Pin Narrow PDIP ......................................... 54°C/W
28 Pin PLCC..................................................... 68°C/W
OPERATING CONDITIONS
T emper ature Range ....................................... 0°C to 70°C
–5.2V Supply Range......................................–5.2V ± 5%
+5V Supply Range ......................................... 5.0V ± 5%
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, VCC = 5V ± 5%, GND = 0V, TA = Operating Temperature Range (Note 1)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
I
CC1
I
CC2
I
V
V
A
V
VTH ADJ External Voltage at VTH ADJ to set V
Range
VCC Supply Current VCC TTL = GND TTL = V
VCC Supply Current VCC TTL = V
CC
CC
65 100 mA
70 110 mA
(TTL OUT Enabled) GND TTL = GND
V
Output Current –5.0 0.5 mA
REF
REF
V
IN
REF
Reference Voltage 2.40 2.55 2.65 V
A1, A2 Amplifier Gain VIN = 5mV 75 V/V
Input Signal Range 2 1400 mV
TH
1 2.5 V
P-P
V
E
Input Offset VDC = V
OS
Input Referred Noise 50MHz BW 25 µV
N
(DC Loop Inactive) 3 mV
REF
BW 3dB Bandwidth 50 65 MHz
VIN PW Minimum Input Pulsewidth 10 ns
R
t
AMP Amplifier Propagation Delay Time From VIN+, VIN– to V
PD
Input Resistance VIN+, VIN–8kΩ
IN
VIN+, = 10mV
P-P
OUT
+, V
–4 8 ns
OUT
tPD ECL ECL Comparator Propagation Delay Time From CMP+, CMP– to ECL+, ECL– 4 8 ns
VIN+, = 10mV
P-P
tPD TTL TTL Comparator Propagation Delay Time From ECL+, ECL– to TTL OUT 4 8 ns
R
VTH ADJVTH
I
V
OUT
I
CMP
VCM
CMP
ECL V
OH
VIN+, = 10mV
ADJ Input Resistance 6.8 kΩ
V
OUT
+, V
– Output Current 3mA
OUT
CMP+, CMP– Leakage Current 25 µA
CMP+, CMP– Common Mode Range GND + 2 VCC – 1 V
ECL+, ECL– Output High Voltage With 200Ω Load Tied to VCC – 2V 3.90 4.30 V
P-P
TA = 25ºC
ECL V
ECL+, ECL– Output Low Voltage With 200Ω Load Tied to VCC – 2V 3.11 3.38 V
OL
TA = 25ºC
4
ML4621
ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
AV ECL ECL CMP Gain 100 V/V
TTL V
TTL V
TTL VIHTTL Input High Voltage Level 2.0 V
TTL VILTTL Input Low Voltage Level 0.8 V
TTL I
TTL IILTTL Input Low Current Level VIH = 0.4V –1.6 0 mA
I
NOM
Note 1: Limits are guaranteed by 100% testing, sampling, or correlation with worst case test conditions.
TTL Output High Voltage VCC TTL = 5V, IOH = –50µA 2.4 V
OH
TTL Output Low Voltage VCC TTL = 5V, IOL = 2mA 0.4 V
OL
TTL Input High Current Level VIH = 2.4V –50 50 µA
IH
I
NOM
= I
SET
125 µA
5
ML4621
FUNCTIONAL DESCRIPTION
AMPLIFIER
The quantizer has a two stage limiting amplifier with an
input common mode range of (GND + 1.8V) to (VCC –
1.5V). Maximum sensitivity is achieved through the use
of a DC restoration feedback loop and AC coupling on
the input. The input DC bias voltage is set by an on-chip
network at about 1.9V when it is AC coupled. These
coupling capacitors, in conjunction with the input
impedance of the amplifier, establish a highpass filter
with a 3dB corner frequency, fL, at:
=
f
L
1
¥¥
2 8000π
C
(1)
Two capacitors of equal value are required since the
amplifier has a differential input. One of the coupling
capacitors can be tied to VCC as shown in Figure 1 if the
signal driving the input is single ended. The high corner
frequency can also be adjusted by attaching capacitors to
CF1 and CF2. The equation for adjusting this corner is:
f
=
H
1
¥¥
2 425π
C
(2)
The offset voltage within the amplifier will be present at
the amplifier’s output even though the input is AC
coupled. This is represented by VOS in Figure 2. In order
to reduce this error a DC feedback loop is incorporated.
This negative feedback loop nulls the offset voltage,
forcing VOS to be zero. An external capacitor at VDC is
used to store the offset voltage. Although the value of
this capacitor is noncritical, the pole it creates can affect
the stability of the feedback loop. The value of this
capacitor should be at least 100 times smaller than the
input coupling capacitors to avoid stability problems
using the ML4621.
The output of the ML4621 amplifier is isolated from the
comparator and made available to the user. This allows
the user to add circuitry between the amplifier and the
comparator for wave shaping and other signal
conditioning.
COMPARATOR
Two types of comparators are employed in the output
section of these quantizers. The high speed ECL
comparator is used to provide the ECL level outputs, and
in turn drives the TTL comparator. The enable pin, CMP
ENABLE, is provided to control the ECL comparator.
When CMP ENABLE is low the comparators function
normally. When it is high it forces ECL+ high, ECL– low,
and TTL OUT high. The CMP ENABLE pin can be
controlled with TTL level signals when the quantizer is
powered by 5V and ground.
LINK MONITOR
This function is implemented by the minimum signal
discriminator and the threshold generator circuits. The
purpose of this function is to monitor the input signal and
provide a status signal indicating when the input falls
below a preset voltage level. This is done by peak
detecting the output of the amplifier section and
comparing this level with the voltage at VTHADJ.
470Ω
5V
4 3 2 1 28 27 26
CC
V
TTL LINK MON
ECL LINK MON
ML4621
CMP–NCECL–
NOM
I
ECL+
SET
I
C
PEAK
V
V
TH
GND
TTL OUT
V
CC
GND TTL
NC
REF
ADJ
TTL
25
24
23
22
21
20
19
0.001µF
0.5µF
18pF
18pF
0.1µF
NC
5
VIN–
6
VIN+
7
NC
8
VDC
9
CF2
10
CF1
11
V
–
OUT
CMP ENABLE
+
OUT
V
CMP+
12 13 14 15 16 17 18
Figure 1. ML4621 Configured for 20MHz Bandwidth with TTL Output
5V
0.1µF
6
FUNCTIONAL DESCRIPTION (Continued)
V
+
OUT
V
OS
–
V
OUT
ML4621
V
REF
R
1
VTHADJ
R
2
REF
THRESHOLD
GENERATOR
Figure 2.
The equation which determines the droop rate of the peak
detector is:
dV
ISET
=
dtIC
In this equation C is the peak capacitor at C
PEAK
(3)
. On the
ML4621 the droop rate of the peak detector can be
adjusted two ways:
1) By adjusting the value of the peak capacitor at C
PEAK
2) By adjusting the charge current into the peak capacitor
at I
.
SET
The charge current, I
connecting a resistor, R
, can be controlled externally by
ISET
, between I
EXT
and VCC. I
SET
ISET
will then be:
V
–.07
I
ISET
CC
=
R
+
1700
EXT
(4)
For convenience an on-chip current source of 125µA is
available by connecting I
NOM
to I
SET
.
Figure 3.
Since the ML4621 has a relatively low input impedance
of 6.8kΩ and is offset by one diode drop, the equation
which accounts for the load and offset is:
VADJ
TH
6800 07
bgbg
ch
21
=
6800
REF
RR RR
¥+ +¥
bg
12 12
.
(6)
RVR
¥¥+¥
THRESHOLD ADJUSTMENT EXAMPLE
To make the link monitor trigger when the received
.
optical power goes below 1µW (-30dBm), you first need to
calculate the resultant voltage at VIN+ and VIN–. If a
Hewlett-Packard HFBR-24X6 fiber-optic receiver with a
responsive level of 8mV/µW is used, the peak-to-peak
voltage would be:
8
1
mV
¥=
W
µ
W
8µ
mV
-
PP
(7)
Then the link monitor should trigger at some point slightly
lower than 4mV peak. Setting VTH in Equation 5 to 3mV
and solving for VTHADJ yields:
VTHADJ = (600 × 0.003) + 0.7 = 2.5V (8)
The threshold generator level-shifts the reference voltage
at VTHADJ through a circuit which has a temperature
coefficient matching that of the limiting amplifier. The
relationship between VTHADJ and VTH (the minimum
peak voltage at the input which will trigger the link
monitor) is:
VADJ V
The on-chip reference voltage, V
=¥+600 07
TH TH
bg
. (5)
, can be tied directly
REF
to VTHADJ to set the threshold level. This will set the
minimum input signal on the ML4621 at about 3mV
(peak). A lower threshold level can be set by dividing
down V
with a resistor string, as in Figure 3.
REF
This is a convenient value since the reference voltage
supplied by the quantizer, V
, is 2.5V.
REF
The link monitor has about 0.4mV (peak) hysteresis
built-in. More hysteresis can be induced by connecting a
resistor between TTL LINK MON and VTHADJ creating a
positive feedback loop.
Refer to Micro Linear’s Application Note 6 for more
detail.
7
ML4621
PHYSICAL DIMENSIONS inches (millimeters)
Package: P24N
24-Pin Narrow PDIP
1.240 - 1.260
(31.49 - 32.01)
24
0.070 MIN
(1.77 MIN)
(4 PLACES)
0.170 MAX
(4.32 MAX)
0.125 MIN
(3.18 MIN)
0.042 - 0.048
(1.07 - 1.22)
PIN 1 ID
1
8
0.485 - 0.495
(12.32 - 12.57)
0.450 - 0.456
(11.43 - 11.58)
1
PIN 1 ID
0.050 - 0.065
(1.27 - 1.65)
0.016 - 0.022
(0.40 - 0.56)
0.450 - 0.456
22
(11.43 - 11.58)
0.100 BSC
(2.54 BSC)
SEATING PLANE
Package: Q28
28-Pin PLCC
0.485 - 0.495
(12.32 - 12.57)
0.240 - 0.270
(6.09 - 6.86)
0.015 MIN
(0.38 MIN)
0.042 - 0.056
(1.07 - 1.42)
0.295 - 0.325
(7.49 - 8.26)
0º - 15º
0.025 - 0.045
(0.63 - 1.14)
(RADIUS)
0.300 BSC
(7.62 BSC)
0.390 - 0.430
(9.90 - 10.92)
0.008 - 0.012
(0.20 - 0.31)
0.050 BSC
(1.27 BSC)
0.026 - 0.032
(0.66 - 0.81)
0.013 - 0.021
(0.33 - 0.53)
15
SEATING PLANE
0.165 - 0.180
(4.06 - 4.57)
0.148 - 0.156
(3.76 - 3.96)
0.009 - 0.011
(0.23 - 0.28)
0.099 - 0.110
(2.51 - 2.79)
ORDERING INFORMATION
PART NUMBER TEMPERATURE RANGE PACKAGE
ML4621CP 0°C to 70°C 24 Pin Narrow PDIP (P24N)
ML4621CQ 0°C to 70°C 28 Pin PLCC (Q28)
© Micro Linear 1998. is a registered trademark of Micro Linear Corporation. All other trademarks are the property of their respective owners.
Products described herein may be covered by one or more of the following U.S. patents: 4,897,611; 4,964,026; 5,027,116; 5,281,862; 5,283,483; 5,418,502;
5,508,570; 5,510,727; 5,523,940; 5,546,017; 5,559,470; 5,565,761; 5,592,128; 5,594,376; 5,652,479; 5,661,427; 5,663,874; 5,672,959; 5,689,167; 5,714,897;
5,717,798. Japan: 2,598,946; 2,619,299; 2,704,176. Other patents are pending.
Micro Linear reserves the right to make changes to any product herein to improve reliability, function or design. Micro Linear does not assume any liability
arising out of the application or use of any product described herein, neither does it convey any license under its patent right nor the rights of others. The circuits
contained in this data sheet are offered as possible applications only. Micro Linear makes no warranties or representations as to whether the illustrated circuits
infringe any intellectual property rights of others, and will accept no responsibility or liability for use of any application herein. The customer is urged to consult
with appropriate legal counsel before deciding on a particular application.
8
2092 Concourse Drive
San Jose, CA 95131
T el: (408) 433-5200
Fax: (408) 432-0295
www .microlinear .com
2/27/98 Printed in U.S.A.
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