The ML2281 family are 8-bit successive approximation
A/D converters with serial I/O and configurable input
multiplexers with up to 8 input channels.
All errors of the sample-and-hold, incorporated on the
ML2281 family are accounted for in the analog-to-digital
converters accuracy specification.
The voltage reference can be externally set to any value
between GND and VCC, thus allowing a full conversion
over a relatively small voltage span if desired.
The ML2281 family is an enhanced double polysilicon
CMOS pin compatible second source for the ADC0831,
ADC0832, ADC0834, and ADC0838 A/D converters. The
ML2281 series enhancements are faster conversion time,
true sample-and-hold function, superior power supply
rejection, improved AC common mode rejection, faster
digital timing, and lower power dissipation. All parameters
are guaranteed over temperature with a power supply
voltage of 5V ±10%.
BLOCK DIAGRAM
ML2281
FEATURES
■ Conversion time: 6µs
■ Total unadjusted error: ±1/2LSB or ±1LSB
■ Sample-and-hold: 375ns acquisition
■ 2, 4 or 8-input multiplexer options
■ 0 to 5V analog input range with single 5V
power supply
■ Operates ratiometrically or with up to 5V
voltage reference
■ No zero or full-scale adjust required
■ ML2281 capable of digitizing a 5V, 40kHz sine wave
■ Low power: 12.5mW MAX
■ Superior pin compatible replacement for ADC0831,
ADC0832, ADC0834, and ADC0838
■ Analog input protection: 25mA (min) per input
■ Now in 8-Pin SOIC Package (ML2281, ML2282)
(* Indicates Part is Obsolete)
(# Indicates Part is End Of Life as Of July 1, 2000)
ML2288
ML2284
ML2284
(8-Channel SE or 4-Channel Diff Multiplexer)
(4-Channel SE or 2-Channel Diff Multiplexer)
(2-Channel SE or 1-Channel Diff Multiplexer)
A/D WITH SAMPLE & HOLD FUNCTION
V
IN+
V
IN–
8pF
8pF
+
+
Σ
COMP
–
–
CONTROL
AND
TIMING
OUTPUT
SHIFT-REGISTER
SUCCESSIVE
APPROXIMATION
REGISTER
D/A
CONVERTER
V
CC
GND
CLK
V
CS
DO
REF
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COMMON
4-BIT
MULTIPLEXER
(ML2288 SHOWN)
AGND
INPUT
SHIFT-REGISTER
CONTROL
AND
TIMING
OUTPUT
SHIFT-REGISTER
A/D
CONVERTER
WITH
SAMPLE & HOLD
FUNCTION
V
REF
V
CC
DI
SARS
CLK
CS
DO
SE
DGND
SHUNT
REGULATOR
V+
1
ML2281, ML2282, ML2284, ML2288
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
COM
DGND
V
CC
V+
CS
DI
CLK
SARS
DO
SE
V
REF
AGND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TOP VIEW
PIN CONFIGURATION
ML2281
Single Differential Input
8-Pin DIP
CS
V
IN+
V
IN–
GND
1
2
3
4
TOP VIEW
8
7
6
5
ML2281
8-Pin SOIC
V
IN+
V
IN–
GND
CS
1
2
3
4
TOP VIEW
8
7
6
5
ML2284
14-Pin SOIC
V
CLK
DO
V
CC
REF
V
CLK
DO
V
CC
REF
2-Channel MUX
CS
CH0
CH1
GND
CS
CH0
CH1
GND
4-Channel MUX
ML2282
8-Pin DIP
1
2
3
4
TOP VIEW
ML2282
8-Pin SOIC
1
2
3
4
TOP VIEW
ML2284
14-Pin DIP
V
8
CLK
7
DO
6
DI
5
8
7
6
5
CC (VREF
VCC (V
CLK
DO
DI
REF
)
)
2
V+
CS
CH0
CH1
CH2
CH3
DGND
1
2
3
4
5
6
7
TOP VIEW
14
13
12
11
10
V
CC
DI
CLK
SARS
DO
V
9
8
REF
AGND
V+
CS
CH0
CH1
CH2
CH3
DGND
1
2
3
4
5
6
7
14
13
12
11
10
V
CC
DI
CLK
SARS
DO
V
9
REF
AGND
8
TOP VIEW
ML2288
8-Channel MUX
20-Pin PCC
ML2288
8-Channel MUX
20-Pin DIP
CH2
CH1
CH0
VCCV+
CH3
CH4
CH5
CH6
CH7
3212019
4
5
6
7
8
910111213
COM
TOP VIEW
DGND
AGND
V
REF
18
CS
17
DI
16
CLK
15
SARS
14
DO
SE
PIN DESCRIPTION
ML2281, ML2282, ML2284, ML2288
NAMEFUNCTION
V
CC
DGNDDigital ground. 0 volts. All digital inputs and
AGNDAnalog ground. The negative reference voltage
CH0-7,Analog inputs. Digitally selected to be single
VIN+, VIN– ended (VIN) or; VIN+ or VIN– of a differential
COMCommon reference point for analog inputs.
V
REF
SEShift enable. Input controls whether LSB first
V+Input to the Shunt Regulator.
Positive supply. 5V ± 10%
outputs are referenced to this point.
for A/D converter.
input. Analog range = GND - VIN - VCC.
A/D conversion is performed on voltage
difference between analog input and this
common reference point if single-end
conversion is specified.
Reference. The positive reference voltage for
A/D converter.
bit stream is shifted out on serial output DO.
If SE = 1, MSB first is shifted out only. If SE = 0,
an MSB first bit stream is shifted out, then a
second bit stream with LSB first is shifted out
after end of conversion.
NAMEFUNCTION
DOData out. Digital output which contains result
of A/D conversion. The serial data is clocked
out on falling edges of CLK.
SARSSuccessive approximation register status.
Digital output which indicates that a
conversion is in progress. When SARS goes
to 1, the sampling window is closed and
conversion begins. When SARS goes to 0,
conversion is completed. When CS = 1, SARS
is in high impedance state.
CLKClock. Digital input which clocks data in on
DI on rising edges and out on DO on falling
edges. Also used to generate clocks for A/D
conversion.
DIData input. Digital input which contains serial
data to program the MUX and channel
assignments.
CSChip select. Selects the chip for multiplexer
and channel assignment and A/D conversion.
When CS = 1, all digital outputs are in high
impedance state. When CS = 0, normal A./D
conversion takes place.
3
ML2281, ML2282, ML2284, ML2288
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond which
the device could be permanently damaged. Absolute
maximum ratings are stress ratings only and functional
device operation is not implied.
Current into V+ ...................................................... 15mA
,Rising Edge of CS to DataCL = 10pF, RL = 10k (see high impedance4090ns
1H
t
0H
Output and SARS Hi-Ztest circuits) (Note 5)
CL = 100pF, RL = 2k (Note 4)80160ns
C
IN
C
OUT
Note 1: When the input voltage (VIN) at any pin exceeds the power supply rails (VIN < GND or VIN > VCC) the absolute value of current at that pin should be limited to 25mA
Note 2: 0°C to 70°C and –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by
Note 3: Typicals are parametric norm at 25°C.
Note 4: Parameter guaranteed and 100% production tested.
Note 5: Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
Note 6: Total unadjusted error includes offset, full-scale, linearity, multiplexer and sample-and-hold errors.
Note 7: Cannot be tested for ML2282.
Note 8: For V
Note 9: Leakage current is measured with the clock not switching.
Note 10: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits, the
Note 11: Because of multiplexer addressing, test conditions for the ML2282 would be V
Note 12: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to allow for
Capacitance of Logic Input5pF
Capacitance of Logic Outputs5pF
or less.
correlation with worst-case test conditions.
– ³ VIN+ the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for
IN
analog input voltages one diode drop below ground or one diode drop greater than the V
analog inputs (5V) can cause this input diode to conduct—especially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows
50mV forward bias of either diode. This means that as long as the analog V
correct. To achieve an absolute 0V to 5V input voltage range will therefore require a minimum supply voltage of 4.950V
tolerance and loading.
minimum time the clock is high or the minimum time the clock is low must be at least 300ns. The maximum time the clock can be high or low is 60µs.
(f
comparator response time.
» 95kHz); ML2288 VIN = 30kHz, 5V sine (f
SAMPLING
SAMPLING
» 89kHz).
or V
IN
= 34kHz, 5V sine (f
IN
supply. Be careful, during testing at low VCC levels (4.5V), as high level
CC
does not exceed the supply voltage by more than 50mV, the output code will be
REF
» 102kHz); ML2284 VIN = 32kHz, 5V sine
SAMPLING
over temperature variations, initial
DC
6
ML2281, ML2282, ML2284, ML2288
DATA
OUTPUT
DATA
OUTPUT
t
1H
V
CC
CS
R
C
L
L
DO AND
SARS OUTPUTS
t
0H
V
CC
R
L
C
L
DO AND
SARS OUTPUTS
CS
GND
V
OH
GND
V
GND
V
V
t
1H
t
r
90%
50%
10%
t
1H
90%
t
0H
t
50%
10%
t
r
90%
0H
10%
CC
CC
OL
Figure 1. High Impedance Test Circuits and Waveforms
CLK
CS
DATA
IN (DI)
Data Input Timing
t
SET-UP
t
HOLD
CLK
CS
t
SET-UP
t
HOLD
ML2281 Start Conversion Timing
t
SET-UP
START CONVERSION
CLK
DATA
OUT (DO)
Data Output Timing
t
PD0, tPD1
SE
t
SET-UP
t
PD0, tPD1
DO
BIT 7
(MSB)
Figure 2. Timing Diagrams
BIT 6
7
ML2281, ML2282, ML2284, ML2288
ML2281 Timing
1
234567891011
CLOCK (CLK)
t
SET-UP
CHIP SELECT (CS)
t
C
DATA OUT (DO)
SAMPLE & HOLD
ACQUISITION (t
1234567891011121314151617181920
CLOCK (CLK)
ACQ
HI-Z
)
76 543210
(MSB)
*LSB FIRST OUTPUT NOT AVAILABLE ON ML2281
ML2282 Timing
(LSB)
*
HI-Z
CHIP SELECT (CS)
DATA IN (DI)
DATA OUT (DO)
ACQUISITION (t
CLOCK (CLK)
CHIP SELECT (CS)
DATA IN (DI)
SAR STATUS (SARS)
ADDRESS MUX
START
BIT
SGL/DIF
HI-ZHI-Z
SAMPLE & HOLD
ACQ
t
SET-UP
)
ODD/
SIGN
DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION CYCLE)
7654 321123456
(MSB)
OUTPUT DATA
0
(LSB)
LSB FIRST DATAMSB FIRST DATA
7
(MSB)
ML2284 Timing
1234567891011121314151617181920
t
SET-UP
ADDRESS MUX
START
ODD/SIGN
BIT
DON’T CARE (DI DISABLED UNTIL NEXT CONVERSION CYCLE)
SGL/DIF SELECT
BIT 1
HI-ZHI-Z
A/D CONVERSION IN PROCESS
OUTPUT DATA
LSB FIRST DATAMSB FIRST DATA
DATA OUT (DO)
8
HI-ZHI-Z
SAMPLE & HOLD
ACQUISITION (t
ACQ
765432012345
)
(MSB)
1
(LSB)
67
(MSB)
Figure 2. Timing Diagrams (Continued)
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