Microlinear ML2258 Technical data

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May 1997

ML2258*

µP Compatible 8-Bit A/D Converter

with 8-Channel Multiplexer

GENERAL DESCRIPTION

The ML2258 combines an 8-bit A/D converter, 8-channel
analog multiplexer, and a microprocessor compatible 8­bit parallel interface and control logic in a single
monolithic device.

Easy interface to microprocessors is provided by the
latched and decoded multiplexer address inputs and
latched three-state outputs.

The device is suitable for a wide range of applications
from process and machine control to consumer,
automotive, and telecommunication applications.

The ML2258 is an enhanced, pin-compatible, second
source for the industry standard ADC0808/ADC0809. The
ML2258 enhancements are faster conversion time, true
sample and hold function, superior power supply
rejection, wider reference range, and a double buffered
data bus as well as faster digital timing. All parameters
are guaranteed over temperature with a power supply
voltage of 5V ±10%.

BLOCK DIAGRAM

FEATURES

■ Conversion time 6.6µs

■ Total unadjusted error ±1/2LSB or ±1LSB

■ No missing codes

■ Sample and hold 390ns acquisition

■ Capable of digitizing a 5V, 50kHz sine wave

■ 8-input multiplexer

■ 0V to 5V analog input range with single 5V

power supply

■ Operates ratiometrically or with up to 5V

voltage reference

■ No zero-or full-scale adjust required

■ Analog input protection 25mA per input min

■ Low power dissipation 3mA max

■ TTL and CMOS compatible digital inputs and outputs

■ Standard 28-pin DIP or surface mount PCC

■ Superior pin compatible replacement for ADC0808 and

ADC0809

* Some Packages Are End Of Life As Of August 1, 2000

START CLOCK

IN0

IN1

IN2

IN3

IN4

IN5

IN6

IN7

ADDR0
ADDR1

ADDR2

ADDRESS

LATCH ENABLE

8-CHANNEL

MULTIPLEXER

ADDRESS

LATCH

AND

DECODER

A/D WITH

SAMPLE HOLD

COMPARATOR

GNDV

CC

+V

CONTROL & TIMING

REF

S.A.R.

SWITCH TREE

CAPACITOR/

RESISTOR

ARRAY

–V

REF

THREE
STATE

OUTPUT

LATCH

BUFFER

OUTPUT

ENABLE

END OF CONVERSION
(INTERRUPT)

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

1

ML2258

PIN CONFIGURATION

ML2258

28-Pin DIP (P28)

IN3
IN4
IN5
IN6
IN7

START

EOC
DB3

OE
CLK
V

CC

+V

REF

GND

DB1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

TOP VIEW

IN2

28

IN1

27

IN0

26

ADDR0

25

ADDR1

24

ADDR2

23

ALE

22

DB7

21

DB6

20

DB5

19

DB4

18

DB0

17

–V

16

15

REF

DB2

PIN DESCRIPTION

PIN# NAME FUNCTION

1 IN3 Analog input 3.
2 IN4 Analog input 4.
3 IN5 Analog input 5.
4 IN6 Analog input 6.
5 IN7 Analog input 7.
6 START Start of conversion. Active high digital

input pulse initiates conversion.

7 EOC End of conversion. This output goes

low after a START pulse occurs, stays
low for the entire A/D conversion, and
goes high after conversion is
completed. Data on DB0–DB7 is valid
on rising edge of EOC and stays valid

until next EOC rising edge.
8 DB3 Data output 3.
9 OE Output enable input. When OE = 0,

DB0–DB7 are in high impedance

state; OE = 1, DB0–DB7 are active

outputs.

10 CLK Clock. Clock input provides timing for

A/D converter, S/H, and digital

interface.

11 V
12 +V

CC

REF

Positive supply. 5V ± 10%.

Positive reference voltage.

ML2258

28-Pin PCC (Q28)

IN6

IN5

IN4

IN3

IN2

IN1

IN0

IN7

START

EOC

DB3

OE

CLK

V

432128

5

6

7

8

9

10

11

CC

12 13 14 15 16

REF

+V

GND

DB1

TOP VIEW

DB2

REF

–V

27 26

17 18

DB0

25

24

23

22

21

20

19

DB4

ADDR0

ADDR1

ADDR2

ALE

DB7

DB6

DB5

PIN# NAME FUNCTION

13 GND Ground. 0V, all analog and digital

inputs or outputs are reference to this

point.
14 DB1 Data output 1.
15 DB2 Data output 2.
16 –V

REF

Negative reference voltage.
17 DB0 Data output 0.
18 DB4 Data output 4.
19 DB5 Data output 5.
20 DB6 Data output 6.
21 DB7 Data output 7.
22 ALE Address latch enable. Input to latch in

the digital address (ADDR2–0) on the

rising edge of the multiplexer.
23 ADDR0 Address input 0 to multiplexer. Digital

input for selecting analog input.
24 ADDR1 Address input 1 to multiplexer. Digital

input for selecting analog input.
25 ADDR2 Address input 2 to multiplexer. Digital

input for selecting analog input.
26 IN0 Analog input 0.
27 IN1 Analog input 1.
28 IN2 Analog input 2.

2

ML2258

ABSOLUTE MAXIMUM RATINGS

(Note 1)
Supply Voltage, V

.............................................................. 6.5V

CC

Voltage

Logic Inputs .................................. –0.3V to VCC +0.3V

Analog Inputs ............................... –0.3V to VCC +0.3V

Input Current per Pin (Note 2) .............................. ±25mA

Storage Temperature ..............................–65°C to +150°C

Package Dissipation

at TA = 25°C (Board Mount) .............................875mW

Lead Temperature (Soldering 10 sec.)

Dual-In-Line Package (Plastic)............................ 260°C

ELECTRICAL CHARACTERISTICS

Unless otherwise specified, TA = T

PARAMETER NOTES CONDITIONS MIN (NOTE 4) MAX MIN (NOTE 4) MAX UNITS

Converter and Multiplexer

Total Unadjusted Error 5, 7 V
+V

Voltage Range 6 –V

REF

–V

Voltage Range 6 GND – 0.1 +V

REF

Reference Input Resistance 5 14 20 28 14 20 28 k ý
Analog Input Range 5, 8 GND – 0.1 VCC + 0.1 GND – 0.1 VCC + 0.1 V
Power Supply Sensitivity 6 DC, VCC = 5V ± 10% ±1/32 ±1/4 ±1/32 ±1/4 LSB

, Off Channel Leakage 5, 9 On Channel = V

I

OFF

Current (Note 9) Off Channel = 0V

ION, On Channel Leakage 5, 9 On Channel = 0V –1 –1 µA
Current (Note 9) Off Channel = V

Digital and DC

V

, Logical “1” Input 5 2.0 2.0 V

IN(1)

Voltage

, Logical “0” Input 5 0.8 0.8 V

V

IN(0)

Voltage
I

, Logical “1” Input 5 VIN = V

IN(1)

Current
I

, Logical “0” Input 5 VIN = 0V –1 –1 µA

IN(0)

Current
V

, Logical “1” 5 I

OUT(1)

Output Voltage

, Logical “0” 5 I

V

OUT(0)

Output Voltage
I

, Three-State Output 5 V

OUT

Current V

I

, Supply Current 5 1.5 3 1.5 3 mA

CC

MIN

to T

REF

, VCC = +V

MAX

= V

CC

REF

REF

100mVp-p, 100kHz ±1/16 ±1/16 LSB

sine on VCC, V

IN

= 0

CC

–1 –1 µA

On Channel = 0V 1 1 µA

Off Channel = V

On Channel = V

CC

CC

CC

Off Channel = 0V

CC

= –2mA 4.0 4.0 V

OUT

= 2mA 0.4 0.4 V

OUT

= 0V –1 –1 µA

OUT

= V

OUT

CC

Molded Chip Carrier Package

Vapor Phase (60 sec.) ..................................... 215°C

Infrared (15 sec.) ............................................ 220°C

OPERATING CONDITIONS

Supply Voltage, V

Temperature Range (Note 3) ................. T

ML2258BIP, ML2258BIQ, ML2258CIP,

ML2258CIQ ........................................ –40°C to +85°C

= 5V ±10%, –V

ML2258B ML2258C

TYP TYP

REF

±1/2 ±1 LSB

VCC + 0.1 –V

.................................... 4.5V

CC

MIN

= GND and f

GND – 0.1 +V

REF

CLK

REF

= 10.24MHz

VCC + 0.1 V

11µA

11µA

11µA

to 6.3V

DC

- TA - T

REF

MAX

V

DC

3

ML2258

ELECTRICAL CHARACTERISTICS

(Continued)

TYP

SYMBOL PARAMETER NOTES CONDITIONS MIN (NOTE 4) MAX UNITS

AC and Dynamic Performance Characteristics (Note 10)

t

ACQ

f

CLK

t

C

Sample and Hold Acquisition 4 1/f

CLK

Clock Frequency 5 100 10240 kHz
Conversion Time 5 67 67 + 250ns 1/f

CLK

SNR Signal to Noise Ratio VIN = 51kHz, 5V sine. 47 dB

= 10.24MHz

f

CLK

(f

SAMPLING

> 150kHz). Noise is sum
of all nonfundamental components
up to 1/2 of f

SAMPLING

THD Total Harmonic Distortion VIN = 51kHz, 5V sine. –60 dB

= 10.24MHz

f

CLK

(f

SAMPLING

> 150kHz). THD is sum
of 2, 3, 4, 5 harmonics relative to
fundamental

IMD Intermodulation Distortion V

= fA + fB. fA = 49kHz, 2.5V sine. –60 dB

IN

fB = 47.8kHz, 2.5V sine,

= 10.24MHz

f

CLK

(f

SAMPLING

> 150kHz). IMD is (fA + fB),
(fA – fB), (2fA + fB), (2fA – fB), (fA + 2fB),
(fA – 2fB) relative to fundamental

FR Frequency Response V

= 0 to 50kHz. 5V sine relative 0.1 dB

IN

to 1kHz

t

DC

t

EOC

t

WS

t

SS

t

WALE

t

S

t

H

t

H1, H0

Clock Duty Cycle 6, 11 40 60 %
End of Conversion Delay 5 8 8 + 250ns 1/f
Start Pulse Width 5 50 ns
Start Pulse Setup Time 6, 12 Synchronous only 40 ns
Address Latch Enable Pulse Width 5 50 ns
Address Setup 5 0 ns
Address Hold 5 50 ns
Output Enable for DB0–DB7 6 Figure 1, CL = 50pF 100 ns

CLK

6 Figure 1, CL = 10pF 50 ns

t

1H, 0H

Output Disable for DB0–DB7 6 Figure 1, CL = 50pF 200 ns

6 Figure 1, CL = 10pF 100 ns

C

IN

C

OUT

Note 1: Absolute maximum ratings are limits beyond which the life of the integrated circuit may be impaired. All voltages unless otherwise specified are measured with

Note 2: When the input voltage (V
Note 3: –40°C to +85°C operating temperature range devices are 100% tested with temperature limits guaranteed by 100% testing, sampling, or by correlation with worst-

Note 4: Typicals are parametric norm at 25°C.
Note 5: Parameter guaranteed and 100% production tested.
Note 6: Parameter guaranteed. Parameters not 100% tested are not in outgoing quality level calculation.
Note 7: Total unadjusted error includes offset, full scale, linearity, multiplexer and sample and hold errors.
Note 8: For –V

Note 9: Leakage current is measured with the clock not switching.
Note 10: C
Note 11: A 40% to 60% clock duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limits,

Note 12: The conversion start setup time requirement only needs to be satisfied if a conversion must be synchronized to a given clock rising edge. If the setup time is not met,

Capacitance of Logic Input 5 pF
Capacitance of Logic Outputs 10 pF

respect to ground.

case test conditions.

• VIN (+) the digital output code will be 0000 0000. Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages

REF

one diode drop below ground or one diode drop greater than the V
cause this input diode to conduct — especially at elevated temperatures, and cause errors for analog inputs near full scale. The spec allow 100mV forward bias of either
diode. This means that as long as the analog V
absolute 0V

= 50pF, timing measured at 50% point.

L

the minimum time the clock is high or the minimum time the clock is low must be at least 40ns. The maximum time the clock can be high or low is 60µs.

start conversion will have an uncertainty of one clock pulse.

to 5VDC input voltage range will therefore require a minimum supply voltage of 4.900VDC over temperature variations, initial tolerance and loading.

DC

) at any pin exceeds the power supply rails (VIN < V– or VIN > V+) the absolute value of current at that pin should be limited to 25mA or less.

IN

supply. Be careful, during testing at low VCC levels (4.5V), as high level analog inputs (5V) can

CC

or V

does not exceed the supply voltage by more than 100mV, the output code will be correct. To achieve an

IN

REF

4