Micro crystal RV-1805-C3 Applications Manual

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RV-1805-C3

Application Manual

Date: November 2018

Revision N°: 3.1

Headquarters:

Micro Crystal AG Mühlestrasse 14 CH-2540 Grenchen Switzerland

Tel. Fax Internet Email

+41 32 655 82 82 +41 32 655 82 83

www.microcrystal.com sales@microcrystal.com

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TABLE OF CONTENTS

1. OVERVIEW ........................................................................................................................................................ 6

GENERAL DESCRIPTION ......................................................................................................................... 6 1.1.

APPLICATIONS ......................................................................................................................................... 7 1.2.

2. BLOCK DIAGRAM ............................................................................................................................................. 8

PINOUT ...................................................................................................................................................... 9 2.1.

PIN DESCRIPTION .................................................................................................................................. 10 2.2.

FUNCTIONAL DESCRIPTION ................................................................................................................. 11 2.3.

DEVICE PROTECTION DIAGRAM ......................................................................................................... 11 2.4.

3. REGISTER ORGANIZATION .......................................................................................................................... 12

REGISTER OVERVIEW ........................................................................................................................... 12 3.1.

TIME AND DATE REGISTERS ................................................................................................................ 14 3.2.

ALARM REGISTERS ............................................................................................................................... 17 3.3.

CONFIGURATION REGISTERS.............................................................................................................. 20 3.4.

CALIBRATION REGISTERS ................................................................................................................... 25 3.5.

SLEEP CONTROL REGISTER ................................................................................................................ 27

3.6.

TIMER REGISTERS ................................................................................................................................. 28 3.7.

OSCILLATOR REGISTERS..................................................................................................................... 31 3.8.

MISCELLANEOUS REGISTERS ............................................................................................................. 32 3.9.

ANALOG CONTROL REGISTERS ......................................................................................................... 33 3.10.

ID REGISTERS ........................................................................................................................................ 35 3.11.

RAM REGISTERS .................................................................................................................................... 37 3.12.

REGISTER RESET VALUES SUMMARY ............................................................................................... 39 3.13.

4. DETAILED FUNCTIONAL DESCRIPTION ..................................................................................................... 40

C INTERFACE ....................................................................................................................................... 41 4.2.

BUS NOT BUSY ................................................................................................................................ 41 4.2.1.

BIT TRANSFER ................................................................................................................................ 41 4.2.2.

START AND STOP CONDITIONS ................................................................................................... 41 4.2.3.

DATA VALID ..................................................................................................................................... 42 4.2.4.

SYSTEM CONFIGURATION ............................................................................................................ 42 4.2.5.

ACKNOWLEDGE .............................................................................................................................. 42 4.2.6.

ADDRESSING ................................................................................................................................... 43 4.2.7.

WRITE OPERATION ......................................................................................................................... 44 4.2.8.

READ OPERATION AT SPECIFIC ADDRESS ................................................................................ 44 4.2.9.

READ OPERATION .......................................................................................................................... 45 4.2.10.

XT OSCILLATOR ..................................................................................................................................... 45 4.3.

RC OSCILLATOR .................................................................................................................................... 45 4.4.

RTC COUNTER ACCESS ........................................................................................................................ 45 4.5.

HUNDREDTHS SYNCHRONIZATION .................................................................................................... 46 4.6.

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GENERATING HUNDREDTHS OF A SECOND ..................................................................................... 46 4.7.

WATCHDOG TIMER ................................................................................................................................ 46 4.8.

DIGITAL CALIBRATION .......................................................................................................................... 47 4.9.

XT OSCILLATOR DIGITAL CALIBRATION ...................................................................................... 47 4.9.1.

RC OSCILLATOR DIGITAL CALIBRATION ..................................................................................... 48 4.9.2.

AUTOCALIBRATION ............................................................................................................................... 50 4.10.

BASIC AUTOCALIBRATION OPERATION ............................................................................................ 50 4.11.

AUTOCALIBRATION OPERATION .................................................................................................. 50 4.11.1.

XT AUTOCALIBRATION MODE ....................................................................................................... 51 4.11.2.

RC AUTOCALIBRATION MODE ...................................................................................................... 51 4.11.3.

AUTOCALIBRATION FREQUENCY AND CONTROL ..................................................................... 51 4.11.4.

Cap_RC PIN ...................................................................................................................................... 52 4.11.5.

AUTOCALIBRATION FAILURE ........................................................................................................ 52 4.11.6.

FREQUENCY ACCURACY IN RC AUTOCALIBRATION MODE..................................................... 52 4.11.7.

A REAL WORLD EXAMPLE ............................................................................................................. 55 4.11.8.

RC AUTOCALIBRATION TIMING ACCURACY EXAMPLE ............................................................. 56 4.11.9.

POWER ANALYSIS ................................................................................................................... 57 4.11.10.

DISANDVANTAGES RELATIVE TO THE XT OSCILLATOR ................................................... 57 4.11.11.

XT OSCILLATOR FAILURE DETECTION .............................................................................................. 58 4.12.

INTERRUPTS ........................................................................................................................................... 58 4.13.

INTERRUPT SUMMARY .................................................................................................................. 58 4.13.1.

ALARM INTERRUPT AIRQ .............................................................................................................. 59 4.13.2.

COUNTDOWN TIMER INTERRUPT TIRQ....................................................................................... 59 4.13.3.

WATCHDOG TIMER INTERRUPT WIRQ ........................................................................................ 59 4.13.4.

BATTERY LOW INTERRUPT BLIRQ ............................................................................................... 59 4.13.5.

EXTERNAL INTERRUPT EIRQ ........................................................................................................ 59 4.13.6.

XT OSCILLATOR FAILURE INTERRUPT OFIRQ ........................................................................... 59 4.13.7.

AUTOCALIBRATION FAILURE INTERRUPT ACIRQ ...................................................................... 59 4.13.8.

SERVICING INTERRUPTS .............................................................................................................. 60 4.13.9.

POWER CONTROL AND SWITCHING ................................................................................................... 60 4.14.

AUTOMATIC SWITCHOVER SUMMARY ........................................................................................ 61 4.14.1.

BATTERY LOW FLAG AND INTERRUPT ........................................................................................ 61 4.14.2.

ANALOG COMPARATOR ................................................................................................................ 62 4.14.3.

PIN CONTROL AND LEAKAGE MANAGEMENT (POWER CONTROL) ........................................ 62 4.14.4.

POWER UP TIMING ......................................................................................................................... 63 4.14.5.

RESET SUMMARY .................................................................................................................................. 63 4.15.

POWER UP RESET .......................................................................................................................... 64 4.15.1.

WATCHDOG TIMER ......................................................................................................................... 64 4.15.2.

SLEEP ............................................................................................................................................... 65 4.15.3.

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SOFTWARE RESET ................................................................................................................................ 65 4.16.

SLEEP CONTROL STATE MACHINE .................................................................................................... 65 4.17.

RUN STATE ...................................................................................................................................... 66 4.17.1.

SWAIT STATE (SLEEP_WAIT STATE) ............................................................................................ 66 4.17.2.

SLEEP STATE .................................................................................................................................. 66 4.17.3.

SLP PROTECTION ........................................................................................................................... 68 4.17.4.

PSWS, PSWB AND LKP ................................................................................................................... 68 4.17.5.

PIN CONTROL AND LEAKAGE MANAGEMENT (SLEEP CONTROL) .......................................... 68 4.17.6.

SYSTEM POWER CONTROL APPLICATIONS ...................................................................................... 69 4.18.

POWER SWITCHED .................................................................................................................. 69 4.18.1.

POWER SWITCHED .................................................................................................................. 70 4.18.2.

RESET DRIVEN ................................................................................................................................ 70 4.18.3.

INTERRUPT DRIVEN ....................................................................................................................... 71 4.18.4.

TYPICAL SYSTEM IMPLEMENTATION ................................................................................................. 71 4.19.

ALARMS ............................................................................................................................................ 72 4.19.1.

COUNTDOWN TIMER ...................................................................................................................... 72 4.19.2.

WAKE BUTTON/SWITCH ................................................................................................................. 72 4.19.3.

EXTERNAL DEVICE INPUT ............................................................................................................. 72 4.19.4.

ANALOG INPUT ................................................................................................................................ 72 4.19.5.

BATTERY LOW DETECTION ........................................................................................................... 72 4.19.6.

ERRORS ........................................................................................................................................... 72 4.19.7.

SAVING PARAMETERS .......................................................................................................................... 73 4.20.

POWER SWITCH ELECTRICAL CHARACTERISTICS ......................................................................... 73 4.21.

AVOIDING UNEXPECTED LEAKAGE PATHS ...................................................................................... 73 4.22.

SYSTEM POWER ANALYSIS ................................................................................................................. 73 4.23.

USING AN EXTERNAL RTC WITH POWER MANAGEMENT......................................................... 73 4.23.1.

MANAGING MCU ACTIVE POWER ................................................................................................. 74 4.23.2.

LOWER COST MCUs ....................................................................................................................... 74 4.23.3.

HIGH PERFORMANCE PROCESSORS .......................................................................................... 74 4.23.4.

TRICKLE CHARGER ............................................................................................................................... 74 4.24.

5. DIGITAL ARCHITECTURE SUMMARY .......................................................................................................... 75

6. ELECTRICAL SPECIFICATIONS .................................................................................................................... 76

ABSOLUTE MAXIMUM RATINGS .......................................................................................................... 76 6.1.

POWER SUPPLY PARAMETERS .......................................................................................................... 76 6.2.

OPERATING PARAMETERS .................................................................................................................. 78 6.3.

OSCILLATOR PARAMETERS ................................................................................................................ 78 6.4.

XT FREQUENCY CHARACTERISTICS .................................................................................................. 80 6.5.

XT FREQUENCY VS. TEMPERATURE CHARACTERISTICS ........................................................ 80 6.5.1.

SUPPLY CURRENT .......................................................................................................................... 81 6.6.

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Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

BACKUP

SUPPLY CURRENT ................................................................................................................... 85 6.7.

BREF ELECTRICAL CHARACTERISTICS ............................................................................................. 88 6.8.

C AC ELECTRICAL CHARACTERISTICS ........................................................................................... 89 6.9.

POWER ON AC ELECTRICAL CHARACTERISTICS ............................................................................ 90 6.10.

AC ELECTRICAL CHARACTERISTICS ........................................................................................ 91 6.11.

7. APPLICATION INFORMATION ....................................................................................................................... 92

OPERATING RV-1805-C3 ....................................................................................................................... 92 7.1.

OPERATING RV-1805-C3 WITH BACKUP BATTERY/SUPERCAP ..................................................... 93 7.2.

8. RECOMMENDED REFLOW TEMPERATURE (LEADFREE SOLDERING) .................................................. 94

9. PACKAGE ........................................................................................................................................................ 95

DIMENSIONS AND SOLDERPADS LAYOUT ........................................................................................ 95 9.1.

MARKING AND PIN #1 INDEX ................................................................................................................ 95 9.2.

10. PACKING & SHIPPING INFORMATION ......................................................................................................... 96

11. HANDLING PRECAUTIONS FOR CRYSTALS OR MODULES WITH EMBEDDED CRYSTALS ................ 97

12. DOCUMENT REVISION HISTORY .................................................................................................................. 98

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RV-1805-C3

Extreme Low Power Real Time Clock / Calendar Module with I2C Interface

1. OVERVIEW

 Ultra-low supply current (all at 3V):

- 17 nA with RC oscillator

- 22 nA with RC oscillator and Autocalibration (ACP = 512 seconds)

- 60 nA with crystal oscillator

 Baseline timekeeping features:

- 32.768 kHz built-in “Tuning Fork” crystal oscillator with integrated load capacitor/resistor

- Counters for hundredths, seconds, minutes, hours, date, month, year, century, and weekday

- Alarm capability on all counters

- Programmable output clock generation (32.768 kHz to 1/year)

- Countdown timer with repeat function

- Automatic leap year calculation

 Advanced timekeeping features:

- Integrated power optimized RC oscillator

- Factory calibrated frequency offset compensation to ± 2 ppm

- Advanced RC calibration to ± 16 ppm

- Automatic calibration of RC oscillator to the compensated crystal oscillator

- Watchdog timer with hardware reset

- Up to 512 bytes of general purpose RAM

 Power management features:

- Integrated ~1 Ω power switch for off-chip components such as a host MCU

- System sleep manager for managing host processor wake/sleep states

- Reset output generator

- Supercapacitor trickle charger with programmable charging current

- Automatic switchover to V

- External interrupt monitor

- Programmable low battery detection threshold

- Programmable analog voltage comparator

 I2C (up to 400 kHz) serial interface  Operating voltage 1.5-3.6 V  Clock and RAM retention voltage 1.5-3.6 V  Operating temperature –40 to +85 °C  All inputs include Schmitt Triggers  Available in small and compact package size, RoHS-compliant and 100% leadfree: C3: 3.7 x 2.5 x 0.9 mm

GENERAL DESCRIPTION 1.1.

BACKUP

The RV-1805-C3 Real Time Clock with Power Management provides a groundbreaking combination of ultra-low power coupled with a highly sophisticated feature set. The power requirement is significantly lower than any other industry RTC (as low as 17 nA). The RV-1805-C3 includes an on-chip oscillator to provide a minimum power consumption, full RTC functions including battery backup and programmable counters and alarms for timer and watchdog functions, and either an I2C serial interface for communication with a host controller. An integrated power switch and a sophisticated system sleep manager with counter, timer, alarm, and interrupt capabilities allows the RV-1805-C3 to be used as a supervisory component in a host microcontroller based system.

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APPLICATIONS 1.2.

The RV-1805-C3 RTC module has been specially designed for ultimate low power consumption:

 60 nA with crystal oscillator (at 3V)  22 nA with RC oscillator and Autocalibration (ACP = 512 sec. at 3V)  17 nA with RC oscillator (at 3V)  Permits to operate this RTC module several hours at Backup Supply Voltage using low-cost MLCC

These unique features make this product perfectly suitable for many applications:

 Communication: Wireless Sensors and Tags, Handsets, Communications equipment  Metering: E-Meter / Heating Counter / Smart Meters / PV Converter  Outdoor: ATM & POS systems / Ticketing Systems  Medical: Glucose Meter / Health Monitoring Systems  Safety: Security & Camera Systems / Door Lock & Access Control  Consumer: Gambling Machines / TV & Set Top Boxes / White Goods  Automation: Data Logger / Home & Factory Automation / Industrial and Consumer Electronics

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Cap_RC Control

Trickle Charge

BREF Control

Batmode IO

Analog Status

Output Control

Ext. RAM Addr.

User RAM

20 26

0F 10

40 FF

Hundredths

Hours

Interrupt Mask

Control2

Control1

Status

Weekdays Alarm

Months Alarm

Hours Alarm

Minutes Alarm

Seconds Alarm

Hundredths Alarm

Weekdays

Years

Months

Minutes

Seconds

Timer Control

Sleep Control

Calibration XT

Square Wave SQW

Date Alarm

Oscillator Status

Oscillator Control

Timer Initial

Timer

Watchdog Timer

Date

System Control

logic

PSW

INPUT

OUTPUT

CONTROL

WDI

RST

Reset

Cap_RC

Xtal Osc

RC Osc

Divider

Calibration Engine

I2C-BUS Interface

SCL

SDA

Power

Control

BACKUP

Analog

Compare

CLK/INT

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

2. BLOCK DIAGRAM

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RV-1805-C3 Package:

#1 #5

#6#10

1805

#1 VDD

#10

RST

#2 Cap_RC

#9 WDI

#3 CLK/INT

#8 PSW

#4 SCL

#7 V

BACKUP

#5 SDA

#6 VSS

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

PINOUT 2.1.

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Symbol

Pin #

Description

VDD 1 Primary power connection. If a single power supply is used, it must be connected to VDD.

Cap_RC

Autocalibration filter connection. A 47 pF ceramic capacitor should be placed between this pin and VSS for improved Autocalibration mode timing accuracy.

INT/CLK

Clock Output / Interrupt. Primary interrupt output connection. It is an open drain output. An external pull-up resistor must be added to this pin. It should be connected to the host device and is used to indicate when

the RTC can be accessed via the I2C interface.

INT/CLK

may be configured to generate several signals

as a function of the CLKS field (see CONFIGURATION REGISTERS, 11h - Control2).

INT/CLK

is also

asserted low on a power up until the RV-1805-C3 has exited the reset state and is accessible via the I2C interface.

INT/CLK

can drive the static value of the CLKB bit.

INT/CLK

can drive the inverse of the combined interrupt signal IRQ (see INTERRUPTS).

INT/CLK

can drive the square wave signal SQW (see CONFIGURATION REGISTERS, 13h –

Square Wave SQW) if enabled by SQWE.

INT/CLK

can drive the inverse of the alarm interrupt signal AIRQ (see INTERRUPTS).

SCL 4 I2C Serial Clock Input. A pull-up resistor is required on this pin.

SDA 5 I2C Serial Data. A pull-up resistor is required on this pin.

VSS 6 Ground connection

BACKUP

Backup Supply Voltage. If a backup voltage is not present, V

BACKUP

is normally left floating or grounded, but it may also be used to provide the analog input to the internal comparator (see ANALOG COMPARATOR). Requires series resistor. The optimal total series impedance = V

BACKUP

power source ESR (Equivalent

Series Resistance) + external resistor value = 1.5 kΩ.

PSW

Power Switch Output. Secondary interrupt output connection. It is an open drain output. This pin can be left floating if not used. PSW may be configured to generate several signals as a function of the PSWS field (see CONFIGURATION REGISTERS, 11h - Control2). This pin will be configured as an ~1 Ω switch if the PSWC bit is set.

1. PSW can drive the static value of the PSWB bit.

2. PSW can drive the square wave signal SQW (see CONFIGURATION REGISTERS, 13h Square Wave SQW) if enabled by SQWE.

3. PSW can drive the inverse of the combined interrupt signal IRQ (see INTERRUPTS).

4. PSW can drive the inverse of the alarm interrupt signal AIRQ (see INTERRUPTS).

5. PSW can drive the inverse or the not inverse of the timer interrupt signal TIRQ.

6. PSW can function as the power switch output for controlling the power of external devices (see SLEEP CONTROL).

WDI

Watchdog Timer reset input connection. It may also be used to generate an External interrupt with polarity selected by the EIP bit if enabled by the EIE bit. The value of the WDI pin may be read in the WDIS register bit. This pin does not have an internal pull-up or pull-down resistor and so one must be added externally. It must not be left floating or the RTC may consume higher current. Instead, it must be connected directly to either VDD or VSS if not used.

RST

Reset Output. It is an open drain output. If this pin is used, an external pull-up resistor must be added to this pin. If the pin is not used, it can be left floating. The polarity is selected by the RSTP bit, which will initialize to 0 on power up to produce an active low output. See AUTOCALIBRATION FAILURE

INTERRUPT ACIRQ for details of the generation of

RST

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

PIN DESCRIPTION 2.2.

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INT/CLK

RST

ESD

Clamp

ESD

Clamp

ESD

Clamp

ESD

Clamp

BACKUP

SYS

(internal supply)

CLK/INT

RST

ESD

Clamp

All I/Os including: 3 4 SCL 5 SDA 8 PSW 9 WDI

Cap_RC

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

FUNCTIONAL DESCRIPTION 2.3.

The RV-1805-C3 is an extreme low power CMOS Real-Time Clock / Calendar module with built-in “Tuning-Fork” crystal with the nominal frequency of 32.768 kHz and an on-chip auto-calibrated RC-oscillator; no external components are required for the oscillator circuitry. The oscillator frequency on all devices is tested not to exceed a time deviation of ± 20 ppm (parts per million) at 25°C, which equates to about ± 52 seconds per month. This time accuracy can be further improved to ± 2 ppm (factory calibrated at 25°C) or better by individually measuring the frequency-deviation in the application at a given temperature and programming a correction value into the frequency compensation register.

Up to 512 bytes/registers of general purpose ultra-low leakage RAM enable the storage of key parameters when operating on backup power. The registers are accessed by selecting a register address and then performing read or write operations. Multiple reads or writes may be executed in a single access, with the address automatically incrementing after each byte.

DEVICE PROTECTION DIAGRAM 2.4.

The following Figure illustrates the internal ESD structure. The ESD Clamp devices are not simple diodes and are more complex structured. The VDD, V supply, which route a positive ESD discharge to VSS. Note that the V and V supply present), the internal V

supplies dependent upon the mode of operation. In V

BACKUP

supply is switched to V

SYS

VDD is present and regardless if a supply is present on V by additional internal circuitry. Note that V

onto the other digital I/O pads ( V

. In addition, there are simple diodes between V

SYS

shown in the diagram. These diodes take care of negative discharges to any of those pads. Internal ESD structure:

and Cap_RC pins have these ESD clamps as well as the internal V

BACKUP

does not directly touch a pin, but all of the positive charge injected

SYS

BACKUP

, SCL, SDA, PSW, WDI and

and VSS as well as between the digital I/O pads and VSS as

SYS

by additional internal circuitry. In VDD mode (when

or not), the internal V

internal supply is switched between the VDD

SYS

mode (when VDD goes away with a V

BACKUP

supply is switched to VDD

SYS

) gets routed to this ESD clamp on

SYS

BACKUP

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Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00h

Hundredths

10 8 4 2 1

01h

Seconds

GP0

10 8 4 2 1

02h

Minutes

GP1

10 8 4 2 1

03h

Hours (24 hour)

GP3

GP2

10 8 4 2 1

Hours (12 hour)

GP3

GP2

AM/PM

10 8 4 2 1

04h

Date

GP5

GP4

10 8 4 2 1

05h

Months

GP8

GP7

GP6

10 8 4 2 1

06h

Years

10 8 4 2 1

07h

Weekdays

GP13

GP12

GP11

GP10

GP9 4 2

08h

Hundredths Alarm

10 8 4 2 1

09h

Seconds Alarm

GP14

10 8 4 2 1

0Ah

Minutes Alarm

GP15

10 8 4 2 1

0Bh

Hours Alarm (24 hour)

GP17

GP16

10 8 4 2 1

Hours Alarm (12 hour)

GP17

GP16

AM/PM

10 8 4 2 1

0Ch

Date Alarm

GP19

GP18

10 8 4 2 1

0Dh

Months Alarm

GP22

GP21

GP20

10 8 4 2 1

0Eh

Weekdays Alarm

GP27

GP26

GP25

GP24

GP23 4 2

0Fh

Status

BAT

WDF

BLF

EVF

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

3. REGISTER ORGANIZATION

Registers are accessed by selecting a register address and then performing read or write operations. Multiple reads or writes may be executed in a single access, with the address automatically incrementing after each byte. The following tables Register Definitions (00h to 0Fh) and Register Definitions (10h to FFh) summarize the function of each register. In the table Register Definitions (00h to 0Fh), the GPx bits (where x is between 0 and 27) are 28 register bits which may be used as general purpose storage. These bits are not described in the sections below. All of the GPx bits are cleared when the RV-1805-C3 powers up, and they can therefore be used to allow software to determine if a true Power On Reset (POR) has occurred or hold other initialization data.

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Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

10h

Control1

STOP

12/24

PSWB

CLKB

RSTP

ARST

PSWC

WRTC

11h

Control2

RESERVED X PSWS

CLKS

12h

Interrupt Mask

CBE

BLIE

TIE

AIE

EIE

13h

Square Wave SQW

SQWE

RESERVED

SQWS

14h

Calibration XT

CMDX

OFFSETX

15h

Calibration RC Upper

CMDR

OFFSETRU[13:8]

16h

Calibration RC Lower

OFFSETRL[7:0]

17h

Sleep Control

SLP

SLRST

EIP X SLF

SLW

18h

Countdown Timer Control

TRPT

ARPT

TFS

19h

Countdown Timer

128

16 8 4 2 1

1Ah

Timer Initial Value

128

16 8 4 2 1

1Bh

Watchdog Timer

WDS

WDM

1Ch

Oscillator Control

OSEL

ACAL

BOS

FOS

IOPW

OFIE

ACIE

1Dh

Oscillator Status Register

XTCAL

LKP

OMODE

RESERVED

ACF

1Eh

RESERVED

1Fh

Configuration Key

CONFKEY

20h

Trickle Charge

TCS

DIODE

ROUT

21h

BREF Control

BREF

RESERVED

22h

RESERVED

23h

RESERVED

24h

RESERVED

25h

RESERVED

26h

Cap_RC Control

CAPRC

27h

IO Batmode Register

IOBM

RESERVED

28h

ID0 (Read only)

Part Number – MS Byte = 00011000 (18h)

29h

ID1 (Read only)

Part Number – LS Byte = 00000101 (05h)

2Ah

ID2 (Read only)

Revision – Major = 00010

Revision – Minor = 011

2Bh

ID3 (Read only)

Lot[7:0]

2Ch

ID4 (Read only)

Lot[9]

Unique ID[14:8]

2Dh

ID5 (Read only)

Unique ID[7:0]

2Eh

ID6 (Read only)

Lot[8]

Wafer

RESERVED

2Fh

Analog Stat. (Read Only)

BREFD

BMIN

RESERVED

VINIT

RESERVED

30h

Output Control Register

WDBM

WDDS

RSTSL X X

CLKSL

3Fh

Extension RAM Address

BPOL

WDIS

RESERVED

XADA

XADS

40h

7Fh

Standard RAM

RAM data (4 x 64 bytes = 256 bytes)

80h

FFh

Alternate RAM

RAM data (2 x 128 bytes = 256 bytes)

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

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Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00h

Hundredths

10 8 4 2 1

Reset 1 0 0 1 1 0 0 1

Bit

Symbol

Value

Description

7:0

Hundredths

00 to 99

Holds the count of hundredths of seconds, coded in BCD format.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

01h

Seconds

GP0

10 8 4 2 1

Reset 0 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

GP0

0 or 1

6:0

Seconds

00 to 59

Holds the count of seconds, coded in BCD format.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

02h

Minutes

GP1

10 8 4 2 1

Reset 0 0 0 0 0 0 0 0 Bit

Symbol

Value

Description

GP1

0 or 1

6:0

Minutes

00 to 59

Holds the count of minutes, coded in BCD format.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

TIME AND DATE REGISTERS 3.2.

00h - Hundredths

This register holds the count of hundredths of seconds, in two binary coded decimal (BCD) digits. Values will be from 00 to 99. Note that in order to divide from 32.768 kHz, the hundredths register will not be fully accurate at all times but will be correct every 500 ms. Maximum jitter of this register will be less than 1 ms. The Hundredths Counter is not valid if the RC Oscillator is selected.

01h - Seconds

This register holds the count of seconds, in two binary coded decimal (BCD) digits. Values will be from 00 to 59.

02h – Minutes

This register holds the count of minutes, in two binary coded decimal (BCD) digits. Values will be from 00 to 59.

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Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

03h

Hours

GP3

GP2

10 8 4 2 1

Reset 0 0 0 0 0 0 0 0 Bit

Symbol

Value

Description

GP3

0 or 1

GP2

0 or 1

5:0

Hours

00 to 23

Holds the count of hours, coded in BCD format.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

03h

Hours

GP3

GP2

AM/PM

10 8 4 2 1

Reset 0 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

GP3

0 or 1

GP2

0 or 1

AM/PM

AM hours.

PM hours.

4:0

Hours

1 to 12

Holds the count of hours, coded in BCD format.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

04h

Date

GP5

GP4

10 8 4 2 1

Reset 0 0 0 0 0 0 0 1

Bit

Symbol

Value

Description

GP5

0 or 1

GP4

0 or 1

5:0

Date

01 to 31

Holds the current day of the month, coded in BCD format.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

03h - Hours

This register holds the count of hours, in two binary coded decimal (BCD) digits. Values will be from 00 to 23 if the 12/24 bit (see CONFIGURATION REGISTERS, 10h - Control1) is clear. If the 12/24 bit is set, the AM/PM bit will be 0 for AM hours and 1 for PM hours, and hour values will range from 1 to 12.

Hours Register (24 Hour Mode)

Hours Register (12 Hour Mode)

04h – Date

This register holds the current day of the month, in two binary coded decimal (BCD) digits. Values will range from 01 to 31. Leap years are correctly handled from 1900 to 2199.

15/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

05h

Months

GP8

GP7

GP6

10 8 4 2 1

Reset 0 0 0 0 0 0 0 1

Bit

Symbol

Value

Description

GP8

0 or 1

GP7

0 or 1

GP6

0 or 1

4:0

Months

01 to 12

Holds the current month, coded in BCD format.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

06h

Years

10 8 4 2 1

Reset 0 0 0 0 0 0 0 0 Bit

Symbol

Value

Description

7:0

Years

00 to 99

Holds the current year, coded in BCD format. When the Years register rolls over from 99 to 00 the Century bit CB will be toggled (see CONFIGURATION REGISTERS, 0Fh - Status) if the CBE bit is a 1 (see CONFIGURATION REGISTERS,12h - Interrupt Mask).

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

07h

Weekdays

GP13

GP12

GP11

GP10

GP09 4 2

Reset 0 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

GP13

0 or 1

GP12

0 or 1

GP11

0 or 1

GP10

0 or 1

GP09

0 or 1

2:0

Weekdays

0 to 6

Holds the weekday counter value.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

05h - Months

This register holds the current month, in two binary coded decimal (BCD) digits. Values will range from 01 to 12.

06h - Years

This register holds the current year, in two binary coded decimal (BCD) digits. Values will range from 00 to 99.

07h - Weekdays

This register holds the current day of the week. Values will range from 0 to 6.

16/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

08h

Hundredths Alarm

10 8 4 2 1

Reset 0 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

7:0

Hundredths Alarm

FFh

Once per hundredth in XT mode. Once per second in RC mode. ARPT bit must be 7.

F0h to

F9h

Once per tenth in XT mode. Once per second in RC mode. ARPT bit must be 7.

00 to 99

Holds the alarm value for hundredths of seconds, coded in BCD format. If the ARPT bit is 0 to 6.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

09h

Seconds Alarm

GP14

10 8 4 2 1

Reset 0 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

GP14

0 or 1

6:0

Seconds Alarm

00 to 59

Holds the alarm value for seconds, coded in BCD format.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Ah

Minutes Alarm

GP15

10 8 4 2 1

Reset 0 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

GP15

0 or 1

6:0

Minutes Alarm

00 to 59

Holds the alarm value for minutes, coded in BCD format.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

ALARM REGISTERS 3.3.

08h - Hundredths Alarm

This register holds the alarm value for hundredths of seconds, in two binary coded decimal (BCD) digits. Values will range from 00 to 99. It holds the special values FFh and (F0h to F9h) when ARPT bit is 7. See TIMER REGISTERS, 18h - Countdown Timer Control.

09h - Seconds Alarm

This register holds the alarm value for seconds, in two binary coded decimal (BCD) digits. Values will range from 00 to 59.

0Ah - Minutes Alarm

This register holds the alarm value for minutes, in two binary coded decimal (BCD) digits. Values will range from 00 to 59.

17/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh

Hours Alarm

GP17

GP16

10 8 4 2 1

Reset 0 0 0 0 0 0 0 0 Bit

Symbol

Value

Description

GP17

0 or 1

GP16

0 or 1

5:0

Hours Alarm

00 to 23

Holds the alarm value for hours, coded in BCD format.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Bh

Hours Alarm

GP17

GP16

AM/PM

10 8 4 2 1

Reset 0 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

GP17

0 or 1

GP16

0 or 1

AM/PM

AM hours.

PM hours.

4:0

Hours Alarm

1 to 12

Holds the alarm value for hours, coded in BCD format.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Ch

Date Alarm

GP19

GP18

10 8 4 2 1

Reset 0 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

GP19

0 or 1

GP18

0 or 1

5:0

Date Alarm

01 to 31

Holds the alarm value for the date, coded in BCD format.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

0Bh - Hours Alarm

This register holds the alarm value for hours, in two binary coded decimal (BCD) digits. Values will range from 00 to 23 if the 12/24 bit (see CONFIGURATION REGISTERS, 10h - Control1) is clear. If the 12/24 bit is set, the AM/PM bit will be 0 for AM hours and 1 for PM hours, and hour values will be from 1 to 12.

Hours Alarm Register (24 Hour Mode)

Hours Alarm Register (12 Hour Mode)

0Ch - Date Alarm

This register holds the alarm value for the date, in two binary coded decimal (BCD) digits. Values will range from 01 to 31. Leap years are correctly handled from 1900 to 2199.

18/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Dh

Months Alarm

GP22

GP21

GP20

10 8 4 2 1

Reset 0 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

GP22

0 or 1

GP21

0 or 1

GP20

0 or 1

4:0

Months Alarm

01 to 12

Holds the alarm value for months, coded in BCD format.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Eh

Weekdays Alarm

GP27

GP26

GP25

GP24

GP23 4 2 1 Reset 0 0 0 0 0 0 0 0 Bit

Symbol

Value

Description

GP27

0 or 1

GP26

0 or 1

GP25

0 or 1

GP24

0 or 1

GP23

0 or 1

2:0

Weekdays Alarm

0 to 6

Holds the weekdays alarm value.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

0Dh - Months Alarm

This register holds the alarm value for months, in two binary coded decimal (BCD) digits. Values will range from 01 to 12.

0Eh - Weekdays Alarm

This register holds the alarm value for the day of the week. Values will range from 0 to 6.

19/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0Fh

Status

BAT

WDF

BLF

EVF

Reset 0 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

Century bit. This bit will be toggled when the Years register rolls over from 99 to 00 if

the CBE bit is a 1 (see 12h - Interrupt Mask register).

Assuming that the current Year is in the 20xx century the CB bit has to be set to 1.

Assumes the century is 19xx or 21xx. – Default value

Assumes it is 20xx for leap year calculations.

BAT

(read only) – VBACKUP Power state

System is in POR or VDD Power state.

System is in VBACKUP Power state.

WDF

Watchdog Timer Flag

No Watchdog Timer timeout trigger detected.

The Watchdog Timer is enabled and is triggered, and the WDS bit is 0 (see TIMER REGISTERS, 1Bh Watchdog Timer).

BLF

Battery Low Flag

No crossing of the reference voltage detected.

The battery voltage V

BACKUP

crossed the reference voltage selected by BREF (see ANALOG CONTROL REGISTERS, 21h - BREF Control) in the direction selected by BPOL (see RAM REGISTERS, 3Fh - Extension RAM Address).

Countdown Timer Flag

No zero detected.

Countdown Timer is enabled and reaches zero.

Alarm Flag

No match detected.

The Alarm function is enabled and all selected Alarm registers match their respective counters.

EVF

External Event Flag

No external trigger detected.

An external trigger is detected on the WDI pin. The EIE bit (see CONFIGURATION REGISTERS , 12h - Interrupt Mask) must be set in order for this interrupt to occur, but subsequently clearing EIE will not automatically clear this flag.

X 0 Unused flag. Always 0.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

CONFIGURATION REGISTERS 3.4.

0Fh – Status

This register holds a variety of status bits. The register may be written at any time to clear or set any status flag. If the ARST bit is set (see 10h - Control1), any read of the Status Register will clear interrupt flags in this register (WDF, BLF, TF, AF and EVF). The bits CB and BAT are not affected.

20/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

10h

Control1

STOP

12/24

PSWB

CLKB

RSTP

ARST

PSWC

WRTC

Reset 0 0 0 1 0 0 1 1

Bit

Symbol

Value

Description

STOP

The clocking system is not stopped.

Stops the clocking system. The XT and RC Oscillators are not stopped. In XT Mode the 32.768 kHz clock output will continue to run. In RC Mode, the RC clock output will continue to run. Other clock output selections will produce static outputs. This bit allows the clock system to be precisely started, by setting it to 1 and back to 0.

12/24

The Hours register operates in 24 hour mode.

The Hours register operates in 12 hour mode.

PSWB

0 or 1

A static bit value which may be driven on the PSW pin. The PSWB bit cannot be set to 1 if the LKP bit is 1 (see OSCILLATOR REGISTERS, 1Dh – Oscillator Status).

CLKB

0 or 1

A static bit value which may be driven on the

INT/CLK

pin. This bit also

defines the default value for the square wave signal SQW when SQWE is not asserted high. The default value of CLKB is 1 (high impedance).

RSTP

RST

Pin Polarity

The

RST

pin is asserted low.

The

RST

pin is asserted high.

ARST

Auto reset enable (Interrupt flags in Status register)

The interrupt flags must be explicitly cleared by writing the Status register.

A read of the Status register will cause the interrupt flags in the Status register to be cleared (WDF, BLF, TF, AF, EVF).

PSWC

PSW Pin Control (1Ω / normal)

The PSW pin is a normal open drain output.

The PSW pin is driven by an approximately 1 Ω pull-down which allows the RV-1805-C3 to switch power to other system devices through this pin.

WRTC

Write RTC

Prevents inadvertent software access to the Counters.

In order to write to any of the Counter registers (Hundredths, Seconds, Minutes, Hours, Date, Months, Years or Weekdays).

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

10h - Control1

This register holds some major control signals.

21/98

Micro Crystal

INT/CLK

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

11h

Control2

RESERVED X PSWS

CLKS

Reset 0 0 1 1 1 1 0 0

Set X to 0

Bit

Symbol

Value

Description

7:6

RESERVED

00 to 11

RESERVED

0 or 1

Unused, but has to be 0 to avoid extraneous leakage.

4:2

PSWS

PSW Pin Function Selection

000

Inverse of the combined interrupt signal IRQ if at least one interrupt is enabled, else static PSWB

001

SQW if SQWE = 1, else static PSWB

010

RESERVED

011

Inverse AIRQ if AIE is set, else static PSWB

100

TIRQ if TIE is set, else static PSWB

101

Inverse TIRQ if TIE is set, else static PSWB

110

SLEEP signal

111

Static PSWB

1:0

CLKS

INT/CLK

Pin Function Selection

Inverse of the combined interrupt signal IRQ if at least one interrupt is enabled, else static CLKB

SQW if SQWE = 1, else static CLKB

SQW if SQWE = 1, else inverse of the combined interrupt signal IRQ if at least one interrupt is enabled, else static CLKB

Inverse AIRQ if AIE is set, else static CLKB

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

11h - Control2

This register holds additional control and configuration signals for the flexible output pins Note that PSW and

are open drain outputs.

and PSW.

22/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

12h

Interrupt Mask

CBE

BLIE

TIE

AIE

EIE

Reset 1 1 1 0 0 0 0 0

Bit

Symbol

Value

Description

CBE

Century Bit Enable

The CB bit will never be automatically updated.

The CB bit will toggle when the Years register rolls over from 99 to 00.

6:5

Alarm Interrupt Mode.

This controls the duration of the Inverse AIRQ interrupt as shown below. The interrupt

output always goes high when the corresponding flag in the Status Register is cleared.

In order to minimize current drawn by the RV-1805-C3 this field should be kept at 3h.

Level (static) for both XT mode and RC mode.

1/8192 seconds for XT mode. 1/64 seconds for RC mode.

1/64 seconds for both XT mode and RC mode.

1/4 seconds for both XT mode and RC mode. – Default value

BLIE

Battery Low Interrupt Enable

Disables the battery low interrupt.

The battery low detection will generate an interrupt BLIRQ.

TIE

Timer Interrupt Enable

Disables the timer interrupt.

The Countdown Timer will generate a TIRQ interrupt signal and set the TF flag when the timer reaches 0.

AIE

Alarm Interrupt Enable

Disables the alarm interrupt.

A match of all the enabled alarm registers will generate an AIRQ interrupt signal.

EIE

External Interrupt Enable

Disables the external interrupt.

The WDI input pin will generate an external interrupt EIRQ when the edge specified by EIP occurs (see CONFIGURATION REGISTERS, 12h Interrupt Mask).

X 0 Unused, but has to be 0 to avoid extraneous leakage.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

12h - Interrupt Mask

This register holds the interrupt enable bits and other configuration information.

23/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

13h

Square Wave SQW

SQWE

RESERVED

SQWS

Reset 0 0 1 0 0 1 1 0

Bit

Symbol

Value

Description

SQWE

Square Wave enable (internal SQW)

The square wave signal SQW is held at the static value of CLKB.

The square wave signal SQW is enabled.

6:5

RESERVED

00 to 11

RESERVED

4:0

SQWS

Square Wave selection (internal SQW)

00000

11111

Selects the frequency of the square wave signal SQW, as shown in the following table. Note that some selections are not valid if the RC oscillator is selected. Some selections also produce short pulses rather than square waves, and are intended primarily for test usage.

SQWS

Square Wave Signal SQW Select

00000

1 century

(2)

00001

32.768 kHz

(1)

00010

8.192 kHz

(1)

00011

4.096 kHz

(1)

00100

2.048 kHz

(1)

00101

1.024 kHz

(1)

00110

512 Hz

(1)

– Default value

00111

256 Hz

(1)

01000

128 Hz

(3)

01001

64 Hz – highest calibrated frequency in RC mode

01010

32 Hz

01011

16 Hz

01100

8 Hz

01101

4 Hz

01110

2 Hz

01111

1 Hz

10000

½ Hz

10001

¼ Hz

10010

1/8 Hz

10011

1/16 Hz

10100

1/32 Hz

10101

1/60 Hz (1 minute)

10110

16.384 kHz

(1)

– highest calibrated frequency in XT mode

10111

100 Hz

(1)(2)

11000

1 hour

(2)

11001

1 day

(2)

11010

TIRQ

11011

Inverse TIRQ

11100

1 year

(2)

11101

1 Hz to Counters

(2)

11110

1/32 Hz from Autocalibration

(2)

11111

1/8 Hz from Autocalibration

(2)

(1)

Not applicable if the RC Oscillator is selected.

(2)

Pulses for Test Usage.

(3)

If the RC Oscillator is selected the frequency is typically 122 Hz.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

13h – Square Wave SQW

This register holds the control for the square wave signal SQW. Note that some frequency selections are not valid if the RC Oscillator is selected.

24/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

14h

Calibration XT

CMDX

OFFSETX

Reset

Preconfigured (Factory Calibrated)

Bit

Symbol

Value

Description

CMDX

XT calibration adjust mode

Normal Mode, each adjustment step is ± 2 ppm. The calibration period is 32 seconds.

Coarse Mode, each adjustment step is ± 4 ppm. The calibration period is 16 seconds.

6:0

OFFSETX

-64 to +63

The amount to adjust the effective time. This is a two's complement number with a range of -64 to +63 adjustment steps (Factory Calibrated).

OFFSETX (7 Bits)

Unsigned value

Two’s complement

Correction value in ppm

(*)

CMDX = 0

CMDX = 1

011’1111

120.163

240.326

011’1110

118.256

236.511

: : 000’0001 1 1

1.907

3.815

000’0000 0 0

0.000

111’1111

127

-1

-1.907

-3.815

111’1110

126

-2

-3.815

-7.629

: : 100’0001

-63

-120.163

-240.326

100’0000

-64

-122.070

-244.141

(*)

Calculated with 5 decimal places (1’000’000/219 = 1.90735 ppm)

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

CALIBRATION REGISTERS 3.5.

14h - Calibration XT

This register holds the control signals for the digital calibration function of the XT Oscillator. This register is initialized with a factory value which calibrates the XT Oscillator. The highest modified frequency is 16.384 kHz (see XT OSCILLATOR DIGITAL CALIBRATION).

25/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

15h

Calibration RC Upper

CMDR

OFFSETRU

Reset

Preconfigured

Preconfigured (Factory Calibrated)

Bit

Symbol

Value

Description

7:6

CMDR

00 to 11

The calibration adjust mode for the RC calibration adjustment. CMDR selects the highest possible calibration period used in the RC Calibration process as shown in the following table.

5:0

OFFSETRU

000000

111111

The upper 6 bits of the OFFSETR field, which is used to set the amount to adjust the effective time. OFFSETR is a two's complement number with a range of -213 to +213-1 adjustment steps (Factory Calibrated). See Table 1.

CMDR

Calibration Period

Minimal Adjustment Step

Maximum Adjustment

8’192 seconds

+/-1.91 ppm

+/-1.56%

4’096 seconds

+/-3.82 ppm

+/-3.13%

2’048 seconds

+/-7.63 ppm

+/-6.25%

1’024 seconds

+/-15.26 ppm

+/-12.5%

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

16h

Calibration RC Lower

OFFSETRL

Reset

Preconfigured (Factory Calibrated)

Bit

Symbol

Value

Description

7:0

OFFSETRL

00h to

FFh

The lower 8 bits of the OFFSETR field, which is used to set the amount to adjust the effective time. OFFSETR is a two's complement number with a range of -213 to +213-1 adjustment steps (Factory Calibrated). See Table 1.

OFFSETR (14 Bits)

Unsigned value

Two’s

complement

Correction value in ppm

(*)

CMDR = 00

CMDR = 01

CMDR = 10

CMDR = 11

01’1111’1111’1111

8191

15623

31246

62492

124985

01’1111’1111’1110

8190

15621

31242

62485

124970 : : : : : :

00‘0000‘0000’0001

1 1 1.907

3.815

7.629

15.259

00‘0000‘0000’0000

0 0 0.000

0.000

11’1111’1111’1111

16383

-1

-1.907

-3.815

-7.629

-15.259

11’1111’1111’1110

16382

-2

-3.815

-7.629

-15.259

-30.518

: : : : : : :

10‘0000‘0000’0001

8193

-8191

-15623

-31246

-62492

-124985

10‘0000‘0000’0000

8192

-8192

-15625

-31250

-62500

-125000

(*)

Calculated with 5 decimal places (1’000’000/2

= 1.90735 ppm)

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

15h - Calibration RC Upper

This register holds the control signals for the fine digital calibration function of the low power RC Oscillator. This register is initialized with a factory value which calibrates the RC Oscillator. The highest modified frequency is 64 Hz (see RC OSCILLATOR DIGITAL CALIBRATION).

16h - Calibration RC Lower

This register holds the lower 8 bits of the OFFSETR field for the digital calibration function of the low power RC Oscillator. This register is initialized with a factory value which calibrates the RC Oscillator. The highest modified frequency is 64 Hz (see RC OSCILLATOR DIGITAL CALIBRATION).

Table 1: Calibration RC

26/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

17h

Sleep Control

SLP

SLRST

EIP X SLF

SLW

Reset 0 0 0 0 0 0 0 0 Bit

Symbol

Value

Description

SLP

Sleep Request signal, see also SLEEP CONTROL STATE MACHINE

The Sleep Control State Machine is in RUN mode. If either STOP is 1 or no interrupt is enabled, SLP will remain at 0 even after an attempt to set it to 1.

When set to 1, the Sleep Control State Machine will transition to the SWAIT state as long as a valid interrupt is enabled. This bit will be cleared when the Sleep Control State Machine returns to the RUN state.

SLRST

Reset

RST

when in SLEEP mode

RST

does not indicate the SLEEP state.

Asserts

RST

low when the Sleep Control State Machine is in the SLEEP

state.

EIP

External Interrupt polarity

The external interrupt will trigger on a falling edge of the WDI pin.

The external interrupt will trigger on a rising edge of the WDI pin.

X 0 Unused, but has to be 0 to avoid extraneous leakage.

SLF

Sleep Flag

No previous SLEEP state occurred.

Flag is set when the RV-1805-C3 enters Sleep Mode. This allows software to determine if a SLEEP has occurred since the last time this bit was read.

2:0

SLW

Sleep Wait periods.

The number of ~8 ms waiting periods after SLP is set until the Sleep Control State

Machine goes into the SLEEP state. If SLW is not 0, the actual delay is guaranteed to

be between SLW and (SLW + 1) periods.

SLW

Wait time

000

The transition will occur with no delay.

001

8 to 16 ms

010

16 to 24 ms

011

24 to 32 ms

100

32 to 40 ms

101

40 to 48 ms

110

48 to 56 ms

111

56 to 64 ms

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

SLEEP CONTROL REGISTER 3.6.

17h - Sleep Control

This register controls the Sleep function of the Power Control system.

27/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

18h

Countdown Timer Control

TRPT

ARPT

TFS

Reset 0 0 1 0 0 0 1 1 Bit

Symbol

Value

Description

Timer Enable

The Countdown Timer retains the current value. The clock to the Timer is disabled for power minimization.

The Countdown Timer will count down.

Timer Mode.

Along with TRPT, this controls the Countdown Timer Interrupt function as shown in

Table 2.

A Pulse interrupt will cause the inverse of the combined interrupt signal IRQ signal to

be driven low for the time shown in Table 2 or until the flag is cleared.

A Level Interrupt will cause the inverse of the combined interrupt signal IRQ signal to

be driven low by a Countdown Timer interrupt until the associated flag is cleared.

Pulse (TRPT is 0 or 1)

Level if TRPT = 0. Pulse if TRPT = 1.

TRPT

Timer Repeat.

Along with TM, this controls the Countdown Timer Interrupt function as shown in Table

Single is selected. The Countdown Timer will halt when it reaches zero. If TM = 0, it allows the generation of periodic interrupts of virtually any frequency. If TM = 1, it is a Level.

Repeat is selected. The Countdown Timer reloads the value from the Timer Initial register upon reaching 0, and continues counting.

4:2

ARPT

Alarm Repeat

0 to 7

These bits enable the Alarm Interrupt repeat function together with the Hundredths Alarm register value, as shown in the following table.

1:0

TFS

Timer Frequency Selection

00 to

Select the clock frequency and interrupt pulse width of the Countdown Timer, as defined in Table 2. The RC Pulse is a short negative going 100400 µs pulse.

ARPT

08h - Hundredths Alarm

Repeat When

FFh

Once per hundredth (100 Hz)

(1)

F0h to F9h

Once per tenth (10 Hz)

(1)

00 to 99

Hundredths match (once per second)

(2)

Hundredths and seconds match (once per minute)

(2)

Hundredths, seconds and minutes match (once per hour)

(2)

Hundredths, seconds, minutes and hours match (once per day)

(2)

Hundredths, seconds, minutes, hours and weekday match (once per week)

(2)

Hundredths, seconds, minutes, hours and date match (once per month)

(2)

Hundredths, seconds, minutes, hours, date and month match (once per year)

(2)

Alarm Disabled

(1)

Once per second if RC Oscillator selected.

(2)

The Hundredths are not valid if the RC Oscillator is selected.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

TIMER REGISTERS 3.7.

18h - Countdown Timer Control

This register controls the Countdown Timer function. Note that the TFS = 00 frequency selection is slightly different depending on whether the 32.768 kHz XT Oscillator or the RC Oscillator is selected. In some RC Oscillator modes, the interrupt pulse output is specified as RC Pulse. In these cases the interrupt output will be a short negative going pulse which is typically between 100 and 400 µs. This allows control of external devices which require pulses shorter than the minimum 7.8 ms pulse created directly by the RC Oscillator.

28/98

Micro Crystal

TRPT

TFS

Interrupt signal

Countdown Timer Frequency

Interrupt Pulse Width

Pulse/

Level

Single/

Repeat

XT Oscillator

RC Oscillator

XT Oscillator

RC Oscillator

0 0 00

Pulse

Single

4096 Hz

Typ. 122 Hz

1/4096 s

Typ. 1/122 s

0 0 01

Pulse

Single

64 Hz

1/128 s

Typ. 1/122 s

0 0 10

Pulse

Single

1 Hz

1/64 s

0 0 11

Pulse

Single

1/60 Hz

1/64 s

1/64 s 0 1

Pulse

Repeat

4096 Hz

Typ. 122 Hz

1/4096 s

Typ. 1/122 s

0 1 01

Pulse

Repeat

64 Hz

1/128 s

Typ. 1/122 s

0 1 10

Pulse

Repeat

1 Hz

1/64 s

0 1 11

Pulse

Repeat

1/60 Hz

1/64 s

1/64 s 1 0

Level

Single

4096 Hz

Typ. 122 Hz

- - 1 0 01

Level

Single

64 Hz

1 0 10

Level

Single

1 Hz

1 Hz - - 1 0

Level

Single

1/60 Hz

1 1 00

Pulse

Repeat

4096 Hz

Typ. 122 Hz

1/4096 s

RC Pulse

1 1 01

Pulse

Repeat

64 Hz

1/4096 s

RC Pulse

1 1 10

Pulse

Repeat

1 Hz

1/4096 s

RC Pulse

1 1 11

Pulse

Repeat

1/60 Hz

1/4096 s

RC Pulse

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

19h

Countdown Timer

128

16 8 4 2 1

Reset 0 0 0 0 0 0 0 0 Bit

Symbol

Value

Description

7:0

Countdown Timer

0 to 255

The current value of the Countdown Timer in binary format.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1Ah

Timer Initial Value

128

16 8 4 2 1

Reset 0 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

7:0

Timer Initial Value

0 to 255

The value in binary format reloaded into the Countdown Timer when it reaches zero if the TRPT bit is a 1.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

Table 2: Countdown Timer Function Select

19h - Countdown Timer

This register holds the current value of the Countdown Timer. It may be loaded with the desired starting value when the Countdown Timer is stopped.

1Ah - Timer Initial Value

This register holds the value which will be reloaded into the Countdown Timer when it reaches zero if the TRPT bit is a 1. This allows for periodic timer interrupts (see calculation below).

Calculation of the period:

period = (Timer Initial Value + 1)

Countdown Timer Frequency

Example: For a period of 4 minutes (240 seconds) and with a Countdown Timer Frequency of 1 Hz (TFS = 10) a Timer Initial Value of 239 is needed:

period = (239 + 1)

= 240 seconds

1 Hz

29/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1Bh

Watchdog Timer

WDS

WDM

Reset 0 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

WDS

Watchdog Timer Steering

The Watchdog Timer will generate a WIRQ interrupt signal and sets the WDF flag to 1 when it times out.

The Watchdog Timer will generate a Reset

RST

when it times out.

RST

pin is asserted low within 1/16 second of the timer reaching zero and remains asserted low for 1/16 second. The WDF flag is not set.

6:2

WDM

Watchdog Timer cycle multiplier

Disables the Watchdog Timer function.

1 to 31

Watchdog Multiplier value. The number of clock cycles which must occur before the Watchdog Timer times out. See table below.

1:0

Watchdog Timer clock frequency

16 Hz

4 Hz

1 Hz

1/4 Hz

Clock Period

WDM

Timeout

62.5 ms

1 to 31

62.5 to 1937.5 ms

250 ms

1 to 31

250 to 7750 ms

1 second

1 to 31

1 to 31 seconds

4 seconds

1 to 31

4 to 124 seconds

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

1Bh - Watchdog Timer

This register controls the Watchdog Timer function.

30/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1Ch

Oscillator Control

OSEL

ACAL

BOS

FOS

IOPW

OFIE

ACIE

Reset 0 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

OSEL

Oscillator Selection

Request the XT Oscillator to generate a 32.768 kHz clock to the timer circuit. Note that if the XT Oscillator is not operating, the oscillator switch will not occur. The OMODE field (see OSCILLATOR REGISTERS,1Dh – Oscillator Status) indicates the actual oscillator which is selected.

Request the RC Oscillator to generate the clock for the timer circuits (nominal 128 Hz).

6:5

ACAL

Autocalibration Mode.

Controls the automatic calibration function (see AUTOCALIBRATION FREQUENCY

AND CONTROL).

No Autocalibration

RESERVED

Autocalibrate every 1024 seconds (~17minutes)

Autocalibrate every 512 seconds (~8.5 minutes)

BOS

Oscillator switch when VBACKUP

No automatic oscillator switching occurs.

The oscillator will automatically switch to the RC oscillator (Autocalibration Mode according to the ACAL field) when the system is powered from the battery (VBACKUP Power state).

FOS

Oscillator switch when XT oscillator failure

No automatic oscillator switching occurs.

The oscillator will automatically switch to the RC oscillator (Autocalibration Mode according to the ACAL field) when an XT oscillator failure is detected.

IOPW

I2C in function of the PSW pin configuration and setting

The I2C interface remains enabled independent of the PSW control bits PSWC and PSWS.

The I2C interface will be disabled when the PSW pin is configured as the low resistance power switch (PSWC = 1) and set to open (PSW pin = 1, high impedance). In order for the I2C interface to be disabled, the PSW pin must be configured for the sleep function by setting the PSWS field to a value of 6. This insures that a powered down I2C master (i.e., the host controller) does not corrupt the RV-1805-C3.

OFIE

XT Oscillator Failure Interrupt Enable

Disables the XT oscillator failure interrupt.

An XT Oscillator Failure will generate an OFIRQ interrupt signal.

ACIE

Autocalibration Failure Interrupt Enable

Disables the Autocalibration Failure Interrupt

An Autocalibration Failure will generate an ACIRQ interrupt signal.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

OSCILLATOR REGISTERS 3.8.

1Ch - Oscillator Control

This register controls the overall Oscillator function. It may only be written if the Configuration Key register value CONFKEY contains the value A1h. An Autocalibration cycle is initiated immediately whenever this register is written with a value in the ACAL field which is not zero.

31/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1Dh

Oscillator Status Register

XTCAL

LKP

OMODE

RESERVED

ACF

Reset 0 0 1 0 0 0 1 0

Bit

Symbol

Value

Description

7:6

XTCAL

Extended Crystal Calibration.

This field defines the compensation of a higher XT oscillator frequency, independent

of the normal Crystal Calibration function controlled by the Calibration XT Register.

The frequency generated by the Crystal Oscillator is slowed by 122 ppm times the

value in the XTCAL field. Normally, this field remains 00.

0 ppm

-122 ppm

-244 ppm

-366 ppm

LKP

Locking of the PSW pin

PSW pin is not locked.

Locks PSW pin. The PSWB bit (see CONFIGURATION REGISTERS, 10h – Control1) cannot be set to 1. This is typically used when PSW is configured as a power switch, and setting PSWB to a 1 would turn off the switch (high impedance).

OMODE

(read only) – Oscillator Mode.

If the STOP bit is set, the OMODE bit is invalid.

The XT Oscillator is selected to drive the internal clocks.

The RC Oscillator is selected to drive the internal clocks.

3:2

RESERVED

00 to 11

RESERVED

XT Oscillator Failure

No XT oscillator failure has occurred.

XT Oscillator Failure. This bit is set on a power on reset (POR), when both the system and battery voltages have dropped below acceptable levels. It is also set if an XT Oscillator Failure occurs, indicating that the crystal oscillator is running at less than 8 kHz. It can be cleared by writing a 0 to the bit.

ACF

Autocalibration Failure

No autocalibration failure has occurred.

Set when an Autocalibration Failure occurs, indicating that either the RC Oscillator frequency is too different from 128 Hz to be correctly calibrated or the XT Oscillator did not start.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

1Fh

Configuration Key

CONFKEY

Reset 0 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

7:0

CONFKEY

Configuration Key.

Written with specific values in order to access some registers and functions.

A1h

Writing a value of A1h enables write access to the Oscillator Control register.

3Ch

Writing a value of 3Ch does not update the CONFKEY value, but generates a Software Reset (see SOFTWARE RESET).

9Dh

Writing a value of 9Dh enables write access to the Trickle Charge Register (20h), the BREF Register (21h), the CAPRC Register (26h), the IO Batmode Register (27h) and the Output Control Register (30h).

00h

CONFKEY is reset to 00h on any register write.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

1Dh – Oscillator Status Register

This register holds several miscellaneous bits used to control and observe the oscillators.

MISCELLANEOUS REGISTERS 3.9.

1Fh - Configuration Key

This register contains the Configuration Key CONFKEY, which must be written with specific values in order to access some registers and functions. CONFKEY is reset to 00h on any register write.

32/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

20h

Trickle Charge

TCS

DIODE

ROUT

Reset 0 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

7:4

TCS

1010

Trickle Charge Select.

A value of 1010 enables the trickle charge function. All other values disable

the Trickle Charger.

3:2

DIODE

Diode for the Trickle Charger

Disables the Trickle Charger.

Inserts a schottky diode into the trickle charge circuit, with a voltage drop of

0.3V.

Inserts a standard diode into the trickle charge circuit, with a voltage drop of 0.6V.

Disables the Trickle Charger.

1:0

ROUT

Resistor for the Trickle Charger

Disables the Trickle Charger.

The series resistor of the trickle charge circuit is 3 kΩ

The series resistor of the trickle charge circuit is 6 kΩ

The series resistor of the trickle charge circuit is 11 kΩ

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

21h

BREF Control

BREF

RESERVED

Reset 1 1 1 1 0 0 0 0

Bit

Symbol

Value

Description

7:4

BREF

Voltage Reference

This selects the voltage reference which is compared to the battery voltage V

BACKUP

produce the BREFD signal (see ANALOG CONTROL REGISTERS, 2Fh – Analog

Status and BREF ELECTRICAL CHARACTERISTICS). The valid BREF values are

7h, Bh, Dh, and Fh. All other values are RESERVED.

BACKUP

Falling Voltage (TYP),

(BPOL = 0)

BACKUP

Rising Voltage (TYP),

(BPOL = 1)

0111

2.5V

3.0V

1011

2.1V

2.5V

1101

1.8V

2.2V

1111

1.4V – Default value

1.6V – Default value

3:0

RESERVED

0000 to

1111

RESERVED

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

ANALOG CONTROL REGISTERS 3.10.

20h - Trickle Charge

This register controls the Trickle Charger. The Configuration Key CONFKEY must be written with the value 9Dh in order to enable access to this register. See TRICKLE CHARGER.

21h - BREF Control

This register controls the reference voltages used for the Analog Comparator. CONFKEY must be written with the value 9Dh in order to enable access to this register.

33/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

26h

Cap_RC Control

CAPRC

Reset 0 0 0 0 0 0 0 0 Bit

Symbol

Value

Description

7:0

CAPRC

00h

Disables the Cap_RC pin.

A0h

Enables the Cap_RC pin.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

27h

IO Batmode Register

IOBM

RESERVED

Reset 1 0 0 0 0 0 0 0

Bit

Symbol

Value

Description

IOBM

I2C in VBACKUP Power state

The I2C interface is disabled in the VBACKUP Power state in order to prevent erroneous accesses to the RV-1805-C3 if the bus master loses power.

The RV-1805-C3 will not disable the I2C interface even if VDD goes away and V

BACKUP

is still present. This allows external access while the RV-1805-

C3 is powered by V

BACKUP

6:0

RESERVED

0000000

RESERVED - must write only 0000000.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

2Fh

Analog Status Register (Read Only)

BREFD

BMIN

RESERVED

VINIT

RESERVED

Reset

Bit

Symbol

Value

Description

BREFD

The V

BACKUP

input voltage is below the BREF threshold.

The V

BACKUP

input voltage is above the BREF threshold.

BMIN

The V

BACKUP

input voltage is below the minimum operating voltage (1.2 V).

The V

BACKUP

input voltage is above the minimum operating voltage (1.2 V).

5:2

RESERVED

0000 to

1111

RESERVED

VINIT

The VDD input voltage is below the minimum power up voltage (1.6 V).

The VDD input voltage is above the minimum power up voltage (1.6 V).

RESERVED

0 or 1

RESERVED

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

26h – Cap_RC Control

This register holds the enable code for the Autocalibration Filter Capacitor connected to the Cap_RC pin. Writing the value A0h to this register enables the Cap_RC pin. Writing the value 00h to this register disables the Cap_RC pin. No other value may be written to this register. The Configuration Key CONFKEY must be written with the value 9Dh prior to writing the CAPRC Register.

27h – IO Batmode Register

This register holds the IOBM bit which controls the enabling and disabling of the I2C interface when a Brownout Detection occurs. It may only be written if the Configuration Key CONFKEY contains the value 9Dh. All undefined bits must be written with 0.

2Fh – Analog Status Register (Read Only)

This register holds eight status bits which indicate the voltage levels of the VDD and V

power inputs.

BACKUP

34/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

30h

Output Control Register

WDBM

WDDS

RSTSL X X

CLKSL

Reset 0 0 0 0 0 0 0 0

Set X to 1

Bit

Symbol

Value

Description

WDBM

The WDI input is disabled when the RV-1805-C3 is powered from V

BACKUP

The WDI input is enabled when the RV-1805-C3 is powered from V

BACKUP

Unused, but has to be 0 to avoid extraneous leakage. Disables an internal input when the RV-1805-C3 is powered from V

BACKUP

WDDS

The WDI input is enabled when the RV-1805-C3 is in Sleep Mode.

The WDI input is disabled when the RV-1805-C3 is in Sleep Mode. If WDI is disabled, it will appear as a 1 to the internal logic.

Unused, but has be set to 1 to avoid extraneous leakage. Disables an internal input when the RV-1805-C3 is in Sleep Mode.

RSTSL

The

RST

output pin is completely disconnected when the RV-1805-C3 is

in Sleep Mode.

The

RST

output pin is enabled when the RV-1805-C3 is in Sleep Mode.

Unused, but has to be 0 to avoid extraneous leakage. If 0, an internal output is completely disconnected when the RV-1805-C3 is in Sleep Mode.

CLKSL

The

INT/CLK

output pin is completely disconnected when the RV-1805-

C3 is in Sleep Mode.

The

INT/CLK

output pin is enabled when the RV-1805-C3 is in Sleep

Mode.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

28h

ID0 - Part Number Upper Register (Read Only)

Part Number - Digit 3

Part Number - Digit 2

Reset 0 0 0 1 1 0 0 0

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

29h

ID1 - Part Number Lower Register (Read Only)

Part Number - Digit 1

Part Number - Digit 0

Reset 0 0 0 0 0 1 0 1

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

30h – Output Control Register

This register holds bits which control the behavior of the I2C pins under various power down conditions. The Configuration Key CONFKEY must be written with the value 9Dh in order to enable access to this register.

ID REGISTERS 3.11.

28h – ID0 - Part Number Upper Register (Read Only)

This register holds the upper eight bits of the part number in BCD format, which is always 18h for the RV-1805-C3.

29h – ID1 - Part Number Lower Register (Read Only)

This register holds the lower eight bits of the part number in BCD format, which is always 05h for the RV-1805-C3.

35/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

2Ah

ID2 - Part Revision (Read Only)

MAJOR

MINOR

Reset 0 0 0 1 0 0 1 1

Bit

Symbol

Value

Description

7:3

MAJOR

00010

This field holds the major revision of the RV-1805-C3.

2:0

MINOR

011

This field holds the minor revision of the RV-1805-C3.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

2Bh

ID3 – Lot Lower (Read Only)

Lot[7:0]

Reset

Preconfigured Lot Number

Bit

Symbol

Value

Description

7:0

Lot[7:0]

00h to

FFh

This field holds the lower 8 bits of the manufacturing lot number.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

2Ch

ID4 – ID Upper (Read Only)

Lot[9]

ID[14:8]

Reset

Preconfigured Value

Bit

Symbol

Value

Description

Lot[9]

0 or 1

This field holds bit 9 of the manufacturing lot number.

6:0

ID[14:8]

0000000

1111111

This field holds the upper 7 bits of the unique part ID.

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

2Dh

ID5 – Unique Lower (Read Only)

ID[7:0]

Reset

Preconfigured Value

Bit

Symbol

Value

Description

7:0

ID[7:0]

00h to

FFh

This field holds the lower 8 bits of the unique part ID.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

2Ah – ID2 - Part Revision (Read Only)

This register holds the Revision number of the part.

2Bh – ID3 – Lot Lower (Read Only)

This register holds the lower 8 bits of the manufacturing lot number.

2Ch – ID4 – Unique ID Upper (Read Only)

This register holds part of the manufacturing information of the part, including bit 9 of the manufacturing lot number and the upper 7 bits of the unique part identifier. The 15-bit ID field contains a unique value for each RV-1805-C3 part.

2Dh – ID5 – Unique ID Lower (Read Only)

This register holds the lower 8 bits of the unique part identifier. The 15-bit ID field contains a unique value for each RV-1805-C3 part.

36/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

2Eh

ID6 – Wafer (Read Only)

Lot[8]

Wafer

RESERVED

Reset

Preconfigured Value

Bit

Symbol

Value

Description

Lot[8]

0 or 1

This field holds bit 8 of the manufacturing lot number.

6:1

Wafer

00000

11111

This field holds the manufacturing wafer number.

1:0

RESERVED

00 to 11

RESERVED

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

3Fh

Extension RAM Address

BPOL

WDIS

RESERVED

XADA

XADS

Reset 0 0

Read Only

0 0 0

Bit

Symbol

Value

Description

Unused, but must be set to 0 to avoid extraneous leakage. If 0, an internal output is completely disconnected when the RV-1805-C3 is powered from V

BACKUP

BPOL

BLF Polarity

The Battery Low flag BLF is set when the V

BACKUP

voltage goes below the

BREF threshold.

The Battery Low flag BLF is set when the V

BACKUP

voltage goes above the

BREF threshold.

WDIS

(read only) – WDI status. Currently low level on the WDI pin.

(read only) – WDI status. Currently high level on the WDI pin.

X 0 (read only) – Unused

RESERVED

0 or 1

RESERVED

XADA

0 or 1

This bit supplies the upper bit for the Alternate RAM address space.

1:0

XADS

00 to 11

This field supplies the two upper bits for the Standard RAM address space.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

2Eh – ID6 – Wafer (Read Only)

RAM REGISTERS 3.12.

3Fh - Extension RAM Address

This register controls access to the Extension RAM, and includes some miscellaneous control bits.

37/98

Micro Crystal

XADS

Standard RAM address

Effective RAM

RAM data

Upper 2 bits

Lower 6 bits

Upper 2 & Lower 6

40h

7Fh

01000000 (64)

01111111 (127)

000000 (0)

111111 (63)

00000000 (0)

00111111 (63)

64 bytes

01000000 (64)

01111111 (127)

64 bytes

10000000 (128)

10111111 (191)

64 bytes

11000000 (192)

11111111 (255)

64 bytes

Total RAM data

00000000 (0)

11111111 (255)

256 bytes

XADA

Alternate RAM address

Effective RAM

RAM data

Upper bit

Lower 7 bits

Upper 1 & Lower 7

80h

FFh

10000000 (128)

11111111 (255)

0000000 (0)

1111111 (127)

00000000 (0)

01111111 (127)

128 bytes

10000000 (128)

11111111 (255)

128 bytes

Total RAM data

00000000 (0)

11111111 (255)

256 bytes

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

40h - 7Fh – Standard RAM

64 bytes of RAM space. The data in the RAM is held when using battery power. The upper 2 bits of the effective memory RAM address are taken from the XADS field, and the lower 6 bits are taken from the address offset, supporting a total RAM of 256 bytes. The initial values of the RAM locations are undefined.

80h - FFh – Alternate RAM

128 bytes of RAM space. The data in the RAM is held when using battery power. The upper bit of the effective RAM address is taken from the XADA bit, and the lower 7 bits are taken from the address offset, supporting a total RAM of 256 bytes. The initial values of the RAM locations are undefined.

38/98

Micro Crystal

Address

Function

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

00h

Hundredths

1 0 0 1 1 0 0

01h

Seconds

0 0 0 0 0 0 0

02h

Minutes 0 0 0 0 0 0 0 0

03h

Hours 0 0 0 0 0 0 0 0

04h

Date 0 0 0 0 0 0 0 1

05h

Months 0 0 0 0 0 0 0 1

06h

Years 0 0 0 0 0 0 0 0

07h

Weekdays

0 0 0 0 0 0 0 0 08h

Hundredths Alarm

0 0 0 0 0 0 0

09h

Seconds Alarm

0 0 0 0 0 0 0

0Ah

Minutes Alarm

0 0 0 0 0 0 0 0 0Bh

Hours Alarm

0 0 0 0 0 0 0 0 0Ch

Date Alarm

0 0 0 0 0 0 0

0Dh

Months Alarm

0 0 0 0 0 0 0

0Eh

Weekdays Alarm

0 0 0 0 0 0 0 0 0Fh

Status 0 0 0 0 0 0 0 0

10h

Control1

0 0 0 1 0 0 1

11h

Control2

0 0 1 1 1 1 0

12h

Interrupt Mask

1 1 1 0 0 0 0 0 13h

Square Wave SQW

0 0 1 0 0 1 1

14h

Calibration XT 0 Preconfigured (Factory Calibrated)

15h

Calibration RC Upper

Preconfigured

Preconfigured (Factory Calibrated)

16h

Calibration RC Lower

Preconfigured (Factory Calibrated)

17h

Sleep Control

0 0 0 0 0 0 0 0 18h

Countdown Timer Control

0 0 1 0 0 0 1

19h

Countdown Timer

0 0 0 0 0 0 0

1Ah

Timer Initial Value

0 0 0 0 0 0 0 0 1Bh

Watchdog Timer

0 0 0 0 0 0 0 0 1Ch

Oscillator Control

0 0 0 0 0 0 0

1Dh

Oscillator Status Register

0 0 1 0 0 0 1

1Fh

Configuration Key

0 0 0 0 0 0 0 0 20h

Trickle Charge

0 0 0 0 0 0 0 0 21h

BREF Control

1 1 1 1 0 0 0

26h

Cap_RC Control

0 0 0 0 0 0 0

27h

IO Batmode Register

1 0 0 0 0 0 0

28h

ID0 - Part Number Upper Register (Read Only)

0 0 0 1 1 0 0 0 29h

ID1 - Part Number Lower Register (Read Only)

0 0 0 0 0 1 0 1 2Ah

ID2 - Part Revision (Read Only)

0 0 0 1 0 0 1 1 2Bh

ID3 – Lot Lower (Read Only)

Preconfigured Lot Number

2Ch

ID4 – Unique ID Upper (Read Only)

Preconfigured Value

2Dh

ID5 – Unique ID Lower (Read Only)

Preconfigured Value

2Eh

ID6 – Wafer (Read Only)

Preconfigured Value

2Fh

Analog Status Register (Read Only)

30h

Output Control Register

0 0 0 0 0 0 0 0 3Fh

Extension RAM Address

0 0 Read Only

0 0 0

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

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Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

4. DETAILED FUNCTIONAL DESCRIPTION

The RV-1805-C3 serves as a companion part for host processors including microcontrollers, radios, and digital signal processors. It tracks time as in a typical RTC product and additionally provides unique power management functionality that makes it ideal for highly energy-constrained applications. To support such operation, the RV1805-C3 includes 3 distinct feature groups: 1) baseline timekeeping features, 2) advanced timekeeping features, and 3) power management features. Functions from each feature group may be controlled via I/O offset mapped registers. These registers are accessed using the I2C serial interface. Each feature group is described briefly below and in greater detail in subsequent sections.

1. The baseline timekeeping feature group supports two modes: a) XT oscillator mode and b) XT Autocalibration mode.

a. In XT mode the 32.768 kHz crystal is active and the 16.384 kHz level is digitally offset

compensated for a maximum frequency accuracy (factory calibrated) and has an ultra-low current draw of 60 nA. The baseline timekeeping feature group also includes a standard set of counters monitoring hundredths of a second up through centuries. A complement of countdown timers and alarms may additionally be set to initiate interrupts or resets on several of the outputs.

b. The XT Autocalibration mode has the same features as the XT mode but additionally calibrates the

RC oscillator periodically to the compensated XT oscillator.

2. The advanced timekeeping feature group supports two additional oscillation modes: a) RC oscillator mode, and b) RC Autocalibration mode.

a. At only 17 nA, the temperature-compensated RC oscillator mode with factory calibrated frequency

at the 64 Hz level provides an even lower current draw than the XT oscillator for applications with reduced frequency accuracy requirements. A proprietary calibration algorithm allows the RV-1805C3 to digitally tune the RC oscillator frequency to ± 16 ppm to the digitally offset compensated XT oscillator frequency with the accuracy as low as ± 2 ppm at a given temperature.

b. In Autocalibration mode, the RC oscillator is used as the primary oscillation source and is

periodically calibrated against the digitally tuned XT oscillator. Autocalibration may be done automatically every 8.5 minutes or 17 minutes and may also be initiated via software. This mode enables average current draw of only 22 nA with frequency accuracy similar to the XT oscillator. The advanced timekeeping feature group also includes a rich set of input and output configuration options that enables the monitoring of external interrupts (e.g., pushbutton signals), the generation of clock outputs, and watchdog timer functionality.

3. Power management features built into the RV-1805-C3 enable it to operate as a backup device in both line-powered and battery-powered systems. An integrated power control module automatically detects when main power (VDD) falls below a threshold and switches to backup power (V ultra-low leakage RAM enable the storage of key parameters when operating on backup power.

The RV-1805-C3 is the first RTC to incorporate a number of more advanced power management features. In particular, the RV-1805-C3 includes a finite Sleep Control State Machine (integrated with the power control) that can control a host processor as it transitions between sleep/reset states and active states. Digital outputs can be configured to control the reset signal or interrupt input of the host controller. The RV-1805-C3 additionally

integrates a power switch with ~1 Ω impedance that can be used to cut off ground current on the host

microcontroller and reduce sleep current to <1 nA. The RV-1805-C3 parts can wake up a sleeping system using internally generated timing interrupts or externally generated interrupts generated by digital inputs (e.g., using a pushbutton) or an analog comparator. The aforementioned functionality enables users to seamlessly power down host processors, leaving only the energy-efficient RV-1805-C3 chip awake. The RV-1805-C3 also includes voltage detection on the backup power supply.

Each functional block is explained in detail in the remainder of this section. Functional descriptions refer to the registers shown in the two Tables in Section REGISTER OVERVIEW. A detailed description of all registers can be found in Section REGISTER ORGANIZATION.

). Up to 512 bytes of

BACKUP

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SDA

SCL

change of

data

allowed

data line

stable;

data valid

SDA

SCL

START

condition

STOP

condition

SDA

SCL

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

I2C INTERFACE 4.2.

The I2C interface is for bidirectional, two-line communication between different ICs or modules. The device is accessed at addresses D2h/D3h, and supports Fast Mode (up to 400 kHz). The I2C interface consists of two lines: one bi-directional data line (SDA) and one clock line (SCL). Both lines are connected to a positive supply via pullup resistors. Data transfer is initiated only when the interface is not busy.

I2C termination resistors should be above 2.2 kΩ, and for systems with short I2C bus wires/traces and few connections these terminators can typically be as large as 22 kΩ (for 400 kHz operation) or 56 kΩ (for 100 kHz operation). Larger resistors will produce lower system current consumption.

BUS NOT BUSY 4.2.1.

Both SDA and SCL remain high.

BIT TRANSFER 4.2.2.

One data bit is transferred during each clock pulse. The data on the SDA line remains stable during the HIGH period of the clock pulse, as changes in the data line at this time are interpreted as a control signals. Data changes should be executed during the LOW period of the clock pulse (see figure below).

Bit transfer:

START AND STOP CONDITIONS 4.2.3.

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line, while the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH transition of the data line, while the clock is HIGH, is defined as the STOP condition (P) (see figure below).

Definition of START and STOP conditions:

A START condition which occurs after a previous START but before a STOP is called a RESTART condition, and functions exactly like a normal STOP followed by a normal START.

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MASTER

TRANSMITTER

RECEIVER

SLAVE

RECEIVER

SLAVE

TRANSMITTER

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER

RECEIVER

SDA

SCL

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

DATA VALID 4.2.4.

After a START condition, SDA is stable for the duration of the high period of SCL. The data on SDA may be changed during the low period of SCL. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and STOP conditions is not limited. The information is transmitted byte-wise and each receiver acknowledges with a ninth bit.

SYSTEM CONFIGURATION 4.2.5.

Since multiple devices can be connected with the I2C bus, all I2C bus devices have a fixed and unique device number built-in to allow individual addressing of each device.

The device that controls the I2C bus is the Master; the devices which are controlled by the Master are the Slaves. A device generating a message is a Transmitter; a device receiving a message is the Receiver. The RV-1805-C3 acts as a Slave-Receiver or Slave-Transmitter.

Before any data is transmitted on the I2C bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The clock signal SCL is only an input signal, but the data signal SDA is a bidirectional line.

System configuration:

ACKNOWLEDGE 4.2.6.

The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge cycle.

• A slave receiver, which is addressed, must generate an acknowledge cycle after the reception of each byte

• Also a master receiver must generate an acknowledge cycle after the reception of each byte that has been

clocked out of the slave transmitter

• The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that

the SDA line is stable LOW during the HIGH period of the related acknowledge clock pulse (set-up and hold times must be considered)

• A master receiver must signal an end of data to the transmitter by not generating an acknowledge cycle on

the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition

Acknowledgement on the I2C bus is shown on the figure below.

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SCL form

master

2 8 9

START

condition

data output

by receiver

data output

by transmitter

not acknowledge

acknowledge

clock pulse for

acknowledgement

Bit

Slave address

6 5 4 3 2

1 0

MSB

LSB

1 1 0 1 0 0 1

WWW

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

Acknowledgement on the I2C bus:

ADDRESSING 4.2.7.

On the I2C bus the 7-bit slave address 1101001b is reserved for the RV-1805-C3. The entire I2C bus slave address byte is shown in the table below.

I2C slave address byte:

After a START condition, the I2C slave address has to be sent to the RV-1805-C3 device. The R/ bit defines the direction of the following single or multiple byte data transfer. The 7-bit address is transmitted MSB first. If this

address is 1101001b, the RV-1805-C3 is selected, the eighth bit indicate a write (R/ = 0) or a read (R/ = 1) operation (results in D2h or D3h) and the RV-1805-C3 supplies the ACK. The RV-1805-C3 ignores all other address values and does not respond with an ACK. In the write operation, a data transfer is terminated by sending either the STOP condition or the START condition of the next data transfer.

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1) Master sends out the START condition.

2) Master sends out Slave Address, D2h for the RV-1805-C3; the R/ bit is a 0 indicating a write operation.

3) Acknowledgement from the RV-1805-C3.

4) Master sends out the Register Address to the RV-1805-C3.

5) Acknowledgement from the RV-1805-C3.

6) Master sends out the Data to write to the specified address in step 4).

7) Acknowledgement from the RV-1805-C3.

8) Steps 6) and 7) can be repeated if necessary. The address will be incremented automatically in the RV-1805-C3.

9) Master sends out the STOP Condition.

S 0 PA A A

Acknowledge from RV-1805-C3

R / W

DATA

2 3 4 5 61 7 8 9

1) Master sends out the START condition.

2) Master sends out Slave Address, D2h for the RV-1805-C3; the R/ bit is a 0 indicating a write operation.

3) Acknowledgement from the RV-1805-C3.

4) Master sends out the Register Address to the RV-1805-C3.

5) Acknowledgement from the RV-1805-C3.

6) Master sends out the RESTART condition (STOP condition followed by START condition)

7) Master sends out Slave Address, D3h for the RV-1805-C3; the R/ bit is a 1 indicating a read operation.

8) Acknowledgement from the RV-1805-C3. At this point, the Master becomes a Receiver, the Slave becomes the Transmitter.

9) The Slave sends out the Data from the Register Address specified in step 4).

10) Acknowledgement from the Master.

11) Steps 9) and 10) can be repeated if necessary. The address will be incremented automatically in the RV-1805-C3.

12) The Master, addressed as Receiver, can stop data transmission by not generating an acknowledge on the last byte that has been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the data line HIGH to enable the Master to generate a STOP condition.

13) Master sends out the STOP condition.

DATA DATA

S 0 A SA

SLAVE ADDRESS SLAVE ADDRESS

R / W

Acknowledge from Master

Acknowledge from RV-1805-C3

2 3 4 5 61 7 8 9 10 11 12

No acknowledge

RESTART

WWW

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

WRITE OPERATION 4.2.8.

Master transmits to Slave-Receiver at specified address. The Register Address is an 8-bit value that defines which register is to be accessed next. After reading or writing one byte, the Register Address is automatically incremented by 1.

READ OPERATION AT SPECIFIC ADDRESS 4.2.9.

Master reads data after setting Register Address:

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1) Master sends out the START condition.

2) Master sends out Slave Address, D3h for the RV-1805-C3; the R/ bit is a 1 indicating a read operation.

3) Acknowledgement from the RV-1805-C3. At this point, the Master becomes a Receiver, the Slave becomes the Transmitter

4) The RV-1805-C3 sends out the Data from the last accessed Register Address incremented by 1.

5) Acknowledgement from the Master.

6) Steps 4) and 5) can be repeated if necessary. The address will be incremented automatically in the RV-1805-C3.

7) The Master, addressed as Receiver, can stop data transmission by not generating an acknowledge on the last byte that has been sent from the Slave-Transmitter. In this event, the Slave-Transmitter must leave the data line HIGH to enable the Master to generate a STOP condition.

8) Master sends out the STOP condition.

S 1 PA A

DATASLAVE ADDRESS DATA

Acknowledge from Master

R / W

Acknowledge from RV-1805-C3

2 3 4 5 61 7 8

No acknowledge

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

READ OPERATION 4.2.10.

Master reads Slave-Transmitter immediately after first byte:

XT OSCILLATOR 4.3.

The RV-1805-C3 includes a very power efficient crystal (XT) oscillator which runs at 32.768 kHz. This oscillator is selected by setting the OSEL bit to 0 and includes a low jitter calibration function.

RC OSCILLATOR 4.4.

The RV-1805-C3 includes an extremely low power RC oscillator which runs at typically 122 Hz (Fnom = 128 Hz). This oscillator is selected by setting the OSEL bit to 1. Switching between the XT and RC Oscillators is guaranteed to produce less than one second of error in the Calendar Counters. The RV-1805-C3 may be configured to automatically switch to the RC Oscillator when VDD drops below its threshold by setting the BOS bit, and/ or be configured to automatically switch if an XT Oscillator failure is detected by setting the FOS bit.

RTC COUNTER ACCESS 4.5.

When reading any of the counters in the RTC using a burst operation, the 1 Hz and 100 Hz clocks are held off during the access. This guarantees that a single burst will either read or write a consistent timer value (other than the Hundredths Counter – see HUNDREDTHS SYNCHRONIZATION). There is a watchdog function to insure that a very long pause on the interface does not cause the RTC to lose a clock.

On a write to any of the Calendar Counters, the entire timing chain up to 100 Hz (if the XT Oscillator is selected) or up to 1Hz (if the RC Oscillator is selected) is reset to 0. This guarantees that the Counters will begin counting immediately after the write is complete, and that in the XT oscillator case the next 100 Hz clock will occur exactly 10 ms later. In the RC Oscillator case, the next 1 Hz clock will occur exactly 1 second later. This allows a burst write to configure all of the Counters and initiate a precise time start. Note that a Counter write may cause one cycle of a Square Wave SQW output to be of an incorrect period.

The WRTC bit must be set in order to write to any of the Counter registers. This bit can be cleared to prevent inadvertent software access to the Counters.

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INT

RST

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

HUNDREDTHS SYNCHRONIZATION 4.6.

If the Hundredths Counter is read as part of the counter burst, there is a small probability (approximately 1 in 109) that the Hundredths Counter rollover from 99 to 00 and the Seconds Counter increment will be separated by the read. In this case, correct read information can be guaranteed by the following algorithm.

1. Read the Counters, using a burst read. If the Hundredths Counter is neither 00 nor 99, the read is correct.

2. If the Hundredths Counter was 00, perform the read again. The resulting value from this second read is guaranteed to be correct.

3. If the Hundredths Counter was 99, perform the read again.

a. If the Hundredths Counter is still 99, the results of the first read are guaranteed to be correct. Note

that it is possible that the second read is not correct.

b. If the Hundredths Counter has rolled over to 00, and the Seconds Counter value from the second

read is equal to the Seconds Counter value from the first read plus 1, both reads produced correct values. Alternatively, perform the read again. The resulting value from this third read is guaranteed to be correct.

c. If the Hundredths Counter has rolled over to 00, and the Seconds Counter value from the second

read is equal to the Seconds Counter value from the first read, perform the read again. The resulting value from this third read is guaranteed to be correct.

GENERATING HUNDREDTHS OF A SECOND 4.7.

The generation of an exact 100 Hz signal for the Hundredths Counter requires a special logic circuit. The 2.048 kHz clock signal is divided by 21 for 12 iterations, and is alternately divided by 20 for 13 iterations. This produces an effective division of:

(21 * 12 + 20 * 13)/25 = 20.48 producing an exact long-term average 100 Hz output, with a maximum jitter of less than 1 ms. The Hundredths

Counter is not available when the RC Oscillator is selected.

WATCHDOG TIMER 4.8.

The RV-1805-C3 includes a Watchdog Timer, which can be configured to generate an interrupt or a reset if it times out. The Watchdog Timer is controlled by the Watchdog Timer Register (see TIMER REGISTERS, 1Bh - Watchdog Timer). The WD field selects the frequency at which the timer is decremented, and the WDM field determines the multiplier value loaded into the timer when it is restarted. If the timer reaches a value of zero, the WDS bit

determines whether an interrupt is generated at CLK/ WDS is 1). If interrupt selected and timer reaching zero, the WDF flag in the Status Register is set to 1, which may

be cleared by setting the WDF flag to zero. If reset is selected, the second of the timer reaching zero and remains asserted low for 1/16 second, and the WDF flag is not set.

Two actions will restart the Watchdog Timer:

1. Writing the Watchdog Timer Register with a new watchdog value.

2. A change in the level of the WDI pin.

If the Watchdog Timer generates an interrupt or reset, the Watchdog Timer Register must be written in order to restart the Watchdog Timer function. If the WDM field is 0, the Watchdog Timer function is disabled.

The WDM multiplier field describes the maximum timeout delay. For example, if WD = 01 so that the clock period is 250 ms, a WDM value of 9 implies that the timeout will occur between 2000 ms and 2250 ms after writing the Watchdog Timer Register.

(if WDS is 0) or the

output pin is asserted low within 1/16

output pin is asserted low (if

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INT/CLK

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

DIGITAL CALIBRATION 4.9.

XT OSCILLATOR DIGITAL CALIBRATION 4.9.1.

In order to improve the accuracy of the XT oscillator, a Distributed Digital Calibration function is included (see CALIBRATION REGISTERS, 14h - Calibration XT). This function uses a calibration value, OFFSETX, to adjust the clock period over a 16 second or 32 second calibration period. When the 32.768 kHz XT oscillator is selected, the clock at the 16.384 kHz level of the divider chain is modified on a selectable interval. Clock pulses are either added or subtracted to ensure accuracy of the counters. If the CMDX bit is a 0 (normal calibration), OFFSETX cycles of the 16.384 kHz clock level are gated (negative calibration) or replaced by 32.768 kHz level pulses (positive calibration) within every 32 second calibration period. In this mode, each step in OFFSETX modifies the clock frequency by 1.907 ppm, with a maximum adjustment of ~+120/-122 ppm. If the CMDX bit is 1 (coarse calibration), OFFSETX cycles of the 16.384 kHz clock level are gated or replaced by the 32.768 kHz level pulses within every 16 second calibration period. In this mode, each step in OFFSETX modifies the clock frequency by 3.815 ppm, with a maximum adjustment of ~+240/-244 ppm. OFFSETX contains a two's complement value, so the possible steps are from -64 to +63 (7 bits). Note that unlike other implementations, the Distributed Digital Calibration guarantees that the clock is precisely calibrated every 32 seconds with normal calibration and every 16 seconds when coarse calibration is selected.

The pulses which are added to or subtracted from the 16.384 kHz clock level are spread evenly over each 16 or 32 second period using the Distributed Calibration algorithm. This insures that in XT mode the maximum cycle-to-cycle jitter in any clock of a frequency 16.384 kHz or lower caused by calibration will be no more than one 16.384 kHz period. This maximum jitter applies to all clocks in the RV-1805-C3, including the Calendar Counter, Countdown

Timer and Watchdog Timer clocks and the clock driven onto the In addition to the normal calibration, the RV-1805-C3 also includes an Extended Calibration field to compensate a

higher XT oscillator frequency. The frequency generated by the Crystal Oscillator may be reduced by -122 ppm multiplied by the value in the XTCAL (see OSCILLATOR REGISTERS, 1Dh – Oscillator Status Register) field (0,

-122, -244 or -366 ppm). The clock is still precisely calibrated in 16 or 32 seconds. Normally, this field remains 0.  At POR, the CMDX and OFFSETX values in register 14h are initialized with factory calibrated; non-volatile

frequency offset compensation values (± 2 ppm at 25°C).

 Customer can adjust these values by overwriting the register 14h with new calculated values. See process

below.

The XT oscillator calibration values CMDX, OFFSETX and XTCAL are determined by the following process:

1. Set the CMDX, OFFSETX and XTCAL register fields to 0 to ensure calibration is not occurring.

2. Select the XT oscillator by setting the OSEL bit to 0.

3. Configure a square wave SQW output on the output pin

4. Measure the frequency Fmeas at the output pin in Hz.

5. Compute the adjustment value required in ppm: PAdj = ((32’768 – Fmeas)*1’000’000)/32’768

6. Compute the adjustment value in steps: Adj = PAdj/(1’000’000/219) = PAdj/(1.90735)

7. If Adj < -320, the XT frequency is too high to be calibrated

8. Else if Adj < -256, set XTCAL = 3, CMDX = 1, OFFSETX = (Adj +192)/2

9. Else if Adj < -192, set XTCAL = 3, CMDX = 0, OFFSETX = Adj +192

10. Else if Adj < -128, set XTCAL = 2, CMDX = 0, OFFSETX = Adj +128

11. Else if Adj < -64, set XTCAL = 1, CMDX = 0, OFFSETX = Adj + 64

12. Else if Adj < 64, set XTCAL = 0, CMDX = 0, OFFSETX = Adj

13. Else if Adj < 128, set XTCAL = 0, CMDX = 1, OFFSETX = Adj/2

14. Else the XT frequency is too low to be calibrated

pin.

of frequency Fnom = 32’768 Hz.

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INT/CLK

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

RC OSCILLATOR DIGITAL CALIBRATION 4.9.2.

The RC Oscillator has a Distributed Digital Calibration function similar to that of the XT Oscillator (see CALIBRATION REGISTERS, 15h - Calibration RC Upper and 16h - Calibration RC Lower). However, because the RC Oscillator has a greater fundamental variability, the range of calibration is much larger, with four calibration ranges selected by the CMDR field. When the RC oscillator is selected, the clock at the 64 Hz level of the divider chain is modified on a selectable interval using the calibration value OFFSETR. Clock pulses are either added or subtracted to ensure accuracy of the counters. If the CMDR field is 00, OFFSETR cycles of the 64 Hz clock level are gated (negative calibration) or replaced by 128 Hz level pulses (positive calibration) within every 8’192 second calibration period. In this mode, each step in OFFSETR modifies the clock frequency by 1.907 ppm, with a maximum adjustment of +15’623/-15’625 ppm (+/- 1.56%). If the CMDR field is 01, OFFSETR cycles of the 64 Hz clock level are gated or replaced by the 128 Hz level pulses within every 4’096 second calibration period. In this mode, each step in OFFSETR modifies the clock frequency by 3.815 ppm, with a maximum adjustment of +31’246/

-31’250 ppm (+/-3.12%). If the CMDR field is 10, OFFSETR cycles of the 64 Hz clock level are gated (negative

calibration) or replaced by 128 Hz level pulses (positive calibration) within every 2’048 second calibration period. In this mode, each step in OFFSETR modifies the clock frequency by 7.63 ppm, with a maximum adjustment of +62’487/-62’500 ppm (+/- 6.25%). If the CMDR field is 11, OFFSETR cycles of the 64 Hz clock level are gated or replaced by pulses from the 128 Hz clock level within every 1’024 second calibration period. In this mode, each step in OFFSETR modifies the clock frequency by 15.26 ppm, with a maximum adjustment of +124’985/-125’000 ppm (+/-12.5%). OFFSETR contains a two's complement value, so the possible steps are from -8’192 to +8’191 (14 bits).

The pulses which are added to or subtracted from the 64 Hz clock level are spread evenly over each 8’192, 4’096, 2’048 or 1’024 second period using the Distributed Calibration algorithm. This insures that in RC mode the maximum cycle-to-cycle jitter in any clock of a frequency 64 Hz or lower caused by calibration will be no more than one 64 Hz period. This maximum jitter applies to all clocks in the RV-1805-C3, including the Calendar Counter,

Countdown Timer and Watchdog Timer clocks and the clock driven onto the

pins.

 At POR, the CMDR and OFFSETR (OFFSETRU and OFFSETRL) values in register 15h and 16h are

initialized with factory calibrated, non-volatile frequency offset compensation values (± 16 ppm at 25°C, VDD = 2.8 V).

 Customer can adjust these values by overwriting the registers 15h and 16h with new calculated values.

See process below.

 The RC oscillator digital calibration is also used by the XT Autocalibration and RC Autocalibration function

(see XT AUTOCALIBRATION MODE and RC AUTOCALIBRATION MODE).

The RC oscillator calibration values CMDR and OFFSETR are determined by the following process:

1. Set the CMDR and OFFSETR register fields to 0 to insure calibration is not occurring.

2. Select the RC oscillator by setting the OSEL bit to 1.

3. Configure a square wave SQW output on the output pin

of frequency Fnom = 128 Hz.

4. Measure the frequency Fmeas at the output pin.

5. Compute the adjustment value required in ppm as ((128 – Fmeas)*1’000’000)/Fmeas = PAdj

6. Compute the adjustment value in steps as PAdj/(1’000’000/219) = PAdj/(1.90735) = Adj

7. If Adj < -65’536, the RC frequency is too high to be calibrated

8. Else if Adj < -32’768, set CMDR = 3, OFFSETR = Adj/8

9. Else if Adj < -16’384, set CMDR = 2, OFFSETR = Adj/4

10. Else if Adj < -8’192, set CMDR = 1, OFFSETR = Adj/2

11. Else if Adj < 8’192, set CMDR = 0, OFFSETR = Adj

12. Else if Adj < 16’384, set CMDR = 1, OFFSETR = Adj/2

13. Else if Adj < 32’768, set CMDR = 2, OFFSETR = Adj/4

14. Else if Adj < 65’536, set CMDR = 3, OFFSETR = Adj/8

15. Else the RC frequency is too low to be calibrated

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-500

-400

-300

-200

-100

100

200

300

400

500

100

110

120

130

95 95.2 95.4 95.6 95.8 96

f and f

AVER

in Hz

Time in seconds

f in Hz f

AVER

in Hz

ACC

in ppm

ACC

in ppm

SYMBOL

DESCRIPTION

UNIT

Frequency of every measured period. The RC oscillator frequency in this example is about 120 Hz and therefore the divided frequency about 60 Hz.

AVER

The average frequency from t0 to the current time (64 Hz level: after 96 seconds: -120 ppm to +20 ppm).

ACC

The average time accuracy from t0 to the current time (after 96 seconds: -120 ppm to +20 ppm).

ppm

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

The following figure shows the modified clock at the 64 Hz level with the achieved average time accuracy in ppm at 96 seconds (arbitrary). The average calculation was started at the time t0 = 0 seconds (TA = 25°C and VDD = 3.0 V).

Example with the modified RC oscillator clock at the 64 Hz level:

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RC/Acal

360'000

100 150 3'600 36'000

Expected Time Accuracy for 1 Year in Seconds

ACP = 512 sec.

TA = 25°C VDD = 3.0 V

RC/Acal

ACP = 1024 sec.

XT/Acal

Average Current in nA

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

AUTOCALIBRATION 4.10.

The RV-1805-C3 includes the capability of using the internal RC Oscillator for all timing functions. For increased accuracy at a small power penalty, the RC Oscillator may be periodically calibrated to the digitally calibrated Crystal (XT) Oscillator which is turned on only during this calibration. The overall process is referred to as Autocalibration and under most conditions produces a clock with long term accuracy essentially indistinguishable from the digitally calibrated XT Oscillator alone, as shown in the RC/Acal bubble in the following Figure.

Basic Mode Comparison:

BASIC AUTOCALIBRATION OPERATION 4.11.

The RV-1805-C3 includes a very powerful automatic calibration feature, referred to as Autocalibration, which allows the RC Oscillator to be automatically calibrated to the digitally calibrated XT Oscillator. The digitally calibrated XT Oscillator typically has much better stability than the RC Oscillator, but the RC Oscillator requires significantly less power. Autocalibration enables many system configurations to achieve accuracy and stability similar to that of the digitally calibrated XT Oscillator while drawing current similar to that of the RC Oscillator. Autocalibration functions in two primary modes: XT Autocalibration Mode and RC Autocalibration Mode.

AUTOCALIBRATION OPERATION 4.11.1.

The Autocalibration operation counts the number of calibrated XT clock cycles within a specific period as defined by the RC Oscillator and then loads new values into the Calibration RC Upper and RC Lower registers which will then adjust the RC Oscillator output to match the digitally calibrated XT frequency. In most cases Autocalibration is configured by the host controller over the serial interface when the RV-1805-C3 is initialized.

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ACAL Value

Autocalibration Mode

No Autocalibration

RESERVED

Autocalibrate every 1024 seconds (~17minutes)

Autocalibrate every 512 seconds (~8.5 minutes)

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

XT AUTOCALIBRATION MODE 4.11.2.

XT Autocalibration Mode is used when the digitally calibrated XT Oscillator is normally active, but the system is configured to switch to the RC Oscillator on a failure or a switchover to battery power (see also AUTOMATIC SWITCHOVER SUMMARY). In XT Autocalibration Mode, the OSEL register bit is set to 0, ACAL is set to 10 or 11 and the RV-1805-C3 uses the XT Oscillator whenever the system power VDD is above the V

voltage. The RC

DDSWF

Oscillator is periodically automatically calibrated to the XT Oscillator. If the BOS bit is set, when VDD drops below the V

threshold the system will switch to using V

DDSWF

, the clocks will begin using the RC Oscillator

BACKUP

(Autocalibration Mode according to the ACAL field) and the XT Oscillator will be disabled to reduce power requirements. Because the RC Oscillator has been continuously calibrated to the digitally calibrated XT Oscillator, it will be already very accurate when the switch occurs. When VDD is again above the threshold, the system will switch back to use the XT Oscillator in the XT Autocalibration Mode. It is possible to gain or lose up to one second during a switchover between the oscillators.

RC AUTOCALIBRATION MODE 4.11.3.

RC Autocalibration Mode is used when the RC Oscillator is always used as the clock but it is desired to maintain the frequency of the RC Oscillator as close to the digitally calibrated XT Oscillator as possible. In RC Autocalibration Mode, the OSEL register bit is set to 1, ACAL is set to 10 or 11 and the RV-1805-C3 uses the RC Oscillator at all times. However, periodically the XT Oscillator is turned on and the RC Oscillator is calibrated to the XT Oscillator. This allows the system to operate most of the time with the XT Oscillator off but allow continuous calibration of the RC Oscillator and maintain high accuracy for the RC Oscillator.

AUTOCALIBRATION FREQUENCY AND CONTROL 4.11.4.

The Autocalibration function is controlled by the ACAL field in the Oscillator Control register as shown in the following Table. If ACAL is 00, no Autocalibration occurs. If ACAL is 10 or 11, Autocalibration occurs every 1024 or 512 seconds, which is referred to as the Autocalibration Period (ACP). In RC Autocalibration Mode, an Autocalibration operation results in the digitally calibrated XT Oscillator being enabled for roughly 50 seconds. The 512 second Autocalibration cycles have the XT Oscillator enabled approximately 10% of the time, while 1024 second Autocalibration cycles have the XT Oscillator enabled approximately 5% of the time.

If ACAL is 00 and is then written with a different value, an Autocalibration cycle is immediately executed. This allows Autocalibration to be completely controlled by software. As an example, software could choose to execute an Autocalibration cycle every 2 hours by keeping ACAL at 00, getting a two hour interrupt using the alarm function, generating an Autocalibration cycle by writing ACAL to 10 or 11, and then returning ACAL to 00.

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Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

Cap_RC PIN 4.11.5.

In order to produce the optimal accuracy for the Autocalibrated RC Oscillator, a 47 pF capacitor must be connected between the Cap_RC pin and VSS. In order to enable the filter, the value A0h must be written to CAPRC at address 26h (Section ANALOG CONTROL REGISTERS). The Cap_RC filter is disabled by writing 00h to CAPRC. No other values should be written to this register. The Configuration Key CONFKEY must be written with the value 9Dh immediately prior to writing to the Cap_RC Control Register CAPRC.If the filter capacitor is not connected to the Cap_RC pin or is not enabled, the Autocalibrated RC Oscillator frequency will typically be between 10 and 50 ppm lower than the digitally calibrated XT Oscillator. If the capacitor is connected to the Cap_RC pin and enabled, the RC Oscillator frequency will be within the accuracy range specified in the OSCILLATOR PARAMETERS table of the XT Oscillator.

AUTOCALIBRATION FAILURE 4.11.6.

If the operating temperature of the RV-1805-C3 exceeds the Autocalibration range specified in the Oscillator Parameters table or internal adjustment parameters are altered incorrectly, it is possible that the basic frequency of the RC Oscillator is so far away from the nominal 128 Hz value (off by more than 12%) that the RC Calibration circuitry does not have enough range to correctly calibrate the RC Oscillator. If this situation is detected during an Autocalibration operation, the ACF interrupt flag is set, an interrupt is generated if the ACIE register bit is set and the Calibration RC registers (15h and 16h) are not updated.

If an Autocalibration failure is detected while running in RC Autocalibration mode, it is advisable to switch into XT Autocalibration mode to maintain the timing accuracy. This is done by first ensuring a XT oscillator failure has not occurred (OF flag = 0) and then clearing the OSEL bit. The ACAL field should remain set to either 11 (512 second period) or 10 (1024 second period). After the switch occurs, the OMODE bit is cleared.

While continuing to operate in XT Autocalibration mode, the following steps can be used to determine when it is safe to return to RC Autocalibration mode.

1. Clear the ACF flag and ACIE register bit.

2. Setup the Countdown Timer or Alarm to interrupt after the next Autocalibration cycle completes or longer

time period.

3. After the interrupt occurs, check the status of the ACF flag.

4. If the ACF flag is set, it is not safe to return to RC Autocalibration mode. Clear the ACF flag and repeat

steps 2-4.

5. If the ACF flag is still cleared, it is safe to return to RC Autocalibration mode by setting the OSEL bit.

As mentioned in the RC oscillator section, switching between XT and RC oscillators is guaranteed to produce less than one second of error. However, this error needs to be considered and can be safely managed when implementing the steps above. For example, switching between oscillator modes every 48 hours will produce less than 6 ppm of deviation.

FREQUENCY ACCURACY IN RC AUTOCALIBRATION MODE 4.11.7.

RC Autocalibration Mode is typically the most useful mode, because it allows a dramatic reduction in the power used by the RV-1805-C3 while maintaining the accuracy of the internal clock. The RC is always used as the internal clock so that no time deviations occur as can be seen with XT Autocalibration Mode and automatic switchover. RC Autocalibration Mode is the only applicable mode in systems where there is only a single battery supply, which is very common. Because the RC Oscillator is fundamentally less stable with temperature (typically +/- 1%, or 10’000 ppm, over the full temperature range) than the digitally calibrated XT Oscillator (typically within 150 ppm over the full temperature range), many applications cannot use the RC Oscillator alone as the timing clock. RC Autocalibration improves the accuracy of the RC Oscillator by continuously adjusting it to match the calibrated XT Oscillator.

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Time

Freq

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

64 Hz

Raw RC frequency on the 64 Hz level

Autocalibrated RC frequency

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

Autocalibration maintains the RC Oscillator at a frequency very close to the digitally calibrated XT Oscillator, but there are obviously small deviations which can occur on each cycle. However, as temperature and the raw RC Oscillator frequency vary, deviations typically cancel each other out and produce very low accumulated deviation. The following Figure shows a time sequence with varying frequency. The heavy shaded line shows the variation of the raw RC Oscillator on the 64 Hz level, and the vertical dashed lines indicate the boundaries of Autocalibration Periods (ACPs, either 512 or 1024 seconds). The RC Oscillator is calibrated within a small number of PPM at the beginning of each ACP to the digitally calibrated XT Oscillator, so the calibrated RC frequency is the saw tooth function in the center of the figure, with the accumulated deviation in each ACP shown by the shaded triangles.

Autocalibration Deviation Cancellation:

Although some deviation is accumulated in each ACP, it can be seen that the positive deviations which occur when the frequency is rising are cancelled by the negative deviations when the frequency is falling. Over any significant period of time, the net accumulated deviation is almost completely determined by the frequency difference between the beginning and end of the period and the rate of change of the frequency with time.

Since the frequencies of both the RC and the XT Oscillators are functions of temperature, and temperature changes are easy to understand and quantify, accumulated deviation is measured as a function of the temperature profile. The behavior of RC Autocalibration has been modeled by varying the temperature in a random way and simulating the desired period, which in the cases below is one year. The temperature rises or falls at a random rate between twice the average rate specified and the negative of that value, and is limited to the specified maximum and minimum temperatures. One thousand simulations were executed, and the specified deviation is the worst case result of all iterations.

The following Figure shows the maximum accumulated time deviation relative to the digitally calibrated XT Oscillator as a function of the maximum temperature range and the average temperature change rate over a one year period, in seconds (31 seconds in a year = 1 ppm), with an Autocalibration Period of 512 seconds. Note that even the lowest average change rate of 0.025 equates to one degree C every 40 minutes, which is still quite fast when averaged over an entire year. At this change rate, the deviation over the full temperature range is less than 95 seconds (<3 ppm).

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100

150

200

250

300

0 0.1 0.2 0.3 0.4 0.5

Time Accuracy for 1 Year in Seconds

Average Temperature Change Rate in °C/min.

ACP = 512 Seconds

-40 to 85

-25 to 75

-10 to 60 10 to 40

100

200

300

400

500

600

700

800

900

1000

0 0.1 0.2 0.3 0.4 0.5

ACP = 1024 Seconds

-40 to 85

-25 to 75

-10 to 60 10 to 40

Average Temperature Change Rate in °C/min.

Time Accuracy for 1 Year in Seconds

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

Autocalibration Time Deviation relative to the digitally calibrated XT Oscillator, ACP = 512 seconds:

The following Figure shows the results when the ACP is 1024 seconds. At high temperature change rates, this setting produces roughly 3 times the deviation of the 512 second case, but the deviations for low change rates are still negligible.

Autocalibration Time Deviation relative to the digitally calibrated XT Oscillator, ACP = 1024 seconds:

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200

400

600

800

1000

1200

0 0.1 0.2 0.3 0.4 0.5

XT Only Deviation

-40 to 85

-25 to 75

-10 to 60 10 to 40

Average Temperature Change Rate in °C/min.

Time Accuracy for 1 Year in Seconds

Mode

Conditions

Accumulated Deviation

Unit

XT Only

Calibrated (0 ppm at 25°C)

-3.3

ppm/year

-104

s/year

RC Autocalibration

ACP = 512 seconds

±6.1

ppm/year

±192

s/year

ACP = 1024 seconds

±8.4

ppm/year

±245

s/year

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

The deviations in both of the cases above for relatively low temperature change rates are less than the deviation introduced by the XT Oscillator itself. The following Figure shows the raw XT deviation, which is more strongly a function of the maximum temperature range than the calibrated RC deviation. The XT deviation is a similar function of the temperature change rate but is more influenced by the maximum temperature variation. Deviations in the XT Oscillator are larger when the temperature is further away from the nominal 25 degrees C, and therefore it is expected that the accumulated deviation will be greater if the temperature range is larger.

Raw Deviation, XT Oscillator:

A REAL WORLD EXAMPLE 4.11.8.

Even if the temperature occasionally reaches the extremes of the allowable range and changes relatively quickly, in most real applications the temperature is reasonably stable. A proposed “real world” temperature profile assumes that for 30 days per year the temperature has a maximum range of -25 to 75 degrees C and an average change rate of 1 degree C every 5 minutes (0.2 °C/min.). For the remainder of the year, the maximum temperature range is 10 to 40 degrees C with a maximum change rate of 1 degree C every 40 minutes (0.025 °C/min.). Using this profile, the accumulated deviations over the year (including the XT deviation in the calibrated RC cases) are shown in following Table. As can be seen, with an ACP of 512 the clock accuracy using Autocalibration is quite close to the deviation achieved by the XT alone. Extending to an ACP of 1024 seconds adds a small incremental deviation.

Real World Accumulated Deviations for 1 Year (1 ppm = 31.6 seconds in a year):

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0.1

100

1000

1h 4h 12h 24h 1 week1 month1 year

Autocalibration Mode Timing Accuracy, ACP = 512 sec.

Accuracy in ppm Accuracy in sec.

TA = 25°C VDD = 3.0 V

Timing Accuracy in ppm and seconds

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

RC AUTOCALIBRATION TIMING ACCURACY EXAMPLE 4.11.9.

The RC Oscillator displays relatively high internal jitter caused by pulse addition or subtraction of the Autocalibration process as well as the inherent thermal noise jitter of the RC Oscillator itself. This jitter introduces significant time accuracy errors for short time periods.

The following Figure shows a typical Autocalibration mode timing accuracy for the time periods from 1 hour to 1 year relative to the digitally calibrated XT Oscillator, ACP = 512 seconds. The temperature does not varying. TA = 25°C, VDD = 3.0V.

Autocalibration Mode Timing Accuracy Example:

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Average Current (nA)

XT Only

Cal RC, ACP = 512 seconds

Cal RC, ACP = 1024 seconds

Time Interval

Std. Dev. (ppm)

Std. Dev. (ms)

0.5 hours

90.9

163.6

1 hour

45.5

163.8

2 hours

32.3

232.6

4 hours

22.5

324.0

1 day

9.3

803.5

2 days

6.5

1123.2

3 days

5.3

1373.8

1 week

3.5

2116.8

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

POWER ANALYSIS 4.11.10.

The power comparisons between the various cases are quite straightforward. During an Autocalibration, the XT Oscillator is powered up for 50 seconds. Therefore if the RV-1805-C3 draws 60 nA when the XT Oscillator is running and 17 nA when the XT Oscillator is off, the average current for each ACP case is shown in the following Table. Even the shortest ACP results in a savings of more than 60% of the current.

Autocalibration Current (TA = 25°C, VDD = 3.0V):

DISANDVANTAGES RELATIVE TO THE XT OSCILLATOR 4.11.11.

Maximum Output Clock Frequency

The primary disadvantage of using the autocalibrated RC Oscillator is that the highest calibrated output clock frequency which can be generated is 64 Hz (i.e., circa the half of the uncalibrated RC Oscillator frequency). In applications where a higher frequency clock is required, the XT Oscillator must be used. If such a clock is required only occasionally, the RV-1805-C3 may be temporarily placed in XT Mode by setting the OSEL bit to 0, and then returned to RC Mode by setting OSEL back to 1 when the high frequency clock is no longer required. The RV1805-C3 will continue to autocalibrate the RC Oscillator while the XT Oscillator is selected, but the calendar counters may gain or lose up to 1 second on each of the oscillator switchovers.

Large/Rapid Temperature Fluctuations

The XT Oscillator may also be preferable to Autocalibration when there are frequent, rapid and large temperature changes. In such a situation, the digitally calibrated XT Oscillator may provide a measurable improvement in accuracy, although at a significant power penalty relative to using Autocalibration.

Short Term Jitter

A third disadvantage of using the RC Oscillator is that it displays higher internal jitter relative to the XT oscillator. This jitter is caused by pulse addition or subtraction of the Autocalibration process as well as the inherent thermal noise jitter of the RC Oscillator itself. This jitter may introduce significant frequency errors over short time periods. In both cases the mean of the jitter is zero, and the following Table shows the standard deviation of the clock period for several short time periods including both jitter and temperature effects. A typical worst case metric is 4 standard deviations, which covers approximately 99.99% of all cases.

Short Term Jitter Standard Deviation:

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INT/CLK

Interrupt

Function

Enable

Pulse/Level/Repeat

Flag

AIRQ

Alarm Match

AIE

IM, ARPT

TIRQ

Countdown Timer

TIE, TE

TM, TRPT, TFS

WIRQ

Watchdog Timer (WDI)

WDS = 0, WDM, WD

Level Only

WDF

BLIRQ

Battery Low

BLIE, BREF, BPOL

Level Only

BLF

EIRQ

External Interrupt (WDI)

EIE, EIP

Level Only

EVF

OFIRQ

XT Oscillator Failure

OFIE

Level Only

ACIRQ

Autocalibration Failure

ACIE

Level Only

ACF

IRQ = AIRQ + TIRQ + WIRQ + BLIRQ + EIRQ + OFIRQ + ACIRQ

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

XT OSCILLATOR FAILURE DETECTION 4.12.

If the 32.768 kHz XT Oscillator generates clocks at less than 8 kHz for a period of more than 32 ms, the RV-1805C3 detects an XT Oscillator Failure. The XT Oscillator Failure function is controlled by several bits in the OSCILLATOR REGISTERS (see 1Ch Oscillator Control and 1Dh - Oscillator Status Register). The OF flag is set when an XT Oscillator Failure occurs, and is also set when the RV-1805-C3 initially powers up. If the OFIE bit is set, the OF flag will generate an interrupt OFIRQ.

If the FOS bit is set and the RV-1805-C3 is currently using the XT Oscillator, it will automatically switch to the RC Oscillator on an XT Oscillator Failure. This guarantees that the system clock will not stop in any case. The OMODE bit indicates the currently selected oscillator, which will not match the oscillator requested by the OSEL bit if the XT Oscillator is not running.

The OF flag will be set when the RV-1805-C3 powers up, and will also be set whenever the XT Oscillator is stopped. This can happen when the STOP bit is set or the OSEL bit is set to 1 to select the RC Oscillator. Since the XT Oscillator is stopped in RC Autocalibration mode (see RC AUTOCALIBRATION MODE), OF will always be set in this mode. The OF flag should be cleared whenever the XT Oscillator is enabled prior to enabling the OF interrupt with OFIE.

INTERRUPTS 4.13.

The RV-1805-C3 may generate a variety of interrupts which are ORed into the IRQ signal. This may be driven onto either the

pin or the PSW pin depending on the configuration of the CLKS and PSWS fields (see

CONFIGURATION REGISTERS, 11h - Control2).

INTERRUPT SUMMARY 4.13.1.

The possible interrupts are summarized in the following Table. All enabled interrupts are ORed into the IRQ signal when their respective flags are set. Note that most interrupt outputs use the inverse of the interrupt, denoted as e.g. inverse IRQ. The fields are:

 Interrupt - the name of the specific interrupt.  Function - the functional area which generates the interrupt.  Enable - the register bit which enables the interrupt. Note that for the Watchdog interrupt, WDS is the

steering bit, so that the flag generates an Interrupt if WDS is 0 and a Reset if WDS is 1. In either case, the WDM field must be non-zero to generate the Interrupt or Reset.

 Pulse/Level/Repeat - some interrupts may be configured to generate a pulse based on the register bits in

this column. "Level Only" implies that only a level may be generated, and the interrupt will only go away when the flag is reset by software.

 Flag - the register bit which indicates that the function has occurred. Note that the flag being set will only

generate an interrupt signal on an external pin if the corresponding interrupt enable bit is also set.

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Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

ALARM INTERRUPT AIRQ 4.13.2.

The RV-1805-C3 may be configured to generate the AIRQ interrupt when the values in the Time and Date Registers match the values in the Alarm Registers. Which register comparisons are required to generate AIRQ is controlled by the ARPT field as described in TIMER REGISTERS, 18h - Countdown Timer Control, allowing software to specify the interrupt interval. When an Alarm Interrupt is generated, the AF flag is set and an output signal is generated based on the AIE bit and the pin configuration settings. The IM field controls the period of the signal, including both level and pulse configurations.

COUNTDOWN TIMER INTERRUPT TIRQ 4.13.3.

The RV-1805-C3 may be configured to generate the TIRQ interrupt when the Countdown Timer is enabled by the TE bit and reaches the value of zero, which will set the TF flag. The TM, TRPT and TFS fields control the interrupt timing (see TIMER REGISTERS, 18h - Countdown Timer Control), and the TIE bit and the pin configuration settings control the output signal generation.

WATCHDOG TIMER INTERRUPT WIRQ 4.13.4.

The RV-1805-C3 may be configured to generate the WIRQ interrupt when the Watchdog Timer reaches its timeout value. This sets the WDF flag and is described in section WATCHDOG TIMER.

BATTERY LOW INTERRUPT BLIRQ 4.13.5.

The RV-1805-C3 may be configured to generate the BLIRQ when the voltage on the V

pin crosses one of the

BACKUP

thresholds set by the BREF field. The polarity of the detected crossing is set by the BPOL bit.

EXTERNAL INTERRUPT EIRQ 4.13.6.

The RV-1805-C3 may be configured to generate the EIRQ interrupt when the WDI input toggles. The register bit EIP control whether the rising or falling transitions generate the respective interrupt. Changing EIP may cause an immediate interrupt, so the interrupt flag should be cleared after changing this bit. The value of the WDI pin may be directly read in the WDIS bit (see RAM REGISTERS, 3Fh - Extension RAM Address). By connecting the input such as a pushbutton to WDI, software can debounce the switch input using software configurable delays.

XT OSCILLATOR FAILURE INTERRUPT OFIRQ 4.13.7.

The RV-1805-C3 may be configured to generate the OFIRQ interrupt if the XT oscillator fails (see XT OSCILLATOR FAILURE DETECTION).

AUTOCALIBRATION FAILURE INTERRUPT ACIRQ 4.13.8.

The RV-1805-C3 may be configured to generate the ACIRQ interrupt if an Autocalibration operation fails (see AUTOCALIBRATION FAIL).

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Power State

POR

DDST

DDRST

VDD Power

DDST

POR

DDSWF

VDD Power VBACKUP Power

BACKUPSW

DDSWR

VDD Power

DDSWF

BACKUPRST

VBACKUP Power POR

BACKUP

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

SERVICING INTERRUPTS 4.13.9.

When an interrupt is detected, software must clear the interrupt flag in order to prepare for a subsequent interrupt. If only a single interrupt is enabled, software may simply write a zero to the corresponding interrupt flag to clear the interrupt. However, because all of the flags in the Status register are written at once, it is possible to clear an interrupt which has not been detected yet if multiple interrupts are enabled. The ARST register bit is provided to insure that interrupts are not lost in this case. If ARST is a 1, a read of the Status register will produce the current state of all the interrupt flags in the Status register (WDF, BLF, TF, AF and EVF) and then clear them. An interrupt occurring at any time relative to this read is guaranteed to either produce a 1 on the Status read, or to set the corresponding flag after the clear caused by the Status read. After servicing all interrupts which produced 1s (ones) in the read, software should read the Status register again until it returns all zeros in the flags, and service any interrupts with flags of 1.

Note that the OF and ACF interrupts are not handled with this process because they are in the Oscillator Status register, but error interrupts are very rare and typically do not create any problems if the interrupts are cleared by writing the flag directly.

POWER CONTROL AND SWITCHING 4.14.

The main power supply to the RV-1805-C3 is the VDD pin, which operates over the range specified by the V

DDIO

parameter if there are I2C interface operations required, and the range specified by the VDD parameter if only timekeeping operations are required. The RV-1805-C3 also include a backup supply which is provided on the V below V power supplies and switchover. There are several functions which are directly related to the V

pin and must be in the range specified by the V

BACKUP

. Refer to Table in Section POWER SUPPLY PARAMETERS for the specifications related to the

DDSWF

parameter in order to supply battery power if VDD is

BACKUP

input. If a

single power supply is used it must be connected to the VDD pin. The following Figure illustrates the various power states and the transitions between them. There are three power

states:

1. POR – the power on reset state. If the RV-1805-C3 is in this state, all registers including the Counter

Registers are initialized to their reset values.

2. VDD Power – the RV-1805-C3 is powered from the VDD supply.

3. VBACKUP Power – the RV-1805-C3 is powered from the V

BACKUP

supply.

Initially, VDD is below the V state. VDD rising above the V below V

BACKUPSW

, VDD falling below the V

voltage, V

DDST

voltage causes the RV-1805-C3 to enter the VDD Power state. If V

DDST

DDRST

is below the V

BACKUP

BACKUPSW

voltage and the RV-1805-C3 is in the POR

voltage returns the RV-1805-C3 to the POR state.

BACKUP

remains

Power States:

If V 1805-C3 to be built into a module with a battery included, and minimal current will be drawn from the battery until

rises above V

BACKUP

BACKUPSW

in the POR state, the RV-1805-C3 remains in the POR state. This allows the RV-

VDD is applied to the module the first time.

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BOS

Used oscillator

Description

VDD Power state

VBACKUP Power state

No automatic oscillator switching

occurs.

RC Autocalibration

XT Autocalibration

The oscillator will automatically

switch to the RC oscillator

(Autocalibration Mode according

ACAL).

RC Autocalibration

XT Autocalibration

RC Autocalibration

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

If the RV-1805-C3 is in the VDD Power state and V VDD Power state but automatic switchover becomes available. V power state as long as VDD remains above V V

BACKUPSW

the RV-1805-C3 switches to the VBACKUP Power state. VDD rising above V

DDSWF

rises above V

BACKUP

BACKUPSW

falling below V

. If VDD falls below the V

, the RV-1805-C3 remains in the

BACKUPSW

voltage while V

DDSWF

DDSWR

has no effect on the

BACKUP

returns the RV-1805-

is above

C3 to the VDD Power state. There is hysteresis in the rising and falling VDD thresholds to insure that the RV-1805C3 does not switch back and forth between the supplies if VDD is near the thresholds. V independent of the V supply by switching to V

voltage and allow the RV-1805-C3 to minimize the current drawn from the V

BACKUP

only at the point where VDD is no longer able to power the device.

BACKUP

DDSWF

and V

DDSWR

BACKUP

are

If the RV-1805-C3 is in the VBACKUP Power state and V

BACKUP

falls below V

BACKUPRST

, the RV-1805-C3 will return

to the POR state. Whenever the RV-1805-C3 enters the VBACKUP Power state, the BAT status bit (Read Only) (see

CONFIGURATION REGISTERS, 0Fh - Status) is set and may be polled by software if the I2C bus is driven by V

. If the XT oscillator is selected and the BOS bit is set (see OSCILLATOR REGISTERS, 1Ch - Oscillator

BACKUP

Control), the RV-1805-C3 will automatically switch to the RC oscillator in the VBACKUP Power state in order to conserve battery power (Autocalibration Mode according to the ACAL field). If the IOBM bit is clear (see ANALOG CONTROL REGISTERS, 27h – IO Batmode Register), the I2C interface is disabled in the VBACKUP Power state in order to prevent erroneous accesses to the RV-1805-C3 if the bus master loses power.

AUTOMATIC SWITCHOVER SUMMARY 4.14.1.

When the RV-1805-C3 switches over from VDD Power state to the VBACKUP Power state and vice versa an Automatic Oscillator Switchover can be controlled by the BOS bit. The Autocalibration Mode is according to the ACAL field.

Automatic Oscillator Switchover using the BOS bit:

When using the FOS bit to control the switchover, an Automatic Oscillator Switchover occurs when a XT oscillator failure is detected and FOS is set to 1.

BATTERY LOW FLAG AND INTERRUPT 4.14.2.

If the V

voltage drops below the Falling Threshold selected by the BREF field (see ANALOG CONTROL

BACKUP

REGISTERS, 21h – BREF Control), the BLF flag (see CONFIGURATION REGISTERS, 0Fh - Status) is set. If the BLIE interrupt enable bit (see CONFIGURATION REGISTERS, 12h - Interrupt Mask) is set, the BLIRQ interrupt is generated. This allows software to determine if a backup battery has been drained. Note that the BPOL bit must be set to 0. The algorithm in the ANALOG COMPARATOR section should be used when configuring the BREF value.

If the V set. At that point the V status bit is set and a falling edge BLF interrupt is generated. If BREFD is clear, the V

voltage is above the rising voltage which corresponds to the current BREF setting, BREFD will be

BACKUP

voltage must fall below the falling voltage in order to clear the BREFD bit and the BAT

BACKUP

voltage must rise

BACKUP

above the rising voltage in order to clear the BREFD bit and generate a rising edge BLF interrupt.

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ANALOG COMPARATOR 4.14.3.

If a backup battery is not required, the V comparison level is set by the BREF field. If the BPOL bit is 0, the BLF flag will be set when the V

pin may be used as an analog comparator input. The voltage

BACKUP

voltage crosses from above the BREF Falling Threshold to below it. If the BPOL bit is 1, the BLF flag will be set when the V CONTROL REGISTERS, 2Fh – Analog Status Register (Read Only)) may be read to determine if the V

voltage crosses from below the BREF Rising Threshold to above it. The BREFD bit (see ANALOG

BACKUP

voltage is currently above the BREF threshold (BREFD = 1) or below the threshold (BREFD = 0). There is a reasonably large delay t

(on the order of seconds) between changing the BREF field and a valid

BREF

value of the BREFD bit. Therefore, the algorithm for using the Analog Comparator should comprise the following steps:

1. Set the BREF and BPOL fields to the desired values.

2. Wait longer than the maximum t

BREF

time.

3. Clear the BLF flag, which may have been erroneously set as BREFD settles.

4. Check the BREFD bit to insure that the V

pin is at a level for which an interrupt can occur. If a falling

BACKUP

interrupt is desired (BPOL = 0), BREFD should be 1. If a rising interrupt is desired (BPOL = 1), BREFD should be 0.

If the comparison voltage on the V

pin can remain when VDD goes to 0, it is recommended that a Software

BACKUP

Reset is generated to the RV-1805-C3 after power up.

4.14.4.

PIN CONTROL AND LEAKAGE MANAGEMENT (POWER CONTROL)

Like most ICs, the RV-1805-C3 may draw unnecessary leakage current if an input pin floats to a value near the threshold or an output pin is pulled to a power supply. Because external devices may be powered from VDD, extra care must be taken to insure that any input or output pins are handled correctly to avoid extraneous leakage when VDD goes away and the RV-1805-C3 is powered from V

. The 30h – Output Control Register (see ANALOG

BACKUP

CONTROL REGISTERS), the 27h – IO Batmode Register (see ANALOG CONTROL REGISTERS) and the 3Fh Extension RAM Address register (see RAM REGISTERS) include bits to manage this leakage, which should be used as follows:

1. IOBM (Bit 7, address 27h) should be cleared if the I2C bus master is powered down when the RV-1805-C3 is in the VBACKUP Power state.

2. WDBM (Bit 7, address 30h) should be cleared if the WDI pin is connected to a device which is powered down when the RV-1805-C3 is in the VBACKUP Power state.

3. X (Bit 6, address 30h) is unused, but has to be 0 to avoid extraneous leakage. Disables an internal input when the RV-1805-C3 is in the VBACKUP Power state.

4. X (Bit 7, address 3Fh) is unused, but must be set to 0 to avoid extraneous leakage. If 0, an internal output is completely disconnected when the RV-1805-C3 is in the VBACKUP Power state.

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INT/CLK

State

Power UpPower DownOperation Operation

No I2C Access

VH:CLK

INT/CLK

BACKUP

VDD

PORVDD Power VDD Power

Power State

RST

Function

Enable

Power Up

Always Enabled

Watchdog

WDS

Sleep

SLRST

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

POWER UP TIMING 4.14.5.

When the voltage levels on both the VDD and V Power On Reset state (POR). Once VDD rises above V

access via the I2C interface will be disabled for a period of t will go high when t

expires. Software should poll the

VH:CLK

signals drop below V

BACKUP

, the RV-1805-C3 will enter the VDD Power state. The

DDST

VH:CLK

, the RV-1805-C3 will enter the

DDRST

. The

value to determine when the RV-1805-C3 may

pin will be low at power up, and

be accessed. The following Figure illustrates the timing of a power down/up operation. Power Up Timing:

RESET SUMMARY 4.15.

The RV-1805-C3 controls the

is a low signal if the RSTP bit is 0, and the assertion is high if RSTP is 1. RSTP always powers up as a zero

so that on power

is always asserted low.

Reset Summary:

output in a variety of ways, as shown in the following Table. The assertion of

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INT/CLK

RST

INT/CLK

RST

INT/CLK

State

Power UpPower DownOperation Operation

No I2C Access

VH:CLK

Delay

VH:NRST

VDD

BACKUP

INT/CLK

RST

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

POWER UP RESET 4.15.1.

When the RV-1805-C3 powers up (see POWER UP TIMING) accesses are enabled. At that point

t should sample the

, and will then be deasserted to high. The following Figure illustrates the reset timing on Power Up. Software

VH:NRST

signal prior to accessing the RV-1805-C3.

will go high, and

Power Up Reset Timing:

and

will be asserted low until I2O

will continue to be asserted low for the delay

WATCHDOG TIMER 4.15.2.

If the WDS bit is 1, expiration of the Watchdog Timer (see WATCHDOG TIMER) will cause low for approximately 60 ms.

to be asserted

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RST

State

SleepOperation OperationDelay

VH:NRST

RST

PSW

RST

POR

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

SLEEP 4.15.3.

If the SLRST bit is set, CONTROL). Once a trigger is received and the RV-1805-C3 exits Sleep Mode,

low for the t

delay. The following Figure illustrates the timing of this operation.

VH:NRST

will be asserted low whenever the RV-1805-C3 is in Sleep Mode (see SLEEP

will continue to be asserted

Sleep Reset Timing:

SOFTWARE RESET 4.16.

Software may reset the RV-1805-C3 by writing the special value of 3Ch to the Configuration Key CONFKEY at register address 1Fh. This will provide the equivalent of a power on reset (POR) by initializing all of the RV-1805-

C3 registers. A software reset will not cause the

signal to be asserted low.

SLEEP CONTROL STATE MACHINE 4.17.

The RV-1805-C3 includes a sophisticated Sleep Control system that allows the RV-1805-C3 to manage power for other chips in a system. The Sleep Control system provides two outputs which may be used for system power control:

1. A reset (

) may be generated to put any host controller into a minimum power mode and to control

sequencing during power up and power down operations.

2. A power switch signal (PSW) may be generated, which allows the RV-1805-C3 to completely power down other chips in a system by allowing the PSW pin to float. The PSWS field must be set to a value of 6 to select the SLEEP signal.

a. When setting PSWC bit to 1 (default value), PSW is configured as an open drain pin with

approximately 1 Ω resistance. This allows the RV-1805-C3 to directly switch power with no external components for small systems, or to control a single external transistor for higher current switching. If the I2C master (i.e., the host controller) is powered down by the power switch, the IOPW bit should be set to insure that a floating bus does not corrupt the RV-1805-C3.

b. When setting PSWC bit to 0, PSW will be configured as a high true Sleep state which may be used

as an interrupt.

The Sleep Control State Machine in the Figure in Section SLEEP STATE receives several inputs which it uses to determine the current Sleep State:

- the indicator that power on reset state is finished and power is valid, i.e. the RV-1805-C3 is in

either the VDD Power state or the VBACKUP Power state.

2. SLP - the Sleep Request signal which is generated by a software access to the bit SLP.

3. VAL - the OR of the enabled valid interrupt request from the Alarm comparison, Countdown Timer, Watchdog Timer and External Interrupt (WDI pin). The Battery Low detection interrupt, the Autocalibration Failure interrupt and the XT Oscillator Failure interrupt are not integrated to the internal VAL information but also ORed to the internal IRQ signal.

4. TF- the timeout signal from the Countdown Timer, indicating that it has decremented to 0.

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RST

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

RUN STATE 4.17.1.

RUN is the normal operating state of the RV-1805-C3. PSW is 0,

is 1, SLP is 0, and SLF flag holds the state

of the previous Sleep. The SLF flag should be cleared by software before entering the SWAIT state.

SWAIT STATE (SLEEP_WAIT STATE) 4.17.2.

Software can put the chip to sleep by setting the SLP bit, as long as a valid interrupt is enabled (indicated by the internal status signal VAL being asserted high) (see SLP PROTECTION). If the SLW field is between 1 and 7 the Sleep Control State Machine moves to the SWAIT state and waits for between SLW and (SLW+1) times the ~8 ms periode. This allows software to perform additional cleanup functions after setting SLP before the MCU is shut down. Operation is the same in SWAIT as it is in RUN, and if an enabled operational interrupt occurs (combined interrupt signal IRQ) the Sleep Control State Machine returns to the RUN state and clears the SLP bit. PSW stay at

stay at 1 and the SLF flag is still 0.

If SLW is set to 0, the Sleep Control State Machine moves immediately to the SLEEP state. If the MCU is configured to be powered down in Sleep Mode, the I2C operation to write the Sleep Register must be the last instruction executed by the MCU.

SLEEP STATE 4.17.3.

Once the programmed number of periods has elapsed in the SWAIT state, the TF signal is asserted and the machine moves to the SLEEP state, putting the RV-1805-C3 into Sleep Mode. In this case PSW is asserted high,

and

is asserted low if SLRST = 1. Once an enabled operational interrupt occurs (combined interrupt signal IRQ), the Sleep Control State Machine returns to the RUN state, re-enables power and removes reset as appropriate. The SLF flag in the Sleep Register is set when the SLEEP state is entered, allowing software to determine if a SLEEP has occurred.

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RUN state

___ RST = 1 (RSTP = 0) PSW = 0 SLF = cleared to 0 SLP = 0

SWAIT state

___ RST = 1 (RSTP = 0) PSW = 0 SLF = 0 SLP = 1

SLEEP state

___ RST = 0 (if SLRST = 1) PSW = 1 SLF = 1 SLP = 1

IRQ

___ ___ SLP + VAL + STOP

____ POR

_____ SLP * VAL * (SLW=0) * STOP

SLP * VAL *

(SLW>0) *

__ ___ TF * IRQ

IRQ

___

TF * IRQ

___

IRQ

_____ STOP

Interrupt functions

VAL: Minimum one valid interrupt is enabled (internal status signal). IRQ: An enabled interrupt occurs (internal combined interrupt signal).

Bits and fields

SLP bit: Sleep Request signal SLW field: Number of ~8 ms waiting periods STOP bit: Stops clocking system SLF bit: Flag is set when the RV-1805-C3 enters SLEEP state. Can be cleared by software. TF bit: Countdown Timer Flag. Set when timer reaches zero.

Outputs

RST

PSW pin

+ logic OR * logic AND

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

Sleep Control State Machine:

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INT/CLK

RST

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

SLP PROTECTION 4.17.4.

Since going into Sleep Mode may prevent an MCU from accessing the RV-1805-C3, it is critical to insure that the RV-1805-C3 can receive an interrupt signal (combined interrupt signal IRQ). To guarantee this, the SLP signal cannot be set unless the STOP bit is 0 and at least one of the following interrupt functions are enabled (sets the internal status signal VAL to 1):

1. The AIE bit is 1, enabling an Alarm interrupt.

2. The TIE and the TE bits are 1, enabling a Countdown Timer interrupt.

3. The EIE bit is 1, enabling the External interrupt.

4. The WDM field is not zero and the WDS bit is zero, enabling a Watchdog Interrupt.

In addition, SLP cannot be set if there is an interrupt pending. Software should read the SLP bit after attempting to set it. If SLP is not asserted, the attempt to set SLP was unsuccessful either because a correct trigger was not enabled or because an interrupt was already pending. Once SLP is set, software should continue to poll it until the Sleep actually occurs, in order to handle the case where a trigger occurs before the RV-1805-C3 enters Sleep Mode.

PSWS, PSWB AND LKP 4.17.5.

If the PSWS field is set to the initial value of 7, the PSW pin will be driven with the static value of the PSWB bit which is initially zero. If this pin is used as the power switch, setting PSWB will remove power from the system and may prevent further access to the RV-1805-C3. In order to insure that this does not happen inadvertently, the LKP bit must be cleared in order to change the PSWB bit to a 1. Note that in this power switch environment the PSWS register field must not be written to any value other than 6 or 7, even if the PSW pin would remain at zero, because it is possible that a short high pulse could be generated on the PSW pin which could create a power down.

PIN CONTROL AND LEAKAGE MANAGEMENT (SLEEP CONTROL) 4.17.6.

Like most ICs, the RV-1805-C3 may draw unnecessary leakage current if an input pin floats to a value near the threshold or an output pin is pulled to a power supply. Because Sleep Mode can power down external devices connected to the RV-1805-C3, extra care must be taken to insure that any input or output pins are handled correctly to avoid extraneous leakage. The Output Control register includes bits to manage this leakage, which should be used as follows:

1. CLKSL (Bit 0, address 30h) should be cleared if the

pin is connected to a device which is

powered down in Sleep Mode.

2. RSTSL (Bit 3, address 30h) should be cleared if the

pin is connected to a device which is powered

down in Sleep Mode.

3. WDDS (Bit 5, address 30h) should be set if the WDI pin is connected to a device which is powered down in Sleep Mode.

4. X (Bit 1, address 30h) is unused, but has to be 0 to avoid extraneous leakage. If 0, an internal output is completely disconnected when the RV-1805-C3 is in Sleep Mode.

5. X (Bit 2, address 30h) is unused, but has to be 0 to avoid extraneous leakage. If 0, an internal output is completely disconnected when the RV-1805-C3 is in Sleep Mode.

6. X (Bit 4, address 30h) is unused, but must be set to 1 to avoid extraneous leakage. Disables an internal input when the RV-1805-C3 is in Sleep Mode.

The Oscillator Control register includes a bit to manage the I2C interface:

7. IOPW (Bit 2, address 1Ch) must be set to 1 to avoid extraneous leakage. If 1, the I2C interface pins are disabled in Sleep Mode. This is a particularly important function because there are multiple leakage paths in the I2C interface.

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IRQ

RV-1805-C3

MCU

PSW

I2C

INT/CLK

WDI

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

SYSTEM POWER CONTROL APPLICATIONS 4.18.

In addition to fundamentally low power RTC operation, the RV-1805-C3 includes the capability to effectively manage the power of other devices in a system. It allows the creation of extremely power efficient systems with minimal additional components. This configuration is typically used when the entire system is powered from a battery.

VSS POWER SWITCHED 4.18.1.

The following Figure illustrates the recommended implementation, in which the internal power switch of the RV1805-C3 is used to completely turn off the MCU and/or other system elements. In this case the PSW output is configured to generate the system sleep function, the PSWC bit is asserted to high and the SLRST bit is set to 0. Under normal circumstances, the PSW pin is pulled to VSS with approximately 1 Ω of resistance, so that the MCU receives full power. The MCU initiates a sleep operation by setting SLP to 1, and when the RV-1805-C3 enters the SLEEP state the PSW pin is opened and power is completely removed from the MCU. This results in significant additional power savings relative to the other alternatives because even very low power MCUs require more current in their lowest power state than the RV-1805-C3.

The RV-1805-C3 normally powers up selecting the PSWB bit to drive the PSW pin, and the default value of the PSWB bit is zero. This insures that the power switch is enabled at power up. If the power switch function is used, software should only change the PSW selection between PSWB (111b) and SLEEP (110b) to insure no glitches occur in the power switching function.

Switched VSS Power Control:

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RV-1805-C3

PSW

INT/CLK

I2C

IRQ

MCU

WDI

RST

RESET

RV-1805-C3

MCU

I2C

RST

WDI

RST

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

VDD POWER SWITCHED 4.18.2.

The following Figure illustrates the application in which an external transistor switch T is used to turn off power to the MCU. The SLP function operates identically to the VSS switched case above, but this implementation allows switching higher current and maintains a common ground. R can be on the order of megohms, so that negligible current is drawn when the circuit is active and PSW is low.

Switched VDD Power Control:

RESET DRIVEN 4.18.3.

The following Figure illustrates the application in which the RV-1805-C3 communicates with the system MCU using the reset function. In this case the MCU sets the SLRST bit so that when the RV-1805-C3 enters the SLEEP state,

it brings

low to reset the MCU, and initiates a sleep operation. When the trigger occurs, the RV-1805-C3 releases the MCU from reset, and may also generate an interrupt which the MCU can query to determine how reset was exited. Since some MCUs use much less power when reset, this implementation can save system power.

Reset Driven Power Control:

One potential issue with this approach is that many MCUs include internal pull-up resistors on their reset inputs, and the current drawn through that resistor when the reset input is held low is generally much higher than the MCU

would draw in its inactive state. Any additional pull-up resistor should be removed and the 1805-C3 should be configured like a push-pull output.

output of the RV-

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IRQ

RV-1805-C3

MCU

I2C

INT/CLK

WDI

INT/CLK

RST

INT

RV-1805-C3

MCU

PSW

I2C

INT/CLK

WDI

RESET or

WAKE

RST

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

INTERRUPT DRIVEN 4.18.4.

The following Figure illustrates the simplest application, in which the RV-1805-C3 communicates with the system MCU using an interrupt. The MCU can go into standby mode, reducing power somewhat, until the RV-1805-C3 generates an interrupt based on an alarm or a timer function. This produces smaller power savings than other alternatives, but allows the MCU to wake in the shortest time.

Interrupt Driven Power Control:

TYPICAL SYSTEM IMPLEMENTATION 4.19.

The following Figure is a more detailed view of a typical system using the VSS Power Switched approach. The VSS pin of the MCU, and potentially other system components, is switched using the PSW pin of the RV-1805-C3. The

pin of the RV-1805-C3 is connected to an interrupt input of the MCU, allowing the MCU to utilize the

RTC interrupt functions of the RV-1805-C3 when it is awake. The the reset input of the MCU, enabling the RV-1805-C3 to control power on reset and integrate an external MCU reset button RESET. The MCU controls the RV-1805-C3 over the I2C channel.

System Example:

output of the RV-1805-C3 is connected to

The key value of the RV-1805-C3 in this type of system is the ability to put the MCU into an off state, and providing a very rich variety of triggers which can cause the RV-1805-C3 to wake the MCU from the off state. There are a number of different triggers which may be useful.

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Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

ALARMS 4.19.1.

The system may require the MCU to wake up at particular times, which is accomplished by configuring the Alarm Interrupt function of the RV-1805-C3.

COUNTDOWN TIMER 4.19.2.

The system may require the MCU to wake up at periodic intervals which do not necessarily correspond to specific calendar times. The Countdown Timer of the RV-1805-C3 provides highly flexible time interval configuration to support this function.

WAKE BUTTON/SWITCH 4.19.3.

A very common requirement is the capability to wake the system with a manual input such as a pushbutton or switch, typified by the WAKE button in the System Example above. The external interrupt input WDI may be simply connected to the button. The WDI input includes a Schmitt trigger circuitry to enable clean interrupts. If additional debouncing of the input is required, the RV-1805-C3 provides direct access to the interrupt input pin to facilitate software implementations.

EXTERNAL DEVICE INPUT 4.19.4.

In some systems an external device such as a wakeup radio may provide a signal which must wake the MCU. The RV-1805-C3 external interrupt WDI pin provides this capability.

ANALOG INPUT 4.19.5.

Some systems include analog signals, such as light sensors or detectors on radio antennas, which must wake the MCU. The Analog Comparator function, which allows the voltage on the V

input of the RV-1805-C3 to be

BACKUP

compared with a configurable voltage threshold and generate an interrupt, can easily be used in this application, and it allows flexible configuration, both in voltage levels and in transition direction to support different environments. The Analog Comparator may also be used to provide a second external digital interrupt if necessary by selecting the proper digital threshold.

BATTERY LOW DETECTION 4.19.6.

The Analog Comparator can provide a battery low detection function. In this case the VDD pin would be tied to the V

pin, and the thresholds would be adjusted to insure that the Battery Low interrupt occurs prior to any

BACKUP

Brownout Detection on the VDD input. This allows software to prepare for a potential battery failure in advance without having to poll the battery level.

ERRORS 4.19.7.

Any failure interrupt in the RV-1805-C3 may also be configured to wake the MCU. This can be particularly valuable for an XT Oscillator Failure detection, when software may need to respond to the error in order to report the problem quickly.

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Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

SAVING PARAMETERS 4.20.

If the MCU is powered down in Sleep Mode, there is often some data which must be preserved until the next power up. The internal RAM of the RV-1805-C3 is always available, so software can easily save any necessary parameters prior to entering Sleep Mode and retrieve them when the MCU wakes up.

POWER SWITCH ELECTRICAL CHARACTERISTICS 4.21.

The power switch on the RV-1805-C3 PSW pin has a typical on resistance of 1 Ω over the full temperature range so that currents up to 50 mA may be handled without appreciable voltage drop. This allows the RV-1805-C3 to switch power to multiple devices in most systems, which can be particularly important for components without internal Sleep functions. If the PSW pin is not used as a power switch, the maximum leakage current of the ~1 Ω switch is less than 250 pA at 25 °C.

AVOIDING UNEXPECTED LEAKAGE PATHS 4.22.

One potential problem which can occur when the RV-1805-C3 powers other devices down is that unexpected leakage paths can be created between the powered RV-1805-C3 and the unpowered device. The RV-1805-C3 can be configured to disable inputs and outputs in Sleep Mode to prevent leakage. In general, any input or output pin connected to a device which is powered down should be disabled. Any pins which remain powered in Sleep Mode, such as pushbutton inputs used to wake the system, must not be disabled. See chapter 4.17.6 PIN CONTROL AND LEAKAGE MANAGEMENT (SLEEP CONTROL)

SYSTEM POWER ANALYSIS 4.23.

The RV-1805-C3 can significantly improve the power characteristics of many different types of systems. A specific example will be presented, and several other generalizations can be made from this. The fundamental advantage provided by the RV-1805-C3 is that it allows the system designer to essentially ignore the sleep current of other system components, which allows the utilization of components which have be optimized for other parameters, such as active power, cost or functionality.

USING AN EXTERNAL RTC WITH POWER MANAGEMENT 4.23.1.

The key element in any system power analysis is the usage profile, and for this example we assume the system is active for T when the system is inactive. The average current I

and inactive for T

act

. I

is the current drawn when the system is active, and I

inact

act

is therefore:

avg

is the current drawn

inact

= (T

* I

avg

act

+ T

inact

* I

inact

)/(T

act

+ T

inact

)

An example will use a PIC16LF1947 MCU, which is highly optimized for low power operation. This MCU draws 80 nA in Sleep Mode, 1.8 µA in Sleep Mode with the internal oscillator and RTC active, and 120 µA in 500 KHz active mode. Assume a usage profile where the system in active for 1 second every 30 minutes, so that T

is 1 and T

act

inact

is 1799. If this MCU is used alone and supplies the RTC functions, the average current for the usage profile is: I

= (1 * 120 µA + 1799* 1.8 µA)/1800 = 1.865 µA // PIC alone

avg

If the RV-1805-C3 is used to provide the RTC functionality in RC Autocalibration Mode (<20 nA continuous current, when TA = 25°C, V

= 3.0V, ACP = 1024 seconds) and the PIC is placed into Sleep Mode, the average current for

the usage profile is dramatically lower: I

= (1 * 120 µA + 1799* 80 nA)/1800 + 20 nA = 166 nA // PIC in Sleep mode & RV-1805-C3

avg

This is a significant improvement, but the current can be further reduced by having the RV-1805-C3 switch power to the MCU. The resulting average current is ~50% lower:

= (1 * 120 µA + 1799* 0 nA)/1800 + 20 nA = 86 nA // PIC switched & RV-1805-C3

avg

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TCS DIODE

ROUT

3 kΩ 6 kΩ

11 kΩ

BACKUP

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

MANAGING MCU ACTIVE POWER 4.23.2.

In many cases, the duration of the active time is a function of how much processing must be accomplished, and can therefore be assumed to be a linear function of the MCU clock frequency in active mode. The examples in the previous section assumed that the MCU ran for 1 second at 500 KHz, so 500’000 cycles of an 8-bit processor were required. Like most MCUs, the PIC has a relatively constant active current as a function of clock frequency, so using a higher internal frequency in the same MCU would have little effect on the overall power. However, there may be other MCUs (such as those with 32-bit processors) which have better active power efficiency but poor sleep power, and power switching with the RV-1805-C3 eliminates any sleep power considerations.

4.23.3.

LOWER COST MCUs

Lower cost MCUs often have poor sleep power characteristics relative to sleep optimized parts. Since the RV1805-C3 eliminates sleep power considerations, these lower cost processors may provide equivalent overall average power at significant cost savings.

HIGH PERFORMANCE PROCESSORS 4.23.4.

In some applications very high performance processors such as DSPs must be used due to real time processing requirements. These processors are generally not optimized for sleep performance, but they may be used in applications with low duty cycles. One example of this is fingerprint recognition, which is rarely accessed but must provide very fast response with complex processing. The RV-1805-C3 power management functions enable a system design where the processor is powered down the vast majority of the time, providing low average power combined with very high instantaneous performance.

TRICKLE CHARGER 4.24.

The devices supporting the V connected to the V

pin to be charged from the power supply connected to the VDD pin. The circuit of the

BACKUP

pin include a trickle charging circuit which allows a battery or supercapacitor

BACKUP

Trickle Charger is shown in the following Figure. The Trickle Charger configuration is controlled by the 20h - Trickle Charge register (see ANALOG CONTROL REGISTERS). The Trickle Charger is enabled if a) the TCS field is 1010, b) the DIODE field is 01 or 10 and c) the ROUT field is not 00. A diode, with a typical voltage drop of 0.6V, is inserted in the charging path if DIODE is 10. A Schottky diode, with a typical voltage drop of 0.3V, is inserted in the charging path if DIODE is 01. The series current limiting resistor is selected by the ROUT field as shown in the figure.

Trickle Charger:

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Countdown

Timer

TIRQ

Alarms

SQWS

Mux

Calendar

Counters

CLKB

CLKS

Mux

AIRQ

IRQ

OR + Mask

PSWS

Mux

WDI

PSWB

IRQ

Watchdog

Timer

Sleep

Control

OFIRQ

ACIRQ

BLIRQ

PSW

RST

Power

Brown

Out

SQW

INT/CLK

RST

Analog

Compare

BACKUP

analog

WIRQ

EIRQ

RST

OR +

Mask

SLEEP

Operation

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

5. DIGITAL ARCHITECTURE SUMMARY

The following Figure illustrates the overall architecture of the pin inputs and outputs of the RV-1805-C3. Digital Architecture Summary:

75/98

Micro Crystal

SYMBOL

PARAMETER

TEST

MIN

TYP

MAX

UNIT

VDD

Power Supply Voltage

-0.3 3.8

BACKUP

Backup Supply Voltage

-0.3 3.8

Input voltage

VDD Power state

-0.3

VDD+ 0.3

Input voltage

VBACKUP Power state

-0.3

BACK

+ 0.3

Output voltage

VDD Power state

-0.3

VDD+ 0.3

Output voltage

VBACKUP Power state

-0.3

BACK

+ 0.3

Input current

-10 10

Output current

-20 20

OPC

PSW Output continuous current

OPP

PSW Output pulsed current

1 second pulse

150

ESD

ESD Voltage CDM

(1)

±500

HBM

(2)

±4000

ILU

Latch-up Current

100

STG

Storage Temperature

-55 125

°C

TOP

Operating Temperature

-40 85

°C

SLD

Lead temperature

Hand soldering for 10 seconds

300

°C

REF

Reflow soldering temperature

Reflow profile per JEDEC JSTD-020D

260

°C

(1)

CDM – Charged-Device Model

(2)

HBM – Human Body Model

Power State

POR

DDST

DDRST

VDD Power

DDST

POR

DDSWF

VDD Power VBACKUP Power

BACKUPSW

DDSWR

VDD Power

DDSWF

BACKUPRST

VBACKUP Power POR

BACKUP

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

6. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS 6.1.

The following Table lists the absolute maximum ratings. Absolute Maximum Ratings:

POWER SUPPLY PARAMETERS 6.2.

The following Figure and Table describe the power supply and switchover parameters. See POWER CONTROL AND SWITCHING for a detailed description of the operations.

Power Supply Switchover:

76/98

Micro Crystal

SYMBOL

PARAMETER

PWR

TYPE

POWER STATE

TEST

CONDITIONS

MIN

TYP

MAX

UNIT

VDD

System Power Voltage

VDD

Static

VDD Power

Clocks operating and RAM and registers retained

1.5 3.6

DDIO

VDD I2C Interface Voltage

VDD

Static

VDD Power

I2C operation

1.5 3.6

DDST

VDD Start-up Voltage

(1)

VDD

Rising

POR -> VDD Power

1.6

DDRST

VDD Reset Voltage

VDD

Falling

VDD Power -> POR

BACKUP

BACKUP,MIN

or no

BACKUP

1.3

1.5

DDSWR

VDD Rising Switch-over Threshold Voltage

VDD

Rising

VBACKUP Power

-> VDD Power

BACKUP

≥ V

BACKRST

1.6

1.7

DDSWF

VDD Falling Switch- over Threshold Voltage

VDD

Falling

VDD Power -> VBACKUP Power

BACKUP

≥

BACKSW,MIN

1.2

1.5 V

DDSWH

VDD Switchover Threshold Hysteresis

(2)

VDD

Hyst.

VDD Power <-> VBACKUP Power

70 mV

DDFS

VDD Falling Slew Rate to switch to VBACKUP

state

(4)

VDD

Falling

VDD Power -> VBACKUP Power

VDD < V

DDSW,MAX

0.7

1.4 V/ms

BACKUP

Backup Voltage

BACKUP

Static

VBACKUP Power

Clocks operating and RAM and registers retained

1.4 3.6

BACKSW

Backup Switchover Voltage Range

(5)

BACKUP

Static

VDD Power -> VBACKUP Power

1.6 3.6

BACKRST

Falling Backup POR Voltage

(7)

BACKUP

Falling

VBACKUP Power

-> POR

VDD < V

DDSWF

1.1

1.4

BMRG

BACK

Margin above

(3)

BACKUP

Static

VBACKUP Power

200

BACKESR

BACK

supply series

resistance

(6)

BACKUP

Static

VBACKUP Power

1.0

1.5 kΩ

(1)

VDD must be above V

DDST

to exit the POR state, independent of the V

BACKUP

voltage.

(2)

Difference between V

DDSWR

and V

DDSWF

(3)

BACKUP

must be higher than VDD by at least this voltage to insure the RV-1805-C3 remains in the VBACKUP Power state.

(4)

Maximum VDD falling slew rate to guarantee correct switchover to VBACKUP Power state. There is no VDD falling slew rate

requirement if switching to the VBACKUP power source is not required.

(5)

BACKUP

voltage to guarantee correct transition to VBACKUP Power state when VDD falls.

(6)

Total series resistance of the power source attached to the V

BACKUP

pin. The optimal value is 1.5 kΩ, which may require an external

resistor. V

BACKUP

power source ESR (Equivalent Series Resistance) + external resistor value = 1.5 kΩ.

(7)

BACKRST

is also the static voltage required on V

BACKUP

for register data retention.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

For all tables, TA = -40 °C to 85 °C, TYP values at 25 °C. Power Supply and Switchover Parameters:

77/98

Micro Crystal

SYMBOL

PARAMETER

TEST

CONDITIONS

VDD

MIN

TYP

MAX

UNIT

VT+

Positive-going Input Threshold Voltage

3.0V

1.5

2.0

1.8V

1.1

1.25

VT-

Negative-going Input Threshold Voltage

3.0V

0.8

0.9

1.8V

0.5

0.6

ILEAK

Input leakage current

3.0V

0.02

Input capacitance

3 pF

DSON

PSW output resistance to VDD

PSW Enabled

1.7V 1.7

5.8

Ω

1.8V 1.6

5.4

3.0V 1.1

3.8

3.6V 1.05

3.7

OLEAK

Output leakage current

1.7V – 3.6V

0.02

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

FXT

Crystal Frequency

32.768

kHz

FOF

XT Oscillator failure detection frequency

8 kHz

RCC

Calibrated RC Oscillator Frequency

(1)

Factory Calibrated at 25°C, VDD = 2.8V

64 Hz

RCU

Uncalibrated RC Oscillator Frequency

Calibration Disabled (OFFSETR = 0) – 128 Hz level

122

220

RCCC

Uncalibrated RC Oscillator cycle-to-cycle jitter, |Median|

Calibration Disabled (OFFSETR = 0) – 128 Hz level

2000

ppm

Calibration Disabled (OFFSETR = 0) – 1 Hz level

500

RC Oscillator cycle-to-cycle jitter, MIN, MAX

128 Hz level at 25°C

1 1

128 Hz level, -10°C to 70°C

3.5 3.5

128 Hz level, -40°C to 85°C

10 10

AXT

XT mode digital calibration accuracy

(1)

Calibrated at an initial temperature and voltage. Factory Calibrated at 25°C, VDD = 3.0V

-2 +2

ppm

AAC

Autocalibration mode timing accuracy, 512 second period,

TA = -10°C to 60°C

(1)

24 hour run time

ppm

1 week run time

1 month run time

1 year run time

TAC

Autocalibration mode operating temperature

(2)

-10 60

°C

(1)

Timing accuracy is specified at 25°C after digital calibration of the internal RC oscillator and digital calibration of the 32.768 kHz crystal. The 32.768 kHz tuning fork crystal has a negative temperature coefficient with a parabolic frequency deviation, which can result in a change of up to 150 ppm across the entire operating temperature range of -40°C to 85°C in XT mode. Autocalibration mode timing accuracy is specified relative to XT mode timing accuracy from -10°C to 60°C.

(2)

Outside of this temperature range, the RC oscillator frequency change due to temperature may be outside of the allowable RC digital calibration range (+/-12%) for autocalibration mode. When this happens, an autocalibration failure will occur and the ACF interrupt flag is set. The RV-1805-C3 should be switched to use the XT oscillator as its clock source when this occurs. Please see the AUTOCALIBRATION FAILURE section for more details.

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

OPERATING PARAMETERS 6.3.

The following Table lists the operating parameters. For this table, TA = -40 °C to 85 °C, TYP values at 25 °C. Operating Parameters:

OSCILLATOR PARAMETERS 6.4.

The following Table lists the oscillator parameters. For this Table, TA = -40 °C to 85 °C unless otherwise indicated. VDD = 1.7 to 3.6V, TYP values at 25 °C and 3.0V. See also XT FREQUENCY CHARACTERISTICS.

Oscillator Parameters:

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Micro Crystal

57.5

62.5

67.5

72.5

Frequency

(Hz)

Temperature (°C)

VDD = 1.8V

VDD = 3.0V

-40 -30 -20 -10 0

10 20 30

40 50

60 70 80

Autocalibration mode operating temperature (-10 to 60°C)

57.5

62.5

67.5

72.5

Frequency

(Hz)

Temperature (°C)

VDD = 1.8V

VDD = 3.0V

-40 -30 -20 -10 0

10 20 30

40 50

60 70 80

Autocalibration mode operating temperature (-10 to 60°C)

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

The following Figure shows the typical calibrated RC oscillator frequency variation vs. temperature. The RC oscillator is factory calibrated at 2.8V, 25°C (OFFSETR = Preconfigured reset value).

Factory Calibrated RC Oscillator, Typical Frequency Variation vs. Temperature (64 Hz level is modified):

The following Figure shows the typical uncalibrated RC oscillator frequency variation vs. temperature. Uncalibrated RC Oscillator at 64 Hz level, Typical Frequency Variation vs. Temperature:

79/98

Micro Crystal

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

ΔF/F

Frequency accuracy

TA = +25°C, Calibration Disabled (OFFSETX = 0)

±100

(1)

ppm

ΔF/F

Frequency vs. temperature characteristics

OPR

= -40°C to +85°C

-0.035

ppm

°C

OPR-T0

)2 ±10%

ppm

Turnover temperature

+25 ±5

°C

ΔF/F

Aging first year max.

TA = +25°C

±3

ppm

START

Oscillator start-up voltage

TA = -40 °C to 85 °C

1.6

START

Oscillator start-up time

VDD = 1.7V–3.6V

1.0 s

CLKOUT

CLKOUT duty cycle

CLKOUT

= 32.768 kHz

TA = +25°C

60 ±10

(1)

The XT mode digital calibration accuracy is +/-2 ppm, see OSCILLATOR PARAMETERS.

-180.0

-160.0

-140.0

-120.0

-100.0

-80.0

-60.0

-40.0

-20.0

0.0

20.0

-60 -40 -20 0 20 40 60 80 100

T [°C]

ΔF/F [ppm]

-0.035 * (T-T0)2 ppm (±10%)

T0 = 25°C (±5°C)

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

XT FREQUENCY CHARACTERISTICS 6.5.

For this Table, TA = -40 °C to 85 °C unless otherwise indicated. VDD = 1.7 to 3.6V, TYP values at 25 °C and 3.0V, f

= 32.768 kHz.

OSC

XT Frequency Characteristics:

XT FREQUENCY VS. TEMPERATURE CHARACTERISTICS 6.5.1.

80/98

Micro Crystal

SYMBOL

PARAMETER

TEST CONDITIONS

VDD

MIN

TYP

MAX

UNIT

VDD:I2C

VDD supply current during I2C burst read/write

400kHz bus speed, 2.2k pull-up resistors on SCL/SDA

(1)

3.0V 6

µA

1.8V 1.5

VDD:XT

VDD supply current in XT oscillator mode.

Time keeping mode with XT oscillator running

(2)

3.0V 60

330

1.8V 57

290

VDD:RC

VDD supply current in RC oscillator mode.

Time keeping mode with only the RC oscillator running (XT

oscillator is off)

(2)

3.0V 17

220

1.8V 14

170

VDD:ACAL

Average VDD supply current in Autocalibrated RC oscillator mode.

Time keeping mode with only RC oscillator running and Autocalibration enabled. ACP =

512 seconds

(2)

3.0V 22

235

1.8V 18

190

VDD:CK32

Additional VDD supply current with

INT/CLK

at 32.768 kHz.

Time keeping mode with XT oscillator running, 32.768 kHz

square wave on

INT/CLK

(3)

3.0V 0.71

µA

1.8V 0.34

VDD:CK64

Additional VDD supply current with

INT/CLK

at 64 Hz.

All time keeping modes, 64 Hz square wave on

INT/CLK

(3)

3.0V 0.6

1.8V 0.3

(1)

Excluding external peripherals and pull-up resistor current. All other inputs (besides SDA and SCL) are at 0V or VDD. Test conditions: Continuous burst read/write, 55h data pattern, 25 µs between each data byte, 20 pF load on each bus pin.

(2)

All inputs and outputs are at 0V or VDD.

(3)

All inputs and outputs except

INT/CLK

are at 0V or VDD. 15 pF load on

INT/CLK

, pull-up resistor current not included.

100

110

120

130

VDD

Power

State,

XT Mode Current

(nA)

Temperature (°C)

VDD = 1.8V

VDD = 3.0V

-40 -30 -20 -10 0

10 20 30

40 50

60 70 80

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

VDD SUPPLY CURRENT 6.6.

The following Table lists the current supplied into the VDD power input under various conditions. For this table, TA =

-40 °C to 85 °C, V VDD Supply Current:

= 0 V to 3.6 V, TYP values at 25 °C, VDD Power state.

BACKUP

The following Figure shows the typical VDD power state operating current vs. temperature in XT mode. Typical VDD Current vs. Temperature in XT Mode:

81/98

Micro Crystal

VDD

Power

State,

Mode

Current

(nA)

Temperature (°C)

VDD = 1.8V

VDD =

3.0V

-40 -30 -20 -10 0

10 20 30

40 50

60 70 80

VDD

Power State,

Autocal Mode

Current (nA)

Temperature (°C)

VDD = 1.8V

VDD = 3.0V

-40 -30 -20 -10 0

10 20 30

40 50

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

The following Figure shows the typical VDD power state operating current vs. temperature in RC mode. Typical VDD Current vs. Temperature in RC Mode:

The following Figure shows the typical VDD power state operating current vs. temperature in RC Autocalibration mode.

Typical VDD Current vs. Temperature in RC Autocalibration Mode, ACP = 512 seconds:

82/98

Micro Crystal

1.5

RC Autocalibration Mode, ACP = 512 sec.

XT Oscillator Mode

RC Oscillator Mode

2 2.5

3 3.5

VDD Voltage (V)

VDD Power State Current (nA)

TA = 25 °C

1.8

2.2

2.4 2.6 2.8 3 3.2

3.4 3.6

VDD Voltage (V)

Current (µA)

TA = 25°C

I2C Burst Read/Write

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

The following Figure shows the typical VDD power state operating current vs. voltage for XT Oscillator and RC Oscillator modes and the average current in RC Autocalibrated mode with ACP = 512 seconds.

Typical VDD Current vs. Voltage, Different Modes of Operation:

The following Figure shows the typical VDD power state operating current during continuous I2C burst read and write activity. Test conditions: TA = 25 °C, 55h data pattern, 25 µs between each data byte, 20 pF load on each bus pin, pull-up resistor current not included.

Typical VDD Current vs. Voltage, I2C Burst Read/Write:

83/98

Micro Crystal

INT/CLK

0.2

0.4

0.6

0.8

1.0

1.8

Current (µA)

VDD Voltage (V)

TA = 25°C

2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

The following Figure shows the typical additional VDD power state operating current with a 32.768 kHz clock output on the capacitive load on the

pin. Test conditions: TA = 25 °C. All inputs and outputs except

pin, pull-up resistor current not included.

are at 0 V or VDD. 15 pF

Typical additional VDD Current vs. Voltage, 32.768 kHz Clock Output:

84/98

Micro Crystal

SYMBOL

PARAMETER

TEST CONDITIONS

VDD

BACK

MIN

TYP

MAX

UNIT

VBACK:XT

BACKUP

supply current in XT

oscillator mode.

Time keeping mode with XT oscillator running

(1)

< V

DDSWF

3.0V 63

330

1.8V 60

290

VBACK:RC

BACKUP

supply current in RC

oscillator mode.

Time keeping mode with only the RC oscillator running (XT

oscillator is off)

(1)

< V

DDSWF

3.0V 19

220

1.8V 16

170

VBACK:ACAL

BACKUP

supply current in Autocalibrated RC oscillator mode.

Time keeping mode with the RC oscillator running and Autocalibration enabled.

ACP = 512 seconds

(1)

< V

DDSWF

3.0V 25

235

1.8V 21

190

VBACK:VDD

BACKUP

supply current in VDD powered mode.

VDD powered mode

(1)

1.7-3.6 V

3.0V

-5

0.6

1.8V

-10

0.5

(1)

Test conditions: All inputs and outputs are at 0V or VDD.

100

110

120

130

VBACKUP Power State, XT Mode Current

(nA)

Temperature (°C)

BACKUP

= 1.8V

BACKUP

3.0V

-40 -30 -20 -10 0

10 20 30

40 50

60 70 80

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

BACKUP

The following Table lists the current supplied into the V

SUPPLY CURRENT 6.7.

power input under various conditions. For this table,

BACKUP

TA = -40 °C to 85 °C, TYP values at 25 °C, MAX values at 85 °C, VBACKUP Power state. V

Supply Current:

BACKUP

The following Figure shows the typical VBACKUP power state operating current vs. temperature in XT mode. Typical V

Current vs. Temperature in XT Mode:

BACKUP

85/98

Micro Crystal

VBACKUP Power

State,

Mode

Current (nA)

Temperature (°C)

BACKUP

= 1.8V

BACKUP

= 3.0V

-40 -30 -20 -10 0

10 20 30

40 50

60 70 80

VBACKUP Power State,

Autocal Mode

Current (nA)

Temperature (°C)

BACKUP

= 1.8V

BACKUP

= 3.0V

-40 -30 -20 -10 0

10 20 30

40 50

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

The following Figure shows the typical VBACKUP power state operating current vs. temperature in RC mode. Typical V

Current vs. Temperature in RC Mode:

BACKUP

The following Figure shows the typical VBACKUP power state operating current vs. temperature in RC Autocalibration mode.

Typical V

86/98

Current vs. Temperature in RC Autocalibration Mode, ACP = 512 seconds:

BACKUP

Micro Crystal

1.5

TA = 25°C

BACKUP

Current (nA)

XT Oscillator Mode

RC Autocalibration Mode, ACP = 512 sec.

RC Oscillator Mode

BACKUP

Voltage (V)

2 2.5 3 3.5

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.5

TA = 25°C, VDD = 1.7V

BACKUP

Current (nA)

BACKUP

Voltage (V)

2.5 3 3.5

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

The following Figure shows the typical VBACKUP power state operating current vs. voltage for XT Oscillator and RC Oscillator modes and the average current in RC Autocalibrated mode with ACP = 512 seconds, VDD = 0 V.

Typical V

Current vs. Voltage, Different Modes of Operation:

BACKUP

The following Figure shows the typical V

current when operating in the VDD power state, VDD = 1.7 V.

BACKUP

Typical V

87/98

Current vs. Voltage in VDD Power State:

BACKUP

Micro Crystal

SYMBOL

PARAMETER

BREF

MIN

TYP

MAX

UNIT

BRF

BACKUP

falling threshold

0111

2.3

2.5

3.3 V 1011

1.9

2.1

2.8

1101

1.6

1.8

2.5

1111 1.4

BRR

BACKUP

rising threshold

0111

2.6

3.0

3.4 V 1011

2.1

2.5

2.9

1101

1.9

2.2

2.7

1111 1.6

BRH

BACKUP

threshold hysteresis

0111 0.5

V 1011 0.4 1101 0.4

1111 0.2

BREF

BREF/BPOL change to BBOD valid

All valid BREF

values

1000 ms

TBR

BACKUP

analog comparator recommended operating temperature range

-20 70

°C

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

BREF ELECTRICAL CHARACTERISTICS 6.8.

The following Table lists the parameters of the V

voltage thresholds. BREF values other than those listed in

BACKUP

the table are not supported. For this table, TA = -20 °C to 70 °C, TYP values at 25 °C, VDD = 1.7 to 3.6V. BREF Parameters:

88/98

Micro Crystal

BUF

SCL

SDA

HD:STA

LOW

RISE

SDA

SU:STA

HD:DAT

HIGH

SU:DAT

SU:STO

FALL

SYMBOL

PARAMETER

VDD

MIN

TYP

MAX

UNIT

SCL

SCL input clock frequency

1.7V-3.6V

10 400

kHz

LOW

Low period of SCL clock

1.7V-3.6V

1.3

µs

HIGH

High period of SCL clock

1.7V-3.6V

600

RISE

Rise time of SDA and SCL

1.7V-3.6V

300

FALL

Fall time of SDA and SCL

1.7V-3.6V

300

HD:STA

START condition hold time

1.7V-3.6V

600

SU:STA

START condition setup time

1.7V-3.6V

600

SU:DAT

SDA setup time

1.7V-3.6V

100

HD:DAT

SDA hold time

1.7V-3.6V 0 ns

SU:STO

STOP condition setup time

1.7V-3.6V

600

BUF

Bus free time before a new transmission

1.7V-3.6V

1.3

µs

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

I2C AC ELECTRICAL CHARACTERISTICS 6.9.

The following Figure and Table describe the I2C AC electrical parameters. I2C AC Parameter Definitions:

For the following Table, TA = -40 °C to 85 °C, TYP values at 25 °C. I2C AC Electrical Parameters:

89/98

Micro Crystal

INT/CLK

VL:CLK

LOW:VDD

VH:CLK

DDRST

DDST

XTST

INT/CLK

SYMBOL

PARAMETER

VDD

MIN

TYP

MAX

UNIT

LOW:VDD

Low period of VDD to insure a valid POR

1.7V-3.6V 85 °C 0.1

s 25 °C 0.1

-20 °C 1.5

-40 °C 10

VL:CLK

VDD low to

INT/CLK

low

1.7V-3.6V 85 °C 0.1

s 25 °C 0.1

-20 °C 1.5

-40 °C 10

VH:CLK

VDD high to

INT/CLK

high

1.7V-3.6V 85 °C 0.4

s 25 °C 0.5

-20 °C 3

-40 °C 20

XTST

INT/CLK

high to XT oscillator start

1.7V-3.6V 85 °C 0.4

s 25 °C 0.4

-20 °C 0.5

-40 °C 1.5

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

POWER ON AC ELECTRICAL CHARACTERISTICS 6.10.

The following Figure and Table describe the power on AC electrical characteristics for the oscillator.

Power On AC Electrical Characteristics:

For the following Table, TA = -40 °C to 85 °C, V

BACKUP

< 1.2 V

Power On AC Electrical Parameters:

pin and XT

90/98

Micro Crystal

RST

DDRST

VL:NRST

LOW:VDD

VH:NRST

DDST

RST

SYMBOL

PARAMETER

VDD

MIN

TYP

MAX

UNIT

LOW:VDD

Low period of VDD to insure a valid POR

1.7V-3.6V

85°C 0.1

25°C 0.1 -20°C 1.5

-40°C 10

VL:NRST

VDD low to

RST

low

1.7V-3.6V

85°C 0.1

25°C 0.1 -20°C 1.5

-40°C 10

VH:NRST

VDD high to

RST

high

1.7V-3.6V

85°C 0.5

25°C 0.5 -20°C 3.5

-40°C 25

Extrem Low Power Real Time Clock / Calendar Module RV-1805-C3

AC ELECTRICAL CHARACTERISTICS 6.11.

The following Figure and Table describe the

AC Parameter Characteristics:

For the following Table, TA = -40 °C to 85 °C, V

AC Electrical Parameters:

AC electrical characteristics.

< 1.2 V.

BACKUP

91/98

Micro Crystal

RV-1805-C3 MCU

WDI

RST

RESET

Cap_RC

47 pF

SCL

SDA

SCL

SDA

10 nF

INT/CLK

BACKUP

PSW

A 10 nF decoupling capacitor is recommended close to the device.

INT/CLK

RST

and interface lines SCL, SDA are open drain and require pull-up resistors to V

DD.

INT/CLK

offers selectable frequencies 32.768 kHz to 1/60 Hz for application use. If not used, it is

recommended to disable

INT/CLK

for optimized current consumption (SQWE = 0 and CLKB = 1).

A 47 pF ceramic capacitor must be placed between the Cap_RC pin and VSS for improved Autocalibration

mode timing accuracy.

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7. APPLICATION INFORMATION

OPERATING RV-1805-C3 7.1.

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RV-1805-C3 MCU

RST

RESET

Cap_RC

47 pF

SCL

SDA

SCL

SDA

INT/CLK

Main

Battery

1.5 kΩ

BACKUP

10 nF

Backup

Battery/

Supercap

WDI

PSW

Total series resistance of the power source attached to the V

BACKUP

pin. The optimal value is 1.5 kΩ,

which may require an external resistor. V

BACKUP

power source ESR (Equivalent Series Resistance) + external resistor value = 1.5 kΩ. In particular when using a Lithium Battery it is recommended to insert a protection resistor to limit battery current and to prevent damage in case of soldering issues causing short between supply pins.

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OPERATING RV-1805-C3 WITH BACKUP BATTERY/SUPERCAP 7.2.

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Maximum Reflow Conditions in accordance with IPC/JEDEC J-STD-020C “Pb-free”

Time

Temperature

t 25°C to Peak

Ramp-up

Preheat

Tsmin

Critical Zone TL to T

Tsmax

Ramp-down

Temperature Profile

Symbol

Condition

Unit

Average ramp-up rate

(Ts

max

to Tp)

3°C / second max

°C / s

Ramp down Rate

cool

6°C / second max

°C / s

Time 25°C to Peak Temperature

to-peak

8 minutes max

min

Preheat

Temperature min

min

150

°C

Temperature max

max

200

°C

Time Ts

min

to Ts

max

60 – 180

sec

Soldering above liquidus

Temperature liquidus

217

°C

Time above liquidus

60 – 150

sec

Peak temperature

Peak Temperature

260

°C

Time within 5°C of peak temperature

20 – 40

sec

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8. RECOMMENDED REFLOW TEMPERATURE (LEADFREE SOLDERING)

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RV-1805-C3 Package:

Package dimensions (bottom view): Recommended solder pad layout:

max

0,8

3,7

0,3

0,8 0,8 0,8 0,8

0,5

3,7

10 9 8 7 6

1 2 3 4 5

Metal lid is connected to VSS (pin #6) Tolerances: unless otherwise specified ± 0.1mm

Drawing: RV-1805-C3_Pack-drw_20181025

Laser marking RV-1805-C3 Package: (top view)

#1 #5

#6#10

Pin 1 Index

Product Date Code

Part Designation

M843A1

1805

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9. PACKAGE

DIMENSIONS AND SOLDERPADS LAYOUT 9.1.

All dimensions in mm typical.

MARKING AND PIN #1 INDEX 9.2.

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Reel: 7” = 178 mm

178

max. 17

min. 12.4

Ø 13

Product Label

768

kHz

Carrier Tape:

Material: Polycarbonate, conductive Width: 12 mm Tape Leader and Trailer: Minimum length 300 mm

±0,05

±0,1

3,95

±0,1

5,5

±0,05

1,75

±0,1

0,28

±0,02

2,73

±0,1

0,061

Cover Tape

0,341

±0,05

+0,3

-0,1

All dimensions are in mm RV-1805-C3_Tape-drw_20181025

Direction of feed

1,03

±0,1

1805

Cover Tape:

Tape: Polypropylene, 3M™ Universal Cover Tape (UCT) Adhesive Type: Pressure sensitive, Synthetic Polymer Thickness: 0.061 mm

Peel Method: Medial section removal, both lateral stripes remain on carrier

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10. PACKING & SHIPPING INFORMATION

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11. HANDLING PRECAUTIONS FOR CRYSTALS OR MODULES WITH EMBEDDED CRYSTALS

The built-in tuning-fork crystal consists of pure Silicon Dioxide in crystalline form. The cavity inside the package is evacuated and hermetically sealed in order for the crystal blank to function undisturbed from air molecules, humidity and other influences.

Shock and vibration:

Keep the crystal / module from being exposed to excessive mechanical shock and vibration. Micro Crystal guarantees that the crystal / module will bear a mechanical shock of 5000g / 0.3 ms.

The following special situations may generate either shock or vibration:

Multiple PCB panels - Usually at the end of the pick & place process the single PCBs are cut out with a router. These machines sometimes generate vibrations on the PCB that have a fundamental or harmonic frequency close to 32.768 kHz. This might cause breakage of crystal blanks due to resonance. Router speed should be adjusted to avoid resonant vibration.

Ultrasonic cleaning - Avoid cleaning processes using ultrasonic energy. These processes can damages crystals due to mechanical resonance of the crystal blank.

Overheating, rework high temperature exposure:

Avoid overheating the package. The package is sealed with a seal ring consisting of 80% Gold and 20% Tin. The eutectic melting temperature of this alloy is at 280°C. Heating the seal ring up to >280°C will cause melting of the metal seal which then, due to the vacuum, is sucked into the cavity forming an air duct. This happens when using hot-air-gun set at temperatures >300°C.

Use the following methods for rework:

 Use a hot-air- gun set at 270°C.  Use 2 temperature controlled soldering irons, set at 270°C, with special-tips to contact all solder-joints from

both sides of the package at the same time, remove part with tweezers when pad solder is liquid.

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Date

Revision #

Revision Details

July 2014

2.0

First release

January 2015

2.1

- Changed 41 variable names

- Updated Register Function Descriptions

- Completed Standard and Alternate RAM

- Added two's complement and ppm values for OFFSETX and OFFSETR

- Modified application examples (PSW pin)

- Modified interrupt names

- Completed INTERRUPT SUMMARY

- Completed Digital Architecture Summary

- Completed Sleep State Machine

- Added SLW table

- Clarified DETAILED FUNCTIONAL DESCRIPTION

- Completed XT OSCILLATOR DIGITAL CALIBRATION

- Completed RC OSCILLATOR DIGITAL CALIBRATION

- Modified Basic Mode Comparison diagram

- Completed OPERATING RV-1805-C3 WITH BACKUP BATTERY/SUPERCAP

- Added additional text to PWGT bit description

- Specified VDD voltage range for I

OLEAK

parameter

- Clarified PIN DESCRIPTION

October 2018

3.0

Updated package drawings, 2.1., 9.1., 9.2., 10.1.

November 2018

3.1

Removed Automotive, 1.2.

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12. DOCUMENT REVISION HISTORY

Information furnished is believed to be accurate and reliable. However, Micro Crystal assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. In accordance with our policy of continuous development and improvement, Micro Crystal reserves the right to modify specifications mentioned in this publication without prior notice. This product is not authorized for use as critical component in life support devices or systems.

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Micro crystal RV-1805-C3 Applications Manual

Specifications and Main Features

Frequently Asked Questions

User Manual