Microchip Technology Inc PIC24HJ12GP201, PIC24HJ12GP202 Datasheet

PIC24HJ12GP201/202

Data Sheet

High-Performance,

16-Bit Microcontrollers

© 2007 Microchip Technology Inc. Advance Information DS70282A

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
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• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digit al Millennium Copyright Act. If suc h a c t s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device
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dsPIC, K

EELOQ, KEELOQ logo, microID, MPLAB, PIC,

PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, an d
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and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,
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Endurance, UNI/O, WiperLock and ZENA are trademarks of
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All other trademarks mentioned herein are property of their
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© 2007, Microchip Technology Incorporated, Pr inted in the
U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The
Company’s quality system processes and procedures are for its PIC
MCUs and dsPIC® DSCs, KEELOQ
EEPROMs, microperipherals, nonvolatile memory and analog
products. In addition, Microchip’s quality system for the design and
manufacture of development systems is ISO 9001:2000 certified.

®

code hopping devices, Serial

DS70282A-page ii Advance Information © 2007 Microchip Technology Inc.

®

PIC24HJ12GP201/202

High-Performance, 16-Bit Digital Signal Controllers

Operating Range:

• Up to 40 MIPS operation (@ 3.0-3.6V):

- Industrial temperature range
(-40°C to +85°C)

- Extended temperature range
(-40°C to +125°C)

High-Performance CPU:

• Modified Harvard architecture

• C compiler optimized instruction set

• 16-bit wide data path

• 24-bit wide instructions

• Linear program memory addressing up to 4M
instruction words

• Linear data memory addressing up to 64 Kbytes

• 71 base instructions, mostly 1 word/1 cycle

• Sixteen 16-bit general purpose registers

• Flexible and powerful addressing modes

• Software stack

• 16 x 16 multiply operations

• 32/16 and 16/16 divide operations

• Up to ±16-bit shifts for up to 40-bit data

Interrupt Controller:

• 5-cycle latency

• 118 interrupt vectors

• Up to 21 available interrupt sources

• Up to 3 external interrupts

• 7 programmable priority levels

• 4 processor exceptions

On-Chip Flash and SRAM:

• Flash program memory (12 Kbytes)

• Data SRAM (1024 bytes)

• Boot and General Security for Program Flash

Digital I/O:

• Peripheral Pin Select Functionality

• Up to 21 programmable digital I/O pins

• Wake-up/Interrupt-on-Change for up to 21 pins

• Output pins can drive from 3.0V to 3.6V

• Up to 5V output with open drain configuration

• All digita l input pins are 5V tolerant

• 4 mA sink on all I/O pins

System Management:

• Flexible clock options:

- External, crystal, resonator, internal RC

- Fully integrated Phase-Locked Loop (PLL)

- Extreme ly low jitter PLL

• Power-up Timer

• Oscillator Start-up Timer/Stabilizer

• Watchdog Timer with its own RC oscillator

• Fail-Safe Clock Monito r

• Reset by multiple sources

Power Management:

• On-chip 2.5V voltage regulator

• Switch between clock sources in real time

• Idle, Sleep and Doze modes with fast wake-up

Timers/Capture/Compare:

• Timer/Counters, up to three 16-bit timers:

- Can pair up to make one 32-bit timer

- 1 timer runs as Real-T ime Clock wi th external

32.768 kHz oscillator

- Programmable prescaler

• Input Capture (up to 4 channels):

- Capture on up, down or both edges

- 16-bit capture input functions

- 4-deep FIFO on each capture

• Output Compare (up to 2 channels):

- Single or Dual 16-Bit Compare mode

- 16-bit Glitchless PWM Mode

© 2007 Microchip Technology Inc. Advance Information DS70282A-page 1

PIC24HJ12GP201/202

Communication Modules:

• 4-wire SPI:

- Framing supports I/O interface to simple
codecs

- Supports 8-bit and 16-bit data

- Supports all serial clock formats and
sampling modes

2

•I

C™:

- Full Multi-Master Slave mode support

- 7-bit and 10-bit addressing

- Bus collision detection and arbitration

- Integrated signal conditioning

- Slave address masking

•UART:

- Interrupt on address bit detect

- Interrupt on UART error

- Wake-up on Start bit from Sleep mode

- 4-character TX and RX FIFO buffers

- LIN bus support

®

-IrDA

- High-Speed Baud mode

- Hardware Flow Control with CTS and RTS

encoding and decodi ng in hardware

Analog-to-Digit al Converters (ADCs):

• 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion:

- 2 and 4 simultaneous samples (10-bit ADC)

- Up to 10 input channels with auto-scanning

- Conversion start can be manual or
synchronized with 1 of 4 trigger sources

- Conversion possible in Sleep mode

- ±2 LSb max integral nonlinearity

- ±1 LSb max differential nonlinearity

CMOS Flash T echnology:

• Low-power, high-speed Flash technology

• Fully static design

• 3.3V (±10%) operating voltage

• Industrial and extended temperature

• Low power consumption

Packaging:

• 18-pin SDIP/SOIC

• 28-pin SDIP/SOIC/QFN
Note: See the device variant tables for exact

peripheral features per device.

DS70282A-page 2 Advance Information © 2007 Microchip Technology Inc.

PIC24HJ12GP201/202

PIC24HJ12GP201/202 Product Families

The device names, pin counts, memory sizes and
peripheral availability of each family are listed below,
followed by their pinout diagrams.

TABLE 1: PIC24HJ12GP201/202 CONTROLLER FAMILIES

Remappable Peripherals

Device

PIC24HJ12GP201 18 12 1

PIC24HJ12GP202 28 12 1

Note 1: Only 2 out of 3 timers are remappable.

Pins

RAM

(Kbyte)

Program Flash Memory

C™

2

(Kbyte)

Pins

16-bit Timer

Remappable

8

3

16

3

Input Capt ur e

(1)

4 2 1 1 1 ADC, 6 ch 1 13 SDIP

(1)

4 2 1 1 1 ADC, 10 ch 1 21 SDIP

Std. PWM

Output Compare

SPI

UART

10-Bit/12-Bit ADC

I

Packages

I/O Pins (Max)

SOIC

SOIC

QFN

© 2007 Microchip Technology Inc. Advance Information DS70282A-page 3

PIC24HJ12GP201/202

Pin Diagrams

18-Pin SDIP, SOIC

PGD2/EMUD2/AN0/VREF+/CN2/RA0

PGC2/EMUC2/AN1/VREF-/CN3/RA1

PGD1/EMUD1/AN2/RP0/CN4/RB0
PGC1/EMUC1/AN3/RP1/CN5/RB1

PGD3/EMUD3/SOSCI/RP4/CN1/RB4

PGC3/EMUC3/SOSCO/T1CK/CN0/RA4

28-Pin SDIP, SOIC

PGD2/EMUD2/AN0/VREF+/CN2/RA0

PGC2/EMUC2/AN1/VREF-/CN3/RA1

PGD1/EMUD1/AN2/RP0/CN4/RB0
PGC1/EMUC1/AN3/RP1/CN5/RB1

PGD3/EMUD3/SOSC/RP4/CN1/RB4

PGC3/EMUC3/SOSCO/T1CK/CN0/RA4

MCLR

OSCI/CLKI/CN30/RA2

OSCO/CLKO/CN29/RA3

MCLR

AN4/RP2/CN6/RB2
AN5/RP3/CN7/RB3

Vss

OSCO/CLK1/CN30/RA2

OSCI/CLKI/CN29/RA3

V

ASDA1/RP5/CN27/RB5

DD

1

PIC24HJ12GP201

2
3
4
5
6
7
8
9

1
2
3
4

PIC24HJ12GP202

5
6
7
8
9
10
11
12
13
14

VDD

18

VSS

17

AN6/RP15/CN11/RB15

16

AN7/RP14/CN12/RB14

15

VDDCORE

14

V

SS

13

SCL1/RP9/CN21/RB9

12

SDA1/RP8/CN22/RB8

11

INT0/RP7/CN23/RB7

10

DD

AV

28

AVSS

27

AN6/RP15/CN11/RB15

26

AN7/RP14/CN12/RB14

25

AN8/RP13/CN13/RB13

24

AN9/RP12/CN14/RB12

23

TMS/RP11/CN15/RB11

22

TDI/RP10/CN16/RB10

21

V

20
19
18
17
16
15

DDCORE

Vss
TDO/SDA1/RP9/CN21/RB9
TCK/SCL1/RP8/CN22/RB8

INT0/RP7/CN23/RB7
ASCL1/RP6/CN24/RB6

DS70282A-page 4 Advance Information © 2007 Microchip Technology Inc.

Pin Diagrams (Continued)

28-Pin QFN

PGD1/EMUD1/AN2/RP0/CN4/RB0
PGC1/EMUC1/AN3/RP1/CN5/RB1

AN4/RP2/CN6/RB2
AN5/RP3/CN7/RB3

OSCI/CLKI/CN30/RA2

OSCO/CLKO/CN29/RA3

28 27 26 25 24 23 22

1
2
3
4

SS

V

5
6
7

8 9 10 11 12 13 14

PIC24HJ12GP201/202

DD

MCLR

AV

PGD2/EMUD2/AN0/VREF+/CN2/RA0

PGC2/EMUC2/AN1/VREF-/CN3/RA1

PIC24HJ12GP202

AVSS

AN6/RP15/CN11/RB15

AN7/RP14/CN12/RB14

AN8/RP13/CN13/RB13

21

AN9/RP12/CN14/RB12

20
19

TMS/RP11/CN15/RB11

18

TDI/RP10/CN16/RB10

DDCORE

V

17

SS

V

16

TDO/SDA1/RP9/CN21/RB9

15

DD

V

INT0/RP7/CN23/RB7

ASCL1/RP6/CN24/RB6

ASDA1/RP5/CN27/RB5

TCK/SCL1/RP8/CN22/RB8

PGD3/EMUD3/SOSCI/RP4/CN1/RB4

PGC3/EMUC3/SOSCO/T1CK/CN0/RA4

© 2007 Microchip Technology Inc. Advance Information DS70282A-page 5

PIC24HJ12GP201/202

Table of Contents

1.0 Device Overview.......................................................................................................................................................................... 7

2.0 CPU ............................................................................................................................................................................................ 11

3.0 Memory Organization................................................................................................................................................................. 17

4.0 Flash Program Memory................................................................................ .............................................................................. 37

5.0 Resets .......................................................................................................................................................................................43

6.0 Interrupt Controlle r.......... ........................................................................................................................................................... 49

7.0 Oscillator Configuration.............................................................................................................................................................. 77

8.0 Power-Saving Features...................................... .......................... .............................................................................................. 87

9.0 I/O Ports..................................................................................................................................................................................... 89

10.0 Timer1......................................................................................................................................................................................109

11.0 Timer2/3 Feature................. .................................................. ...................................................................................................111

12.0 Input Capture......................................................................................................... .... ...............................................................117

13.0 Output Compare.......................................................... ......................... .......................... ..........................................................119

14.0 Serial Peripheral Interface (SPI)...............................................................................................................................................125

15.0 Inter-Integrated Circuit (I

16.0 Universal Asynchronous Receiver Transmitter (UART) ...........................................................................................................143

17.0 10-bit/12-bit Analog-to-Digital Convert er ( ADC)........................................................................... ............................................ 151

18.0 Special Features...................................................................................................................................................................... 163

19.0 Instruction Set Summary .......................................................................................................................................................... 171

20.0 Development Support............................................................................................................................................................... 179

21.0 Electrical Characteristics..........................................................................................................................................................183

22.0 Packaging Information....................................................... ....................................................................................................... 217

Appendix A: Revision History............................................................................................................................................................. 223

Index ................................................................................................................................................................................................. 225

The Microchip Web Site........................................... .......................................................................................................................... 229

Customer Change Notification Service .............................................................................................................................................. 229

Customer Support..............................................................................................................................................................................229

Reader Response..............................................................................................................................................................................230

Product Identific ation System............................................................................................................................................................. 231

2

C)..................................................................................................................................................... 133

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DS70282A-page 6 Advance Information © 2007 Microchip Technology Inc.

1.0 DEVICE OVERVIEW

Note: This data sheet summarizes the features

of the PIC24HJ12GP201/2 02 devices. It i s
not intended to be a co mp rehe ns iv e re fer­ence source. To complement the informa­tion in this dat a sheet, refe r to the “PIC24H
Family Reference Manual”. Please see
the Microchip web site (www.micro­chip.com) for the latest PIC24H Family
Reference Manual chap ters.

This documen t conta i ns dev ic e spec if i c in for m at i on fo r
the following devices:

• PIC24HJ12GP201

• PIC24HJ12GP202
Figure 1-1 shows a general block diagram of the core

and periph eral modules in the PIC24 HJ12GP201/ 202
family of devices. Table 1-1 lists the functions of the
various pins shown in the pinout diagrams.

PIC24HJ12GP201/202

© 2007 Microchip Technology Inc. Advance Information DS70282A-page 7

PIC24HJ12GP201/202

FIGURE 1-1: PIC24HJ12GP201/202 BLOCK DIAGRAM

PSV & Table
Data Access

Control Block

23

Address Latch

Program Memory

Data Latch

OSC2/CLKO

OSC1/CLKI

Interrupt

Controller

23

Timing

Generation

FRC/LPRC

Oscillators

Precision
Band Gap
Reference

Voltage

Regulator

23

Stack

Control

Address Bus

Instruction

Control Signals
to Various Blocks

8

PCH PCL

PCU

Program Counter

Loop

Logic

Control

Logic

24

Decode &

Control

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Brown-out

Reset

16

Data Bus

16

Data Latch

X RAM

Address

Latch

16

Address Generator Units

ROM Latch

Instruction Reg

17 x 17 Multiplier

Divide Support

16

W Register Array

EA MUX

16

Literal Data

16 x 16

16-bit ALU

16

16

16

16

16

PORTA

PORTB

Remappable

Pins

VDDCORE/VCAP

Timers

1-3

IC1,2,7,8

DD, VSS

V

PWM1,2

ADC1

OC/

MCLR

CNx

UART1

SPI1

I2C1

Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins

and features present on each device.

DS70282A-page 8 Advance Information © 2007 Microchip Technology Inc.

PIC24HJ12GP201/202

TABLE 1-1: PINOUT I/O DESCRIPTIONS

Pin Name Pin Type Buffer Type Description

AN0-AN9 I Analog Analog input channels.
CLKI

CLKO

OSC1
OSC2

SOSCI
SOSCO

CN0-CN7
CN11-CN15
CN21-CN24
CN27
CN29-CN30

IC0-IC1
IC7-IC8

OCFA
OC1-OC2

INT0
INT1
INT2

RA0-RA4 I/O ST PORTA is a bidirectional I/O port.
RB0-RB15 I/O ST PORTB is a bidirectional I/O port.
T1CK

T2CK
T3CK

U1CTS
U1RTS
U1RX
U1TX

SCK1
SDI1
SDO1
SS

1

SCL1
SDA1
ASCL1
ASDA1

TMS
TCK
TDI
TDO

PGD1/EMUD1
PGC1/EMUC1
PGD2/EMUD2
PGC2/EMUC2
PGD3/EMUD3
PGC3/EMUC3

DDCORE P — CPU logic filter capacito r connection.

V

SS P — Ground reference for logic and I/O pins.

V
VREF+ I Analog Analog voltage referenc e (h igh) input.

REF- I Analog Analog voltage reference (low) input.

V

Legend: CMOS = CMOS compatible input or output; Analog = Analog input

ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power

I

O

I

I/O

I

O

I ST Change notification inputs.

I ST Capture inputs 1/2

I

O

I
I
I

I
I
I

I

O

I

O

I/O

I

O

I/O
I/O

I/O
I/O
I/O

I
I
I

O

I/O

I

I/O

I

I/O

I

ST/CMOS—External clock source input. Alwa ys associated with OSC1 pin fu nction.

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functions as CLKO in RC and EC modes. Always associated
with OSC2 pin function.

ST/CMOS—Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.

ST/CMOS—32.768 kHz low-powe r os ci lla t or cry stal in put; C M O S ot her wi se.

ST

—

ST
ST
ST

ST
ST
ST

ST

—

ST

—

ST
ST

—

ST
ST

ST
ST
ST

ST
ST
ST

—

ST
ST
ST
ST
ST
ST

Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator
mode. Optionally functio ns as C LKO in R C an d EC m odes.

32.768 kHz low-powe r os ci lla t or cry stal out put.

Can be software programmed for internal weak pull-ups on all inputs.

Capture inputs 7/8
Compare Fault A input (for Compare Channels 1 and 2).

Compare outputs 1 through 2.
External interrupt 0.

External interrupt 1.
External interrupt 2.

Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.

UART1 clear to send.
UART1 ready to send.
UART1 receive.
UART1 transmit.

Synchronous serial clock input/output for SPI1.
SPI1 data in.
SPI1 data out.
SPI1 slave synchronization or frame pulse I/O.

Synchronous serial clock input/output for I2C1 .
Synchronous serial data input/output for I2C1.
Alternate synchronous serial clock input/output for I2C1.
Alternate synchronous serial data input/output for I2C1.

JTAG Test mode select pin.
JTAG test clock input pin.
JTAG test data input pin.
JTAG test data output pin.

Data I/O pin for programmin g/ deb ugging communication channel 1.
Clock input pin for progr am m i ng/ d ebugging communica tion channel 1.
Data I/O pin for programmin g/ deb ugging communication channel 2.
Clock input pin for progr am m i ng/ d ebugging communica tion channel 2.
Data I/O pin for programmin g/ deb ugging communication channel 3.
Clock input pin for progr am m i ng/ d ebugging communica tion channel 3.

© 2007 Microchip Technology Inc. Advance Information DS70282A-page 9

PIC24HJ12GP201/202

TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Name Pin Type Buffer Type Description

AVDD P P Positive supply for analog mo dules.
MCLR

VSS P P Ground refe re nce for analog modules.

A
VDD P — Positive supply for perip her al logi c and I/O pins.

Legend: CMOS = CMOS compatible input or output; Analog = Analog input

ST = Schmitt Trigger input with CMOS levels; O = Output; I = Input; P = Power

I/P ST Master Clear (Reset) input. This pi n is an active-low Reset to the device.

DS70282A-page 10 Advance Information © 2007 Microchip Technology Inc.

PIC24HJ12GP201/202

2.0 CPU

Note: This data sheet summarizes the features

of this group of PIC24HJ12GP201/202
devices. It is not intended to be a compre­hensive reference sourc e. To complement
the information in this data sheet, refer to
the “PIC24H Family Reference Manual”.
Please see the Microchip web site
(www.microchip.com) for the latest
PIC24H Family Reference Manual
chapters.

The PIC24HJ12GP201/202 CPU module has a 16-bit
(data) modified H arvard architecture with an enhanced
instruction set and addressing modes. The CPU has a
24-bit instruction word with a variable length opcode
field. The Program Counter (PC) is 23 bits wide and
addresses up to 4M x 24 bits of user program memory
space. The actual amount of program memory
implemented varies by device. A single-cycle
instruction prefetch mechanism is used to help
maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free,
single-cycle program loop constructs are supported
using the REPEAT instructio n, which is in terruptib le at
any point.

The PIC24HJ12GP201/202 devices have sixteen, 16-bit
working regist ers in the program mer’s model. Each of th e
working registers can serve as a data, address or
address offset register. The 16th working register (W15)
operates as a software Stack Pointer (SP) for interrupts
and calls.

The PIC24HJ12GP201/202 instruction set includes
many addressing modes and is designed for optimum
C compiler efficiency. For most instructions, the
PIC24HJ12GP201/202 is capable of executing a data
(or program data) memory read, a working register
(data) read, a data memory write and a program
(instruction) memory read per instruction cycle. As a
result, three parameter instructions can be supported,
allowing A + B = C operations to be executed in a single
cycle.

A block diagram of the CPU is shown in Figure 2-1,
and the programmer’s model for the
PIC24HJ12GP201/202 is sh ow n in Figu re 2-2.

2.1 Data Addressing Overvi ew

The data space can be linearly addressed as 32K words
or 64 Kbytes using an Addr ess Generation Uni t (AGU).
The upper 32 Kby tes of the data s pace mem ory map ca n
optionally b e mapped into pro gram space at any 16K pro­gram word boundary defined by the 8-bit Program Space
Visibility Page ( PSVPAG) register. The program to data
space mapping feature lets any instruction access pro­gram space as if it were data spac e .

The data space also includes 2 Kbytes of DMA RAM,
which is primarily us ed for DMA dat a transfers, but may
be used as general purpose RAM.

2.2 Special MCU Features

The PIC24HJ12GP201/202 features a 17-bit by 17-bit,
single-cycle multiplier. The multiplier can perform
signed, unsigned and mixed-sign multiplication. Using
a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication makes mixed-sign multiplication
possible.

The PIC24HJ12GP201/202 supports 16/16 and 32/16
integer divide operations. All divide instructions are
iterative operations. They must be executed within a
REPEAT loop, resulting in a total execution time of 19
instruction cycles. The divide operation can be
interrupted during any of those 19 cycles without loss
of data.

A multi-bit data shifter is used to perform up to a 16-bit,
left or right shift in a single cycle.

© 2007 Microchip Technology Inc. Advance Information DS70282A-page 11

PIC24HJ12GP201/202

FIGURE 2-1: PIC24HJ12GP201/202 CPU CORE BLOCK DIAGRAM

PSV & Table
Data Access
Control Block

Interrupt

Controller

23

23

Address Latch

Program Memory

Data Latch

23

8

PCH PCL

PCU

Program Counter

Stack

Control

Logic

Address Bus

24

Instruction

Decode &

Control

Control Signals

to Various Blocks

16

Loop

Control

Logic

X Data Bus

16

Data Latch

X RAM

Address

Latch

Address Generator Units

ROM Latch

Instruction Reg

17 x 17
Multiplier

Divide Support

16

16

EA MUX

16

16

Literal Data

16 x 16

W Register Array

16

16

16

16-bit ALU

16

To Peripheral Modules

DS70282A-page 12 Advance Information © 2007 Microchip Technology Inc.

PIC24HJ12GP201/202

FIGURE 2-2: PIC24HJ12GP201/202 PROGRAMMER’S MODEL

D0D15

W0/WREG

W1
W2
W3
W4
W5

W6
W7

W8
W9
W10
W11

W12

W13

W14/Frame Pointer

W15/Stack Pointer

PUSH.S Shadow

DO Shadow

Legend

Working Registers

PC22

7

TBLPAG

7

PSVPAG

— — ——

SRH

0

0

— —

SPLIM Stack Pointer Limit Register

Data Table Page Address

Program Space Visibility Page Address

15

RCOUNT

15

CORCON

— DC

IPL2 IPL1

IPL0 OV

RA N

SRL

PC0

0

Program Counter

0

REPEAT Loop Counter

0

Core Configuration Register

C

Z

STATUS Register

© 2007 Microchip Technology Inc. Advance Information DS70282A-page 13

PIC24HJ12GP201/202

2.3 CPU Control Registers

REGISTER 2-1: SR: CPU STATUS REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — —DC

bit 15 bit 8

(1)

R/W-0

IPL<2:0>

bit 7 bit 0

Legend:

C = Clear only bit R = Readable bit U = Unimplemented bit, read as ‘0’
S = Set only bit W = Writable bit -n = Value at POR
‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15-9 Unimplemented: Read as ‘0’
bit 8 DC: MCU ALU Half Carry/Borrow

1 = A carry-out from the 4th low-order bit (for byte-si zed data) or 8th lo w-order bit (for word-s ized data)
0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized

bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits

111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)

bit 4 RA: REPEAT Loop Active bit

1 = REPEAT loop in progress
0 = REPEAT loop not in progress

bit 3 N: MCU ALU Negative bit

1 = Result was negative
0 = Result was non-negative (zero or positive)

bit 2 OV: MCU ALU Overflow bit

This bit is used for signed arithm etic (2’s c omplement). It indic ates an overflow of th e magnitude wh ich
causes the sign bit to change state.

1 = Overflow occurred for signed arithmetic (in this arithmetic operation)
0 = No overflow occurred

bit 1 Z: MCU ALU Zero bit

1 = An operation which affects the Z bit has set it at some time in the past
0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result)

bit 0 C: MCU ALU Carry/Borrow

1 = A carry-out from the Most Significant bit (MSb) of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred

Note 1: The IPL<2:0> bits are concaten ated with the IPL<3 > bi t (CORCON<3 >) to form the CPU Inte rrup t Prio rity

Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.

2: The IPL<2:0> Status bits are read only when NSTDIS = 1 (INTCON1<15>).

(2)

R/W-0

(2)

of the result occurred
data) of the result occurred

R/W-0

(2)

R-0 R/W-0 R/W-0 R/W-0 R/W-0

RA N OV Z C

bit

(2)

bit

DS70282A-page 14 Advance Information © 2007 Microchip Technology Inc.

PIC24HJ12GP201/202

REGISTER 2-2: CORCON: CORE CONTROL REGISTER

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

— — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0

— — — —IPL3

bit 7 bit 0

Legend: C = Clear only bit
R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set
0’ = Bit is cleared ‘x = Bit is unknown U = Unimplemented bit, read as ‘0’

bit 15-4 Unimplemented: Read as ‘0’
bit 3 IPL3: CPU Interrupt Priority Level Status bit 3

1 = CPU interrupt priority level is greater than 7
0 = CPU interrupt priori ty level is 7 o r less

bit 2 PSV: Program Space Visibility in Data Space Enable bit

1 = Program space visible in data space
0 = Program space not visible in data space

bit 1-0 Unimplemented: Read as ‘0’

Note 1: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.

(1)

(1)

PSV — —

© 2007 Microchip Technology Inc. Advance Information DS70282A-page 15

PIC24HJ12GP201/202

2.4 Arithmetic Logic Unit (ALU)

The PIC24HJ12GP201/202 ALU is 16 bits wide and is
capable of addition, subtraction, bit shifts and logic
operations. Unless otherwise mentioned, arithmetic
operations are 2’s complement in nature. Depending
on the operation, the ALU may affect the values of the
Carry (C), Zero (Z), Negative (N), Overflow (OV) and
Digit Carry (DC) Status bits in the SR register. The C
and DC S tatus bits op erate as Bo rrow
bits, respectively, for subtraction operations.

The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W reg­ister array , or dat a memory, depending on the address­ing mode of the instruction. Likewise, output data from
the ALU can be written to the W regis ter array or a data
memory locatio n.

Refer to the “dsPIC30F/33F Programmer’s Reference
Manual” (DS70157) for information on the SR bits
affected by each instruction.

The PIC24HJ12GP201/202 CPU incorporates hard­ware support for both multiplication and division. This
includes a dedicated hardware multiplier and support
hardware for 16-bit divisor division.

2.4.1 MULTIPLIER

Using the high-speed 17-bit x 17-bit multiplier, the ALU
supports unsigned, signed or mixed-sign operation in
several multiplication modes:

1. 16-bit x 16-bit signed

2. 16-bit x 16-bit unsigned

3. 16-bit signed x 5-bit (literal) unsigned

4. 16-bit unsigned x 16-bit unsigned

5. 16-bit unsigned x 5-bit (literal) unsigned

6. 16-bit unsigned x 16-bit signed

7. 8-bit unsigned x 8-bit unsigned

and Digit Borrow

2.4.2 DIVIDER

The divide block support s 32-bit/16-bit and 16-b it/16-bit
signed and unsig ne d in teg er d iv ide ope rati on s w it h th e
following data si zes:

1. 32-bit signed/16-bit signed divide

2. 32-bit unsigned/16-bit unsigned divide

3. 16-bit signed/16-bit signed divide

4. 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0

and the remainder in W1. Sixteen-bit signed and
unsigned DIV instructions can specify any W register
for both the 16-bit divisor (Wn) and any W register
(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.
The divide algorithm takes one cycle per bit of divisor,
so both 32-bit/16-bit and 16-bit/16-bit instructions take
the same number of cycles to execute.

2.4.3 MULTI-BIT DATA SHIFTER

The multi-bit data shifter is capable of performing up to
16-bit arithmetic or logic right shifts , or up to 16-bit left
shifts in a single cycle. The source can be either a
working register or a memory location.

The shifter requi res a signed binary value to determine
both the magnitude (num ber of bits) and direction of the
shift operation. A po sitive value shif ts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.

DS70282A-page 16 Advance Information © 2007 Microchip Technology Inc.

PIC24HJ12GP201/202

3.0 MEMORY ORGANIZATION

Note: This data sheet summarizes the features

of the PIC24HJ 12GP201/202 d evices. It is
not intended to be a c om preh ens iv e re fer­ence source. To complement the informa­tion in this data sheet, refer to the “PIC24H
Family Reference Manual”. Please see
the Microchip web site (www.micro­chip.com) for the latest PIC24H Family
Reference Manual chapters.

The PIC24HJ12GP201/202 architecture features sep­arate program and data memory spaces and buses.
This architecture also allows the direct access of pro­gram memory from the data space during code execu­tion.

3.1 Program Address Space

The program address memory space of the
PIC24HJ12GP201/202 devices is 4M instructions. The
space is addressable by a 24-bit value derived either from
the 23-bit Program Counter (PC) during program execu­tion, or from table operation or data space remapping as
described in Section 3.4 “Interfacing Program and Data
Memory Spaces”.

User application a ccess t o the pr ogram me mory s pace is
restricted to the lower half of the address range (0x000000
to 0x7FFFFF). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to the
Configura tion bi ts an d Devic e ID sect ions of the
configuration memory space.

The memory map for the PIC24HJ12GP201/202 device is
shown in Figu re3-1.

FIGURE 3-1: PROGRAM MEMORY FOR PIC24HJ12GP201/202 DEVICES

PIC24HJ12GP201/202

GOTO

Instruction

Reset Address

Interrupt Vector Table

Reserved

Alternate Vector Table

User Program
Flash Memory

(4K instructions)

0x000000
0x000002

0x000004
0x0000FE

0x000100
0x000104
0x0001FE
0x000200

0x001FFE
0x002000

User Memory Space

Unimplemented

Device Configuration

Configuration Memory Space

(Read ‘0’s)

Reserved

Registers

Reserved

DEVID (2)

0x7FFFFE
0x800000

0xF7FFFE
0xF80000
0xF80017
0xF80018

0xFEFFFE
0xFF0000

0xFFFFFE

© 2007 Microchip Technology Inc. Advance Information DS70282A-page 17

PIC24HJ12GP201/202

3.1.1 PROGRAM MEMORY
ORGANIZATION

The program memory space is organized in word­addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of t he upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 3-2).

Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.

3.1.2 INTERRUPT AND TRAP VECTORS

All PIC24HJ12GP201/202 devices reserve the
addresses between 0x00000 and 0x000200 for hard­coded program execution vectors. A hardware Reset
vector is provided to redirect code execution from the
default value of the PC on device Reset to the actual
start of code. A GOTO in stru ction is programmed by the
user application at 0x000000, with the actual address
for the start of code at 0x000002.

PIC24HJ12GP201/202 devic es al so ha ve tw o in terrupt
vector tables, lo cated from 0x 00000 4 to 0x 0000F F and
0x000100 to 0x0001FF. These vector tab les allow each
of the many device interrupt sources to be handled by
separate Interrupt Service Routines (ISRs). A more
detailed discussion of the interrupt vector tables is
provided in Section6.1 “Interrupt Vector Table”.

FIGURE 3-2: PROGRAM MEMORY ORGANIZATION

msw

Address (lsw Address)

0x000001
0x000003
0x000005
0x000007

most significant word

23

00000000

00000000

00000000

00000000

least significant word

PC Address

0816

0x000000
0x000002
0x000004
0x000006

Program Memor y

‘Phantom’ Byte

(read as ‘0’)

Instructi on Width

DS70282A-page 18 Advance Information © 2007 Microchip Technology Inc.

PIC24HJ12GP201/202

3.2 Data Address Space

The PIC24HJ12GP201/202 CPU has a separate 16­bit-wide data memory space. The data space is
accessed using separate Address Generation Units
(AGUs) for read and write operations. The data
memory maps is shown in Figure 3-3.

All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space

Visibility area (see Section 3.4.3 “Reading D ata From

Program Memory Using Program Space Visibility”).
PIC24HJ12GP201/202 devices implement up to

30 Kbytes o f data memory. Should an EA poi nt to a
location outside of this area, an all-zero word or byte
will be returned.

3.2.1 DATA SPACE WIDTH

The data memory space is organized in byte address­able, 16-bit-wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even ad dresses, whil e
the Most Significant Bytes (MSBs) have odd
addresses.

3.2.2 DATA MEMORY ORGANIZATION
AND ALIGNMENT

To ma intain backwa rd compatibili ty with PIC
and improve data space memory usage efficiency, the
PIC24HJ12GP201/202 instruction set supports both
word and byte operations. As a consequence of byte
accessibility , a ll effect ive address calcu lations are inter­nally scaled to step through word-aligned memory. For
example, the core recognizes that Post-Modified
Register Indirect Addre ssing mode [Ws++] w ill resu lt in
a value of W s + 1 for by te operat ions and Ws + 2 for
word operations.

Data byte reads will read the complete word that
contains the byte, using the LSB of any EA to deter­mine which byte to select. The selected byte is placed
onto the LSB of the data path. That is, data memory
and registers are organized as two parallel byte-wide
entities with shared (word) address decode but sepa­rate write lines. D at a by te writ es only wri te to t he co rre­sponding side of the array or register that matches the
byte address.

®

devices

All word accesses m ust be al igned to an even addre ss.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word opera­tions, or translating from 8-bit MCU code. If a mis­aligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed. If the instruction
occurred on a write, the instruction is executed but the
write does not occur. In either case, a trap is then exe­cuted, allowing the system and/or user application to
examine the machine state prior to execution of the
address Fault.

All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is n ot
modified.

A sign-extend instruction (SE) is provided to allow
users to translate 8-bit signed data to 16-bit signed
values. Alternatively, for 16-bit unsigned data, user
applications can clear the MSB of any W register by
executing a zero-extend (ZE) instruction on the
appropriate address.

3.2.3 SF R SPAC E

The first 2 Kbytes of the near data space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
PIC24HJ12GP201/202 core and peripheral modules
for controlling the operation of the device.

SFRs are distributed among the modules that they
control, and are generall y grouped together by mod ule.
Much of the SFR space contains unused addresses;
these are read as ‘0’. A co mplete listing o f implemented
SFRs, including their addresses, is shown in Table 3-1
through Table 3-21.

Note: The actual set of peripheral features and

interrupts varies by the device. Refer to
the corresponding device tables and
pinout diagrams for device-specific
information.

3.2.4 NEAR DATA SPACE

The 8 Kbyte area between 0x0000 and 0x1FFF is
referred to as t he near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data spa ce is addressa ble using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an address pointer.

© 2007 Microchip Technology Inc. Advance Information DS70282A-page 19

PIC24HJ12GP201/202

e

FIGURE 3-3: DATA MEMORY MAP FOR PIC24HJ12GP201/202 DEVICES WITH 1 KB RAM

2 Kbyte
SFR Space

1 Kbyte
SRAM Space

MSB

Address

0x0001

0x07FF

0x0801

0x0BFF
0x0C01

0x1FFF

0x2001

0x8001

16 bits

SFR Space

X Data RAM (X)

LSB

Address

LSbMSb

0x0000

0x07FE
0x0800

8 Kbyte

Near Data Spac
0x0BFE
0x0C00

0x1FFFF
0x2000

0x8000

Optionally
Mapped
into Program
Memory

0xFFFF

X Data

Unimplemented (X)

0xFFFE

DS70282A-page 20 Advance Information © 2007 Microchip Technology Inc.

© 2007 Microchip Technology Inc. Advance Information DS70282A-page 21

TABLE 3-1: CPU CORE REGISTERS MAP

SFR Name

WREG0 0000 Working Re gis ter 0
WREG1 0002 Working Re gis ter 1
WREG2 0004 Working Re gis ter 2
WREG3 0006 Working Re gis ter 3
WREG4 0008 Working Re gis ter 4
WREG5 000A Working Re gis ter 5
WREG6 000C Wo rkin g Re gis ter 6
WREG7 000E Working Re gis ter 7
WREG8 0010 Working Re gis ter 8
WREG9 0012 Working Re gis ter 9
WREG10 0014 Working Register 10
WREG11 0016 Working Register 11
WREG12 0018 Working Register 12
WREG13 001A Working Register 13
WREG14 001C Working Register 14
WREG15 001E Working Register 15
SPLIM 0020 Stack Pointer Limit Register
PCL 002E Program Counter Low Word Register
PCH 0030 — — — — — — — — Program C ounte r Hi gh B yte Re gi ster
TBLP A G 0032 — — — — — — — — Table Page Address Pointer R egis ter
PSVPAG 0034 — — — — — — — — Program Memory Visibility Page Address Pointer Register
RCOUNT 0036 Repeat Loop Counter Register
SR 0042 — — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C
CORCON 0044 — — — — — — — — — — — —
DISICNT 0052 —

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— Disable Interrupts Counter

IPL3 PSV

Register

— —

All

Resets

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0000

0800

xxxx

0000

0000

0000

0000

xxxx

0000

0000

xxxx

PIC24HJ12GP201/202

DS70282A-page 22 Advance Information © 2007 Microchip Technology Inc.

TABLE 3-2: CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ12GP202

SFR

SFR

Name

CNEN1 0060 CN15IE CN14IE CN13IE CN12IE CN11IE
CNEN2 0062
CNPU1 0068 CN15PUE CN14PUE CN13PUE CN1 2PUE CN1 1PUE
CNPU2 006A

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

—- — —

CN30IE CN29IE

—

CN30PUE CN29PUE

—

CN27IE

—

CN27PUE

—

— —
— — —
— —

CN24PUE CN23IE CN22IE CN21IE

CN24PUE CN23PUE CN22PUE CN21PUE

TABLE 3-3: CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ12GP201

SFR

SFR

Name

CNEN1 0060
CNEN2 00C2
CNPU1 0068
CNPU2 006A

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

— — —
—

CN30IE CN29IE
— — —
—

CN30PUE CN29PUE

CN12IE CN11IE

— — — — —

CN12PUE CN11PUE

— — — — —

— — — — —

— — — — —

CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE

— — — —

CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE

— — — —

CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE 0000

CN23IE CN22IE CN21IE

CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000

CN23PUE CN22PUE CN21PUE

— — — — —

— — — — —

CN16IE

CN16PUE

PIC24HJ12GP201/202

All

Resets

0000

0000

0000

0000

All

Resets

0000

0000

© 2007 Microchip Technology Inc. Advance Information DS70282A-page 23

TABLE 3-4: INTERRUPT CONTROLLER REGISTER MAP

SFR

Name

INTCON1 0080 NSTDIS
INTCON2 0082 ALTIVT DISI
IFS0 0084
IFS1 0086
IFS4 008C
IEC0 0094
IEC1 0096
IEC4 009C
IPC0 00A4
IPC1 00A6
IPC2 00A8
IPC3 00AA
IPC4 00AC
IPC5 00AE
IPC7 00B2
IPC16 00C4
INTTREG 00E0

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

— — — — — — — —

— — — — — — — — — — — INT2EP INT1EP INT0EP 0000
— — AD1IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF INT0IF 0000
— —INT2IF — — — — — IC8IF IC7IF — INT1IF CNIF — MI2C1IF SI2C1IF 0000
— — — — — — — — — — — — — —U1EIF— 0000
— — AD1IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE OC2IE IC2IE — T1IE OC1IE IC1IE INT0IE 0000
— —INT2IE — — — — — IC8IE IC7IE — INT1IE CNIE — MI2C1IE SI2C1IE 0000
— — — — — — — — — — — — — —U1EIE— 0000
— T1IP<2:0> —OC1IP<2:0>—IC1IP<2:0>— INT0IP<2:0> 4444
— T2IP<2:0> —OC2IP<2:0>—IC2IP<2:0>— — — — 4444
— U1RXIP<2:0> — SPI1IP<2:0> — SPI1EIP<2:0> — T3IP<2:0> 4444
— — — — — — — — — AD1IP<2:0> — U1TXIP<2:0> 4444
— CNIP<2:0> — — — — — MI2C1IP<2:0> — SI2C1IP<2:0> 4444
— IC8IP<2:0> —IC7IP<2:0>— — — — — INT1IP<2:0> 4444
— — — — — — — — — INT2IP<2:0> — — — — 4444
— — — — — — — — — U1EIP<2:0> — — — — 4444
— — — — ILR<3:0>> — VECNUM<6:0> 4444

DIV0ERR

All

Resets

— MATHERR ADDRERR STKERR OSCFAIL — 0000

PIC24HJ12GP201/202

DS70282A-page 24 Advance Information © 2007 Microchip Technology Inc.

PIC24HJ12GP201/202

TA BLE 3-5: TIMER REGISTER MAP

SFR Name

TMR1 0100 Timer1 Register
PR1 0102 Period Register 1
T1CON 0104 TON
TMR2 0106 Timer2 Register
TMR3HLD 0108 Timer3 Holding Register (for 32-bit timer operations only)
TMR3 010A Timer3 Register
PR2 010C Period Register 2
PR3 010E Period Register 3
T2CON 0110 TON
T3CON 0112 TON

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

—

TSIDL

—

TSIDL

—

TSIDL

— — — — — —

— — — — — —
— — — — — —

TGATE TCKPS<1:0>

TGATE TCKPS<1:0> T32
TGATE TCKPS<1:0>

—

— —

TSYNC TCS

—

TCS
TCS

—

—
—

All

Resets

xxxx

FFFF

0000

xxxx

xxxx

xxxx

FFFF

FFFF

0000

0000

TABLE 3-6: INPUT CAPTURE REGISTER MAP

SFR Name

IC1BUF 0140 Input 1 Capture Register
IC1CON 0142
IC2BUF 0144 Input 2 Capture Register
IC2CON 0146
IC7BUF 0158 Input 7 Capture Register
IC7CON 015A
IC8BUF 015C Input 8C ap tu re R eg iste r
IC8CON 015E

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— —

— —

— —

— —

ICSIDL

ICSIDL

ICSIDL

ICSIDL

— — — — —

— — — — —

— — — — —

— — — — —

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

All

Resets

xxxx

0000

xxxx

0000

xxxx

0000

xxxx

0000

TABLE 3-7: OUTPUT COMPARE REGISTER MAP

SFR Name

OC1RS 0180 Output Comp ar e 1 S ec ond ary Reg iste r
OC1R 0182 Output Compare 1 Register
OC1CON 0184
OC2RS 0186 Output Comp ar e 2 S ec ond ary Reg iste r
OC2R 0188 Output Compare 2 Register
OC2CON 018A

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— —

— —

OCSIDL

OCSIDL

— — — — — — — —

— — — — — — — —

OCFLT OCTSEL OCM<2:0>

OCFLT OCTSEL OCM<2:0>

All

Resets

xxxx

xxxx

0000

xxxx

xxxx

0000

© 2007 Microchip Technology Inc. Advance Information DS70282A-page 25

TABLE 3-8: I2C1 REGISTER MAP

SFR Name

I2C1RCV 0200 — — — — — — — — Receive Register
I2C1 T R N 0202 — — — — — — — — Transmi t Re gister
I2C1BRG 0204 — — — — — — — Baud Rate Generat or Regis ter
I2C1CON 0206 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN
I2C1STAT 0208 ACKSTA T TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W RBF TBF
I2C1ADD 020A — — — — — — Address Register
I2C1MSK 020C — — — — — — Address Mask Re gist er

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-9: UART1 REGISTER MAP

SFR Name

U1MODE 0220 UARTEN — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD URXINV BRGH PDSEL<1:0> STSEL
U1STA 0222 UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA
U1TXREG 0224 — — — — — — — UART T r an smit R e gister
U1RXREG 0226 — — — — — — — UART Receive Re gister
U1BRG 0228 Baud Ra te G en era to r P r es ca le r

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Addr

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TABLE 3-10: SPI1 REGISTER MAP

SFR

Name

SPI1STAT 0240 SPIEN — SPISIDL — — — — — — SPIROV — — — — SPITBF SPIRBF
SPI1CON1 0242 — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP MSTEN SPRE<2:0> PPRE<1:0>
SPI1CON2 0244 FRMEN SPIFSD FRMPOL — — — — — — — — — — — FRMDLY —
SPI1BUF 0248 SPI1 Transmit and Receive Buffer Register

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

SFR

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Addr

All

Resets

0000

00FF

0000

1000

0000

0000

0000

All

Resets

0000

0110

xxxx

0000

0000

All

Resets

0000

0000

0000

0000

PIC24HJ12GP201/202

DS70282A-page 26 Advance Information © 2007 Microchip Technology Inc.

TABLE 3-11: PERIPHERAL PIN SELECT INPUT REGISTER MAP

File

Name

RPINR0 0680
RPINR1 0682
RPINR3 0686
RPINR7 068E
RPINR10 0694
RPINR11 0696
RPINR18 06A4
RPINR20 06A8
RPINR21 06AA

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— — — INT1R<4:0> — — — — — — — —
— — — — — — — — — — —INT2R<4:0>
— — —T3CKR<4:0>— — —T2CKR<4:0>
— — — IC2R<4:0> — — — IC1R<4:0>
— — — IC8R<4:0> — — — IC7R<4:0>
— — — — — — — — — — —OCFAR<4:0>
— — — U1CTSR<4:0> — — —U1RX<R4:0>
— — —SCK1R<4:0>— — —SDI1R<4:0>
— — — — — — — — — — —SS1R<4:0>

All

Resets

1F00

001F

1F1F

1F1F

1F1F

001F

1F1F

1F1F

001F

PIC24HJ12GP201/202

TABLE 3-12: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ12GP202

File

Name

RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0>
RPOR1 0 6C2
RPOR2 0 6C4
RPOR3 0 6C6
RPOR4 0 6C8
RPOR5 06CA
RPOR6 06CC
RPOR7 06CE

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

— — —RP3R<4:0>— — — RP2R<4:0>
— — —RP5R<4:0>— — — RP4R<4:0>
— — —RP7R<4:0>— — — RP6R<4:0>
— — —RP9R<4:0>— — — RP8R<4:0>
— — —RP11R<4:0>— — —RP10R<4:0>
— — —RP13R<4:0>— — —RP12R<4:0>
— — —RP15R<4:0>— — —RP14R<4:0>

All

Resets

0000

0000

0000

0000

0000

0000

0000

0000

TABLE 3-13: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ12GP201

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

RPOR0 06C0 — — — RP1R<4:0> — — — RP0R<4:0>
RPOR2 06C4
RPOR3 06C6
RPOR4 06C8
RPOR7 06CE

Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

— — — — — — — — — — — RP4R<4:0>
— — —RP7R<4:0>— — — — — — — —
— — —RP9R<4:0>— — — RP8R<4:0>
— — —RP15R<4:0>— — —RP14R<4:0>

All

Resets

0000

0000

0000

0000

0000

© 2007 Microchip Technology Inc. Advance Information DS70282A-page 27

TABLE 3-14: ADC1 REGISTER MAP FOR PIC24HJ12GP201

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADC1BUF0 0300 ADC Data Buffer 0 xxxx
ADC1BUF1 0302
ADC1BUF2 0304

ADC1BUF3 0306
ADC1BUF4 0308
ADC1BUF5 030A
ADC1BUF6 030C
ADC1BUF7 030E
ADC1BUF8 0310
ADC1BUF9 0312
ADC1BUFA 0314
ADC1BUFB 0316
ADC1BUFC 0318
ADC1BUFD 031A
ADC1BUFE 031C
ADC1BUFE 031E
AD1CON1 0320 ADON
AD1CON2 0322 VCFG<2:0>
AD1CON3 0324 ADRC
AD1CHS123 0326
AD1CHS0 0328 CH0NB
AD1PCFGL 032C
AD1CSSL 0330
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

— — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000

— — — — — — — — — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000
— — — — — — — — — — CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000

—ADSIDL — — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000

— — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000

— — SAMC<4:0> — — ADCS<5:0> 0000

— — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000

ADC Data Buffer 1 xxxx
ADC Data Buffer 2 xxxx
ADC Data Buffer 3 xxxx
ADC Data Buffer 4 xxxx
ADC Data Buffer 5 xxxx
ADC Data Buffer 6 xxxx
ADC Data Buffer 7 xxxx
ADC Data Buffer 8 xxxx

ADC Data Buffer 9 xxxx
ADC Data Buffer 10 xxxx
ADC Data Buffer 11 xxxx
ADC Data Buffer 12 xxxx
ADC Data Buffer 13 xxxx
ADC Data Buffer 14 xxxx
ADC Data Buffer 15 xxxx

Resets

All

PIC24HJ12GP201/202

DS70282A-page 28 Advance Information © 2007 Microchip Technology Inc.

PIC24HJ12GP201/202

TABLE 3-15: ADC1 REGISTER MAP FOR PIC24HJ12GP202

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ADC1BUF0 0300 ADC Data Buffer 0 xxxx
ADC1BUF1 0302

ADC1BUF2 0304
ADC1BUF3 0306
ADC1BUF4 0308
ADC1BUF5 030A
ADC1BUF6 030C
ADC1BUF7 030E
ADC1BUF8 0310
ADC1BUF9 0312
ADC1BUFA 0314
ADC1BUFB 0316
ADC1BUFC 0318
ADC1BUFD 031A
ADC1BUFE 031C
ADC1BUFF 031E
AD1CON1 0320 ADON
AD1CON2 0322 VCFG<2:0>
AD1CON3 0324 ADRC
AD1CHS123 0326
AD1CHS0 0328 CH0NB
AD1PCFGL 032C
AD1CSSL 0330
Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

— — — — — CH123NB<1:0> CH123SB — — — — — CH123NA<1:0> CH123SA 0000

— — — — — — PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG 3 PCFG2 P CFG1 PCFG0 0000
— — — — — — CSS9 CSS8 CSS7 CSS6 CSS5 CSS4 CSS3 CSS2 CSS1 CSS0 0000

—ADSIDL— — AD12B FORM<1:0> SSRC<2:0> — SIMSAM ASAM SAMP DONE 0000

— — CSCNA CHPS<1:0> BUFS — SMPI<3:0> BUFM ALTS 0000

— — SAMC<4:0> — — ADCS<5:0> 0000

— — CH0SB<4:0> CH0NA — — CH0SA<4:0> 0000

ADC Data Buffer 1 xxxx
ADC Data Buffer 2 xxxx
ADC Data Buffer 3 xxxx
ADC Data Buffer 4 xxxx
ADC Data Buffer 5 xxxx
ADC Data Buffer 6 xxxx
ADC Data Buffer 7 xxxx
ADC Data Buffer 8 xxxx

ADC Data Buffer 9 xxxx
ADC Data Buffer 10 xxxx
ADC Data Buffer 11 xxxx
ADC Data Buffer 12 xxxx
ADC Data Buffer 13 xxxx
ADC Data Buffer 14 xxxx
ADC Data Buffer 15 xxxx

All

Resets