Microchip Technology Inc PIC18C601-I-L, PIC18C801-I-L Datasheet
2001 Microchip Technology Inc. Advance Information DS39541A-page 1
PIC18C601/801
High Performance RISC CPU:
• C compiler optimized archi tecture instr uction set
• Linear program memory addressing up to 2 Mbytes
• Linear data memory addressing to 4 Kbytes
• Up to 160 ns instruction cycle:
- DC - 25 MHz clock input
- 4 MHz - 6 MHz clock input with PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 8 x 8 Single Cy cle Hardware Multiplier
Peripheral Features:
• High current sink/source 25 mA/25 mA
• Up to 47 I/O pins with individual direction control
• Three external interrupt pins
•Timer0 module: 8-bit/16-bit timer/counter with
8-bit programmable prescaler
•Timer1 module: 16-bit timer/counter (time-base for
CCP)
•Timer2 module: 8-bit timer/counter with 8-bit
period register
•Timer3 module: 16-bit timer/counter
• Secondary oscillator clock option - Timer1/Timer3
• Two Capture/Compare/PWM (CCP) modules
CCP pins can be configured as:
- Capture input: 16-bit, max. resolution 10 ns
- Compare is 16-bit, max. resolution 160 ns (TCY)
- PWM output: PWM resolution is 1- to 10-bit
Max. PWM freq. @:
8-bit resolution = 99 kHz
10-bit resolution = 24.4 kHz
• Master Synchronous Serial Port (MSSP) with two
modes of operation:
- 3-wire SPI™ (Supports all 4 SPI modes)
-I
2
C™ Master and Slave mode
• Addressable USART module: Supports Interrupt
on Address bit
Advanced Analog Features:
• 10-bit Analog-to-Digital Converter module (A/D)
with:
- Fast sampling rate
- Conversion available during SLEEP
- DNL = ±1 LSb, INL = ±1 LSb
- Up to 12 channels available
• Programmable Low Voltage Detection (LVD)
module
- Supports interrupt on Low Voltage Detection
Special Microcontroll er Features:
• Power-on Reset (POR), Power-up T imer (PWRT),
and Oscillator S tart-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator
• On-chip Boot RAM for boot loader application
• 8-bit or 16-bit external memory interface modes
• Up to two software programmable chip select sig-
nals (CS1
and CS2)
• One programmable chip I/O select signal (CSIO
)
for memory mapped I/O expansion
• Power saving SLEEP mode
• Different oscillator options, including:
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
CMOS T echnology:
• Low power, high speed CMOS technology
• Fully static design
• Wide operating voltage range (2.0V to 5.5V)
• Industrial and Extended temperature ranges
• Low power consumption
Device
External Program Memory
On-Chip
RAM (bytes)
On-Chip
Maximum
Addressing
(bytes)
Maximum
Single Word
Instructions
PIC18C601 256K 128K 1.5K
PIC18C801 2M 1M 1.5K
High-Performance ROM-less Microcontrollers
with External Memory Bus
PIC18C601/801
DS39541A-page 2 Advance Information 2001 Microchip Technology Inc.
Pin Diagrams
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
RE2/AD10
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/AD15
RD0/AD0
VDDVSS
RD1/AD1
RD2/AD2
RD3/AD3
RD4/AD4
RD5/AD5
RD6/AD6
RD7/AD7
RE1/AD9
RE0/AD8
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
MCLR/VPP
RG4/BA0
V
SS
VDD
RF7/UB
RF6/LB
RF5/CS1
RF4/A16
RF3/CSIO
RF2/AN7
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
RB5
RB6
V
SS
OSC2/CLKO
OSC1/CLKI
V
DD
RB7
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RF0/AN5
RF1/AN6
AV
DD
AV
SS
RA3/AN3/V
REF
+
RA2/AN2/V
REF
-
RA1/AN1
RA0/AN0
V
SS
V
DD
RA4/T0CKI
RA5/SS
/AN4/LVDIN
RC1/T1OSI
RC0/T1OSO/T13CKI
RC7/RX/DT
RC6/TX/CK
RC5/SDO
64-Pin TQFP
PIC18C601
2001 Microchip Technology Inc. Advance Information DS39541A-page 3
PIC18C601/801
Pin Diagrams (Cont.’d)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
9 8 7 6 5 4 3 2 1 6867666564636261
2728 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
RB5
RB6
V
SS
NC
OSC1/CLKI
V
DD
RB7
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RE1/AD9
RE0/AD8
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
MCLR/VPP
RG4/BA0
V
SS
VDD
RF7/UB
RF6/LB
RF5/CS1
RF4/A16
RF3/CSIO
RF2/AN7
RE2/AD10
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/AD15
RD0/AD0
VDDV
SS
RD1/AD1
RD2/AD2
RD3/AD3
RD4/AD4
RD5/AD5
RD6/AD6
RD7/AD7
RF1/AN6
RF0/AN5
AV
DD
AV
SS
RA3/AN3/V
REF
+
RA2/AN2/V
REF
-
RA1/AN1
RA0/AN0
V
DD
RA4/T0CKI
RA5/SS
/AN4/LVDIN
RC1/T1OSI
RC0/T1OSO/T13CKI
RC7/RX/DT
RC6/TX/CK
RC5/SDO
OSC2/CLKO
NC
NC
NC
V
SS
68-Pin PLCC
PIC18C601
PIC18C601/801
DS39541A-page 4 Advance Information 2001 Microchip Technology Inc.
Pin Diagrams (Cont.’d)
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
64 63 62 61
21 22 23 24 25 26 27 2 8 29 30 31 32
RE2/AD10
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/AD15
RD0/AD0
VDDVSS
RD1/AD1
RD2/AD2
RD3/AD3
RD4/AD4
RD5/AD5
RD6/AD6
RD7/AD7
RE1/AD9
RE0/AD8
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
MCLR/VPP
RG4/BA0
V
SS
VDD
RF7/UB
RF6/LB
RF5/CS1
RF4/CS2
RF3/CSIO
RF2/AN7
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
RB5
RB6
V
SS
OSC2/CLKO
OSC1/CLKI
V
DD
RB7
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RF0/AN5
RF1/AN6
AVDD
AVSS
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
V
SS
VDD
RA4/T0CKI
RA5/SS
/AN4/LVDIN
RC1/T1OSI
RC0/T1OSO/T13CKI
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RJ0/D7
RJ1/D6
RH1/A17
RH0/A16
1
2
RH2/A18
RH3/A19
17
18
RH4/AN8
RH5/AN9
RH6/AN10
RH7/AN11
RJ1/D1
RJ0/D0
37
RJ3/D3
RJ2/D2
50
49
RJ5/D5
RJ4/D4
19
20
33 34
35 36 38
58
57
56
55
54
53
52
51
60
59
68 67 66 6572 71 70 6974 73
78
77 76 75
79
80
80-Pin TQFP
PIC18C801
2001 Microchip Technology Inc. Advance Information DS39541A-page 5
PIC18C601/801
Pin Diagrams (Cont.’d)
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
5352
51
50
4948
47
4645
44
987654321
27
28
29
30
31
32
33
3435 36 37 38 39 40 41 42 43
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB4
RB5
RB6
V
SS
NC
OSC1/CLKI
VDD
RB7
RC4/SDI/SDA
RC3/SCK/SCL
RC2/CCP1
RE1/AD9
RE0/AD8
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
MCLR/VPP
RG4/BA0
V
SS
VDD
RF7/UB
RF6/LB
RF5/CS1
RF4/CS2
RF3/CSIO
RF2/AN7
RE2/AD10
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/AD15
RD0/AD0
V
DD
VSS
RD1/AD1
RD2/AD2
RD3/AD3
RD4/AD4
RD5/AD5
RD6/AD6
RD7/AD7
RF1/AN6
RF0/AN5
AV
DD
AVSS
RA3/AN3/VREF+
RA2/AN2/V
REF-
RA1/AN1
RA0/AN0
V
SS
VDD
RA4/T0CKI
RA5/SS
/AN4/LVDIN
RC1/T1OSI
RC0/T1OSO/T13CKI
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RJ5/D5
RJ4/D4
RJ7/D7
RJ6/D6
RJ0/D0
RJ1/D1
RJ3/D3
RJ2/D2
RH1/A17
RH0/A16
RH2/A18
RH3/A19
RH6/AN10
RH7/AN11
RH4/AN8
RH5/AN9
67
66
65
64
63
62
61
68
74
73
72
71
70
76
797877
80
83 82 81
84 75
69
OSC2/CLKO
NC
NC
NC
84-Pin PLCC
PIC18C801
PIC18C601/801
DS39541A-page 6 Advance Information 2001 Microchip Technology Inc.
Table of Contents
1.0 Device Overview.................................................................................... ..... ...... ...................................................9
2.0 Oscillator Configurations....................................................................................................................................21
3.0 RESET...............................................................................................................................................................29
4.0 Memory Organization........................................................................................................................................39
5.0 External Memory Interface............. ..... ...... ....................................... ...... ............................................................63
6.0 Table Reads/Table Writes.................................................................................................................................73
7.0 8 X 8 Hardware Multiplier..................................................................................................................................85
8.0 Interrupts............................................................................................................................................................89
9.0 I/O Ports...........................................................................................................................................................103
10.0 Timer0 Module.................................................................................................................................................127
11.0 Timer1 Module.................................................................................................................................................130
12.0 Timer2 Module.................................................................................................................................................135
13.0 Timer3 Module.................................................................................................................................................137
14.0 Capture/Compare/PWM (CCP) Modules.........................................................................................................141
15.0 Master Synchronous Serial Port (MSSP) Module............................................................................................149
16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).....................................177
17.0 10-bit Analog-to-Digital Converter (A/D) Module.............................................................................................193
18.0 Low Voltage Detect..........................................................................................................................................203
19.0 Special Features of the CPU...........................................................................................................................207
20.0 Instruction Set Summary .................................................................................................................................215
21.0 Development Support......................................................................................................................................259
22.0 Electrical Characteristics............... ..... ...... ....................................... ...... ..... .....................................................265
23.0 DC and AC Characteristics Graphs and Tables..............................................................................................295
24.0 Packaging Information.....................................................................................................................................297
Appendix A: Data Sheet Revision History..................................................................................................................303
Appendix B: Device Differences ................................................................................................................................303
Appendix C: Device Migrations..................................................................................................................................304
Appendix D: Migrating from other PICmicro Devices.................................................................................................304
Appendix E: Development Tool Version Requirements.............................................................................................305
Index ...........................................................................................................................................................................307
On-Line Support..........................................................................................................................................................315
Reader Response.......................................................................................................................................................316
Product Identification System......................................................................................................................................317
2001 Microchip Technology Inc. Advance Information DS39541A-page 7
PIC18C601/801
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
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enhanced as new volumes and updates are introduced.
If you have any questions or co mm ents regarding this publication, please contact the Marketing Communications Department via
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We welcome your feedback.
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The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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To determine if an errata sheet exists for a particular device, please check with one of the following:
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PIC18C601/801
DS39541A-page 8 Advance Information 2001 Microchip Technology Inc.
NOTES:
2001 Microchip Technology Inc. Advance Information DS39541A-page 9
PIC18C601/801
1.0 DEVICE OVERVIEW
This document co nta i ns dev ice sp ec if i c in for m at ion fo r
the following two devices:
1. PIC18C601
2. PIC18C801
The PIC18C601 is ava ilable in 64- pin TQFP and 6 8-pin
PLCC packages. The PIC18C801 is av ailable in 80-pin
TQFP and 84-pin PLCC packages.
An overview of features is shown in Table 1-1.
Device block diagrams are provided in Figure 1-1 for
the 64/68-p in confi gurati on, and Fi gure 1-2 fo r the 80/
84-pin configuration. The pinouts for both packages
are listed in Table 1-2.
TABLE 1-1: DEVICE FEATURES
Features PIC18C601 PIC18C801
Operating Frequency DC - 25 MHz DC - 25 MHz
External
Program Memory
Bytes 256K 2M
Max. # of Single Word
Instructions
128K 1M
Data Memory (Bytes) 1536 1536
Interrupt Sources 15 15
I/O Ports Ports A - G Ports A - H, J
Timers 4 4
Capture/Compare/PWM modules 2 2
Serial Communications
MSSP,
Addressable USART
MSSP,
Addressable USART
10-bit Analog-to-Digital Module 8 input channels 12 input channels
RESETS (and Delays)
POR,
RESET Instruction, Stack Full,
Stack Underflow (PWRT, OST)
POR,
RESET Instruction, Stack Full,
Stack Underflow (P WRT, OST)
Programmable Low Voltage Detect Yes Yes
8-bit External Memory Interface Yes Yes
8-bit De-multiplexed External
Memory Interface
No Yes
16-bit External Memory Interfaces Yes Yes
On-chip Chip Select Signals CS1
CS1, CS2
On-chip I/O Chip Select Signal Yes Yes
Instruction Set 75 Instructions 75 Instructions
Packages
64-pin TQFP
68-pin PLCC
80-pin TQFP
84-pin PLCC
PIC18C601/801
DS39541A-page 10 Advance Information 2001 Microchip Technology Inc.
FIGURE 1-1: PIC18C601 BLOCK DIAGRAM
Instruction
Decode &
Control
OSC1/CLKI
OSC2/CLKO
MCLR
VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4/SS
/LVDIN
RB0/INT0
RC0/T1OSO/T13CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
USART1
CCP1
Synchronous
Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
Timing
Generation
RB1/INT1
Address<12>
12
BSR
FSR0
FSR1
FSR2
inc/dec
logic
4
12 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
WREG
8
BITOP
8
8
ALU<8>
8
Address Latch
Program Memory
(up to 256 Kbytes)
Data Latch
20
21
21
16
8
8
8
Table Pointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
Timer3
PORTD
RD7:RD0/AD7:AD0
CCP2
RB2/INT2
RB3/CCP2
T1OSI
T1OSO
PCLATU
PCU
PORTF
RF0/AN5
RF1/AN6
RF2/AN7
PORTG
10-bit A/D
RB4
RB5
RB6
RB7
RE7:RE0/AD15:AD8
PORTE
RF3/CSIO
RF4/A16
RF5/CS1
RF6/LB
RF7/UB
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
RG4/BA0
AD7:AD0
A16, AD15:AD8
System Bus Interface
Power-up
Timer
Oscillator
Start-upTimer
Power-on
Reset
Watchdog
Timer
Low Voltage
Detect
Decode
Bank0,F
Data Latch
Data RAM
1 Kbyte
Address Latch
5
2001 Microchip Technology Inc. Advance Information DS39541A-page 11
PIC18C601/801
FIGURE 1-2: PIC18C801 BLOCK DIAGRAM
Instruction
Decode &
Control
OSC1/CLKI
OSC2/CLKO
MCLR
VDD, VSS
PORTA
PORTB
PORTC
RA4/T0CKI
RA5/AN4/SS
/LVDIN
RB0/INT0
RC0/T1OSO/T13CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX1/CK1
RC7/RX1/DT1
USART1
CCP1
Synchronous
Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF+
RA2/AN2/VREF-
RA1/AN1
RA0/AN0
Timing
Generation
RB1/INT1
Data Latch
Data RAM
Address<12>
12
Bank0,F
FSR0
FSR1
FSR2
inc/dec
logic
Decode
4
12 4
PCH PCL
PCLATH
8
31 Level Stack
Program Counter
PRODLPRODH
8 x 8 Multiply
WREG
8
BITOP
8
8
ALU<8>
8
Address Latch
Program Memory
(up to 2 Mbytes)
Data Latch
20
21
21
16
8
8
8
TablePointer<21>
inc/dec logic
21
8
Data Bus<8>
Table Latch
8
IR
12
3
ROM Latch
Timer3
PORTD
RD7:RD0/AD7:AD0
CCP2
RB2/INT2
RB3/CCP2
T1OSI
T1OSO
PCLATU
PCU
PORTF
RF0/AN5
RF1/AN6
RF2/AN7
PORTG
10-bit A/D
RB4
RB5
RB6
RB7
RE7:RE0/AD15:AD8
PORTE
RF3/CSIO
RF4/CS2
RF5/CS1
RF6/LB
RF7/UB
RG0/ALE
RG1/OE
RG2/WRL
RG3/WRH
RG4/BA0
PORTH
RH3:RH0/A19:A16
PORTJ
RJ7:RJ0/D7:D0
RH4/AN8
RH5/AN9
RH6/AN10
RH7/AN11
AD7:AD0
A19:A16, AD15:AD0
System Bus Interface
5
Power-up
Timer
Oscillator
Start-upTimer
Power-on
Reset
Watchdog
Timer
Low Voltage
Detect
1 Kbyte
Address Latch
BSR
PIC18C601/801
DS39541A-page 12 Advance Information 2001 Microchip Technology Inc.
TABLE 1-2: PINOUT I/O DESCRIPTIONS
Pin Name
Pin Number
Pin
Type
Buffer
Type
PIC18C601 PIC18C801
TQFP PLCC TQFP PLCC Description
MCLR
/VPP
MCLR
VPP
716920
I
P
ST Master clear (RESET) input. Th is pin is
an active low RESET to the dev i ce.
Programming voltage in pu t.
NC
— 1, 18,
35, 52
— 1, 22,
43, 64
——These pins shou ld be l eft
unconnected.
OSC1/CLKI
OSC1
CLKI
39 50 49 62
IICMOS/ST
CMOS
Oscillator crystal inp ut or ex te rn al cl ock
source input. ST buffer when in RC
mode. Otherwise CMOS.
External clock source input.
Always associated with pi n f unc tion
OSC1 (see OSC1/CLKI, OSC2/CLKO
pins).
OSC2/CLKO
OSC2
CLKO
40 51 50 63
O
O
—
—
Oscillator crystal outp ut .
Connects to crystal or resonator in
Crystal Oscillator mode.
In RC mode, OSC2 pin ou tp ut s CL KO,
which has 1/4 the
frequency of OSC1 and denotes the
instruction cycle rate.
Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open Drain (no P diode to V
DD)
2001 Microchip Technology Inc. Advance Information DS39541A-page 13
PIC18C601/801
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
AN0
24 34 30 42
I/O
I
TTL
Analog
Digital I/O.
Analog input 0.
RA1/AN1
RA1
AN1
23 33 29 41
I/O
I
TTL
Analog
Digital I/O.
Analog input 1.
RA2/AN2/V
REF-
RA2
AN2
V
REF-
22 32 28 40
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 2.
A/D reference voltage (Low ) inp ut.
RA3/AN3/VREF+
RA3
AN3
V
REF+
21 31 27 39
I/O
I
I
TTL
Analog
Analog
Digital I/O.
Analog input 3.
A/D reference voltage (High) input.
RA4/T0CKI
RA4
T0CKI
28 39 34 47
I/OIST/OD
ST
Digital I/O – Open drain when
configured as output.
Timer0 external clock input.
RA5/AN4/SS
/LVDIN
RA5
AN4
SS
LVDIN
27 38 33 46
I/O
I
I
I
TTL
Analog
ST
Analog
Digital I/O.
Analog input 4.
SPI slave select input.
Low voltage detect input .
TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
PIC18C601 PIC18C801
TQFP PLCC TQFP PLCC Description
Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open Drain (no P diode to V
DD)
PIC18C601/801
DS39541A-page 14 Advance Information 2001 Microchip Technology Inc.
PORTB is a bi-directional I/O port. PORTB
can be softw are programmed for internal
weak pull-ups on all inputs.
RB0/INT0
RB0
INT0
48 60 58 72
I/O
I
TTL
ST
Digital I/O.
External interrupt 0.
RB1/INT1
RB1
INT1
47 59 57 71
I/O
I
TTL
ST
Digital I/O.
External interrupt 1.
RB2/INT2
RB2
INT2
46 58 56 70
I/O
I
TTL
ST
Digital I/O.
External interrupt 2.
RB3/CCP2
RB3
CCP2
45 57 55 69
I/O
I/O
TTL
ST
Digital I/O.
Capture2 input, Comp ar e2 output,
PWM2 output.
RB4 44 56 54 68 I/O TTL Digital I/O, Interrupt-on-change pin.
RB5 43 55 53 67 I/O TTL Digital I/O, Interrupt-on-change pin.
RB6 42545266I/OITTL
ST
Digital I/O, Interrupt-on-chang e pin.
ICSP programming clock.
RB7 37484760I/O
I/O
TTL
ST
Digital I/O, Interrupt-on-chang e pin.
ICSP programming data.
TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
PIC18C601 PIC18C801
TQFP PLCC TQFP PLCC Description
Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open Drain (no P diode to V
DD)
2001 Microchip Technology Inc. Advance Information DS39541A-page 15
PIC18C601/801
PORTC is a bi-directional I/O port.
RC0/T1OSO/T13CKI
RC0
T1OSO
T13CKI
30 41 36 49
I/O
O
I
ST
—
ST
Digital I/O.
Timer 1 oscillator output.
Timer1/Timer3 external clock input.
RC1/T1OSI
RC1
T1OSI
29 40 35 48
I/O
I
ST
CMOS
Digital I/O.
Timer1 oscillator input.
RC2/CCP1
RC2
CCP1
33 44 43 56
I/O
I/O
ST
ST
Digital I/O.
Capture1 input/Com par e1
output/PWM1 output .
RC3/SCK/SCL
RC3
SCK
SCL
34 45 44 57
I/O
I/O
I/O
ST
ST
ST
Digital I/O.
Synchronous serial clock
input/output for SPI mode.
Synchronous serial clock
input/output for I
2
C mode.
RC4/SDI/SDA
RC4
SDI
SDA
35 46 45 58
I/O
I
I/O
ST
ST
ST
Digital I/O.
SPI data in.
I
2
C data I/O.
RC5/SDO
RC5
SDO
36 47 46 59
I/O
O
ST
—
Digital I/O.
SPI data out.
RC6/TX/CK
RC6
TX
CK
31 42 37 50
I/O
O
I/O
ST
—
ST
Digital I/O.
USART asynchronous transmit.
USART synchronous clock.
RC7/RX/DT
RC7
RX
DT
32 43 38 51
I/O
I
I/O
ST
ST
ST
Digital I/O.
USART asynchronous receive.
USART synchronous data.
TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
PIC18C601 PIC18C801
TQFP PLCC TQFP PLCC Description
Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open Drain (no P diode to V
DD)
PIC18C601/801
DS39541A-page 16 Advance Information 2001 Microchip Technology Inc.
PORTD is a bi-directional I/O port. These
pins have TTL input buffers wh en external
memory is enabled.
RD0/AD0
RD0
AD0
583723
I/O
I/O
ST
TTL
Digital I/O.
External memory address /d at a 0.
RD1/AD1
RD1
AD1
55 67 69 83
I/O
I/O
ST
TTL
Digital I/O.
External memory address /d at a 1.
RD2/AD2
RD2
AD2
54 66 68 82
I/O
I/O
ST
TTL
Digital I/O.
External memory address /d at a 2.
RD3/AD3
RD3
AD3
53 65 67 81
I/O
I/O
ST
TTL
Digital I/O.
External memory address /d at a 3.
RD4/AD4
RD4
AD4
52 64 66 80
I/O
I/O
ST
TTL
Digital I/O.
External memory address /d at a 4.
RD5/AD5
RD5
AD5
51 63 65 79
I/O
I/O
ST
TTL
Digital I/O.
External memory address /d at a 5.
RD6/AD6
RD6
AD6
50 62 64 78
I/O
I/O
ST
TTL
Digital I/O.
External memory address /d at a 6.
RD7/AD7
RD7
AD7
49 61 63 77
I/O
I/O
ST
TTL
Digital I/O.
External memory address /d at a 7.
TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
PIC18C601 PIC18C801
TQFP PLCC TQFP PLCC Description
Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open Drain (no P diode to V
DD)
2001 Microchip Technology Inc. Advance Information DS39541A-page 17
PIC18C601/801
PORTE is a bi-directional I/O port.
RE0/AD8
RE0
AD8
211415
I/O
I/O
ST
TTL
Digital I/O.
External memory address /d at a 8.
RE1/AD9
RE1
AD9
110314
I/O
I/O
ST
TTL
Digital I/O.
External memory address /d at a 9.
RE2/AD10
RE2
AD10
649789
I/O
I/O
ST
TTL
Digital I/O.
External memory address /d at a 10.
RE3/AD11
RE3
AD11
638778
I/O
I/O
ST
TTL
Digital I/O.
External memory address /d at a 11.
RE4/AD12
RE4
AD12
627767
I/O
I/O
ST
TTL
Digital I/O.
External memory address /d at a 12.
RE5/AD13
RE5
AD13
616756
I/O
I/O
ST
TTL
Digital I/O.
External memory address /d at a 13.
RE6/AD14
RE6
AD14
605745
I/O
I/O
ST
TTL
Digital I/O.
External memory address /d at a 14.
RE7/AD15
RE7
AD15
594734
I/O
I/O
ST
ST
Digital I/O.
External memory address /d at a 15.
TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
PIC18C601 PIC18C801
TQFP PLCC TQFP PLCC Description
Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open Drain (no P diode to V
DD)
PIC18C601/801
DS39541A-page 18 Advance Information 2001 Microchip Technology Inc.
PORTF is a bi-directional I/O port.
RF0/AN5
RF0
AN5
18 28 24 36
I/O
I
ST
Analog
Digital I/O.
Analog input 5.
RF1/AN6
RF1
AN6
17 27 23 35
I/O
I
ST
Analog
Digital I/O.
Analog input 6.
RF2/AN7
RF2
AN7
16 26 18 30
I/O
I
ST
Analog
Digital I/O.
Analog input 7.
RF3/CSIO
RF3
CSIO
15 25 17 29
I/O
I/O
ST
ST
Digital I/O.
System bus chip select I/O.
RF4/A16
RF4/CS2
RF4
A16
CS2
14
—
24
—
—
16
—
28
I/O
I/O
O
ST
TTL
TTL
Digital I/O.
External memory address 16.
Chip select 2.
RF5/CS1
RF5
CS1
13 23 15 27
I/O
O
ST
TTL
Digital I/O.
Chip select 1.
RF6/LB
RF6
LB
12 22 14 26
I/O
O
ST
TTL
Digital I/O.
Low byte select signal for external
memory interface.
RF7/UB
RF7
UB
11 21 13 25
I/O
O
ST
TTL
Digital I/O.
High byte select signal for e xternal
memory interface.
TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
PIC18C601 PIC18C801
TQFP PLCC TQFP PLCC Description
Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open Drain (no P diode to V
DD)
2001 Microchip Technology Inc. Advance Information DS39541A-page 19
PIC18C601/801
PORTG is a bi-directional I/O port.
RG0/ALE
RG0
ALE
312516
I/O
O
ST
TTL
Digital I/O.
Address Lat ch Enable.
RG1/OE
RG1
OE
413617
I/O
O
ST
TTL
Digital I/O.
Output Enable.
RG2/WRL
RG2
WRL
514718
I/O
O
ST
TTL
Digital I/O.
Write Low control.
RG3/WRH
RG3
WRH
615819
I/O
O
ST
TTL
Digital I/O.
Write High control.
RG4/BA0
RG4
BA0
8 171021
I/O
O
ST
TTL
Digital I/O.
System bus byte addres s 0.
PORTH is a bi-directional I/O port.
RH0/A16
RH0
A16
——79 10
I/O
O
ST
TTL
Digital I/O.
External memory address 16.
RH1/A17
RH1
A17
——80 11
I/O
O
ST
—
Digital I/O.
External memory address 17.
RH2/A18
RH2
A18
—— 112
I/O
O
ST
—
Digital I/O.
External memory address 18.
RH3/A19
RH3
A19
—— 213
I/O
O
ST
—
Digital I/O.
External memory address 19.
RH4/AN8
RH4
AN8
——19 31
I/O
I
ST
Analog
Digital I/O.
Analog input 8.
RH5/AN9
RH5
AN9
——20 32
I/O
I
ST
Analog
Digital I/O.
Analog input 9.
RH6/AN10
RH6
AN10
——21 33
I/O
I
ST
Analog
Digital I/O.
Analog input 10.
RH7/AN11
RH7
AN11
——22 34
I/O
I
ST
Analog
Digital I/O.
Analog input 11.
TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
PIC18C601 PIC18C801
TQFP PLCC TQFP PLCC Description
Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open Drain (no P diode to V
DD)
PIC18C601/801
DS39541A-page 20 Advance Information 2001 Microchip Technology Inc.
PORTJ is a bi-directional I/O port.
RJ0/D0
RJ0
D0
——39 52
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 0.
RJ1/D1
RJ1
D1
——40 53
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 1.
RJ2/D2
RJ2
D2
——41 54
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 2.
RJ3/D3
RJ3
D3
——42 55
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 3.
RJ4/D4
RJ4
D4
——59 73
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 4.
RJ5/D5
RJ5
D5
——60 74
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 5.
RJ6/D6
RJ6
D6
——61 75
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 6.
RJ7/D7
RJ7
D7
——62 76
I/O
I/O
ST
TTL
Digital I/O.
System bus data bit 7.
V
SS 9, 25,
41, 56
19, 36,
53, 68
11,31,
51, 70
23, 44,
65, 84
P — Ground referen ce for logic and I/O pins.
V
DD 10,26,
38, 57
2, 20,
37, 49
12,32,
48, 71
2, 24,
45, 61
P — Positive supply fo r logi c and I/O pins.
A
VSS 20 30 26 38 P — Ground reference for analog modules.
A
VDD 19 29 25 37 P — Positive supply fo r an al og modules.
TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Name
Pin Number
Pin
Type
Buffer
Type
PIC18C601 PIC18C801
TQFP PLCC TQFP PLCC Description
Legend: TTL = TTL compatible i nput CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels Analog = Analog input
I = Input O = Output
P = Power OD = Open Drain (no P diode to V
DD)
2001 Microchip Technology Inc. Advance Information DS39541A-page 21
PIC18C601/801
2.0 OSCILLATOR
CONFIGURATIONS
2.1 Oscillator Types
PIC18C601/801 can be o perated in one of four oscillator modes, programmable by configuration bits
FOSC1:FOSC0 in CONFIG1H register:
1. LP Low Power Crystal
2. HS High Speed Crystal/Resonator
3. RC External R esistor/Capacitor
4. EC External Clock
2.2 Crystal Oscillator/Ceramic
Resonators
In LP or HS oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to
establish oscillation. Figure 2-1 shows the pin connections. An external c lock so urce may also be connecte d
to the OSC1 pin, as shown in Figure 2-3 and Figure 2-4.
PIC18C601/801 oscillator design requires the use of a
parallel cut crystal.
FIGURE 2-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS OR LP OSC
CONFIGURATION)
Note: Use of a series cut crystal may give a fre-
quency out of the crystal manufacturer’s
specifications.
Note 1: See Table2-1 and Table 2-2 for recom-
mended values of C1 and C2.
2: A series resistor (R
S) may be required for AT
strip cut crystals.
3: R
F varies with the crystal chosen.
C1
(1)
C2
(1)
XTAL
OSC2
OSC1
RF
(3)
SLEEP
To
Logic
PIC18C601/801
RS
(2)
Internal
PIC18C601/801
DS39541A-page 22 Advance Information 2001 Microchip Technology Inc.
TABLE 2-1: CERAMIC RESONATORS
TABLE 2-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
2.3 RC Oscillator
For timing insensitive applications, the "RC" oscillator
mode offers additional cost savings. The RC oscillator
frequency is a function of the sup pl y vo lt age, the resistor (R
EXT) and capacitor (CEXT) values and the operat-
ing temperature. In addition to this, the oscillator
frequency will vary from unit to unit due to normal process paramete r variatio n. Furtherm ore, the di fference
in lead frame capacitance between package types will
also affect the oscillation frequency, especially for low
C
EXT values. The user also needs to take into account
variation d ue t o t ole ranc e of ex ter nal R an d C c ompo nents used. Figu re 2-2 shows how the RC comb inatio n
is connected.
In the RC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for t est pu rp os es or to sy nc hr o niz e o t he r
logic.
FIGURE 2-2: RC OSCILLATOR MODE
Ranges Tested:
Mode Freq. OSC1 OSC2
HS 8.0 MHz
16.0 MHz
20.0 MHz
25.0 MHz
10 - 68 pF
10 - 22 pF
TBD
TBD
10 - 68 pF
10 - 22 pF
TBD
TBD
HS+PLL 4.0 MHz TBD TBD
These values are for design guidance only.
See notes on this page.
Resonators Used:
4.0 MHz Murata Erie CSA4.00MG ± 0.5%
8.0 MHz Murata Erie CSA8.00MT ± 0.5%
16.0 MHz Murata Erie CSA16.00MX ± 0.5%
All resonators u s ed di d not have built-in capacitor s.
Osc Type
Crystal
Freq.
Cap. Range C1Cap. Range
C2
LP 32.0 kHz 33 pF 33 pF
200 kHz 15 pF 15 pF
HS 4.0 MHz 15 pF 15 pF
8.0 MHz 15-33 pF 15-33 pF
20.0 MHz 15-33 pF 15-33 pF
25.0 MHz TBD TBD
HS+PLL 4.0 MHz 15 pF 15 pF
These values are for design guidance only.
See notes on this page.
Crystals Used
32.0 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz STD XTL 200.000kHz ± 20 PPM
1.0 MHz ECS ECS-10-13-1 ± 50 PPM
4.0 MHz ECS ECS-40-20-1 ± 50 PPM
8.0 MHz EPSON CA-301 8.000M-C ± 30 PPM
20.0 MHz EPSON CA-301 20.000M-C ± 30 PPM
Note 1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 2-1).
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the u ser shoul d consult th e
resonator/crystal manufacturer for appropriate values of external components.
4: Rs may be required in HS mode to avoid
overdriving crystals with low drive level
specification.
OSC2/CLKO
CEXT
REXT
OSC1
F
OSC/4
Internal
Clock
VDD
VSS
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
C
EXT > 20pF
or I/O
PIC18C601/801
2001 Microchip Technology Inc. Advance Information DS39541A-page 23
PIC18C601/801
2.4 External Clock Input
The EC oscillator mode requires an external clock
source to be connec ted to the OSC1 p in. The fe edback
device between O SC 1 a nd OSC2 is turned off in these
modes to save current. There is no oscillator start-up
time required after a Power-on Reset or after a
recovery from SLEEP mode.
In the EC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for t est pu rp os es or to sy nc hr o niz e o t he r
logic. Figure 2-3 shows the pin connections for the EC
oscillator mode.
FIGURE 2-3: EXTERNAL CLOCK INPUT
OPERATION (EC OSC
CONFIGURATION)
2.5 HS4 (PLL)
A Phase Lock Loop (PLL) circuit is provided as a software programmable optio n for us ers that want to m ultiply the frequency of the incoming crystal oscillator
signal by 4. For an input cl ock freq uency of 6 MHz, the
internal clock frequency will be multiplied to 24 MHz.
This is use ful for custom ers who are conc erned with
EMI due to high frequency crystals.
The PLL is enabled by configuring HS oscillator mode
and setting the PLLEN bit in the OSCON register. If HS
oscillator mode is not selected, or PLLEN bit in
OSCCON register is clear, the PLL is not enabled and
the system clock will come directly from OSC1. HS
oscillator mode i s the default for PIC18C601/801. In all
other modes, the PLLEN bit and the SCS1 bit are
forced to ‘0’.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out, referred to as T
PLL.
FIGURE 2-4: PLL BLOCK DIAGRAM
OSC1
OSC2
F
OSC/4
Clock from
ext. system
PIC18C601/801
MUX
VCO
Loop
Filter
Feedback Divider
3210
Crystal
Osc
OSCOUT
OSCIN
PLL Enable
F
IN
FOUT
SYSCLK
Phase
Comparator
CVCO
HS Osc
PIC18C601/801
DS39541A-page 24 Advance Information 2001 Microchip Technology Inc.
2.6 Oscillator Switching Feature
PIC18C601/801 devices include a feature that allows
the system clock source to be switched from the main
oscillator t o an alternate lo w frequency clock s ource.
For PIC18C601/801 devices, this alternate clock
source is the Timer1 oscillator. If a low frequency crystal (32 kHz, for example) has been attached to the
Timer1 oscillator pins and the Timer1 oscillator has
been enabled, the device can switch to a low power
execution mode. Figure 2-5 shows a block diagram of
the system clock sources.
2.6.1 SYSTEM CLOCK SWITCH BIT
The system clock source switching is performed under
software control. The system clock switch bit, SCS0
(OSCCON register), controls the clock switching. When
the SCS0 bit is ’0’, the system clock source comes from
the main oscillator, selected by the FOSC2:FOSC0 co nfiguration bits in C ONFIG1H registe r . When the SCS0 b it
is set, the system clock source will come from the Timer1
oscillator . The SCS0 bit is cle ared on all forms of RESET.
FIGURE 2-5: DEVICE CLOCK SOURCES
Note: The Timer1 oscillator must be enabled to
switch the system clock source. The
Timer1 oscillator is enabled by setting the
T1OSCEN bit in the T imer1 con trol register
(T1CON). If the Timer1 oscillator is not
enabled, an y write to the SCS0 bi t will be
ignored (SCS0 bit forced cleared) and the
main oscillator will continue to be the system clock sour ce.
PIC18C601/801
TOSC
4 x PLL
TT1P
TSCLK
Clock
Source
T
OSC/4
Timer 1 Oscillator
T1OSCEN
Enable
Oscillator
T1OSO
T1OSI
Clock Source option
for other modules
OSC1
OSC2
SLEEP
Main Oscillator
Note: I/O pins have diode protection to VDD and VSS.
MUX
2001 Microchip Technology Inc. Advance Information DS39541A-page 25
PIC18C601/801
REGISTER 2-1: OSCCON REGISTER
2.6.2 OSCIL LA TOR TRANSITIONS
PIC18C601/801 devices contain circuitry to prevent
"glitches" when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to.
This ensures that the new clock source is stable and
that its pulse width will not be less than the shortest
pulse width of the two clock sources.
A timing diagram indicati ng the transition from the main
oscillator to the Timer1 oscillator is shown in Figure 2-6.
The Timer1 oscillator is assumed to be running all the
time. After the SCS0 bit is set, the processor is frozen
at the next occurri ng Q1 c ycle. After eight synchronization cycles are counted from the T imer1 oscillator , operation resumes. No additional delays are required after
the synchronization cycles.
The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external crystal (HS, LP), the tra ns iti on w ill t a ke pl ac e a fter an oscillator start-up time (T
OST) has occurred. A timing
diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS and LP modes is
shown in Figure 2-7.
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — LOCK PLLEN SCS1 SCS0
bit 7 bit 0
bit 7-4 Unimplemented: Read as '0'
bit 3 LOCK: Phase Lock Loop Lock Status bit
1 = Phase Lock Loop output is stable as system clock
0 = Phase Lock Loop output is not stable and cannot be used as system clock
bit 2 PLLEN: Phase Lock Loop Enable bit
1 = Enable Phase Lock Loop output as system clock
0 = Disable Phase Lock Loop
bit 1 SCS1: System Clock Switch bit 1
When PLLEN and LOCK bit are set:
1 = Use PLL output
0 = Use primary oscillator/clock input pin
When PLLEN bit or LOCK bit is cleared:
Bit is forced clear
bit 0 SCS0: System Clock Switch bit 0
When T1OSCEN bit is set:
1 = Switch to Timer1 oscillator/clock pin
0 = Use primary oscillator/clock input pin
When T1OSCEN is cleared:
Bit is forced clear
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC18C601/801
DS39541A-page 26 Advance Information 2001 Microchip Technology Inc.
FIGURE 2-6: TIMING DIAGRAM FOR T R ANSITION FROM OSC1 TO TIMER1 OSCILLATOR
FIGURE 2-7: TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, LP)
Q3Q2Q1Q4Q3Q2
OSC1
Internal
SCS0
(OSCCON<0>)
Program
PC + 2PC
Note: Delay on internal system clock is eight oscillator cycles for synchronization.
Q1
T1OSI
Q4 Q1
PC + 4
Q1
TSCS
Clock
Counter
System
Q2 Q3 Q4 Q1
TDLY
TT1P
TOSC
21 34 5678
Q3
Q3 Q4
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
Internal System
SCS0
(OSCCON<0>)
Program Counter
PC
PC + 2
Note: TOST = 1024TOSC (drawing not to scale).
T1OSI
Clock
OSC2
TOST
Q1
PC + 4
TT1P
TOSC
TSCS
12345678
2001 Microchip Technology Inc. Advance Information DS39541A-page 27
PIC18C601/801
If the main oscillator is configured for HS4 (PLL) mode
with SCS1 bit set to ‘1’, an oscillator start-up time
(T
OST), plus an additional PLL time-out (TPLL) will
occur . The PLL tim e-out is typica lly 2 ms an d allows the
PLL to lock to the main oscillator frequency. A timing
diagram indicating the transition from the Timer1 oscillator to th e main oscill ator for HS4 m ode is shown in
Figure 2-8.
If the main oscill ator is confi gured for HS4 (PLL) m ode,
with SCS1 bit set to ‘0’, only oscillator start-up time
(T
OST) will occur. Since SCS 1 bi t is se t to ‘0’, PLL out-
put is not used, so the sys te m os ci ll ator wi ll c om e from
OSC1 directly and additional delay of TPLL is not
required. A timing diagram indicatin g the transit ion from
the Timer1 oscillator to the main oscillator for HS4
mode is shown in Figure 2-9.
If the main oscillator is configured in the RC or EC
modes, there is no osci llator sta rt-up t ime-out. Operation will resume after ei ght cycles of the main oscil lat or
have been counted. A timing diagram indicating the
transition from the T ime r1 osci llator to the main os cill ator for RC and EC modes is shown in Figure2-10.
FIGURE 2-8: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS4 WITH SCS1 = 1)
FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS4 WITH SCS = 0)
Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
Internal System
SCS0
(OSCCON<0>)
Program Counter
PC PC + 2
Note: T
OST = 1024TOSC (drawing not to scale).
T1OSI
Clock
TOST
Q3
PC + 4
TPLL
TOSC
TT1P
TSCS
Q4
OSC2
PLL Clock
Input
12345678
Q4
Q1
Q1 Q2 Q3 Q4 Q1 Q2
OSC1
Internal
SCS0
(OSCCON<0>)
Program
PC PC + 2
Note: TOST = 1024TOSC (drawing not to scale).
T1OSI
Clock
PLL
TOST
PC + 4
TPLL
TOSC
T
DLY
TT1P
OSC2
Output
Counter
System
Clock
TSCS
PIC18C601/801
DS39541A-page 28 Advance Information 2001 Microchip Technology Inc.
FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
2.6.3 SCS0, SCS 1 PRIORITY
If both SCS0 and SCS1 are set to ‘1’ simultaneously,
the SCS0 bit has priority over the SCS1 bit. Thi s means
that the low power option will t ake prece dence over the
PLL option. If both bits are cle ared si mult a neously, the
system clock will come from OSC1 , after a TOST timeout. If only the SCS0 bit is c leared, the system cloc k will
come from the PLL output, following T
OST
and TPLL
time.
TABLE 2-3: SCS0, SCS1 PRIORITY
2.7 Effects of SLEEP Mode on the
On-Chip Oscillator
When the device executes a SLEEP instruction, the
on-chip clocks and oscillator are turned off and the
device is held at the beginning of an instruction cycle
(Q1 state). With the os ci lla tor o f f, the O SC1 an d OS C2
signals will stop oscillating. Since all the transistor
switching currents have been removed, SLEEP mode
achieves the lowest current consumption of the device
(only leakage currents). Enabling any on-chip feature
that will operate during SLEEP, will increase the cur-
rent consumed during SLEEP. The user can wake from
SLEEP through external RESET, Watchdog Timer
Reset, or through an interrupt.
2.8 Power-up Delays
Power-up delays are controlled by two timers, so that
no external RESET circuitry is required for most applications. The delays ensure that the device is kept in
RESET until the device power sup ply and clock are st able. For additional information on RESET operation,
see Section 3.0 RESET .
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of T
PWRT (parameter
#33) on power-up only. The second timer is the Oscillator St art-u p T i mer (OST), inten ded to keep the c hip in
RESET until the crystal oscillator is stable.
PIC18C601/801 devices provide a configuration bit,
PWRTEN
in CONFIG2L register, to enable or disable
the Power-up Timer. By default, the Power-up Timer is
enabled.
With the PLL enabled (HS4 osc illator mode), the time-ou t
sequence fol lowing a Power-on R eset is different fr om
other oscillator modes. The time-out sequence is as follows: the PWRT time-out is invoked after a POR time
delay has expired, then, the Oscillator Start-up Timer
(OST) is i nvoked. However, this is still not a sufficient
amount of time to allow the PLL to lock at high frequencies. The PWRT ti mer is used to prov ide an addition al
time-out, called T
PLL (parameter #7), to allow the PLL
ample time to loc k to the incoming clock frequency.
TABLE 2-4: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
Q3 Q4
Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3
OSC1
Internal System
SCS0
(OSCCON<0>)
Program Counter
PC PC + 2
Note: RC oscillator mode assumed.
PC + 4
T1OSI
Clock
OSC2
Q4
TT1P
TOSC
TSCS
1
23
45678
SCS1 SCS0 Clock Source
0 0 Ext Oscillator OSC1
0 1 Timer1 Oscillator
10HS + PLL
1 1 Timer1 Oscillator
OSC Mode OSC1 Pin OSC2 Pin
RC Floating, external resistor should pull high At logic low
EC Floating At logic low
LP and HS Feedback inverter disabled, at quiescent voltage level Feedback inverter disabled, at quiescent voltage level
Note: See Table 3-1 in Section 3.0 RESET, for time-outs due to SLEEP and MCLR Reset.
2001 Microchip Technology Inc. Advance Information DS39541A-page 29
PIC18C601/801
3.0 RESET
PIC18C601/801 devices differentiate between various
kinds of RESET:
a) Power-on Reset (POR)
b) MCLR
Reset during normal operation
c) MCLR Reset during SLEEP
d) Watchdog Timer (WDT) Reset during normal
operation
e) RESET Instruction
f) Stack Full Reset
g) Stack Un derflow Reset
Most registers are una ffected b y a RESET. Their status
is unknown on POR and unchanged by all other
RESETS. The other registers are forced to a “RESET”
state on Power-on Reset, MCLR
, WDT Reset, MCLR
Reset during SLEEP, and by the RESET instruction .
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal operation. Status bits from the RCON regi ster, RI
, TO, PD
and POR, are set or cleared differently in different
RESET situations, as i ndicated in Table 3-2. These bits
are used in software to determine the nature of the
RESET. See Table 3-3 for a full description of the
RESET states of all registers.
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 3-1.
PIC18C601/801 has a MCLR
noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
A WDT Reset does not drive MCLR
pin low.
FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF THE ON-CHIP RESET CIRCUIT
S
R
Q
External Reset
MCLR
VDD
OSC1
VDD Rise
Detect
OST/PWRT
On-chip
RC OSC
(1)
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
10-bit Ripple Counter
Reset
Enable OST
(2)
Enable PWRT
SLEEP
Note 1: This is a separate oscillator from the RC oscillator of the CLKI pin.
2: See Table 3-1 for time-out situations.
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
WDT
Module
PIC18C601/801
DS39541A-page 30 Advance Information 2001 Microchip Technology Inc.
3.1 Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when a
V
DD rise is detected. To take advantage of the POR cir-
cuitry, connect the MCLR
pin directly (or through a
resistor) to V
DD. This will eliminate ext ernal RC compo-
nents usually needed to create a Power-on Reset
delay . A minimum rise rat e for V
DD is specified (param -
eter D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (exits the
RESET condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating conditions are m et . Po wer -o n R es et ma y b e us ed t o m ee t
the voltage start-up condition.
FIGURE 3-2: EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD POWER-UP)
3.2 Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33), only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is kept in RESET as long as the PWRT is
active. Th e PWRT tim e dela y al lows V
DD to rise t o an
acceptable level. PIC18C601/801 devices are available with PWRT enabled or disabled.
The power-up time delay wi ll vary from chip to chi p, due
to V
DD, temperature and process variation. See DC
parameter #33 for details.
3.3 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (para meter #32). This ensures th at
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for LP, HS and HS4
modes and only on Power-on Reset or wake-up from
SLEEP.
3.4 PLL Lock Time-out
With the PLL enabled, the time-ou t sequen ce foll owin g
a Power-on Reset is different from other oscillator
modes. A portion of the Power-u p Tim er is used to provide a fixed time-out that i s suff icient for the PLL to lock
to the main oscillato r frequency. This PLL lock time-out
(T
PLL) is typically 1 ms and follows the oscillator start-
up time-out (OST).
3.5 Time-out Sequence
On power-up, the time-out sequence is as follows:
First, PWRT time-out is invoked after the POR time
delay has expired; then, OST is activated. The total
time-out will vary based on oscillator configuration and
the status of th e PW RT. For exam pl e, in R C m ode w i th
the PWRT disabled, there will be no time-out at all.
Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and
Figure 3-7 depict time-out sequences on power-up.
Since the time-outs occur from the PO R pulse, if MCLR
is kept low long enough, the time-outs will expire.
Bringing MCLR
high will begin execution immediately
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18C601/801 device
operating in parallel.
Table 3-2 shows the RESET conditions for some
Special Function Registers, while Table 3-3 shows the
RESET conditions for all registers.
Note 1: External Power-on Reset circuit is required only
if the V
DD power-up slope is too slow. The diode
D helps discharge the capacitor quickly when
V
DD powers down.
2: R < 40 kΩ is recommended to make sure that
the voltage drop across R does not violate the
device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current flowing
into MCLR
from external capacitor C, in the
event of MCLR/
VPP pin breakdown due to
Electrostatic Discharge (ESD), or Electrical
Overstress (EOS).
C
R1
R
D
V
DD
MCLR
PIC18C601/801
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