Microchip Technology Inc PIC18C242-I-SO, PIC18C252-I-SO Datasheet
PIC18CXX2
High-Performance Microcontrollers with 10-Bit A/D
High Performance RISC CPU:
• C-compiler optimized architecture/instruction set
- Source code compatible with the PIC16CXX
instruction set
• Linear program memory addressing to 2M bytes
*
• Linear data memory addressing to 4K bytes
*
Device
On-Chip Program Memory
EPROM
(bytes)
# Single W or d
Instructions
On-Chip
RAM
(bytes)
PIC18C242 16K 8192 512
PIC18C252 32K 16384 1536
PIC18C442 16K 8192 512
PIC18C452 32K 16384 1536
• Up to 10 MIPs operation:
*
- DC - 40 MHz osc./clock input
- 4 MHz - 10 MHz osc./clock input with PLL active
• 16-bit wide instructions, 8-bit wide data path
• Priority levels for interrupts
• 8 x 8 Single Cycle Hardwa re Multiplier
*
Peripheral Features:
• High current sink/source 25 mA/25 mA
• Three external interrupt pins
• Timer0 module: 8-bit/16-bit timer/counter with
8-bit programmable prescaler
• Timer1 module: 16-bit timer/counter
• Timer2 module: 8-bit timer/counter with 8-bit
period register (time-base for PWM)
• Timer3 module: 16-bit timer/counter
*
• Secondary oscillator clock option - Timer1/Timer3
•Two Capture/Compare/PWM (CCP) modules. CCP
pins that can be configured as:
- Capture input: capture is 16-bit,
max. resolution 6.25 ns (T
- Compare is 16-bit, max. resolution 100 ns (T
- PWM output: PWM resolution is 1- to 10-bit.
Max. PWM freq. @:8-bit resolution = 156 kHz
• Master Synchronous Seria l Port (MSSP) module.
Two modes of operation:
- 3-wire SPI™ (supports all 4 SPI modes)
2
C™ master and slave mode
-I
• Addressable USART module:
- Supports interrupt on Address bit
• Parallel Slave Port (PSP) module
CY/16)
10-bit resolution= 39 kHz
CY)
Pin Diagrams
DIP, Windowed CERDIP
RB7
RB6
RB5
RB4
RB3/CCP2
RB2/INT2
RB1/INT1
RB0/INT0
V
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
*
DD
DD
1
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
*
16
17
18
19
20
MCLR/VPP
RA0/AN
RA1/AN1
RA2/AN2/V
RA3/AN3/V
RA5/AN4/SS
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC3/SCK/SCL
* RB3 is the alternate pin for the CCP2 pin multiplexing.
REF-
REF+
RA4/T0CKI
/LVDIN
RE0/RD/AN5
RE1/WR/AN6
RE2/CS/AN7
V
VSS
OSC1/CLKI
RC2/CCP1
RD0/PSP0
RD1/PSP1
40
39
38
37
36
35
34
33
32
31
30
29
PIC18C4X2
28
27
26
25
24
23
22
21
NOTE: Pin compatible with 40-pin PIC16C7X devices
Analog Features:
• 10-bit Analog-to-Digital Converter module (A/D)
with:
- Fast sampling rate
- Conversio n a vailable during sl eep
- DNL = ±1 LSb, INL = ±1 LSb
• Programmable Low-Voltage Detection (LVD)
module
- Supports interrupt on low voltage detection
• Programmable Brown-out Reset (BOR)
Special Microcontroller Features:
• Power-on Reset (POR), Power-up Timer (PWRT)
and Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Pow er saving SLEEP mode
• Selectable oscillator options including:
- 4X Phase Lock Loop (of primary oscillator)
- Secondary Oscillator (32 kHz) clock input
• In-Circuit Serial Programming (ICSP™) via two pins
CMOS Technology:
• Low-power, high-speed EPROM technology
• Fully static design
• Wide operating voltage range (2.5V to 5.5V)
• Industrial and Extended temperature ranges
• Low-power consumption
7/99 Microchip Technology Inc.
Preliminary DS39026B-page 1
PIC18CXX2
Pin Diagrams
PLCC
REF-
/VPP
RA4/T0CKI
RA5/AN4/SS
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
/LVDIN
/AN5
RE0/RD
RE1/WR/AN6
/AN7
RE2/CS
V
VSS
OSC1/CLKI
NC
RA3/AN3/VREF+
65432
7
8
9
10
11
DD
12
13
14
15
16
181920212223242526
17
RC2/CCP1
RC1/T1OSI/CCP2
NC
RB7
RA0/AN0
RB6
MCLR
1
44
43
RA2/AN2/V
RA1/AN1
PIC18C4X2
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RB5
42
27
RC6/TX/CK
RC5/SDO
RB4
41
28
NC
NC
40
39
38
37
36
35
34
33
32
31
30
29
RB3/CCP2*
RB2/INT2
RB1/INT1
RB0/INT0
DD
V
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
*
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2*NC
TQFP
4443424140
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
V
SS
VDD
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
*
* RB3 is the alternate pin for the CCP2 pin multiplexing.
NOTE: Pin compatible with 44-pin PIC16C7X devices
1
2
3
4
5
6
7
8
9
10
11
121314
NC
NC
PIC18C4X2
15
RB5
RB4
16
RB6
39
17
RB7
38
363435
37
1819202122
RA2/AN2/V
RA1/AN1
RA0/AN0
MCLR
/VPP
REF-
33
32
31
30
29
28
27
26
25
24
23
RA3/AN3/VREF+
NC
RC0/T1OSO/T1CKI
OSC2/CLKO/RA6
OSC1/CLKI
SS
V
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS/LVDIN
RA4/T0CKI
DS39026B-page 2 Preliminary
7/99 Microchip Technology Inc.
Pin Diagrams (Cont.’d)
PIC18CXX2
DIP, JW
MCLR/VPP
RA0/AN0
RA1/AN1
RA4/T0CKI
/LVDIN
RE0/RD
RE1/WR
RE2/CS
OSC1/CLKI
RC2/CCP1
RD0/PSP0
RD1/PSP1
REF-
REF+
/AN5
/AN6
/AN7
V
VSS
RA2/AN2/V
RA3/AN3/V
RA5/AN4/SS
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC3/SCK/SCL
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
*
15
16
17
18
19
20
NOTE: Pin compatible with 40-pin PIC16C7X devices
PIC18C4X2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3/CCP2
RB2/INT2
RB1/INT1
RB0/INT0
V
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
*
DD
DIP, SOIC, JW
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2/V
RA3/AN3/V
RA5/AN4/SS
OSC2/CLKO/RA6
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC3/SCK/SCL
REF-
REF+
RA4/T0CKI
/LVDIN
V
OSC1/CLKI
RC2/CCP1
SS
*
* RB3 is the alternate pin for the CCP2 pin multiplexing.
NOTE: Pin compatible with 28-pin PIC16C7X devices
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
PIC18C2X2
19
18
17
16
15
RB7
RB6
RB5
RB4
RB3/CCP2
RB2/INT2
RB1/INT1
RB0/INT0
V
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
*
DD
7/99 Microchip Technology Inc.
Preliminary DS39026B-page 3
PIC18CXX2
Table of Contents
1.0 Device Overview..........................................................................................................................................................................5
2.0 Oscillator Configurations............................................................................................................................................................ 15
3.0 Reset..........................................................................................................................................................................................23
4.0 Memory Organization.................................................................................................................................................................33
5.0 Table Reads/Table Writes..........................................................................................................................................................53
6.0 8 X 8 Hardware Multiplier...........................................................................................................................................................61
7.0 Interrupts....................................................................................................................................................................................65
8.0 I/O Ports...................... ..................................... .......................... ....................................... ...................................... ................... 77
9.0 Timer0 Module ...........................................................................................................................................................................93
10.0 Timer1 Module ...........................................................................................................................................................................97
11.0 Timer2 Module .........................................................................................................................................................................102
12.0 Timer3 Module .........................................................................................................................................................................105
13.0 Capture/Compare/PWM (CCP) Modules .................................................................................................................................109
14.0 Master Synchronous Serial Port (MSSP) Module ....................................................................................................................117
15.0 Addressable Universal Synchronous Asynchronous Receiv er Transmitter (USA RT )..............................................................151
16.0 10-bit Analog-to-Digital Converter (A/D) Module......................................................................................................................167
17.0 Low Voltage Detect ..................................................................................................................................................................175
18.0 Special Features of the CPU.................................................................................................................................................... 181
19.0 Instruction Set Summary..........................................................................................................................................................191
20.0 Development Support. .............................................................................................................................................................. 235
21.0 Electrical Characteristics..........................................................................................................................................................241
22.0 DC and AC Characteristics Graphs and Tables.......................................................................................................................273
23.0 Packaging Information........................................... ............................................................................................................... .... 275
Appendix A: Revision History.........................................................................................................................................................283
Appendix B: Device Differences.....................................................................................................................................................283
Appendix C: Conversion Considerations.......................................................... .. ....... .... .. .... .. .. ....... ................................................284
Appendix D: Migration from Baseline to Enhanced Devices................................................... ....... .... .. .... .. ....................................284
Appendix E: Migration from Midrange to Enhanced Devices........................................................... .. .. .... .. .................................... 285
Appendix F: Migration from High-end to Enhanced Devices ......................................................................................................... 285
Index ....................................................................... .. .. ..... .... .. .. .. .. .. ....... .. .. .. .. .. .... .. ............................................................................287
On-Line Support...................................................................... .... .... .. ......... .... .. .... ....... .... ................................................................... 293
Reader Response..............................................................................................................................................................................294
PIC18CXX2 Product Identification System ........................................................................................................................................ 295
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
Errata
An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and recommended
workarounds. As device/documentation issues become known to us, w e will pub lish an errata sheet. The errata will specify the re vision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include liter-
ature number) you are using.
Corrections to this Data Sheet
We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
that this document is correct. However , w e realize that we ma y ha v e missed a f ew things . If y ou find any inf ormation that is missi n g
or appears in error, please:
• Fill out and mail in the reader response form in the back of this data sheet.
• E-mail us at webmaster@microchip.com.
We appreciate your assistance in making this a better document.
DS39026B-page 4 Preliminary
7/99 Microchip Technology Inc.
PIC18CXX2
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the following four devices:
1. PIC18C242
2. PIC18C252
3. PIC18C442
4. PIC18C452
These devices come in 28 and 40-pin packages. The
28-pin devices do not have a Parallel Slave Port (PSP)
implemented and the numb er of Analog-to-Digital (A/D)
converter input channels is reduced to 5. An overview
of features is shown in Table 1-1.
The following two figures are device block diagrams
sorted by pin count; 28-pin f or Figur e 1-1 and 40-pin f or
Figure 1-2. The 28-pin and 40-pin pinouts are listed in
Table 1-2 and Table 1-3 respectively.
TABLE 1-1: DEVICE FEATURES
Features PIC18C242 PIC18C252 PIC18C442 PIC18C452
Operating Frequency DC - 40 MHz DC - 40 MHz DC - 40 MHz DC - 40 MHz
Program Memory (Bytes) 16K 32K 16K 32K
Program Memory (Instructions) 8192 16384 8192 16384
Data Memory (Bytes) 512 1536 512 1536
Interrupt sources 16 16 17 17
I/O Ports Ports A, B, C Ports A, B, C Ports A, B, C, D, E Ports A, B, C, D, E
Timers 4 4 4 4
Capture/Compare/PW M mod ul es 2 2 2 2
Serial Communications MSSP,
Addressable
USART
Parallel Communications — — PSP PSP
10-bit Analog-to-Digital Module 5 input channels 5 input channels 8 input channels 8 input channels
Resets (and Delays) POR, BOR,
Reset Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
Programmable Low Voltage Detect Yes Yes Yes Yes
Programmable Brown-out Reset Yes Yes Yes Yes
Instruction Set 75 Instructions 75 Instructions 75 Instructions 75 Instructions
Packages 28-pin DIP
28-pin SOIC
28-pin JW
MSSP,
Addressable
USART
POR, BOR,
Reset Instruction ,
Stack Full,
Stack Underflow
(PWRT, OST)
28-pin DIP
28-pin SOIC
28-pin JW
MSSP,
Addressable
USART
POR, BOR,
Reset Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
40-pin DIP
40-pin PLCC
40-pin TQFP
40-pin JW
MSSP,
Addressable
USART
POR, BOR,
Reset Instruction,
Stack Full,
Stack Underflow
(PWRT, OST)
40-pin DIP
40-pin PLCC
40-pin TQFP
40-pin JW
7/99 Microchip Technology Inc.
Preliminary DS39026B-page 5
PIC18CXX2
FIGURE 1-1: PIC18C2X2 BLOCK DIAGRAM
Data Bus<8>
Address Latch
Program Memory
(up to 2M Bytes)
OSC2/CLKO
OSC1/CLKI
T1OSI
T1OSO
21
Data Latch
16
21
Table Pointer < 2>
21
inc/dec logic
TABLELATCH
8
Instruction
Decode &
Control
Timing
Generation
4X PLL
Precision
Voltage
Reference
20
8
PCLATH
PCLATU
PCH
PCU
Program Counter
31 Level Stack
ROMLATCH
Instruction
Register
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
MCLR
8
VDD, VSS
PCL
8
4
BSR
Decode
BIT OP
3
8
Data Latch
Data RAM
Address Latch
12
Address<12>
12 4
FSR0
FSR1
FSR2
inc/dec
logic
PRODLPRODH
8 x 8 Multiply
WREG
8
8
ALU<8>
8
(2)
Bank0, F
PORTA
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
RA6
/L VDIN
12
PORTB
RB0/INT0
RB1/INT1
RB2/INT2
8
RB3/CCP2
RB7:RB4
(1)
8
8
PORTC
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
(1)
Timer0 Timer1 Timer2
Master
CCP1
CCP2
Synchronous
Serial Port
Timer3
Addressable
USART
A/D Converter
Note1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direct Address for the RAM are from the BSR register (except for the MOVFF
instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions. The
multiplexing combinations are device dependent.
DS39026B-page 6 Preliminary
7/99 Microchip Technology Inc.
FIGURE 1-2: PIC18C4X2 BLOCK DIAGRAM
Table Pointe r < 2 >
Address Latch
Program Memory
(up to 2M B y tes)
Data Latch
OSC2/CLKO
OSC1/CLKI
T1OSI
T1OSO
21
8
21
21
16
inc/dec logic
TABLELATCH
Instruction
Decode &
Control
Timing
Generation
4X PLL
20
8
PCLATU
PCLATH
PCH PCL
PCU
Program Counter
31 Level Stack
ROMLATCH
Instruction
Register
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
8
8
4
Decode
BIT OP
BSR
3
8
Data Bus<8>
Data Latch
Data RAM
(up to 4K
address reach )
Address Latch
12
Address<12>
12 4
Bank0, F
FSR0
FSR1
FSR2
inc/dec
logic
PRODLPRODH
8 x 8 Multiply
WREG
8
8
ALU<8>
PIC18CXX2
PORTA
(2)
PORTB
12
PORTC
8
8
8
PORTD
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/T0CKI
RA5/AN4/SS
RA6
RB0/INT0
RB1/INT1
RB2/INT2
RB3/CCP2
RB7:RB4
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD7/PSP7:RD0/PSP0
/L VDIN
(1)
(1)
Precision
Voltage
Reference
Timer0 Timer1 Timer2
CCP1
CCP2
Brown-out
MCLR
Reset
VDD, VSS
Master
Synchronous
Serial Port
8
Timer3
Addressable
USART
PORTE
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
A/D Converter
Parallel Slave Port
Note1: Optional multiplexing of CCP2 input/output with RB3 is enabled by selection of configuration bit.
2: The high order bits of the Direc t Address f or the RAM are from the BSR registe r (e xce pt f or the M O VF F
instruction).
3: Many of the general purpose I/O pins are multiplexed with one or more peripheral module functions.
The multiplexing combinations are device dependent.
7/99 Microchip Technology Inc.
Preliminary DS39026B-page 7
PIC18CXX2
TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS
Pin Name
MCLR
/VPP
MCLR
VPP
NC — — — — These pins should be left unconnected.
OSC1/CLKI
OSC1
CLKI
OSC2/CLKO/RA6
OSC2
CLKO
RA6
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/V
RA3/AN3/V
RA4/T0CKI
RA5/AN4/SS
RA6 See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
REF-
RA2
AN2
REF-
V
REF+
RA3
AN3
REF+
V
RA4
T0CKI
/LVDIN
RA5
AN4
SS
LVDIN
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to V
Pin Number
DIP SOIC Description
11
99
10 10
22
33
44
55
66
77
Pin
Type
Buffer
Type
I
P
I
I
O
O
I/O
I/O
I
I/O
I
I/O
I
I
I/O
I
I
I/OIST/OD
I/O
I
I
I
ST Master clear (reset) input. This pin is an active low reset
ST
CMOS
—
—
TTL
TTL
Analog
TTL
Analog
TTL
Analog
Analog
TTL
Analog
Analog
ST
TTL
Analog
ST
Analog
to the device.
Programming voltage input.
Oscillator crystal input or external clock source input.
ST buffer when configured in RC mode. CMOS otherwise.
External clock source input. Always associated with
pin function OSC1. (See related OSC1/CLKIN,
OSC2/CLKOUT pins).
Oscillator crystal output. Connects to crystal or
resonator in crystal oscillator mode.
In RC mode, OSC2 pin outputs CLKOUT which has 1/4
the frequency of OSC1, and denotes the instruction
cycle rate.
General Purpose I/O pin.
PORTA is a bi-directional I/O port.
Digital I/O.
Analog input 0.
Digital I/O.
Analog input 1.
Digital I/O.
Analog input 2.
A/D Reference Voltage (Low) input.
Digital I/O.
Analog input 3.
A/D Reference Voltage (High) input.
Digital I/O. Open drain when configured as output.
Timer0 external cloc k input .
Digital I/O.
Analog input 4.
SPI Slave Select input.
Low Voltage Detect Input.
DD)
DS39026B-page 8 Preliminary
7/99 Microchip Technology Inc.
TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS (Cont.’d)
PIC18CXX2
Pin Name
RB0/INT0
RB0
INT0
RB1/INT1
RB1
INT1
RB2/INT2
RB2
INT2
RB3/CCP2
RB3
CCP2
RB4 25 25 I/O TTL Digital I/O.
RB5 26 26 I/O TTL Digital I/O.
RB6 27 27 I/O
RB7 28 28 I/O
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to V
Pin Number
DIP SOIC Description
21 21
22 22
23 23
24 24
Pin
Type
I/O
I
I/O
I
I/O
I
I/O
I/O
I
I/O
Buffer
Type
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-ups on all inputs.
TTLSTDigital I/O.
External Interrupt 0.
TTL
ST External Interrupt 1.
TTLSTDigital I/O.
External Interrupt 2.
TTLSTDigital I/O.
Capture2 input, Compare2 output, PWM2 output.
Interrupt on change pin.
Interrupt on change pin.
TTLSTDigital I/O.
Interrupt on change pin.
ICSP programming clock.
TTLSTDigital I/O.
Interrupt on change pin.
ICSP programming data.
DD)
7/99 Microchip Technology Inc.
Preliminary DS39026B-page 9
PIC18CXX2
TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS (Cont.’d)
Pin Name
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
RC2/CCP1
RC2
CCP1
RC3/SCK/SCL
RC3
SCK
SCL
RC4/SDI/SDA
RC4
SDI
SDA
RC5/SDO
RC5
SDO
RC6/TX/CK
RC6
TX
CK
RC7/RX/DT
RC7
RX
DT
SS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
V
VDD 20 20 P — Positive supply for logic and I/O pins.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to V
Pin Number
DIP SOIC Description
11 11
12 12
13 13
14 14
15 15
16 16
17 17
18 18
Pin
Type
I/O
O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
O
I/O
O
I/O
I/O
I
I/O
Buffer
Type
ST
—
ST
ST
CMOS
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
ST
—
ST
ST
ST
ST
PORTC is a bi-directional I/O port.
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
Digital I/O.
Synchronous serial clock input/output for SPI mode.
Synchronous serial clock input/output for I
Digital I/O.
SPI Data In.
2
C Data I/O.
I
Digital I/O.
SPI Data Out.
Digital I/O.
USART Asynchronous Transmit.
USART Synchronous Clock.
(See related RX/DT)
Digital I/O.
USART Asynchronous Receive.
USART Synchronous Data.
(See related TX/CK)
DD)
2
C mode
DS39026B-page 10 Preliminary
7/99 Microchip Technology Inc.
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS
PIC18CXX2
Pin Name
MCLR
/VPP
MCLR
VPP
NC — — — These pins should be left unconnected.
OSC1/CLKI
OSC1
CLKI
OSC2/CLKO/RA6
OSC2
CLKO
RA6
RA0/AN0
RA0
AN0
RA1/AN1
RA1
AN1
RA2/AN2/V
RA3/AN3/V
RA4/T0CKI
RA5/AN4/SS
RA6 See the OSC2/CLKO/RA6 pin.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
REF-
RA2
AN2
REF-
V
REF+
RA3
AN3
REF+
V
RA4
T0CKI
/LVDIN
RA5
AN4
SS
LVDIN
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to V
Pin Number
DIP PLCC TQFP Description
1218
13 14 30
14 15 31
2319
3420
4521
5622
6723
7824
Pin
Type
I/O
I/O
I/O
I/O
I/O
I/OIST/OD
I/O
Buffer
Type
I
P
I
I
O
O
I
I
I
I
I
I
I
I
I
ST Master clear (reset) input. This pin is an active
ST
CMOS
—
—
TTL
TTL
Analog
TTL
Analog
TTL
Analog
Analog
TTL
Analog
Analog
ST
TTL
Analog
ST
Analog
low reset to the device.
Programming voltage input.
Oscillator crystal input or external clock
source input. ST buffer when configured in
RC mode. CMOS otherwise.
External clock source input. Always
associated with pin function OSC1. (See
related OSC1/CLKIN, OSC2/CLKOUT pins).
Oscillator crystal output. Connects to crystal
or resonator in crystal oscillator mode.
In RC mode, OSC2 pin outputs CLKOUT,
which has 1/4 the frequency of OSC1 and
denotes the instruction cycle rate.
General Purpose I/O pin.
PORTA is a bi-directional I/O port.
Digital I/O.
Analog input 0.
Digital I/O.
Analog input 1.
Digital I/O.
Analog input 2.
A/D Reference Voltage (Low) input.
Digital I/O.
Analog input 3.
A/D Reference Voltage (High) input.
Digital I/O . Open dr ain when config ured as outpu t.
Timer0 external clock input.
Digital I/O.
Analog input 4.
SPI Slave Select input.
Low Voltage Detect Input.
DD)
7/99 Microchip Technology Inc.
Preliminary DS39026B-page 11
PIC18CXX2
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (Cont.’d)
Pin Name
RB0/INT0
RB0
INT0
RB1/INT1
RB1
INT1
RB2/INT2
RB2
INT2
RB3/CCP2
RB3
CCP2
RB4 37 41 14 I/O TTL Digital I/O.
RB5 38 42 15 I/O TTL Digital I/O.
RB6 39 43 16 I/O
RB7 40 44 17 I/O
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to VDD)
Pin Number
DIP PLCC TQFP Description
33 36 8
34 37 9
35 38 10
36 39 11
Pin
Type
I/O
I
I/O
I
I/O
I
I/O
I/O
I
I/O
Buffer
Type
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-ups on all
inputs.
TTLSTDigital I/O.
External Interrupt 0.
TTL
ST External Interrupt 1.
TTLSTDigital I/O.
External Interrupt 2.
TTLSTDigital I/O.
Capture2 input, Compare2 output, PWM2 output.
Interrupt on change pin.
Interrupt on change pin.
TTLSTDigital I/O.
Interrupt on change pin.
ICSP programming clock.
TTLSTDigital I/O.
Interrupt on change pin.
ICSP programming data.
DS39026B-page 12 Preliminary
7/99 Microchip Technology Inc.
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (Cont.’d)
PIC18CXX2
Pin Name
RC0/T1OSO/T1CKI
RC0
T1OSO
T1CKI
RC1/T1OSI/CCP2
RC1
T1OSI
CCP2
RC2/CCP1
RC2
CCP1
RC3/SCK/SCL
RC3
SCK
SCL
RC4/SDI/SDA
RC4
SDI
SDA
RC5/SDO
RC5
SDO
RC6/TX/CK
RC6
TX
CK
RC7/RX/DT
RC7
RX
DT
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to V
Pin Number
DIP PLCC TQFP Description
15 16 32
16 18 35
17 19 36
18 20 37
23 25 42
24 26 43
25 27 44
26 29 1
Pin
Type
I/O
O
I
I/O
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I/O
I/O
O
I/O
O
I/O
I/O
I
I/O
Buffer
Type
ST
—
ST
ST
CMOS
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
ST
—
ST
ST
ST
ST
PORTC is a bi-directional I/O port.
Digital I/O.
Timer1 oscillator output.
Timer1/Timer3 external clock input.
Digital I/O.
Timer1 oscillator input.
Capture2 input, Compare2 output, PWM2 output.
Digital I/O.
Capture1 input/Compare1 output/PWM1 output.
Digital I/O.
Synchronous serial clock input/output for
SPI mode.
Synchronous serial clock input/output for
2
C mode.
I
Digital I/O.
SPI Data In.
2
C Data I/O.
I
Digital I/O.
SPI Data Out.
Digital I/O.
USART Asynchronous Transmit.
USART Synchronous Clock.
(See related RX/DT)
Digital I/O.
USART Asynchronous Re ceive.
USART Synchronous Data.
(See related TX/CK)
DD)
7/99 Microchip Technology Inc.
Preliminary DS39026B-page 13
PIC18CXX2
TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (Cont.’d)
Pin Name
RD0/PSP0 19 21 38 I/O ST
RD1/PSP1 20 22 39 I/O ST
RD2/PSP2 21 23 40 I/O ST
RD3/PSP3 22 24 41 I/O ST
RD4/PSP4 27 30 2 I/O ST
RD5/PSP5 28 31 3 I/O ST
RD6/PSP6 29 32 4 I/O ST
RD7/PSP7 30 33 5 I/O ST
RE0/RD
RE1/WR
RE2/CS
V
VDD 11, 32 12, 35 7, 28 P — Positive supply for logic and I/O pins.
Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output
/AN5
RE0
RD
AN5
/AN6
RE1
WR
AN6
/AN7
RE2
CS
AN7
SS 12, 31 13, 34 6, 29 P — Ground reference for logic and I/O pins.
ST = Schmitt Trigger input with CMOS levels
I = Input O = Output
P = Power OD = Open Drain (no P diode to V
Pin Number
DIP PLCC TQFP Description
8 9 25 I/O
9 10 26 I/O
10 11 27 I/O
Pin
Type
Buffer
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
ST
TTL
Analog
ST
TTL
Analog
ST
TTL
Analog
PORTD is a bi-directional I/O port.
Parallel Slave Po rt (PSP) for interfacing to a microprocessor port. These pins have TTL input buffers when
PSP module is enabled.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
Digital I/O.
Parallel Slave Port Data.
PORTE is a bi-directional I/O port.
Digital I/O.
Read control for parallel slave port.
(See also WR
Analog input 5.
Digital I/O.
Write control for parallel slave port.
(See CS
Analog input 6.
Digital I/O.
Chip Select control for parallel slave port.
(See related RD
Analog input 7.
and CS pins)
and RD pins)
and WR)
DD)
DS39026B-page 14 Preliminary
7/99 Microchip Technology Inc.
PIC18CXX2
2.0 OSCILLATOR CONFIGURATIONS
2.1 Oscillator Types
The PIC18CXX2 can be operated in eight different
oscillator modes. The user can program three configuration bits (FOSC 2, FOSC 1, an d FOSC0 ) to s elect one
of these eight modes:
1. LP Low Power Crystal
2. XT Crystal/Resonator
3. HS High Speed Crystal/Resonator
4. HS + PLL High Speed Crystal/Resonator with
PLL enabled
5. RC External Resistor/Capacitor
6. RCIO External Resistor/Capacitor with
I/O pin enabled
7. EC External Clock
8. ECIO External Clock with I/O pin enabled
2.2 Crystal Oscillator/Ceramic Resonators
In XT, LP, HS or HS-PLL oscillator modes, a crystal or
ceramic resonator is connected to the OSC1 and
OSC2 pins to establish oscillation. Figure 2-1 shows
the pin connec tions. An ex ternal clock source ma y als o
be connected to the OSC1 pin in these modes, as
shown in Figure2-2.
The PIC18CXX2 oscillat or desi gn requ ires th e use o f a
parallel cut crystal.
Note: Use of a series cut crystal may give a fre-
quency out of the crystal manufacturers
specifications.
FIGURE 2-1: CRYSTAL/CERAMIC
RESONATOR OPERATION
(HS, XT OR LP
OSC CONFIGURATION)
(1)
C1
(1)
C2
Note 1: See Table 2-1 and Table 2-2 for recom-
Note 2: A series resistor (RS) may be required
Note 3: R
OSC1
XTAL
(2)
RS
OSC2
mended values of C1 and C2.
for AT strip cut crystals.
F varies with the crystal chosen.
RF
(3)
SLEEP
PIC18CXXX
To
internal
logic
FIGURE 2-2: EXTERNAL CLOCK INPUT
OPERATION (HS, XT OR LP
OSC CONFIGURATION)
Clock from
ext. system
Open
OSC1
PIC18CXXX
OSC2
7/99 Microchip Technology Inc.
Preliminary DS39026B-page 15
PIC18CXX2
TABLE 2-1: CERAMIC RESONATORS
Ranges Tested:
Mode Freq OSC1 OSC2
XT 455 kHz
2.0 MHz
4.0 MHz
HS 8.0 MHz
16.0 MHz
These values are for design guidance only. See
notes at bottom of page.
68 - 100 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
68 - 100 pF
15 - 68 pF
15 - 68 pF
10 - 68 pF
10 - 22 pF
Resonators Used:
455 kHz Panasonic EFO-A455K04B
2.0 MHz Murata Erie CSA2.00MG
4.0 MHz Murata Erie CSA4.00MG
8.0 MHz Murata Erie CSA8.00MT
16.0 MHz Murata Erie CSA16.00MX
All resonators used did not have built-in capacitors.
0.3%
±
0.5%
±
0.5%
±
0.5%
±
0.5%
±
TABLE 2-2: CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
Osc Type
LP 32.0 kHz 33 pF 33 pF
XT 200 kHz 47-68 pF 47-68 pF
HS 4.0 MHz 15 pF 15 pF
32.0 kHz Epson C-001R32.768K-A ± 20 PPM
200 kHz STD XTL 200.000KHz ± 20 PPM
1.0 MHz ECS ECS-10-13-1 ± 50 PPM
4.0 MHz ECS ECS-40-20-1 ± 50 PPM
8.0 MHz EPSON CA-301 8.000M-C ± 30 PPM
20.0 MHz E PS ON CA-301 20.000M-C ± 30 PPM
Crystal
Freq
200 kHz 15 pF 15 pF
1.0 MHz 15 pF 15 pF
4.0 MHz 15 pF 15 pF
8.0 MHz 15-33 pF 15-33 pF
20.0 MHz 15-33 pF 15-33 pF
25.0 MHz TBD TBD
These values are for design guidance only. See
notes at bottom of page.
Cap. Range
C1
Crystals Used
Cap.
Range
C2
Note1: Recommended values of C1 and C2 are
identical to the ranges tested (Table 2-1).
2: Higher capacitance increases the stability
of the oscillator, but also increases the st artup time.
3: Since each r esonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for app ropri ate values of external components.
4: Rs may be required in HS mode, as well as
XT mode, to avoid overdriving crystals with
low drive level specification.
2.3 RC Oscillator
For timing insensitive applications, the “RC” and
"RCIO" device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (R
EXT) and capacitor ( CEXT) val-
ues and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit due
to normal process parameter variation. Furthermore,
the difference in lead frame capacitance between
package types will also affect the oscillation frequency,
especially for low C
EXT values. The user also needs to
take into account variation due to tolerance of external
R and C components used. Figure 2-3 shows how the
R/C combination is connected.
In the RC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic.
FIGURE 2-3: RC OSCILLATOR MODE
VDD
REXT
OSC1
CEXT
VSS
F
Recommended values: 3 kΩ ≤ REXT ≤ 100 k
OSC/4
OSC2/CLKO
EXT > 20pF
C
Internal
clock
PIC18CXXX
Ω
The RCIO oscillator mode functions like the RC mode,
except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of
PORTA (RA6).
2.4 External Clock Input
The EC and ECIO oscillator mode s require an e xternal
clock source to be connected to the OSC1 pi n. The
feedback device between OSC1 and OSC2 is turned
off in these modes to sa v e current. There is no osc illator startup time required after a Power-On-Reset or
after a recovery from SLEEP mode.
In the EC oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal
may be used for test purposes or to synchronize other
logic. Figure 2-4 shows the pin conne cti ons for the EC
oscillator mode.
DS39026B-page 16 Preliminary
7/99 Microchip Technology Inc.
PIC18CXX2
FIGURE 2-4: E XTERN AL CLOCK INPUT
OPERATION
(EC OSC CONFIGURATION)
Clock from
ext. system
OSC/4
F
The ECIO oscillator mode functions like the EC mode,
except that the OSC 2 pin be comes a n addit ional general purpose I/O pin. The I/O pin becomes Bit 6 of
PORTA (RA6). Figure 2-5 shows the pin connections
for the ECIO oscillator mode.
OSC1
PIC18CXXX
OSC2
FIGURE 2-5: E XTERN AL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
Clock from
ext. system
RA6
OSC1
PIC18CXXX
I/O (OSC2)
2.5 HS/PLL
A Phase Locked Loop circuit is provided as a programmable option for users that want to multiply the frequency of the incoming crystal oscillator signal by 4.
For an input clock frequency of 10 MHz, the internal
clock frequency will be multiplied to 40 MHz. This is
useful for customers who are concerned with EMI due
to high frequency crystals.
The PLL can only be enabled when the oscillator configuration bits are programmed for HS mode. If they
are programmed for any other mode, the PLL is not
enabled and the system clock will come directly from
OSC1.
The PLL is one of the modes of the FOSC<2:0> configuration bits. The oscillator mode is specified during
device programming.
A PLL lock timer is used to ensure that the PLL has
locked before device execution starts. The PLL lock
timer has a time-out that is called T
PLL.
FIGURE 2-6: PLL BLOCK DIAGRAM
(from configuration
HS Osc
bit register)
PLL Enable
OSC2
Phase
Comparator
IN
F
Crystal
Osc
FOUT
OSC1
Loop
Filter
Divide by 4
VCO
SYSCLK
MUX
7/99 Microchip Technology Inc.
Preliminary DS39026B-page 17
PIC18CXX2
2.6 Oscillator Switching Feature
The PIC18CXX2 devices include a feature that allows
the system clock source to be switched from the main
oscillator to an alternate low frequency clock source.
For the PIC18CXX2 devices, this alternate clock
source is the Timer1 oscilla tor . If a low-freque ncy crystal (32 KHz, for example) has been attached to the
Timer1 oscillator pins and the Timer1 oscillator has
FIGURE 2-7: DEVICE CLOCK SOURCES
PIC18CXXX
OSC2
OSC1
T1OSO
T1OSI
Main Oscillator
Sleep
Timer1 Oscillator
T1OSCEN
Enable
Oscillator
been enabled, the device can switch to a low power
execution mode. Figure2-7 shows a block diagram of
the system clock sources. The clock switching feature
is enabled by programming the Oscillator Switching
Enable (OSCSEN
) bit in Configuration R eg ist er1 H to a
’0’. Clock switching is disabled in an erased device.
See Section 9 f or further details of the T imer1 oscillator .
See Section 18.0 for Configuration Register details.
4 x PLL
TOSC
TT1P
Clock Source option
for other modules
Tosc/4
MUX
Clock
Source
TSCLK
2.6.1 SYSTEM CLOCK SWITCH BIT The system clock source switching is performed under
software control. The system clock switch bit, SCS
(OSCCON<0>) controls the cloc k s wi tching . Whe n the
SCS bit is ’0’, the system clock source comes from the
main oscillator that is sel ect ed by the FOSC configur ation bits in Configuration Register1H. When the SCS
bit is set, th e system clock sour ce will come from the
Timer1 oscillator. The SCS bit is cleared on all forms
of reset.
Register 2-1: OSCCON Register
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-1
— — — — — — —
bit 7 bit 0
bit 7-1 Unim plemented: Read as '0'
bit 0 SCS: System Clock Switch bit
OSCSEN configuration bit = ’0’ and T1OSCEN bit is set:
when
1 = Switch to Timer1 Oscillator/Clock pin
0 = Use primary Oscillator/Clock input pin
OSCSEN and T1OSCEN are in other states:
when
bit is forced clear
Note: The Timer1 oscillator must be enabled to
switch the system clock source. The
Timer1 osci llator i s enabled by setting t he
T1OSCEN bit in the Time r1 control register
(T1CON). If the Timer1 oscillator is not
enabled, then any write to the SCS bit will
be ignored (SCS bit forced cleared) and
the main oscillator will continue to be the
system clock source.
SCS
Legend
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS39026B-page 18 Preliminary
7/99 Microchip Technology Inc.
PIC18CXX2
2.6.2 OSCILLATOR TRANSITIONS
A timing diagram indicating the transition from the
main oscillator to the Timer1 oscillator is shown in
The PIC18CXX2 devices contain circuitry to prevent
"glitches" when switching between oscillator sources.
Essential ly, the circuitry waits for eigh t ri sing ed ges of
the clock s ource t hat the pro cessor is s wi tching to . This
ensures that the new clock source is stable and that its
pulse width will not be less than the shortest pulse
Figure 2-8. The Timer1 oscillator is assumed to be
running all the time. After the SCS bit is set, the processor is frozen at the next occurring Q1 cycle. After
eight synchronization cycles are counted from the
Timer1 oscillator, operation resumes. No additional
delays are required after the synchronization cycles.
width of the two clock sources.
FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
Q1
T1OSI
OSC1
Internal
System
Clock
SCS
(OSCCON<0>)
Program
Counter
TOSC
Q1
TDLY
TT1P
21 345678
Tscs
PC + 2PC
Note1: Delay on internal system clock is eight oscillator cycles for synchronization.
Q3Q2Q1Q4Q3Q2
Q4 Q1
Q2 Q3 Q4 Q1
PC + 4
The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external crystal (HS, XT, LP), then the transition will take place after
an oscillator startup time (T
OST) has occurred. A timing
diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS, XT and LP modes is
shown in Figure 2-9.
FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS,XT,LP)
Q1 Q2 Q3 Q4 Q1 Q2
T1OSI
OSC1
OSC2
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter
Q3 Q4
PC PC + 2
Q1
TOST
Note1: TOST = 1024TOSC (drawing not to scale).
TT1P
12345678
TSCS
TOSC
Q3
PC + 6
7/99 Microchip Technology Inc.
Preliminary DS39026B-page 19
PIC18CXX2
If the main oscillator is configured f or HS-PLL mode , an
oscillator startup time (T
timeout (T
PLL) will occur . The PL L timeout is typic ally 2
OST) plus an additional PLL
quency. A timing diagram indicating the tran sitio n from
the Timer1 oscillator to the main oscillator for HS-PLL
mode is shown in Figure 2 -10.
ms and allows the PLL to lock to the main o scillato r fre-
FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL)
Q4 Q1
T1OSI
OSC1
OSC2
PLL Clock
Input
Internal System
Program Counter
Clock
SCS
(OSCCON<0>)
TOST
PC PC + 2
TPLL
Note 1: TOST = 1024TOSC (drawing not to scale).
TT1P
TOSC
1 234 5678
TSCS
Q1 Q2 Q3 Q4 Q1 Q2
PC + 4
Q3
Q4
If the main os ci lla tor is c on fig ured in the RC, RCIO, EC
or ECIO modes, there is no oscillator startup timeout.
Operation will resume after eight cycles of the main
ing the transition from the Timer1 oscillator to the main
oscillator for R C, RCIO , EC and EC IO modes is shown
in Figure 2-11.
oscillator ha ve been count ed. A timing diagram indicat-
FIGURE 2-11: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC)
Q3 Q4
T1OSI
OSC1
OSC2
Internal System
Clock
SCS
(OSCCON<0>)
Program Counter
PC PC + 2
Note 1: RC oscillator mode assumed.
Q1
TOSC
1
TT1P
23
45678
TSCS
Q1 Q2 Q3 Q4 Q1 Q2 Q3
Q4
PC + 4
DS39026B-page 20 Preliminary
7/99 Microchip Technology Inc.
PIC18CXX2
2.7 Effects of Sleep Mode on the On-chip Oscillator
When the device e xec utes a SLEEP instruction, the onchip clocks and oscillator are turned off and the device
is held at the beginning of an instruction cycle (Q1
state). With the oscill ato r off, the OSC1 and OSC2 si gnals will stop oscillating. Since all the transistor switch-
ing currents have been rem o ved, sleep mode achiev e s
the lowest current consumption of the device (only
leakage currents). Enabling any on-chip feature that
will operate during sleep will increase the current consumed during sleep. The user can wake from SLEEP
through external reset, Watchdog Timer Reset or
through an interrupt.
TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE
OSC Mode OSC1 Pin OSC2 Pin
RC Floating, external resistor should pull
high
RCIO Floating, external resistor should pull
high
ECIO Floating Configured as Port A, bit 6
EC Floating At logic low
LP, XT, and HS Feedback inverter disabled, at quies-
cent voltage level
See Table 3-1, in the “Reset” section, for time-outs due to Sleep and MCLR
2.8 Power-up Delays
Pow er up dela ys are control led by two timers, so that n o
external reset circuitry is required f or most applic ations.
The delays ensure that the device is kept in RESET
until the device power supply and clock are stable. For
additional information on RESET operation, see the
“Reset” section.
The first timer is the Power-up Timer (PWRT), which
optionally provides a fixed delay of 72 ms (nominal) on
power-up only (POR and BOR). The second timer is
the Oscillator Start-up Timer OS T, intended to keep th e
chip in RESET until the crystal oscillator is stable.
With the PLL enabled (HS/PLL oscillator mode), the
time-out sequence following a power-on reset is different from other oscilla tor modes. Th e time-out seque nce
is as follows : First the PWR T time-o ut is inv ok ed after a
POR time delay has expired. Then the Oscillator Startup Timer (OST) is invoked. However, this is still not a
sufficient amount o f time to al low the PL L to loc k at high
frequencies. The PWRT timer is used to provide an
additional fix ed 2ms (nominal) ti me-out to a llow the PLL
ample time to lock to the incoming clock frequency.
At logic low
Configured as P o rt A, bit 6
Feedback inverter disabled, at quiescent voltage level
reset.
7/99 Microchip Technology Inc.
Preliminary DS39026B-page 21
PIC18CXX2
NOTES:
DS39026B-page 22 Preliminary
7/99 Microchip Technology Inc.
PIC18CXX2
3.0 RESET
The PIC18CXXX differentiates between various kinds
of reset:
a) Power-on Reset (POR)
b) MCLR
c) MCLR
d) Watchdog Timer (WDT) Reset (during normal
e) Programmable Brown-out Reset (BOR)
f) Reset Instruction
g) Stack Full rese t
h) Stack Underflow reset
Most registers are unaffected by a reset. Their status is
unknown on POR and unchanged by all other resets.
The other registers are forced to a “reset state” on
reset during normal operation
reset during SLEEP
operation)
Power-on Reset, MCLR
CLR reset during SLEEP and by the RESET instruc-
M
tion.
Most registers are not affected by a WDT wake-up,
since this is viewed as the resumption of normal operation. Stat us bit s from th e RCON r egiste r, RI
and BOR, are set or clea red diff er ently in diff ere nt
POR
reset situations, as indicated in Table 3-2. These bits
are used in software to determine the nature of the
reset. See Table 3-3 for a full descripti on of the rese t
states of all registers.
A simplified bl ock diag ram of the on-ch ip res et circui t is
shown in Figure 3-1.
The Enhanced MCU devices have a MCLR
in the MCLR
reset path. The filter wi ll detect a nd ignore
small pulses.
, WDT reset, Brown-out Reset,
A WDT reset does not drive MCLR pin low.
FIGURE 3-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
RESET
Instruction
Stack
Pointer
Stack Full/Underflow Reset
External Reset
, TO, PD,
noise filter
MCLR
SLEEP
WDT
Time-out
Reset
Power-on Reset
BOREN
OST
10-bit Ripple counter
PWRT
10-bit Ripple counter
Enable PWRT
Enable OST
(2)
VDD
OSC1
Module
V
Brown-out
OST/PWRT
On-chip
RC OSC
WDT
DD rise
detect
Reset
(1)
Note1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
2: See Table 3-1 for time-out situations.
S
Chip_Reset
R
Q
7/99 Microchip Technology Inc.
Preliminary DS39026B-page 23
PIC18CXX2
3.1 Power-On Reset (POR)
A Power-on Reset pulse is generated on-chip when
V
DD rise is detected. To take advantag e of the P OR cir-
cuitry , ju st tie the MC LR
tor) to V
DD. This will elimi nate e xternal R C compon ents
pin directly (or th rough a resi s-
usually needed to create a Power-on Reset delay. A
maximum rise time for VDD is specified (parameter
D004). For a slow rise time, see Figure 3-2.
When the device starts normal operation (exits the
reset condition), d evice operating p arameters (vol tage,
frequency , temperature ,...) must be m et to ensure operation. If these conditions are not met, the device must
be held in reset until the operating conditions are met.
Brown-out Reset may be used to meet the voltage
start-up condition.
FIGURE 3-2: EXTERN AL POWER-ON
RESET CIRCUIT (FOR SLOW
DD POWER-UP)
V
V
DD
D
R
R1
MCLR
C
Note1: External Po wer-on Reset cir cuit is required
only if the V
DD power-up s lop e i s too s low .
The diode D hel ps d isch arge th e ca pacito r
quickly when V
DD powers down.
2: R < 40 kΩ is recommended to make sure
that the voltage drop across R does not
violate the device’s electrical specification.
3: R1 = 100Ω to 1 kΩ will limit any current
flowing into MCLR
C in the event of MCLR/
down due to Electrostatic Discharge
(ESD) or Electrical Overstress (EOS).
PIC18CXXX
from external capacitor
VPP pin break-
3.2 Power-up Timer (PWRT)
The Power-up Timer provides a fixed nominal time-out
(parameter #33) only on power-up from the POR. The
Power-up Timer operates on an internal RC oscillator.
The chip is ke pt in reset a s lon g as the PW R T i s act iv e .
The PWRT’s time delay allows VDD to rise to an acceptable level. A configuration bit is provided to enable/disable the PWRT.
The power-up ti me dela y will v ary from chip-to-chi p due
DD, temperature and process variation. See DC
to V
parameter #33 for details.
3.3 Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycle (from OSC1 input) delay after the
PWRT dela y is ov er (parameter #3 2). This ensures th at
the crystal oscillator or reso nator has started and stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset or wake-up from
SLEEP.
3.4 PLL Lock Timeout
With the PLL enabled, the timeout sequence following
a power-on reset is different from other oscillator
modes. A portion of the P ow er-up Timer is use d to provide a fixed timeout that is sufficient for the PLL to lock
to the main oscillator fre que nc y. This PLL lock timeout
PLL) is typically 2 ms and follows the oscillator startup
(T
timeout (OST).
3.5 Brown-Out Reset (BOR)
A configuration bit, BOREN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below parameter D005 for greater
than parameter #35, the brown-out situation will reset
the chip. A reset may not occur if V
parameter D005 for less than parameter #35. The chip
will remain in Brown-out Reset until VDD rises above
DD. The Po wer-up Tim er will then be in vok ed and will
BV
keep the chip in RESET an additional time delay
(parameter #33). If VDD drops below BVDD while the
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be initialized. Once V
DD rises abo v e BV DD, the Power-up Timer
will execute the additional time delay.
DD falls below
DS39026B-page 24 Preliminary
7/99 Microchip Technology Inc.
PIC18CXX2
3.6 Time-out Sequence
On power-up , the time-out sequence is as f ollows: First,
PWRT time-out is invoked after the POR time delay has
expired. Then, OST is activated. The total time-out will
vary based on oscillat or config urati on and the s tatu s of
the PWRT. For example, in RC mode with the PWRT
disabled, there will be no time-out at all. Figure 3-3,
Figure 3-4, Figure 3-5, Figure 3-6 and Figure 3-7
depict time-out sequences on power-up.
Since the time-outs oc cur from the POR p ulse, if MC LR
is kept low long enough, the time-outs will expire.
Bringing MCLR
(Figure 3-5). This is useful for testing purposes or to
synchronize more than one PIC18CXXX device ope rating in parallel.
Table 3-2 shows the re set condi tio ns for som e Spe cial
Function Registers, while Table 3-3 shows the reset
conditions for all the registers.
high will begin execution immediately
TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS
Oscillator
Configuration
HS with PLL enabled
HS, XT, LP 72 ms + 1024Tosc 1024Tosc 72 ms + 1024Tosc 1024Tosc
EC 72 ms —72 ms —
External RC 72 ms — 72 ms —
Note1: 2 ms = Nominal time required for the 4x PLL to lock.
2: 72 ms is the nominal power-up timer delay
Power-up
(1)
72 ms + 1024Tosc + 2ms 1024Tosc + 2 ms 72 ms + 1024To sc + 2ms 1024Tosc + 2 ms
(2)
Brown-out
(2)
Wake-up from
SLEEP or
Oscillator SwitchPWRTE = 0 PWRTE = 1
Register 3-1: RCON Register Bits and Positions
R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
IPEN LWRT
bit 7 bit 0
—RITO PD POR BOR
TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR
RCON REGISTER
Program
Condition
Power-on Reset 0000h 00-1 1100 1 1 1 0 0 u u
Reset during normal
MCLR
operation
Software Reset during normal
operation
Stack Full Reset during normal
operation
Stack Underflow Reset during
normal operation
MCLR Reset during SLEEP 0000h 00-u 10uu u 1 0 u u u u
WDT Reset 0000h 0u-u 01uu 1 0 1 u u u u
WDT Wake-up PC + 2 uu-u 00uu u 0 0 u u u u
Brown-out Reset 0000h 0u-1 11u0 1 1 1 1 0 u u
Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown, — = unimplemented bit read as '0'.
Note1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the
interrupt vector (0x000008h or 0x000018h).
Counter
0000h 00-u uuuu u u u u u u u
0000h 0u-0 uuuu 0 u u u u u u
0000h 0u-u uu11 u u u u u u 1
0000h 0u-u uu11 u u u u u 1 u
PC + 2
RCON
Register RI TO PD POR BOR STKFUL STKUNF
(1)
uu-u 00uu u 1 0 u u u u
7/99 Microchip Technology Inc.
Preliminary DS39026B-page 25
PIC18CXX2
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS
MCLR
Resets
WDT Reset
Power-on Reset,
Register Applicable Devices
Brown-out Reset
TOSU 242 442 252 452 ---0 0000 ---0 0000
TOSH 242 442 252 452 0000 0000 0000 0000
TOSL 242 442 252 452 0000 0000 0000 0000
STKPTR 242 442 252 452 00-0 0000 00-0 0000
PCLATU 242 442 252 452 ---0 0000 ---0 0000 ---u uuuu
PCLATH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
PCL 242 442 252 452 0000 0000 0000 0000
TBLPTRU 242 442 252 452 --00 0000 --00 0000 --uu uuuu
TBLPTRH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
TBLPTRL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
TABLAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
PRODH 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PRODL 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
INTCON 242 442 252 452 0000 000x 0000 000u
INTCON2 242 442 252 452 1111 -1-1 1111 -1-1
INTCON3 242 442 252 452 11-0 0-00 11-0 0-00
INDF0 242 442 252 452 N/A N/A N/A
POSTINC0 242 442 252 452 N/A N/A N/A
POSTDEC0 242 442 252 452 N/A N/A N/A
PREINC0 242 442 252 452 N/A N/A N/A
PLUSW0 242 442 252 452 N/A N/A N/A
FSR0H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
FSR0L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
WREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
INDF1 242 442 252 452 N/A N/A N/A
POSTINC1 242 442 252 452 N/A N/A N/A
POSTDEC1 242 442 252 452 N/A N/A N/A
PREINC1 242 442 252 452 N/A N/A N/A
PLUSW1 242 442 252 452 N/A N/A N/A
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition
Note1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TO SH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 3-2 for reset value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.
Reset Instruction
Stack Resets
reset.
Wake-up via WDT
or Interrupt
---0 uuuu
uuuu uuuu
uuuu uuuu
uu-u uuuu
PC + 2
uuuu uuuu
uuuu -u-u
uu-u u-uu
(3)
(3)
(3)
(3)
(2)
(1)
(1)
(1)
DS39026B-page 26 Preliminary
7/99 Microchip Technology Inc.
PIC18CXX2
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)
MCLR
Resets
WDT Reset
Power-on Reset,
Register Applicable Devices
FSR1H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
FSR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
BSR 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
INDF2 242 442 252 452 N/A N/A N/A
POSTINC2 242 442 252 452 N/A N/A N/A
POSTDEC2 242 442 252 452 N/A N/A N/A
PREINC2 242 442 252 452 N/A N/A N/A
PLUSW2 242 442 252 452 N/A N/A N/A
FSR2H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
FSR2L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
STATUS 242 442 252 452 ---x xxxx ---u uuuu ---u uuuu
TMR0H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TMR0L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
T0CON 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
OSCCON 242 442 252 452 ---- ---0 ---- ---0 ---- ---u
LVDCON 242 442 252 452 --00 0101 --00 0101 --uu uuuu
WDTCON 242 442 252 452 ---- ---0 ---- ---0 ---- ---u
(4, 6)
RCON
TMR1H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TMR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
T1CON 242 442 252 452 0-00 0000 u-uu uuuu u-uu uuuu
TMR2 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PR2 242 442 252 452 1111 1111 1111 1111 1111 1111
T2CON 242 442 252 452 -000 0000 -000 0000 -uuu uuuu
SSPBUF 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
SSPADD 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
SSPCON1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
SSPCON2 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition
Note1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TO SH and TOSL are
4: See Table 3-2 for reset value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
6: The long write enable is only reset on a POR or MCLR
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.
242 442 252 452 00-1 11q0 00-1 qquu uu-u qquu
vector (0008h or 0018h).
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
oscillator modes, they are disabled and read ’0’.
Brown-out Reset
Reset Instruction
Stack Resets
reset.
Wake-up via WDT
or Interrupt
7/99 Microchip Technology Inc.
Preliminary DS39026B-page 27
PIC18CXX2
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)
MCLR
Resets
WDT Reset
Power-on Reset,
Register Applicable Devices
ADRESH 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
ADRESL 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
ADCON0 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
ADCON1 242 442 252 452 --0- 0000 --0- 0000 --u- uuuu
CCPR1H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCP1CON 242 442 252 452 --00 0000 --00 0000 --uu uuuu
CCPR2H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCPR2L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
CCP2CON 242 442 252 452 --00 0000 --00 0000 --uu uuuu
TMR3H 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TMR3L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
T3CON 242 442 252 452 0000 0000 uuuu uuuu uuuu uuuu
SPBRG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
RCREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TXREG 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
TXSTA 242 442 252 452 0000 -01x 0000 -01u uuuu -uuu
RCSTA 242 442 252 452 0000 000x 0000 000u uuuu uuuu
IPR2 242 442 252 452 ---- 1111 ---- 1111 ---- uuuu
PIR2 242 442 252 452 ---- 0000 ---- 0000
PIE2 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu
IPR1 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
242 442 252 452 -111 1111 -111 1111 -uuu uuuu
PIR1
PIE1 242 442 252 452 0000 0000 0000 0000 uuuu uuuu
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition
Note1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TO SH and TOSL are
4: See Table 3-2 for reset value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
6: The long write enable is only reset on a POR or MCLR
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.
242 442 252 452 0000 0000 0000 0000
242 442 252 452 -000 0000 -000 0000
242
442 252 452 -000 0000 -000 0000 -uuu uuuu
vector (0008h or 0018h).
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
oscillator modes, they are disabled and read ’0’.
Brown-out Reset
Reset Instruction
Stack Resets
reset.
Wake-up via WDT
or Interrupt
---- uuuu
uuuu uuuu
-uuu uuuu
(1)
(1)
(1)
DS39026B-page 28 Preliminary
7/99 Microchip Technology Inc.
PIC18CXX2
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d)
MCLR
Resets
WDT Reset
Power-on Reset,
Register Applicable Devices
Brown-out Reset
TRISE 242 442 252 452 0000 -111 0000 -111 uuuu -uuu
TRISD
242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISC 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISB 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISA
(5, 7)
242 442 252 452
-111 1111
(5)
LATE 242 442 252 452 ---- -xxx ---- -uuu ---- -uuu
LATD 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATB 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATA
(5, 7)
242 442 252 452
-xxx xxxx
(5)
PORTE 242 442 252 452 ---- -000 ---- -000 ---- -uuu
PORTD 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA
(5, 7)
242 442 252 452
-x0x 0000
(5)
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ’0’, q = value depends on condition
Note1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TO SH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack.
4: See Table 3-2 for reset value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read ’0’.
Reset Instruction
Stack Resets
-111 1111
-uuu uuuu
-u0u 0000
reset.
(5)
(5)
(5)
Wake-up via WDT
or Interrupt
-uuu uuuu
-uuu uuuu
-uuu uuuu
(5)
(5)
(5)
7/99 Microchip Technology Inc.
Preliminary DS39026B-page 29
PIC18CXX2
FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
TOST
FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
NOT TIED TO VDD ): CASE 1
TOST
FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
DS39026B-page 30 Preliminary
NOT TIED TO VDD ): CASE 2
TOST
7/99 Microchip Technology Inc.
Loading...