Microchip Technology Inc PIC17C752-08-PT, PIC17C752-08-SP, PIC17C752-08I-JW, PIC17C752-08I-L, PIC17C752-08I-P Datasheet

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Microchip Technology Inc PIC17C752-08-PT, PIC17C752-08-SP, PIC17C752-08I-JW, PIC17C752-08I-L, PIC17C752-08I-P, PIC17C752-08I-PQ, PIC17C752-08I-PT, PIC17C752-08I-SP, PIC17C752-08-JW, PIC17C752-08-L, PIC17C752-08-P, PIC17C752-08-PQ, PIC17C752-25-JW, PIC17C752-25-L, PIC17C752-25-P, PIC17C752-25-PQ, PIC17C752-25-PT, PIC17C752-25-SP, PIC17C752-25I-JW, PIC17C752-25I-L, PIC17C752-25I-P, PIC17C752-25I-PQ, PIC17C752-25I-PT, PIC17C752-25I-SP, PIC17C752-33-JW, PIC17C752-33-L, PIC17C752-33-P, PIC17C752-33-PQ, PIC17C752-33-PT, PIC17C752-33-SP, PIC17C752-33I-JW, PIC17C752-33I-L, PIC17C752-33I-P, PIC17C752-33I-PQ, PIC17C752-33I-PT, PIC17C752-33I-SP, PIC17C752T-08-JW, PIC17C752T-08-L, PIC17C752T-08-P, PIC17C752T-08-PT, PIC17C752T-08-SP, PIC17C752T-08I-JW, PIC17C752T-08I-L, PIC17C752T-08I-P, PIC17C752T-08I-PQ, PIC17C752T-25I-L, PIC17C752T-25I-P, PIC17C752T-25I-PQ, PIC17C752T-25I-PT, PIC17C752T-25I-SP, PIC17C752T-33-JW, PIC17C752T-33-L, PIC17C752T-33-P, PIC17C752T-33-PQ, PIC17C752T-33-PT, PIC17C752T-08I-PT, PIC17C752T-08I-SP, PIC17C752T-25-JW, PIC17C752T-25-L, PIC17C752T-25-P, PIC17C752T-25-PQ, PIC17C752T-25-PT, PIC17C752T-25-SP, PIC17C752T-25I-JW, PIC17C756-08-P, PIC17C756-08-PQ, PIC17C756-08-PT, PIC17C756-08-SP, PIC17C756-08I-JW, PIC17C756-08I-L, PIC17C756-08I-P, PIC17C756-08I-PQ, PIC17C756-08I-PT, PIC17C752T-33-SP, PIC17C752T-33I-JW, PIC17C752T-33I-L, PIC17C752T-33I-P, PIC17C752T-33I-PQ, PIC17C752T-33I-PT, PIC17C752T-33I-SP, PIC17C756-08-JW, PIC17C756-08-L, PIC17C756-08I-SP, PIC17C756-25-JW, PIC17C756-25-L, PIC17C756-25-P, PIC17C756-25-PQ, PIC17C756-25-PT, PIC17C756-25-SP, PIC17C756-25I-JW, PIC17C756-25I-L, PIC17C756-25I-P, PIC17C756-25I-PQ, PIC17C756-25I-PT, PIC17C756-25I-SP, PIC17C756-33-JW, PIC17C756-33-L, PIC17C756-33-P, PIC17C756-33-PQ, PIC17C756T-08-JW, PIC17C756T-08-L, PIC17C756T-08-P, PIC17C756T-08-PQ, PIC17C756T-08-PT, PIC17C756T-08-SP, PIC17C756T-08I-JW, PIC17C756T-08I-L, PIC17C756T-08I-P, PIC17C756T-08I-PQ, PIC17C756T-08I-PT, PIC17C756T-08I-SP, PIC17C756T-25-JW, PIC17C756T-25-P, PIC17C756T-25-PQ, PIC17C756T-25-PT, PIC17C756-33-PT, PIC17C756-33-SP, PIC17C756-33I-JW, PIC17C756-33I-P, PIC17C756-33I-PQ, PIC17C756-33I-PT, PIC17C756-33I-SP, PIC17C756T-25-SP, PIC17C756T-25I-JW, PIC17C756T-25I-L, PIC17C756T-25I-P, PIC17C756T-25I-PQ, PIC17C756T-25I-PT, PIC17C756T-25I-SP, PIC17C756T-33-JW, PIC17C756T-33-L, PIC17C756T-33-P, PIC17C756T-33-PQ, PIC17C756T-33-PT, PIC17C756T-33-SP, PIC17C756T-33I-JW, PIC17C756T-33I-L, PIC17C756T-33I-P, PIC17C756T-33I-PQ, PIC17C756T-33I-PT, PIC17C756T-33I-SP, PIC17LC752-33I-SP, PIC17LC756-08-JW, PIC17LC756-08-L, PIC17LC756-08-P, PIC17LC756-08-PQ, PIC17LC756-08-PT, PIC17LC756-08-SP, PIC17LC756-08I-L, PIC17LC756-08I-P, PIC17LC752-33-P, PIC17LC752-33-PQ, PIC17LC752-33-PT, PIC17LC752-33-SP, PIC17LC752-33I-JW, PIC17LC752-33I-L, PIC17LC752-33I-P, PIC17LC752-33I-PQ, PIC17LC752-33I-PT, PIC17LC752-08I-PQ, PIC17LC752-08I-PT, PIC17LC752-08I-SP, PIC17LC752-25-JW, PIC17LC752-25-L, PIC17LC752-25-P, PIC17LC752-25-PQ, PIC17LC752-25-PT, PIC17LC752-25-SP, PIC17LC756-08I-PQ, PIC17LC756-08I-PT, PIC17LC756-08I-SP, PIC17LC756-25-L, PIC17LC756-25-P, PIC17LC756-25-PQ, PIC17LC756-25-PT, PIC17LC756-25-SP, PIC17LC756-25I-JW, PIC17LC752-25I-JW, PIC17LC752-25I-L, PIC17LC752-25I-P, PIC17LC752-25I-PQ, PIC17LC752-25I-PT, PIC17LC752-25I-SP, PIC17LC752-33-JW, PIC17LC752-33-L, PIC17LC752-08-JW, PIC17LC752-08-L, PIC17LC752-08-P, PIC17LC752-08-PQ, PIC17LC752-08-PT, PIC17LC752-08-SP, PIC17LC752-08I-JW, PIC17LC752-08I-L, PIC17LC752-08I-P, PIC17LC756-25I-P, PIC17LC756-25I-PQ, PIC17LC756-25I-PT, PIC17LC756-25I-SP, PIC17LC756-33-JW, PIC17LC756-33-L, PIC17LC756-33-P, PIC17LC756-33-PQ, PIC17LC756-33-PT, PIC17LC756-33-SP, PIC17LC756-33I-JW, PIC17LC756-33I-L, PIC17LC756-33I-P, PIC17LC756-33I-PQ, PIC17LC756-33I-PT, PIC17LC756-33I-SP Datasheet

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

1997 Microchip Technology Inc.

Preliminary

DS30264A-page 1

Devices included in this data sheet:

• PIC17C752

• PIC17C756

Microcontroller Core Features:

• Only 58 single word instructions to learn

• All single cycle instructions (121 ns) except for program branches and table reads/writes which are two-cycle

• Operating speed:

- DC - 33 MHz clock input

- DC - 121 ns instruction cycle

• Hardware Multiplier

• Interrupt capability

• 16 level deep hardware stack

• Direct, indirect, and relative addressing modes

• Internal/external program memory execution

• Capable of addressing 64K x 16 program memory space

Peripheral Features:

• 50 I/O pins with individual direction control

• High current sink/source for direct LED drive

- RA2 and RA3 are open drain, high voltage

(12V), high current (60 mA), I/O pins

• Four capture input pins

- Captures are 16-bit, max resolution 121 ns

• Three PWM outputs

- PWM resolution is 1- to 10-bits

• TMR0: 16-bit timer/counter with 8-bit programmable prescaler

• TMR1: 8-bit timer/counter

• TMR2: 8-bit timer/counter

• TMR3: 16-bit timer/counter

• Two Universal Synchronous Asynchronous Receiver Transmitters (USART/SCI)

- Independant baud rate generators

• 10-bit, 12 channel analog-to-digital converter

• Synchronous Serial Port (SSP) with SPI™ and I

C™ modes (including I

C master mode)

Device

Memory

Program (x16) Data (x8)

PIC17C752 8K 454 PIC17C756 16K 902

✯

Pin Diagrams

Special Microcontroller Features:

• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

• Brown-out Reset

• Code-protection

• Power saving SLEEP mode

• Selectable oscillator options

CMOS Technology:

• Low-power, high-speed CMOS EPROM technology

• Fully static design

• Wide operating voltage range (2.5V to 6.0V)

• Commercial and Industrial temperature ranges

• Low-power consumption

- < 5 mA @ 5V, 4 MHz

- 100 µ A typical @ 4.5V, 32 kHz

- < 1 µ A typical standby current @ 5V

987654321

68676665646362

RD2/AD10

RD3/AD11

RD4/AD12

RD5/AD13

RD6/AD14

RD7/AD15

RC0/AD0

VDDNC

RC1/AD1

RC2/AD2

RC3/AD3

RC4/AD4

RC5/AD5

RC6/AD6

RC7/AD7

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

2728293031323334353637383940414243

PIC17C75X

RA0/INT RB0/CAP1 RB1/CAP2 RB3/PWM2 RB4/TCLK12 RB5/TCLK3 RB2/PWM1 V

NC OSC2/CLKOUT OSC1/CLKIN V

RB7/SDO RA3/SDI/SDA

RA2/SS

/SCL

RA1/T0CKI

RD1/AD9 RD0/AD8 RE0/ALE

RE1/OE

RE2/WR RE3/CAP4 MCLR

/VPP

TEST

VDD RF7/AN11 RF6/AN10

RF5/AN9 RF4/AN8 RF3/AN7 RF2/AN6

RF1/AN5

RF0/AN4

AVSS

RG3/AN0/VREF+

RG2/AN1/V

REF-

RG1/AN2

RG0/AN3

VDD

RG4/CAP3

RG5/PWM3

RG7/TX2/CK2

RG6/RX2/DT2

RA4/RX1/DT1

RA5/TX1/CK1

RB6/SCK

LCC

Top View

PIC17C75X

High-Performance 8-Bit CMOS EPROM Microcontrollers

PIC17C75X

DS30264A-page 2

Preliminary



1997 Microchip Technology Inc.

Pin Diagrams Cont.’d

PIC17C75X IN 68-PIN LCC

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44

987654321

68676665646362

2728293031323334353637383940414243

Top View

RA0/INT RB0/CAP1 RB1/CAP2 RB3/PWM2 RB4/TCLK12 RB5/TCLK3 RB2/PWM1 V

NC OSC2/CLKOUT OSC1/CLKIN V

RB7/SDO RA3/SDI/SDA

RA2/SS

/SCL

RA1/T0CKI

RD1/AD9 RD0/AD8

RE0/ALE

RE1/OE

RE2/WR RE3/CAP4 MCLR

/VPP

TEST

VDD RF7/AN11 RF6/AN10

RF5/AN9 RF4/AN8 RF3/AN7 RF2/AN6

RD2/AD10

RD3/AD11

RD4/AD12

RD5/AD13

RD6/AD14

RD7/AD15

RC0/AD0

VDDNC

VSS

RC1/AD1

RC2/AD2

RC3/AD3

RC4/AD4

RC5/AD5

RC6/AD6

RC7/AD7

RF1/AN5

RF0/AN4

AVSS

RG3/AN0/VREF+

RG2/AN1/V

REF-

RG1/AN2

RG0/AN3

VDD

RG4/CAP3

RG5/PWM3

RG7/TX2/CK2

RG6/RX2/DT2

RA4/RX1/DT1

RA5/TX1/CK1

RB6/SCK

PIC17C75X



1997 Microchip Technology Inc.

Preliminary

DS30264A-page 3

PIC17C75X

Pin Diagrams Cont.’d

PIC17C75X IN 64-PIN TQFP

Pin Diagrams Cont.’d

PIC17C75X IN 64-PIN Y-SHRINK DIP

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

646362616059585756555453525150

171819202122232425262728293031

Top View

Applicable to 14 x 14 mm TQFP

RD2/AD10

RD3/AD11

RD4/AD12

RD5/AD13

RD6/AD14

RD7/AD15

RC0/AD0

VDDVSS

RC1/AD1

RC2/AD2

RC3/AD3

RC4/AD4

RC5/AD5

RC6/AD6

RC7/AD7

RD1/AD9 RD0/AD8

RE0/ALE

RE1/OE

RE2/WR

RE3/CAP4

MCLR

/VPP

TEST

VDD RF7/AN11 RF6/AN10

RF5/AN9 RF4/AN8 RF3/AN7 RF2/AN6

RA0/INT RB0/CAP1 RB1/CAP2 RB3/PWM2 RB4/TCLK12 RB5/TCLK3 RB2/PWM1 V

OSC2/CLKOUT OSC1/CLKIN VDD RB7/SDO

RA3/SDI/SDA RA2/SS

/SCL

RA1/T0CKI

RF1/AN5

RF0/AN4

AVSS

RG3/AN0/VREF+

RG2/AN1/V

REF-

RG1/AN2

RG0/AN3

VDD

RG4/CAP3

RG5/PWM3

RG7/TX2/CK2

RG6/RX2/DT2

RA4/RX1/DT1

RA5/TX1/CK1

RB6/SCK

PIC17C75X

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45

PIC17C75X

44 43 42 41 40 39

21 22 23 24 25 26 27 28 29 30 31 32

38 37 36 35 34 33

VDD

RC0/AD0 RD7/AD15 RD6/AD14 RD5/AD13 RD4/AD12 RD3/AD11 RD2/AD10

RD1/AD9

RD0/AD8

RE0/ALE

RE1/OE

RE2/WR RE3/CAP4 MCLR

/VPP

TEST

RF7/AN11 RF6/AN10

RF5/AN9 RF4/AN8 RF3/AN7 RF2/AN6 RF1/AN5 RF0/AN4

AVDD

RG3/AN0/VREF+

RG2/AN1/V

REF-

RG1/AN2

VSS RC1/AD1 RC2/AD2 RC3/AD3 RC4/AD4 RC5/AD5 RC6/AD6 RC7/AD7 RA0/INT RB0/CAP1 RB1/CAP2 RB3/PWM2 RB4/TCLK12 RB5/TCLK3 RB2/PWM1 V

OSC2/CLKOUT OSC1/CLKIN V

RB7/SDO RB6/SCK

RA2/SS/SCL RA1/T0CKI RA4/RX1/DT1 RA5/TX1/CK1 RG6/RX2/DT2 RG7/TX2/CK2 RG5/PWM3 RG4/CAP3 V

VSS

RG0/AN3

RA3/SDI/SDA

PIC17C75X

DS30264A-page 4

Preliminary



1997 Microchip Technology Inc.

Table of Contents

1.0 Overview........................................................................................................................................................................................ 5

2.0 Device Varieties............................................................................................................................................................................. 7

3.0 Architectural Overview................................................................................................................................................................... 9

4.0 On-chip Oscillator Circuit ............................................................................................................................................................. 15

5.0 Reset............................................................................................................................................................................................ 21

6.0 Interrupts......................................................................................................................................................................................29

7.0 Memory Organization................................................................................................................................................................... 39

8.0 Table Reads and Table Writes .................................................................................................................................................... 55

9.0 Hardware Multiplier...................................................................................................................................................................... 61

10.0 I/O Ports....................................................................................................................................................................................... 65

11.0 Overview of Timer resources ....................................................................................................................................................... 85

12.0 Timer0.......................................................................................................................................................................................... 87

13.0 Timer1, Timer2, Timer3, PWMs and Captures ............................................................................................................................ 91

14.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) Modules......................................................................107

15.0 Synchronous Serial Port (SSP) Module..................................................................................................................................... 123

16.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................. 167

17.0 Special Features of the CPU ..................................................................................................................................................... 177

18.0 Instruction Set Summary............................................................................................................................................................183

19.0 Development Support ................................................................................................................................................................ 219

20.0 PIC17C752/756 Electrical Characteristics................................................................................................................................. 223

21.0 PIC17C752/756 DC and AC Characteristics ............................................................................................................................. 249

22.0 Packaging Information ............................................................................................................................................................... 261

Appendix A: Modifications..............................................................................................................................................................265

Appendix B: Compatibility .............................................................................................................................................................. 265

Appendix C: What’s New................................................................................................................................................................ 266

Appendix D: What’s Changed........................................................................................................................................................ 266

Appendix E: I

C 

Overview...........................................................................................................................................................267

Appendix F: Status and Control Registers..................................................................................................................................... 273

Appendix G: PIC16/17 Microcontrollers ......................................................................................................................................... 293

Pin Compatibility ................................................................................................................................................................................ 302

Index .................................................................................................................................................................................................. 303

On-Line Support................................................................................................................................................................................. 317

Reader Response.............................................................................................................................................................................. 318

PIC17C75X Product Identification System......................................................................................................................................... 319

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an excep-

tional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you ﬁnd any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.



1997 Microchip Technology Inc.

Preliminary

DS30264A-page 5

PIC17C75X

1.0 OVERVIEW

This data sheet covers the PIC17C75X group of the PIC17CXXX family of microcontrollers. The following devices are discussed in this data sheet:

• PIC17C752

• PIC17C756 The PIC17C75X devices are 68-Pin, EPROM-based

members of the versatile PIC17CXXX family of low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers.

All PIC16/17 microcontrollers employ an advanced RISC architecture. The PIC17CXXX has enhanced core features, 16-lev el deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 16-bit wide instruction word with a separate 8-bit wide data path. The two stage instruction pipeline allows all instructions to execute in a single cycle, e xcept for program branches (which require two cycles). A total of 58 instructions (reduced instruction set) are available. Additionally, a large register set gives some of the architectural innovations used to achieve a very high performance. For mathematical intensive applications all devices have a single cycle 8 x 8 Hardware Multiplier.

PIC17CXXX microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class.

PIC17C75X devices have up to 902 bytes of RAM and 50 I/O pins. In addition, the PIC17C75X adds several peripheral features useful in many high performance applications including:

• Four timer/counters

• Four capture inputs

• Three PWM outputs

• Two independant Universal Synchronous Asynchronous Receiver Transmitters (USARTs)

• An A/D converter (12 channel, 10-bit resolution)

• A Synchronous Serial Port (SPI and I

C w/ Master mode)

These special features reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption.

There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LF oscillator is for low frequency crystals and minimizes power consumption, XT is a standard crystal, and the EC is for external clock input.

The SLEEP (power-down) mode offers additional power saving. W ak e-up from SLEEP can occur through several external and internal interrupts and device resets.

A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software malfunction.

There are four conﬁguration options for the device operational mode:

• Microprocessor

• Microcontroller

• Extended microcontroller

• Protected microcontroller The microprocessor and extended microcontroller

modes allow up to 64K-words of external program memory.

Brown-out Reset circuitry has also been added to the device. This allo ws a device reset to occur if the device V

falls below the Brown-out voltage trip point

(BV

). The chip will remain in Brown-out Reset until

rises above BV

. Table 1-1 lists the features of the PIC17CXXX devices. A UV-erasable CERQUAD-packaged version (compat-

ible with PLCC) is ideal for code de velopment while the cost-effective One-Time Programmable (OTP) version is suitable for production in any volume.

The PIC17C75X ﬁts perfectly in applications that require extremely fast execution of complex software programs. These include applications ranging from precise motor control and industrial process control to automotive, instrumentation, and telecom applications.

The EPROM technology makes customization of application programs (with unique security codes, combinations, model numbers, parameter storage, etc.) fast and convenient. Small footprint package options (including die sales) make the PIC17C75X ideal for applications with space limitations that require high performance.

An In-circuit Serial Programming (ISP) feature allows:

• Flexibility of programming the software code as

one of the last steps of the manufacturing process

High speed execution, powerful peripheral features, ﬂexible I/O, and low power consumption all at low cost make the PIC17C75X ideal for a wide range of embedded control applications.

1.1 Family and

Upward Compatibility

The PIC17CXXX family of microcontrollers have architectural enhancements over the PIC16C5X and PIC16CXX families. These enhancements allow the device to be more efﬁcient in software and hardware requirements. Refer to Appendix A for a detailed list of enhancements and modiﬁcations. Code written for PIC16C5X or PIC16CXX can be easily ported to PIC17CXXX devices (Appendix B).

1.2 Development Support

The PIC17CXXX family is supported by a full-featured macro assembler, a software simulator, an in-circuit emulator, a universal programmer, a “C” compiler, and fuzzy logic support tools. For additional inf ormation see Section 19.0.

PIC17C75X

DS30264A-page 6

Preliminary



1997 Microchip Technology Inc.

TABLE 1-1: PIC17CXXX FAMILY OF DEVICES

Features PIC17CR42 PIC17C42A PIC17C43 PIC17CR43 PIC17C44 PIC17C752 PIC17C756

Maximum Frequency of Operation

33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz

Operating V oltage Range 2.5 - 6.0V 2.5 - 6.0V 2.5 - 6.0V 2.5 - 6.0V 2.5 - 6.0V 3.0 - 6.0V 3.0 - 6.0V Program Memory

( x16)

(EPROM) - 16 K 4K - 8K 8K 16K

(ROM) 2K - - 4K --Data Memory (bytes) 232 232 454 454 454 454 902 Hardware Multiplier (8 x 8) Yes Yes Yes Yes Yes Yes Yes Timer0

(16-bit + 8-bit postscaler)

Yes Yes Yes Yes Yes Yes Yes

Timer1 (8-bit) Yes Yes Yes Yes Yes Yes Yes Timer2 (8-bit) Yes Yes Yes Yes Yes Yes Yes Timer3 (16-bit) Yes Yes Yes Yes Yes Yes Yes Capture inputs (16-bit) 2 2 2 2 244 PWM outputs (up to 10-bit) 2 2 2 2 233 USART/SCI 1 1 1 1 122 A/D channels (10-bit) - - - - -1212

SSP (SPI/I

C w/Master mode)

- - - - - Yes Yes

Power-on Reset

Yes Yes Yes Yes Yes Yes Yes Watchdog Timer Yes Yes Yes Yes Yes Yes Yes External Interrupts Yes Yes Yes Yes Yes Yes Yes Interrupt Sources 11 11 11 11 11 18 18 Code Protect Yes Yes Yes Yes Yes Yes Yes Brown-out Reset - - - - - Yes Yes In-circuit Serial Programming - - - - - Yes Yes I/O Pins 33 33 33 33 33 50 50 I/O High Current

Capability

Source 25 mA 25 mA 25 mA 25 mA 25 mA 25 mA 25 mA Sink

25 mA

(1)

25 mA

(1)

25 mA

(1)

25 mA

(1)

25 mA

(1)

25 mA

(1)

25 mA

(1)

Package Types

40-pin DIP

44-pin PLCC

44-pin MQFP

44-pin TQFP

40-pin DIP

44-pin PLCC

44-pin MQFP

44-pin TQFP

40-pin DIP 44-pin PLCC 44-pin MQFP

44-pin TQFP

40-pin DIP

44-pin PLCC

44-pin MQFP

44-pin TQFP

40-pin DIP

44-pin PLCC

44-pin MQFP

44-pin TQFP

64-pin DIP

68-pin LCC

68-pin TQFP

64-pin DIP

68-pin LCC

68-pin TQFP

Note 1: Pins RA2 and RA3 can sink up to 60 mA.



1997 Microchip Technology Inc.

Preliminary

DS30264A-page 7

PIC17C75X

2.0 DEVICE VARIETIES

Each device has a variety of frequency ranges and packaging options. Depending on application and production requirements, the proper device option can be selected using the information in the PIC17C75X Product Selection System section at the end of this data sheet. When placing orders, please use the “PIC17C75X Product Identiﬁcation System” at the back of this data sheet to specify the correct part number. When discussing the functionality of the device, memory technology and voltage range does not matter.

There are three memory type options. These are speciﬁed in the middle characters of the part number.

1. C , as in PIC17 C 756. These devices have EPROM type memory.

2. CR , as in PIC17 CR 756. These devices have ROM type memory.

3. F , as in PIC17 F 756. These devices have Flash type memory.

All these devices operate over the standard voltage range. Devices are also offered which operate over an extended voltage range (and reduced frequency range). Table 2-1 shows all possible memory types and voltage range designators for a particular device. These designators are in bold typeface.

TABLE 2-1: DEVICE MEMORY

VARIETIES

Memory T ype

Voltage Range

Standard Extended

EPROM PIC17

XXX PIC17

XXX

ROM

PIC17

XXX PIC17

LCR

XXX

Flash

PIC17FXXX PIC17LFXXX

Note: Not all memory technologies are available

for a particular device.

2.1 UV Erasable Devices

The UV erasable version, offered in CERQUAD package, is optimal for prototype dev elopment and pilot programs.

The UV erasable version can be erased and reprogrammed to any of the conﬁguration modes. Microchip's programming of the PIC17C75X. Third party programmers also are available; ref er to the

Third

Party Guide

for a list of sources.

2.2 One-Time-Programmable (OTP) Devices

The availability of OTP devices is especially useful for customers expecting frequent code changes and updates.

The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the conﬁguration bits must be programmed.

2.3 Quick-Turnaround-Production (QTP) Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and conﬁguration options already programmed by the factory. Certain code and prototype veriﬁcation procedures apply before production shipments are available. Please contact your local Microchip Technology sales ofﬁce for more details.

2.4 Serialized Quick-Turnaround Production (SQTPSM) Devices

Microchip offers a unique programming service where a few user-deﬁned locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential.

Serial programming allows each device to have a unique number which can serve as an entry-code, password or ID number.

PIC17C75X

DS30264A-page 8 Preliminary  1997 Microchip Technology Inc.

2.5 Read Only Memory (ROM) Devices

Microchip offers masked ROM versions of several of the highest volume parts, thus giving customers a low cost option for high volume, mature products.

ROM devices do not allow serialization information in the program memory space.

For information on submitting ROM code, please contact your regional sales ofﬁce.

2.6 Flash Memory Devices

These devices are electrically erasable and, therefore, can be offered in the low cost plastic package. Being electrically erasable, these devices can be erased and reprogrammed in-circuit. These devices are the same for prototype development, pilot programs, as well as production.

Note: Presently, NO ROM versions of the

PIC17C75X devices are available.

Note: Presently, NO Flash versions of the

PIC17C75X devices are available.

 1997 Microchip Technology Inc. Preliminary DS30264A-page 9

PIC17C75X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC17CXXX can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC17CXXX uses a modiﬁed Harvard architecture. This architecture has the program and data accessed from separate memories. So , the de vice has a progr am memory bus and a data memory bus. This improves bandwidth over traditional von Neumann architecture, where program and data are fetched from the same memory (accesses over the same bus). Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. PIC17CXXX opcodes are 16-bits wide, enabling single word instructions. The full 16-bit wide program memory bus fetches a 16-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions execute in a single cycle (121 ns @ 33 MHz), except for program branches and two special instructions that transfer data between program and data memory.

The PIC17CXXX can address up to 64K x 16 of program memory space.

The PIC17C752 integrates 8K x 16 of EPROM program memory on-chip.

The PIC17C756 integrates 16K x 16 EPROM program memory.

Program execution can be internal only (microcontroller or protected microcontroller mode), external only (microprocessor mode) or both (extended microcontroller mode). Extended microcontroller mode does not allow code protection.

The PIC17CXXX can directly or indirectly address its register ﬁles or data memory. All special function registers, including the Program Counter (PC) and Working Register (WREG), are mapped in the data memory. The PIC17CXXX has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC17CXXX simple yet efﬁcient. In addition, the learning curve is reduced signiﬁcantly.

One of the PIC17CXXX family architectural enhancements from the PIC16CXX family allows two ﬁle registers to be used in some two operand instructions. This allows data to be moved directly between two registers without going through the WREG register. Thus increasing performance and decreasing program memory usage.

The PIC17CXXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It perf orms arithmetic and Boolean functions between data in the working register and any register ﬁle.

The ALU is 8-bits wide and capable of addition, subtraction, shift, and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature.

The WREG register is an 8-bit working register used for ALU operations.

All PIC17C75X devices have an 8 x 8 hardware multiplier. This m ultiplier generates a 16-bit result in a single cycle.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the ALUSTA register. The C and DC bits operate as a borro

w and digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

Although the ALU does not perform signed arithmetic, the Overﬂow bit (O V) can be used to implement signed math. Signed arithmetic is comprised of a magnitude and a sign bit. The overﬂow bit indicates if the magnitude overﬂows and causes the sign bit to change state. That is if the result of the signed operation is greater then 128 (7Fh) or less then -127 (FFh). Signed math can have greater than 7-bit values (magnitude), if more than one byte is used. The use of the overﬂow bit only operates on bit6 (MSb of magnitude) and bit7 (sign bit) of the value in the ALU. That is, the overﬂow bit is not useful if trying to implement signed math where the magnitude, for example, is 11-bits. If the signed math values are greater than 7-bits (15-, 24- or 31-bit), the algorithm must ensure that the low order bytes ignore the overﬂow status bit.

Care should be taken when adding and subtracting signed numbers to ensure that the correct operation is executed. Example 3-1 shows an item that must be taken into account when doing signed arithmetic on an ALU which operates as an unsigned machine.

EXAMPLE 3-1: SIGNED MATH

Signed math requires the result to be FEh (-126). This would be accomplished by subtracting one as opposed to adding one.

A simpliﬁed block diagram is shown in Figure 3-1. The descriptions of the device pins are listed in Table 3-1.

Hex Value Signed Value

Math

Unsigned Value Math

FFh + 01h = ?

-127 + 1 = -126 (FEh)

255 + 1 = 0 (00h); Carry bit = 1

PIC17C75X

DS30264A-page 10 Preliminary  1997 Microchip Technology Inc.

FIGURE 3-1: PIC17C75X BLOCK DIAGRAM

RB0/CAP1

RB1/CAP2 RB2/PWM1 RB3/PWM2

RB4/TCLK12

RB5/TCLK3

RB6/SCK

RB7/SDO

RA0/INT

RA1/T0CKI

RA2/SS

/SCL

RA3/SDI/SDA RA4/RX1/DT1 RA5/TX1/CK1

PORTA

RC0/AD0 RC1/AD1 RC2/AD2 RC3/AD3 RC4/AD4 RC5/AD5 RC6/AD6 RC7/AD7

RD0/AD8

RD1/AD9 RD2/AD10 RD3/AD11 RD4/AD12 RD5/AD13 RD6/AD14 RD7/AD15

RE0/ALE

RE1/OE

RE2/WR

RE3/CAP4

RF0/AN4 RF1/AN5 RF2/AN6 RF3/AN7 RF4/AN8

RF5/AN9 RF6/AN10 RF7/AN11

RG0/AN3 RG1/AN2

RG2/AN1/V

REF-

RG3/AN0/V

REF+

RG4/CAP3

RG5/PWM3 RG6/RX2/DT2 RG7/TX2/CK2

Timer0

Clock

Generator

Power-on

Reset

Watchdog

Timer

Test Mode

Select

VDD, VSS

OSC1,

MCLR, VSS

Test

Q1, Q2,

Chip_reset

& Other

Control

System Bus Interface

Decode

Data Latch

Address

Program

Memory

(EPROM)

Table Pointer<16>

Stack

16 x 16

Table

ROM Latch <16>

Instruction

Decode

Control Outputs

IR Latch <16>

16K x 16

PCH

PCLATH<8>

Literal

RAM

Data Latch

BSR

Data RAM

902 x 8

Latch

PCL

Read/write

Decode

for

Mapped

in Data

Space

WREG<8>

BITOP

ALU

Shifter

8 x 8 mult

PRODH PRODL

Registers

Latch <16>

Address

Buffer

USART1

Timer1 Timer3

Timer2 PWM1

PWM2

PWM3

Capture1 Capture3

Capture2

Interrupt

Module

10-bit

A/D

PORTB

PORTC

PORTD

PORTE

PORTF

PORTG

AD<15:0>

Signals

Q3, Q4

OSC2

Data Bus<8>

IR<7>

IR<16>

SSP

PORTC, PORTD

ALE, WR

PORTE

IR <7:0>

BSR <7:4>

USART2

Capture4

Brown-out

Reset

17C756 17C752

8K x 16

17C756 17C752

454 x 8

 1997 Microchip Technology Inc. Preliminary DS30264A-page 11

PIC17C75X

TABLE 3-1: PINOUT DESCRIPTIONS

Name

DIP

No.

PLCC

No.

TQFP

No.

I/O/P Type

Buffer

Type

Description

OSC1/CLKIN 47 50 39 I ST Oscillator input in crystal/resonator or RC oscillator mode.

External clock input in external clock mode.

OSC2/CLKOUT 48 51 40 O — Oscillator output. Connects to crystal or resonator in crystal

oscillator mode. In RC oscillator or external clock modes OSC2 pin outputs CLKOUT which has one fourth the frequency (F

OSC/4) of OSC1 and denotes the instruction cycle

rate.

MCLR

/VPP 15 16 7 I/P ST Master clear (reset) input or Programming Voltage (VPP)

input. This is the active low reset input to the chip. PORTA is a bi-directional I/O Port except for RA0 and RA1

which are input only.

RA0/INT 56 60 48 I ST RA0 can also be selected as an external interrupt

input. Interrupt can be conﬁgured to be on positive or negative edge.

RA1/T0CKI 41 44 33 I ST RA1 can also be selected as an external interrupt

input, and the interrupt can be conﬁgured to be on positive or negative edge. RA1 can also be selected to be the clock input to the Timer0 timer/counter.

RA2/SS

/SCL 42 45 34 I/O ST RA2 can also be used as the slave select input for the

SPI or the clock input for the I

C bus. High voltage, high current, open drain input/output port pin.

RA3/SDI/SDA 43 46 35 I/O ST RA3 can also be used as the data input for the SPI or

the data for the I

C bus. High voltage, high current, open drain input/output port pin.

RA4/RX1/DT1 40 43 32 I/O † ST RA4 can also be selected as the USART1 (SCI) Asyn-

chronous Receive or USART1 (SCI) Synchronous Data.

RA5/TX1/CK1 39 42 31 I/O † ST RA5 can also be selected as the USART1 (SCI) Asyn-

chronous Transmit or USART1 (SCI) Synchronous Clock.

PORTB is a bi-directional I/O Port with software conﬁg-

urable weak pull-ups. RB0/CAP1 55 59 47 I/O ST RB0 can also be the Capture1 input pin. RB1/CAP2 54 58 46 I/O ST RB1 can also be the Capture2 input pin. RB2/PWM1 50 54 42 I/O ST RB2 can also be the PWM1 output pin. RB3/PWM2 53 57 45 I/O ST RB3 can also be the PWM2 output pin. RB4/TCLK12 52 56 44 I/O ST RB4 can also be the external clock input to Timer1 and

Timer2. RB5/TCLK3 51 55 43 I/O ST RB5 can also be the external clock input to Timer3. RB6/SCK 44 47 36 I/O ST RB6 can also be used as the master/slave clock for the

SPI. RB7/SDO 45 48 37 I/O ST RB7 can also be used as the data output for the SPI. Legend: I = Input only; O = Output only; I/O = Input/Output; P = Power; — = Not Used; TTL = TTL input;

ST = Schmitt Trigger input.

† The output is only available by the Peripheral operation.

PIC17C75X

DS30264A-page 12 Preliminary  1997 Microchip Technology Inc.

PORTC is a bi-directional I/O Port.

RC0/AD0 2 3 58 I/O TTL This is also the least signiﬁcant byte (LSB) of the 16-bit

wide system bus in microprocessor mode or extended microcontroller mode. In multiplexed system bus conﬁguration, these pins are address output as well as data input or output.

RC1/AD1 63 67 55 I/O TTL RC2/AD2 62 66 54 I/O TTL RC3/AD3 61 65 53 I/O TTL RC4/AD4 60 64 52 I/O TTL RC5/AD5 58 63 51 I/O TTL RC6/AD6 58 62 50 I/O TTL RC7/AD7 57 61 49 I/O TTL

PORTD is a bi-directional I/O Port.

RD0/AD8 10 11 2 I/O TTL This is also the most signiﬁcant byte (MSB) of the

16-bit system bus in microprocessor mode or extended microprocessor mode or extended microcontroller mode. In multiplexed system bus conﬁguration these pins are address output as well as data input or output.

RD1/AD9 9 10 1 I/O TTL RD2/AD10 8 9 64 I/O TTL RD3/AD11 7 8 63 I/O TTL RD4/AD12 6 7 62 I/O TTL RD5/AD13 5 6 61 I/O TTL RD6/AD14 4 5 60 I/O TTL RD7/AD15 3 4 59 I/O TTL

PORTE is a bi-directional I/O Port.

RE0/ALE 11 12 3 I/O TTL In microprocessor mode or extended microcontroller

mode, RE0 is the Address Latch Enable (ALE) output. Address should be latched on the falling edge of ALE output.

RE1/OE

12 13 4 I/O TTL In microprocessor or extended microcontroller mode,

RE1 is the Output Enable (OE

) control output (active

low).

RE2/WR

13 14 5 I/O TTL In microprocessor or extended microcontroller mode,

RE2 is the Write Enable (WR

) control output (active

low).

RE3/CAP4 14 15 6 I/O ST RE3 can also be the Capture4 input pin.

PORTF is a bi-directional I/O Port. RF0/AN4 26 28 18 I/O ST RF0 can also be analog input 4. RF1/AN5 25 27 17 I/O ST RF1 can also be analog input 5. RF2/AN6 24 26 16 I/O ST RF2 can also be analog input 6. RF3/AN7 23 25 15 I/O ST RF3 can also be analog input 7. RF4/AN8 22 24 14 I/O ST RF4 can also be analog input 8. RF5/AN9 21 23 13 I/O ST RF5 can also be analog input 9. RF6/AN10 20 22 12 I/O ST RF6 can also be analog input 10. RF7/AN11 19 21 11 I/O ST RF7 can slso be analog input 11.

TABLE 3-1: PINOUT DESCRIPTIONS

Name

DIP

No.

PLCC

No.

TQFP

No.

I/O/P Type

Buffer

Type

Description

Legend: I = Input only; O = Output only; I/O = Input/Output; P = Power; — = Not Used; TTL = TTL input;

ST = Schmitt Trigger input.

† The output is only available by the Peripheral operation.

 1997 Microchip Technology Inc. Preliminary DS30264A-page 13

PIC17C75X

PORTG is a bi-directional I/O Port. RG0/AN3 32 34 24 I/O ST RG0 can also be analog input 3. RG1/AN2 31 33 23 I/O ST RG1 can also be analog input 2. RG2/AN1/V

REF- 30 32 22 I/O ST RG2 can also be analog input 1, or

the ground reference voltage

RG3/AN0/V

REF+ 29 31 21 I/O ST RG3 can also be analog input 0, or

the positive reference voltage RG4/CAP3 35 38 27 I/O ST RG4 can also be the Capture3 input pin. RG5/PWM3 36 39 28 I/O ST RG5 can also be the PWM3 output pin. RG6/RX2/DT2 38 41 30 I/O ST RG6 can also be selected as the USART2 (SCI) Asyn-

chronous Receive or USART2 (SCI) Synchronous

Data. RG7/TX2/CK2 37 40 29 I/O ST RG7 can also be selected as the USART2 (SCI) Asyn-

chronous Transmit or USART2 (SCI) Synchronous

Clock. TEST 16 17 8 I ST Test mode selection control input. Always tie to V

SS for nor-

mal operation.

SS 17,

33, 49,

19,

36,53,

9, 25,

41, 56

P Ground reference for logic and I/O pins.

DD 1,

18, 34,

2, 20,

37, 49,

10, 26,

38, 57

P Positive supply for logic and I/O pins.

SS 28 30 20 P Ground reference for A/D converter.

This pin MUST be at the same potential as V

SS.

DD 27 29 19 P Positive supply for A/D converter.

This pin MUST be at the same potential as V

DD.

NC - 1, 18,

35, 52

- No Connect. Leave these pins unconnected.

TABLE 3-1: PINOUT DESCRIPTIONS

Name

DIP

No.

PLCC

No.

TQFP

No.

I/O/P Type

Buffer

Type

Description

Legend: I = Input only; O = Output only; I/O = Input/Output; P = Power; — = Not Used; TTL = TTL input;

ST = Schmitt Trigger input.

† The output is only available by the Peripheral operation.

PIC17C75X

DS30264A-page 14 Preliminary  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. Preliminary DS30264A-page 15

PIC17C75X

4.0 ON-CHIP OSCILLATOR CIRCUIT

The internal oscillator circuit is used to generate the device clock. Four device clock periods generate an internal instruction clock (T

CY). There are four modes

that the oscillator can operate in. These are selected b y the device conﬁguration bits during device programming. These modes are:

• LF Low Frequency (F

OSC <= 2 MHz)

• XT Standard Crystal/Resonator Frequency (2 MHz <= F

OSC <= 33 MHz)

• EC External Clock Input (Default oscillator conﬁguration)

• RC External Resistor/Capacitor (F

OSC <= 4 MHz)

There are two timers that offer necessary delays on power-up. One is the Oscillator Star t-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a ﬁxed delay of 96 ms (nominal) on power-up only, designed to keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry.

SLEEP mode is designed to offer a very low current power-down mode. The user can wake from SLEEP through external reset, Watchdog Timer Reset or through an interrupt.

Several oscillator options are made available to allow the part to ﬁt the application. The RC oscillator option saves system cost while the LF crystal option saves power. Conﬁguration bits are used to select various options.

4.1 Oscillator Conﬁgurations

4.1.1 OSCILLATOR TYPES

The PIC17CXXX can be operated in four different oscillator modes. The user can program two conﬁguration bits (FOSC1:FOSC0) to select one of these four modes:

• LF Low Power Crystal

• XT Crystal/Resonator

• EC External Clock Input

• RC Resistor/Capacitor

The main difference between the LF and XT modes is the gain of the internal inverter of the oscillator circuit which allows the different frequency ranges.

For more details on the device conﬁguration bits, see Section 17.0.

4.1.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS

In XT or LF modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 4-2). The PIC17CXXX oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers speciﬁcations.

For frequencies above 20 MHz, it is common for the crystal to be an overtone mode crystal. Use of overtone mode crystals require a tank circuit to attenuate the gain at the fundamental frequency. Figure 4-3 shows an example circuit.

4.1.2.1 OSCILLATOR / RESONATOR START-UP

As the device voltage increases from Vss , the oscillator will start its oscillations. The time required for the oscillator to start oscillating depends on many factors. These include:

• Crystal / resonator frequency

• Capacitor values used (C1 and C2)

• Device V

DD rise time.

• System temperature

• Series resistor value (and type) if used

• Oscillator mode selection of device (which selects

the gain of the internal oscillator inverter)

Figure 4-1 shows an example of a typical oscillator / resonator start-up. The peak-to-peak voltage of the oscillator waveform can be quite low (less than 50% of device V

DD) when the waveform is centered at VDD/2

(refer to parameter number D033 and D043 in the electrical speciﬁcation section).

FIGURE 4-1: OSCILLATOR / RESONATOR

START-UP CHARACTERISTICS

VDD

Crystal Start-up Time

Time

PIC17C75X

DS30264A-page 16 Preliminary  1997 Microchip Technology Inc.

FIGURE 4-2: CRYSTAL OR CERAMIC

RESONATOR OPERATION (XT OR LF OSC CONFIGURATION)

TABLE 4-1: CAPACITOR SELECTION

FOR CERAMIC RESONATORS

Oscillator

Type

Resonator

Frequency

Capacitor Range

C1 = C2

(1)

LF 455 kHz

2.0 MHz

15 - 68 pF 10 - 33 pF

XT 4.0 MHz

8.0 MHz

16.0 MHz

22 - 68 pF 33 - 100 pF 33 - 100 pF

Higher capacitance increases the stability of the oscillator but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.

Note 1: These values include all board capaci-

tances on this pin. Actual capacitor value depends on board capacitance

Resonators Used:

455 kHz Panasonic EFO-A455K04B ± 0.3%

2.0 MHz Murata Erie CSA2.00MG ± 0.5%

4.0 MHz Murata Erie CSA4.00MG ± 0.5%

8.0 MHz Murata Erie CSA8.00MT ± 0.5%

16.0 MHz Murata Erie CSA16.00MX ± 0.5%

Resonators used did not have built-in capacitors.

See Table 4-1 and Table 4-2 for recommended values of C1 and C2.

Note 1: A series resistor (Rs) may be required for

AT strip cut crystals.

XTAL

OSC2

Note1

OSC1

SLEEP

PIC17CXXX

To internal logic

FIGURE 4-3: CRYSTAL OPERATION,

OVERTONE CRYSTALS (XT OSC CONFIGURATION)

TABLE 4-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

Osc

Type

Freq

(3)

LF 32 kHz

(1)

1 MHz 2 MHz

100-150 pF

10-33 pF 10-33 pF

100-150 pF

10-33 pF 10-33 pF

XT 2 MHz

4 MHz

8 MHz

(2)

16 MHz 25 MHz

32 MHz

(3)

47-100 pF

15-68 pF 15-47 pF

TBD

15-47 pF

47-100 pF

15-68 pF 15-47 pF

TBD

15-47 pF

Higher capacitance increases the stability of the oscillator but also increases the start-up time and the oscillator current. These values are for design guidance only. RS may be required in XT mode to avoid overdriving the crystals with low drive level speciﬁcation. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values for external components.

Note 1: For VDD > 4.5V, C1 = C2 ≈ 30 pF is recom-

mended.

2: R

S of 330Ω is required for a capacitor com-

bination of 15/15 pF.

3: These values include all board capaci-

tances on this pin. Actual capacitor value depends on board capacitance

Crystals Used:

32.768 kHz Epson C-001R32.768K-A ± 20 PPM

1.0 MHz ECS-10-13-1 ± 50 PPM

2.0 MHz ECS-20-20-1 ± 50 PPM

4.0 MHz ECS-40-20-1 ± 50 PPM

8.0 MHz ECS ECS-80-S-4 ECS-80-18-1

± 50 PPM

16.0 MHz ECS-160-20-1 TBD

25 MHz CTS CTS25M ± 50 PPM 32 MHz CRYSTEK HF-2 ± 50 PPM

0.1 µF

SLEEP

OSC2

OSC1

PIC17CXXX

To ﬁlter the fundamental frequency

LC2

(2πf)

Where f = tank circuit resonant frequency. This should be midway between the fundamental and the 3rd overtone frequencies of the crystal.

 1997 Microchip Technology Inc. Preliminary DS30264A-page 17

PIC17C75X

4.1.3 EXTERNAL CLOCK OSCILLATOR In the EC oscillator mode, the OSC1 input can be

driven by CMOS drivers. In this mode, the OSC1/CLKIN pin is hi-impedance and the OSC2/CLKOUT pin is the CLKOUT output (4 T

OSC).

FIGURE 4-4: EXTERNAL CLOCK INPUT

OPERATION (EC OSC CONFIGURATION)

Clock from ext. system

OSC1

OSC2

PIC17CXXX

CLKOUT (F

OSC/4)

4.1.4 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT

Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with series resonance, or one with parallel resonance.

Figure 4-5 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 kΩ resistor provides the negative feedback for stability. The 10 kΩ potentiometer biases the 74AS04 in the linear region. This could be used for external oscillator designs.

FIGURE 4-5: EXTERNAL PARALLEL

RESONANT CRYSTAL OSCILLATOR CIRCUIT

Figure 4-6 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180-degree phase shift in a series resonant oscillator circuit. The 330 kΩ resistors provide the negative feedback to bias the inverters in their linear region.

FIGURE 4-6: EXTERNAL SERIES

RESONANT CRYSTAL OSCILLATOR CIRCUIT

20 pF

+5V

20 pF

10k

4.7k

10k

74AS04

XTAL

10k

74AS04

PIC17CXXX

OSC1

To Other Devices

330 kΩ

74AS04

PIC17CXXX

OSC1

To Other Devices

XTAL

330 kΩ

74AS04

0.1 µF

PIC17C75X

DS30264A-page 18 Preliminary  1997 Microchip Technology Inc.

4.1.5 RC OSCILLATOR For timing insensitive applications, the RC device

option offers additional cost savings. RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 4-7 shows how the R/C combination is connected to the PIC17CXXX. For Rext values below

2.2 kΩ, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g. 1 MΩ), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend to keep Rext between 3 kΩ and 100 kΩ.

Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With little or no external capacitance, oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance.

See Section 21.0 for RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more).

See Section 21.0 for variation of oscillator frequency due to V

DD for given Rext/Cext values as well as fre-

quency variation due to operating temperature for given R, C, and V

DD values.

The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 4-8 for waveform).

FIGURE 4-7: RC OSCILLATOR MODE

VDD

Rext

Cext V

OSC1

Internal clock

OSC2/CLKOUT

Fosc/4

PIC17CXXX

4.1.5.1 RC START-UP As the device voltage increases, the RC will immedi-

ately start its oscillations once the pin voltage levels meet the input threshold speciﬁcations (parameter number D032 and D042 in the electrical speciﬁcation section). The time required for the RC to start oscillating depends on many factors. These include:

• Resistor value used

• Capacitor value used

• Device V

DD rise time

• System temperature

 1997 Microchip Technology Inc. Preliminary DS30264A-page 19

PIC17C75X

4.2 Clocking Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3, and Q4. Internally, the program counter (PC) is incremented every Q1, and the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution ﬂow are shown in Figure 4-8.

4.3 Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3, and Q4). The instruction fetch and ex ecute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g. GOTO) then two cycles are required to complete the instruction (Example 4-1).

A fetch cycle begins with the program counter incrementing in Q1.

In the execution cycle, the f etched instruction is latched into the “Instruction Register (IR)” in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

FIGURE 4-8: CLOCK/INSTRUCTION CYCLE

EXAMPLE 4-1: INSTRUCTION PIPELINE FLOW

Q2 Q3 Q4

OSC1

Q1 Q2 Q3

Q4 PC

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal phase clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5

1. MOVLW 55h

Fetch 1 Execute 1

2. MOVWF PORTB

Fetch 2 Execute 2

3. CALL SUB_1

Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP)

Fetch 4 Flush

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

PIC17C75X

DS30264A-page 20 Preliminary  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. Preliminary DS30264A-page 21

PIC17C75X

5.0 RESET

The PIC17CXXX differentiates between various kinds of reset:

• Power-on Reset (POR)

• MCLR

reset during normal operation

• Brown-out Reset

• WDT Reset (normal operation) Some registers are not affected in any reset condition,

their status is unknown on POR and unchanged in any other reset. Most other registers are forced to a “reset state” on Power-on Reset (POR), Brown-out Reset (BOR), on MCLR

or WDT Reset and on MCLR reset during SLEEP. A WDT Reset during SLEEP, is viewed as the resumption of normal operation. The T

O and PD bits are set or cleared differently in different reset situations as indicated in Table 5-3. These bits are used in software to determine the nature of the reset. See Table 5-4 for a full description of reset states of all registers.

A simpliﬁed block diagram of the on-chip reset circuit is shown in Figure 5-1.

Note: While the device is in a reset state, the

internal phase clock is held in the Q1 state. Any processor mode that allows external execution will force the RE0/ALE pin as a low output and the RE1/OE

and RE2/WR

pins as high outputs.

FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR

VDD

OSC1

WDT

Module

DD rise

detect

OST/PWRT

On-chip

RC OSC†

WDT

Time_Out

Power_On_Reset

OST

10-bit Ripple counter

PWRT

Chip_Reset

10-bit Ripple counter

Power_Up (Enable the PWRT timer

only during Power_Up)

(Power_Up) + (Wake_Up) (XT + LF) (Enable the OST if it is Power_Up or Wake_Up

from SLEEP and OSC type is XT or LF)

Reset

Enable OST

Enable PWRT

† This RC oscillator is shared with the WDT

when not in a power-up sequence.

BOR

Module

Brown-out

Reset

PIC17C75X

DS30264A-page 22 Preliminary  1997 Microchip Technology Inc.

5.1 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST), and Brown-out Reset (BOR)

5.1.1 POWER-ON RESET (POR)

The Power-on Reset circuit holds the device in reset until V

DD is above the trip point (in the range of 1.4V -

2.3V). The devices produce an internal reset for both

rising and falling V

DD. To take advantage of the POR,

just tie the MCLR/

VPP pin directly (or through a resistor)

to V

DD. This will eliminate external RC components

usually needed to create Power-on Reset. A minimum rise time for V

DD is required. See Electrical Speciﬁca-

tions for details. Figure 5-2 and Figure 5-3 show two possible POR cir-

cuits.

FIGURE 5-2: USING ON-CHIP POR

FIGURE 5-3: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW V

DD POWER-UP)

VDD

MCLR

PIC17CXXX

VDD

Note 1: An external Power-on Reset circuit is

required only if V

DD power-up time is too

slow. The diode D helps discharge the capacitor quickly when V

DD powers

down.

2: R < 40 kΩ is recommended to ensure

that the voltage drop across R does not exceed 0.2V (max. leakage current spec. on the MCLR/

VPP pin is 5 µA). A larger

voltage drop will degrade V

IH level on the

MCLR/

VPP pin.

3: R1 = 100Ω to 1 kΩ will limit any current

ﬂowing into MCLR

from external capaci-

tor C in the event of MCLR/

VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).

MCLR

PIC17CXXX

VDD

5.1.2 P O WER-UP TIMER (PWRT) The Power-up Timer provides a ﬁxed 96 ms time-out

(nominal) on power-up. This occurs from the rising edge of the POR signal and after the ﬁrst rising edge of MCLR

(detected high). The Power-up Timer operates on an internal RC oscillator. The chip is kept in RESET as long as the PWRT is active. In most cases the PWRT delay allows V

DD to rise to an acceptable level.

The power-up time delay will vary from chip to chip and with V

DD and temperature. See DC parameters for

details.

5.1.3 OSCILLATOR START-UP TIMER (OST) The Oscillator Start-up Timer (OST) provides a 1024

oscillator cycle (1024T

OSC) delay after MCLR is

detected high or a wake-up from SLEEP event occurs. The OST time-out is invoked only for XT and LF oscil-

lator modes on a Power-on Reset or a Wake-up from SLEEP.

The OST counts the oscillator pulses on the OSC1/CLKIN pin. The counter only starts incrementing after the amplitude of the signal reaches the oscillator input thresholds. This delay allows the crystal oscillator or resonator to stabilize before the device exits reset. The length of the time-out is a function of the crystal/resonator frequency.

Figure 5-4 shows the operation of the OST circuit. In this ﬁgure the oscillator is of such a low frequency that OST time out occurs after the power-up timer time-out.

FIGURE 5-4: OSCILLATOR START-UP

TIME

VDD

MCLR

OSC2

OST TIME_OUT

PWRT TIME_OUT

INTERNAL RESET

OSC1

OST

TPWRT

POR or BOR Trip Point

This ﬁgure shows in greater detail the timings involved with the oscillator start-up timer. In this example the low frequency crystal start-up time is larger than power-up time (T

PWRT).

Tosc1 = time for the crystal oscillator to react to an oscillation level detectable by the Oscillator Start-up Timer (ost).

TOST = 1024TOSC.

 1997 Microchip Technology Inc. Preliminary DS30264A-page 23

PIC17C75X

5.1.4 TIME-OUT SEQUENCE On power-up the time-out sequence is as follows: First

the internal POR signal goes high when the POR trip point is reached. If MCLR

is high, then both the OST and PWRT timers start. In general the PWRT time-out is longer, except with low frequency crystals/resonators. The total time-out also varies based on oscillator conﬁguration. Table 5-1 shows the times that are associated with the oscillator conﬁguration. Figure 5-5 and Figure 5-6 display these time-out sequences.

If the device voltage is not within electrical speciﬁcation at the end of a time-out, the MCLR/

VPP pin must be held low until the voltage is within the device speciﬁcation. The use of an external RC delay is sufﬁcient for many of these applications.

The time-out sequence begins from the ﬁrst rising edge of MCLR

Table 5-3 shows the reset conditions for some special registers, while Table 5-4 shows the initialization conditions for all the registers.

TABLE 5-1: TIME-OUT IN VARIOUS SITUATIONS

TABLE 5-2: STATUS BITS AND THEIR SIGNIFICANCE

TABLE 5-3: RESET CONDITION FOR THE PROGRAM COUNTER AND THE CPUSTA REGISTER

Oscillator

Conﬁguration

Power-up Wake up from

SLEEP

MCLR Reset BOR

XT, LF Greater of: 96 ms or 1024TOSC 1024TOSC ——

EC, RC Greater of: 96 ms or 1024T

OSC ———

POR

BOR

(1)

TO PD

Event

0011

Power-on Reset

1110

MCLR Reset during SLEEP or interrupt wake-up from SLEEP

1101

WDT Reset during normal operation

1100

WDT W ake-up during SLEEP

1111

MCLR Reset during normal operation

10xx

Brown-out Reset

000x

Illegal, TO is set on POR

00x0

Illegal, PD is set on POR

xx11

CLRWDT instruction executed

Note 1: When BOR is enabled, else the BOR status bit is unknown

Event PCH:PCL CPUSTA

(4)

OST Active

Power-on Reset 0000h --11 1100 Yes Brown-out Reset 0000h --11 1101 No

MCLR

Reset during normal operation 0000h --11 1111 No

MCLR

Reset during SLEEP 0000h --11 1011

Yes

(2)

WDT Reset during normal operation 0000h --11 0111 No WDT Wake-up during SLEEP

(3)

0000h --11 0011

Yes

(2)

Interrupt wake-up from SLEEP GLINTD is set PC + 1 --11 1011

Yes

(2)

GLINTD is clear

PC + 1

(1)

--10 1011

Yes

(2)

Legend: u = unchanged, x = unknown, - = unimplemented read as '0'. Note 1: On wake-up, this instruction is executed. The instruction at the appropriate interrupt vector is fetched and

then executed. 2: The OST is only active when the Oscillator is conﬁgured for XT or LF modes. 3: The Program Counter = 0, that is, the device branches to the reset vector. This is different from the

mid-range devices. 4: When BOR

is enabled, else the BOR status bit is unknown.

PIC17C75X

DS30264A-page 24 Preliminary  1997 Microchip Technology Inc.

In Figure 5-5, Figure 5-6 and Figure 5-7, TPWRT > T

OST, as would be the case in higher frequency crys-

tals. For lower frequency crystals, (i.e., 32 kHz) T

OST

would be greater.

FIGURE 5-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

FIGURE 5-6: TIME-OUT SEQUENCE ON POWER-UP (MCLR

NOT TIED TO VDD)

FIGURE 5-7: SLOW RISE TIME (MCLR

TIED TO VDD)

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWRT TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

Minimum VDD operating voltage

 1997 Microchip Technology Inc. Preliminary DS30264A-page 25

PIC17C75X

TABLE 5-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS

Power-on Reset

Brown-out Reset

MCLR

Reset

WDT Reset

Wake-up from SLEEP

through interrupt

Unbanked

INDF0 00h N.A. N.A. N.A. FSR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h 0000h 0000h

PC + 1

(2)

PCLATH 03h 0000 0000 0000 0000 uuuu uuuu ALUSTA 04h 1111 xxxx 1111 uuuu 1111 uuuu T0STA 05h 0000 000- 0000 000- 0000 000-

CPUSTA

(3)

06h

--11 1100

(4)

--11 qquu

(4)

--uu qquu

(4)

INTSTA 07h 0000 0000 0000 0000

uuuu uuuu

(1)

INDF1 08h N.A. N.A. N.A. FSR1 09h xxxx xxxx uuuu uuuu uuuu uuuu WREG 0Ah xxxx xxxx uuuu uuuu uuuu uuuu TMR0L 0Bh xxxx xxxx uuuu uuuu uuuu uuuu TMR0H 0Ch xxxx xxxx uuuu uuuu uuuu uuuu TBLPTRL 0Dh 0000 0000 0000 0000 uuuu uuuu TBLPTRH 0Eh 0000 0000 0000 0000 uuuu uuuu BSR 0Fh 0000 0000 0000 0000 uuuu uuuu

Bank 0

PORTA 10h 0-xx xxxx 0-uu uuuu u-uu uuuu DDRB 11h 1111 1111 1111 1111 uuuu uuuu PORTB 12h xxxx xxxx uuuu uuuu uuuu uuuu RCSTA1 13h 0000 -00x 0000 -00u uuuu -uuu RCREG1 14h xxxx xxxx uuuu uuuu uuuu uuuu TXSTA1 15h 0000 --1x 0000 --1u uuuu --uu TXREG1 16h xxxx xxxx uuuu uuuu uuuu uuuu SPBRG1 17h xxxx xxxx uuuu uuuu uuuu uuuu

Bank 1

DDRC 10h 1111 1111 1111 1111 uuuu uuuu PORTC 11h xxxx xxxx uuuu uuuu uuuu uuuu DDRD 12h 1111 1111 1111 1111 uuuu uuuu PORTD 13h xxxx xxxx uuuu uuuu uuuu uuuu DDRE 14h ---- 1111 ---- 1111 ---- uuuu PORTE 15h ---- xxxx ---- uuuu ---- uuuu PIR1 16h x000 0010 u000 0010

uuuu uuuu

(1)

PIE1 17h 0000 0000 0000 0000 uuuu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition. Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt

vector. 3: See Table 5-3 for reset value of speciﬁc condition. 4: If Brown-out is enabled, else the BOR

bit is unknown.

PIC17C75X

DS30264A-page 26 Preliminary  1997 Microchip Technology Inc.

Bank 2

TMR1 10h xxxx xxxx uuuu uuuu uuuu uuuu TMR2 11h xxxx xxxx uuuu uuuu uuuu uuuu TMR3L 12h xxxx xxxx uuuu uuuu uuuu uuuu TMR3H 13h xxxx xxxx uuuu uuuu uuuu uuuu PR1 14h xxxx xxxx uuuu uuuu uuuu uuuu PR2 15h xxxx xxxx uuuu uuuu uuuu uuuu PR3/CA1L 16h xxxx xxxx uuuu uuuu uuuu uuuu PR3/CA1H 17h xxxx xxxx uuuu uuuu uuuu uuuu

Bank 3

PW1DCL 10h xx-- ---- uu-- ---- uu-- ---- PW2DCL 11h xx0- ---- uu0- ---- uuu- ---- PW1DCH 12h xxxx xxxx uuuu uuuu uuuu uuuu PW2DCH 13h xxxx xxxx uuuu uuuu uuuu uuuu CA2L 14h xxxx xxxx uuuu uuuu uuuu uuuu CA2H 15h xxxx xxxx uuuu uuuu uuuu uuuu TCON1 16h 0000 0000 0000 0000 uuuu uuuu TCON2 17h 0000 0000 0000 0000 uuuu uuuu

Bank 4

PIR2 10h 000- 0010 000- 0010

uuu- uuuu

(1)

PIE2 11h 000- 0000 000- 0000 uuu- uuuu

Unimplemented

12h ---- ---- ---- ---- ---- ---RCSTA2 13h 0000 -00x 0000 -00u uuuu -uuu RCREG2 14h xxxx xxxx uuuu uuuu uuuu uuuu TXSTA2 15h 0000 --1x 0000 --1u uuuu --uu TXREG2 16h xxxx xxxx uuuu uuuu uuuu uuuu SPBRG2 17h xxxx xxxx uuuu uuuu uuuu uuuu

Bank 5

DDRF 10h 1111 1111 1111 1111 uuuu uuuu PORTF 11h xxxx xxxx uuuu uuuu uuuu uuuu DDRG 12h 1111 1111 1111 1111 uuuu uuuu PORTG 13h xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 14h 0000 -0-0 0000 -0-0 uuuu uuuu ADCON1 15h 000- 0000 000- 0000 uuuu uuuu ADRESL 16h xxxx xxxx xxxx xxxx uuuu uuuu ADRESH 17h xxxx xxxx xxxx xxxx uuuu uuuu

TABLE 5-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (Cont.’d)

Power-on Reset

Brown-out Reset

MCLR

Reset

WDT Reset

Wake-up from SLEEP

through interrupt

Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition. Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt

vector. 3: See Table 5-3 for reset value of speciﬁc condition. 4: If Brown-out is enabled, else the BOR

bit is unknown.

 1997 Microchip Technology Inc. Preliminary DS30264A-page 27

PIC17C75X

Bank 6

SSPADD 10h 0000 0000 0000 0000 uuuu uuuu SSPCON1 11h 0000 0000 0000 0000 uuuu uuuu SSPCON2 12h 0000 0000 0000 0000 uuuu uuuu SSPSTAT 13h 0000 0000 0000 0000 uuuu uuuu SSPBUF 14h xxxx xxxx uuuu uuuu uuuu uuuu

Unimplemented

15h ---- ---- ---- ---- ---- ----

Unimplemented

16h ---- ---- ---- ---- ---- ----

Unimplemented

17h ---- ---- ---- ---- ---- ----

Bank 7

PW3DCL 10h xxx- ---- uuu- ---- uuu- ---- PW3DCH 11h xxxx xxxx uuuu uuuu uuuu uuuu CA3L 12h xxxx xxxx uuuu uuuu uuuu uuuu CA3H 13h xxxx xxxx uuuu uuuu uuuu uuuu CA4L 14h xxxx xxxx uuuu uuuu uuuu uuuu CA4H 15h xxxx xxxx uuuu uuuu uuuu uuuu TCON3 16h -000 0000 -000 0000 -uuu uuuu

Unimplemented

17h ---- ---- ---- ---- ---- ----

Unbanked

PRODL 18h xxxx xxxx uuuu uuuu uuuu uuuu PRODH 19h xxxx xxxx uuuu uuuu uuuu uuuu

TABLE 5-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (Cont.’d)

Power-on Reset

Brown-out Reset

MCLR

Reset

WDT Reset

Wake-up from SLEEP

through interrupt

Legend: u = unchanged, x = unknown, - = unimplemented read as '0', q = value depends on condition. Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt

vector. 3: See Table 5-3 for reset value of speciﬁc condition. 4: If Brown-out is enabled, else the BOR

bit is unknown.

PIC17C75X

DS30264A-page 28 Preliminary  1997 Microchip Technology Inc.

5.1.5 BROWN-OUT RESET (BOR) PIC17C75X devices have an on-chip Brown-out Reset

circuitry. This circuitry places the device into a reset when the device voltage f alls below a trip point (BV

DD).

This ensures that the device does not continue program execution outside the v alid oper ation range of the device. Brown-out resets are typically used in AC line applications or large battery applications where large loads may be switched in (such as automotive).

A conﬁguration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If V

DD falls below BVDD (Typically 4.0V,

parameter D005 in electrical speciﬁcation section), for greater than parameter D035, the brown-out situation will reset the chip. A reset is not guaranteed to occur if V

DD falls below BVDD for less than parameter D035.

The chip will remain in Brown-out Reset until V

DD rises

above BV

DD. The Power-up Timer will now be invoked

and will keep the chip in reset an additional 96 ms. If V

DD drops below BVDD while the Power-up Timer is

running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V

rises above BVDD, the Power-up Timer will execute a 96 ms time delay. Figure 5-10 shows typical Brown-out situations.

In some applications the Brown-out reset trip point of the device may not be at the desired level. Figure 5-8 and Figure 5-9 are two examples of external circuitry that may be implemented. Each needs to be evaluated to determine if they match the requirements of the application.

Note: Before using the on-chip brown-out for a

voltage supervisory function, please review the electrical speciﬁcations to ensure that they meet your requirements.

FIGURE 5-8: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 1

FIGURE 5-9: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 2

VDD

33k

10k

40 kΩ

MCLR

PIC17CXXX

This circuit will activate reset when VDD goes below (Vz + 0.7V) where Vz = Zener voltage.

This brown-out circuit is less expensive, albeit less accurate. Transistor Q1 turns off when VDD is below a certain level such that:

VDD •

R1 + R2

= 0.7V

40 kΩ

VDD

MCLR

PIC17CXXX

FIGURE 5-10: BROWN-OUT SITUATIONS

96 ms

DD Max.

DD Min.

Internal

Reset

BVDD Max. BV

DD Min.

Internal

Reset

96 ms

< 96 ms

96 ms

BVDD Max. BV

DD Min.

Internal

Reset

 1997 Microchip Technology Inc. Preliminary DS30264A-page 29

PIC17C75X

6.0 INTERRUPTS

The PIC17C75X devices have 18 sources of interrupt:

• External interrupt from the RA0/INT pin

• Change on RB7:RB0 pins

• TMR0 Overﬂow

• TMR1 Overﬂow

• TMR2 Overﬂow

• TMR3 Overﬂow

• USART1 Transmit buffer empty

• USART1 Receive buffer full

• USART2 Transmit buffer empty

• USART2 Receive buffer full

• SSP Interrupt

• SSP I

C bus collision interrupt

• A/D conversion complete

• Capture1

• Capture2

• Capture3

• Capture4

• T0CKI edge occurred There are six registers used in the control and status of

interrupts. These are:

• CPUST A

• INTST A

• PIE1

• PIR1

• PIE2

• PIR2 The CPUSTA register contains the GLINTD bit. This is

the Global Interrupt Disable bit. When this bit is set, all interrupts are disabled. This bit is part of the controller core functionality and is described in the Memory Organization section.

When an interrupt is responded to, the GLINTD bit is automatically set to disable any further interrupts, the return address is pushed onto the stack and the PC is loaded with the interrupt vector address. There are four interrupt vectors. Each vector address is for a speciﬁc interrupt source (except the peripheral interrupts which all vector to the same address). These sources are:

• External interrupt from the RA0/INT pin

• TMR0 Overﬂow

• T0CKI edge occurred

• Any peripheral interrupt When program execution vectors to one of these inter-

rupt vector addresses (except for the peripheral interrupts), the interrupt ﬂag bit is automatically cleared. Vectoring to the peripheral interrupt vector address does not automatically clear the source of the interrupt. In the peripheral interrupt service routine, the source(s) of the interrupt can be determined by testing the interrupt ﬂag bits. The interrupt ﬂag bit(s) must be cleared in software before re-enabling interrupts to avoid inﬁnite interrupt requests.

When an interrupt condition is met, that individual interrupt ﬂag bit will be set regardless of the status of its corresponding mask bit or the GLINTD bit.

For external interrupt events, there will be an interrupt latency. For two cycle instructions, the latency could be one instruction cycle longer.

The “return from interrupt” instruction, RETFIE, can be used to mark the end of the interrupt service routine. When this instruction is executed, the stack is “POPed”, and the GLINTD bit is cleared (to re-enable interrupts).

FIGURE 6-1: INTERRUPT LOGIC

RBIF RBIE

TMR3IF TMR3IE

TMR2IF TMR2IE

TMR1IF TMR1IE

CA2IF CA2IE

CA1IF CA1IE

TX1IF TX1IE

RC1IF RC1IE

T0IF T0IE

INTF INTE

T0CKIF T0CKIE

GLINTD (CPUSTA<4>)

PEIE

Wake-up (If in SLEEP mode) or terminate long write

Interrupt to CPU

PEIF SSPIF SSPIE

BCLIF BCLIE

ADIF ADIE

CA4IF CA4IE

CA3IF CA3IE

TX2IF TX2IE

RC2IF RC2IE

PIR1 / PIE1

PIR2 / PIE2

INTSTA

PIC17C75X

DS30264A-page 30 Preliminary  1997 Microchip Technology Inc.

6.1 Interrupt Status Register (INTSTA)

The Interrupt Status/Control register (INTSTA) records the individual interrupt requests in ﬂag bits, and contains the individual interrupt enable bits (not for the peripherals).

The PEIF bit is a read only , bit wise OR of all the peripheral ﬂag bits in the PIR registers (Figure 6-5 and Figure 6-6).

Care should be taken when clearing any of the INTSTA register enable bits when interrupts are enabled (GLINTD is clear). If any of the INTSTA ﬂag bits (T0IF, INTF, T0CKIF, or PEIF) are set in the same instruction cycle as the corresponding interrupt enable bit is cleared, the device will vector to the reset address (0x00).

When disabling any of the INTSTA enable bits, the GLINTD bit should be set (disabled).

Note: T0IF, INTF, T0CKIF, and PEIF get set by

their speciﬁed condition, even if the corresponding interrupt enable bit is clear (interrupt disabled) or the GLINTD bit is set (all interrupts disabled).

FIGURE 6-2: INTSTA REGISTER (ADDRESS: 07h, UNBANKED)

R - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE

R = Readable bit W = Writable bit

- n = Value at POR reset

bit7 bit0 bit 7: PEIF: Peripheral Interrupt Flag bit

This bit is the OR of all peripheral interrupt ﬂag bits AND’ed with their corresponding enable bits. 1 =A peripheral interrupt is pending 0 =No peripheral interrupt is pending

bit 6: T0CKIF: External Interrupt on T0CKI Pin Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to vector (18h). 1 =The software speciﬁed edge occurred on the RA1/T0CKI pin 0 =The software speciﬁed edge did not occur on the RA1/T0CKI pin

bit 5: T0IF: TMR0 Overﬂow Interrupt Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to vector (10h). 1 =TMR0 overﬂowed 0 =TMR0 did not overﬂow

bit 4: INTF: External Interrupt on INT Pin Flag bit

This bit is cleared by hardware, when the interrupt logic forces program execution to vector (08h). 1 =The software speciﬁed edge occurred on the RA0/INT pin 0 =The software speciﬁed edge did not occur on the RA0/INT pin

bit 3: PEIE: Peripheral Interrupt Enable bit

This bit enables all peripheral interrupts that have their corresponding enable bits set. 1 =Enable peripheral interrupts 0 =Disable peripheral interrupts

bit 2: T0CKIE: External Interrupt on T0CKI Pin Enable bit

1 =Enable software speciﬁed edge interrupt on the RA1/T0CKI pin 0 =Disable interrupt on the RA1/T0CKI pin

bit 1: T0IE: TMR0 Overﬂow Interrupt Enable bit

1 =Enable TMR0 overﬂow interrupt 0 =Disable TMR0 overﬂow interrupt

bit 0: INTE: External Interrupt on RA0/INT Pin Enable bit

1 =Enable software speciﬁed edge interrupt on the RA0/INT pin 0 =Disable software speciﬁed edge interrupt on the RA0/INT pin

 1997 Microchip Technology Inc. Preliminary DS30264A-page 31

PIC17C75X

6.2 Peripheral Interrupt Enable Register1 (PIE1) and Register2 (PIE2)

These registers contains the individual enable bits for the peripheral interrupts.

FIGURE 6-3: PIE1 REGISTER (ADDRESS: 17h, BANK 1)

R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0

RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE

R = Readable bit W = Writable bit

-n = Value at POR reset

bit7 bit0 bit 7: RBIE: PORTB Interrupt on Change Enable bit

1 =Enable PORTB interrupt on change 0 =Disable PORTB interrupt on change

bit 6: TMR3IE: TMR3 Interrupt Enable bit

1 =Enable TMR3 interrupt 0 =Disable TMR3 interrupt

bit 5: TMR2IE: TMR2 Interrupt Enable bit

1 =Enable TMR2 interrupt 0 =Disable TMR2 interrupt

bit 4: TMR1IE: TMR1 Interrupt Enable bit

1 =Enable TMR1 interrupt 0 =Disable TMR1 interrupt

bit 3: CA2IE: Capture2 Interrupt Enable bit

1 =Enable Capture2 interrupt 0 =Disable Capture2 interrupt

bit 2: CA1IE: Capture1 Interrupt Enable bit

1 =Enable Capture1 interrupt 0 =Disable Capture1 interrupt

bit 1: TX1IE: USART1 Transmit Interrupt Enable bit

1 =Enable USART1 Transmit buffer empty interrupt 0 =Disable USART1 Transmit buffer empty interrupt

bit 0: RC1IE: USART1 Receive Interrupt Enable bit

1 =Enable USART1 Receive buffer full interrupt 0 =Disable USART1 Receive buffer full interrupt

PIC17C75X

DS30264A-page 32 Preliminary  1997 Microchip Technology Inc.

FIGURE 6-4: PIE2 REGISTER (ADDRESS: 11h, BANK 4)

R/W - 0 R/W - 0 R/W - 0 U - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0

SSPIE BCLIE ADIE

—

CA4IE CA3IE TX2IE RC2IE

R = Readable bit W = Writable bit

-n = Value at POR reset

bit7 bit0 bit 7: SSPIE: Synchronous Serial Port Interrupt Enable

1 =Enable SSP Interrupt 0 = Disable SSP Interrupt

bit 6: BCLIE: Bus Collision Interrupt Enable

1 =Enable Bus Collision Interrupt 0 =Disable Bus Collision Interrupt

bit 5: ADIE: A/D Module Interrupt Enable

1 =Enable A/D Module Interrupt

0 =Disable A/D Module Interrupt bit 4: Unimplemented: Read as ‘0’ bit 3: CA4IE: Capture4 Interrupt Enable

1 =Enable Capture4 Interrupt

0 =Disable Capture4 Interrupt bit 2: CA3IE: Capture3 Interrupt Enable

1 =Enable Capture3 Interrupt

0 =Disable Capture3 Interrupt bit 1: TX2IE: USART2 Transmit Interrupt Enable

1 =Enable USART2 Transmit Interrupt

0 =Disable USART2 Transmit Interrupt bit 0: RC2IE: USART2 Receive Interrupt Enable

1 =Enable USART2 Receive Interrupt

0 =Disable USART2 Receive Interrupt

 1997 Microchip Technology Inc. Preliminary DS30264A-page 33

PIC17C75X

6.3 Peripheral Interrupt Request Register1 (PIR1) and Register2 (PIR2)

These registers contains the individual ﬂag bits for the peripheral interrupts.

Note: These bits will be set by the speciﬁed con-

dition, even if the corresponding interrupt enable bit is cleared (interrupt disabled), or the GLINTD bit is set (all interrupts disabled). Before enabling an interrupt, the user may wish to clear the interrupt ﬂag to ensure that the program does not immediately branch to the peripheral interrupt service routine.

FIGURE 6-5: PIR1 REGISTER (ADDRESS: 16h, BANK 1)

R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R - 1 R - 0

RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF

R = Readable bit W = Writable bit

-n = Value at POR reset

bit7 bit0 bit 7: RBIF: PORTB Interrupt on Change Flag bit

1 =One of the PORTB inputs changed (software must end the mismatch condition) 0 =None of the PORTB inputs have changed

bit 6: TMR3IF: TMR3 Interrupt Flag bit

If Capture1 is enab

led (CA1/PR3 = 1) 1 =TMR3 overﬂowed 0 =TMR3 did not overﬂow

If Capture1 is disab

led (CA1/PR3 = 0) 1 =TMR3 value has rolled over to 0000h from equalling the period register (PR3H:PR3L) value 0 =TMR3 value has not rolled over to 0000h from equalling the period register (PR3H:PR3L) value

bit 5: TMR2IF: TMR2 Interrupt Flag bit

1 =TMR2 value has rolled over to 0000h from equalling the period register (PR2) value 0 =TMR2 value has not rolled over to 0000h from equalling the period register (PR2) value

bit 4: TMR1IF: TMR1 Interrupt Flag bit

TMR1 is in 8-bit mode (T16 = 0) 1 =TMR1 value has rolled over to 0000h from equalling the period register (PR1) value 0 =TMR1 value has not rolled over to 0000h from equalling the period register (PR1) value

Timer1 is in 16-bit mode (T16 = 1) 1 =TMR2:TMR1 value has rolled over to 0000h from equalling the period register (PR2:PR1) value 0 =TMR2:TMR1 value has not rolled over to 0000h from equalling the period register (PR2:PR1) value

bit 3: CA2IF: Capture2 Interrupt Flag bit

1 =Capture event occurred on RB1/CAP2 pin 0 =Capture event did not occur on RB1/CAP2 pin

bit 2: CA1IF: Capture1 Interrupt Flag bit

1 =Capture event occurred on RB0/CAP1 pin 0 =Capture event did not occur on RB0/CAP1 pin

bit 1: TX1IF: USART1 Transmit Interrupt Flag bit (State controlled by hardware)

1 =USART1 Transmit buffer is empty 0 =USART1 Transmit buffer is full

bit 0: RC1IF: USART1 Receive Interrupt Flag bit (State controlled by hardware)

1 =USART1 Receive buffer is full 0 =USART1 Receive buffer is empty

PIC17C75X

DS30264A-page 34 Preliminary  1997 Microchip Technology Inc.

FIGURE 6-6: PIR2 REGISTER (ADDRESS: 10h, BANK 4)

R/W - 0 R/W - 0 R/W - 0 U - 0 R/W - 0 R/W - 0 R - 1 R - 0

SSPIF BCLIF ADIF

—

CA4IF CA3IF TX2IF RC2IF

R = Readable bit W = Writable bit

-n = Value at POR reset

bit7 bit0 bit 7: SSPIF: Synchronous Serial Port (SSP) Interrupt Flag

1 = The SSP interrupt condition has occured, and must be cleared in software before returning from the

interrupt service routine. The conditions that will set this bit are: SPI

A transmission/reception has taken place.

C Slave / Master

A transmission/reception has taken place.

C Master

The initiated start condition was completed by the SSP module. The initiated stop condition was completed by the SSP module. The initiated restart condition was completed by the SSP module. The initiated acknowledge condition was completed by the SSP module. A start condition occurred while the SSP module was idle (Multimaster system). A stop condition occurred while the SSP module was idle (Multimaster system).

0 = An SSP interrupt condition has occurred.

bit 6: BCLIF: Bus Collision Interrupt Flag

1 =A bus collision has occurred in the SSP, when conﬁgured for I

C master mode

0 =No bus collision has occurred

bit 5: ADIF: A/D Module Interrupt Flag

1 =An A/D conversion is complete

0 =An A/D conversion is not complete bit 4: Unimplemented: Read as '0' bit 3: CA4IF: Capture4 Interrupt Flag

1 =Capture event occurred on RE3/CAP4 pin

0 =Capture event did not occur on RE3/CAP4 pin bit 2: CA3IF: Capture3 Interrupt Flag

1 =Capture event occurred on RG4/CAP3 pin

0 =Capture event did not occur on RG4/CAP3 pin bit 1: TX2IF:USART2 Transmit Interrupt Flag (State controlled by hardware)

1 =USART2 Transmit buffer is empty

0 = USART2 Transmit buffer is full bit 0: RC2IF: USART2 Receive Interrupt Flag (State controlled by hardware)

1 =USART2 Receive buffer is full

0 =USART2 Receive buffer is empty

 1997 Microchip Technology Inc. Preliminary DS30264A-page 35

PIC17C75X

6.4 Interrupt Operation

Global Interrupt Disable bit, GLINTD (CPUSTA<4>), enables all unmasked interrupts (if clear) or disables all interrupts (if set). Individual interrupts can be disabled through their corresponding enable bits in the INTSTA register. Peripheral interrupts need either the global peripheral enable PEIE bit disabled, or the speciﬁc peripheral enable bit disabled. Disabling the peripherals via the global peripheral enable bit, disables all peripheral interrupts. GLINTD is set on reset (interrupts disabled).

The RETFIE instruction allows retur ning from interrupt and re-enables interrupts at the same time.

When an interrupt is responded to, the GLINTD bit is automatically set to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with the interrupt vector. There are four interrupt vectors which help reduce interrupt latency.

The peripheral interrupt vector has multiple interrupt sources. Once in the peripheral interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt ﬂag bits. The peripheral interrupt ﬂag bit(s) must be cleared in software before re-enabling interrupts to avoid continuous interrupts.

The PIC17C75X devices have four interrupt vectors. These vectors and their hardware priority are shown in Table 6-1. If two enabled interrupts occur “at the same time”, the interrupt of the highest priority will be serviced ﬁrst. This means that the vector address of that interrupt will be loaded into the program counter (PC).

TABLE 6-1: INTERRUPT

VECTORS/PRIORITIES

Address Vector Priority

0008h External Interrupt on

RA0/INT pin (INTF)

1 (Highest)

0010h TMR0 overﬂow interrupt

(T0IF)

0018h External Interrupt on T0CKI

(T0CKIF)

0020h Peripherals (PEIF) 4 (Lowest)

Note 1: Individual interrupt ﬂag bits are set regard-

less of the status of their corresponding mask bit or the GLINTD bit.

Note 2: Before disabling any of the INTSTA enable

bits, the GLINTD bit should be set (disabled).

6.5 RA0/INT Interrupt

The external interrupt on the RA0/INT pin is edge triggered. Either the rising edge, if INTEDG bit (T0STA<7>) is set, or the falling edge, if INTEDG bit is clear. When a valid edge appears on the RA0/INT pin, the INTF bit (INTSTA<4>) is set. This interrupt can be disabled by clearing the INTE control bit (INTSTA<0>). The INT interrupt can wake the processor from SLEEP. See Section 17.4 for details on SLEEP operation.

6.6 T0CKI Interrupt

The external interrupt on the RA1/T0CKI pin is edge triggered. Either the rising edge, if the T0SE bit (T0STA<6>) is set, or the falling edge, if the T0SE bit is clear. When a valid edge appears on the RA1/T0CKI pin, the T0CKIF bit (INTSTA<6>) is set. This interrupt can be disabled by clearing the T0CKIE control bit (INTSTA<2>). The T0CKI interrupt can wake up the processor from SLEEP. See Section 17.4 for details on SLEEP operation.

6.7 Peripheral Interrupt

The peripheral interrupt ﬂag indicates that at least one of the peripheral interrupts occurred (PEIF is set). The PEIF bit is a read only bit, and is a bit wise OR of all the ﬂag bits in the PIR registers AND’ed with the corresponding enable bits in the PIE registers. Some of the peripheral interrupts can wake the processor from SLEEP. See Section 17.4 for details on SLEEP operation.

6.8 Context Saving During Interrupts

During an interrupt, only the returned PC value is saved on the stack. Typically, users ma y wish to sa v e k e y registers during an interrupt; e.g. WREG, ALUSTA and the BSR registers. This requires implementation in software.

Example 6-2 shows the saving and restoring of information for an interrupt service routine. This is for a simple interrupt scheme, where only one interrupt may occur at a time (no interrupt nesting). The SFRs are stored in the non-banked GPR area.

Example 6-2 shows the saving and restoring of information for a more complex interrupt service routine. This is useful where nesting of interrupts is required. A maximum of 6 levels can be done b y this example. The BSR is stored in the non-banked GPR area, while the other registers would be stored in a particular bank. Therefore 6 saves may be done with this routine (since there are 6 non-banked GPR registers). These routines require a dedicated indirect addressing register, FSR0 has been selected for this.

The PUSH and POP code segments could either be in each interrupt service routine or could be subroutines that were called. Depending on the application, other registers may also need to be saved.

PIC17C75X

DS30264A-page 36 Preliminary  1997 Microchip Technology Inc.

FIGURE 6-7: INT PIN / T0CKI PIN INTERRUPT TIMING

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1 OSC2

RA0/INT or

RA1/T0CKI

INTF or

T0CKIF

GLINTD

Instruction executed

System Bus

Instruction

Fetched

PC PC + 1 Addr (Vector)

PC Inst (PC) Inst (PC+1)

Inst (PC) Dummy Dummy

YY YY + 1

RETFIE

Inst (PC+1)

Inst (Vector)

Addr

Addr Addr

Inst (YY + 1)

Dummy

PC + 1

 1997 Microchip Technology Inc. Preliminary DS30264A-page 37

PIC17C75X

EXAMPLE 6-1: SAVING STATUS AND WREG IN RAM (SIMPLE)

PIC17C75X

DS30264A-page 38 Preliminary  1997 Microchip Technology Inc.

EXAMPLE 6-2: SAVING STATUS AND WREG IN RAM (NESTED)

; The addresses that are used to store the CPUSTA and WREG values must be in the data memory ; address range of 1Ah - 1Fh. Up to 6 locations can be saved and restored using the MOVFP ; instruction. This instruction neither affects the status bits, nor corrupts the WREG register. ; This routine uses the FRS0, so it controls the FS1 and FS0 bits in the ALUSTA register. ; Nobank_FSR EQU 0x40 Bank_FSR EQU 0x41 ALU_Temp EQU 0x42 WREG_TEMP EQU 0x43 BSR_S1 EQU 0x01A ; 1st location to save BSR BSR_S2 EQU 0x01B ; 2nd location to save BSR (Label Not used in program) BSR_S3 EQU 0x01C ; 3rd location to save BSR (Label Not used in program) BSR_S4 EQU 0x01D ; 4th location to save BSR (Label Not used in program) BSR_S5 EQU 0x01E ; 5th location to save BSR (Label Not used in program) BSR_S6 EQU 0x01F ; 6th location to save BSR (Label Not used in program) ; INITIALIZATION ; CALL CLEAR_RAM ; Must Clear all Data RAM ; INIT_POINTERS ; Must Initialize the pointers for POP and PUSH CLRF BSR, F ; Set All banks to 0 CLRF ALUSTA, F ; FSR0 post increment BSF ALUSTA, FS1 CLRF WREG, F ; Clear WREG MOVLW BSR_S1 ; Load FSR0 with 1st address to save BSR MOVWF FSR0 MOVWF Nobank_FSR MOVLW 0x20 MOVWF Bank_FSR : : ; Your code : : ; At Interrupt Vector Address PUSH BSF ALUSTA, FS0 ; FSR0 has auto-increment, does not affect status bits BCF ALUSTA, FS1 ; does not affect status bits MOVFP BSR, INDF0 ; No Status bits are affected CLRF BSR, F ; Periperal and Data RAM Bank 0 No Status bits are affected MOVPF ALUSTA, ALU_Temp ; MOVPF FSR0, Nobank_FSR ; Save the FSR for BSR values MOVPF WREG, WREG_TEMP ; MOVFP Bank_FSR, FSR0 ; Restore FSR value for other values MOVFP ALU_Temp, INDF0 ; Push ALUSTA value MOVFP WREG_TEMP, INDF0 ; Push WREG value MOVFP PCLATH, INDF0 ; Push PCLATH value MOVPF FSR0, Bank_FSR ; Restore FSR value for other values MOVFP Nobank_FSR, FSR0 ; ; : ; Interrupt Service Routine (ISR) code ; POP CLRF ALUSTA, F ; FSR0 has auto-decrement, does not affect status bits MOVFP Bank_FSR, FSR0 ; Restore FSR value for other values DECF FSR0, F ; MOVFP INDF0, PCLATH ; Pop PCLATH value MOVFP INDF0, WREG ; Pop WREG value BSF ALUSTA, FS1 ; FSR0 does not change MOVPF INDF0, ALU_Temp ; Pop ALUSTA value MOVPF FSR0, Bank_FSR ; Restore FSR value for other values DECF Nobank_FSR, F ; MOVFP Nobank_FSR, FSR0 ; Save the FSR for BSR values MOVFP ALU_Temp, ALUSTA ; MOVFP INDF0, BSR ; No Status bits are affected ; RETFIE ; Return from interrupt (enable interrupts)

 1997 Microchip Technology Inc. Preliminary DS30264A-page 39

PIC17C75X

7.0 MEMORY ORGANIZATION

There are two memory blocks in the PIC17C75X; program memory and data memory. Each block has its own bus, so that access to each bloc k can occur during the same oscillator cycle.

The data memory can further be broken down into General Purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the “core” are described here. The SFRs used to control the peripheral modules are described in the section discussing each individual peripheral module.

7.1 Program Memory Organization

PIC17C75X devices have a 16-bit program counter capable of addressing a 64K x 16 program memory space. The reset vector is at 0000h and the interrupt vectors are at 0008h, 0010h, 0018h, and 0020h (Figure 7-1).

7.1.1 PROGRAM MEMORY OPERATION The PIC17C75X can operate in one of four possible

program memory conﬁgurations. The conﬁguration is selected by conﬁguration bits. The possible modes are:

• Microprocessor

• Microcontroller

• Extended Microcontroller

• Protected Microcontroller The microcontroller and protected microcontroller

modes only allow internal execution. Any access beyond the program memory reads unknown data. The protected microcontroller mode also enables the code protection feature.

The extended microcontroller mode accesses both the internal program memory as well as external program memory. Execution automatically switches between internal and external memory. The 16-bits of address allow a program memory range of 64K-words.

The microprocessor mode only accesses the external program memory. The on-chip program memory is ignored. The 16-bits of address allow a program memory range of 64K-words. Microprocessor mode is the default mode of an unprogrammed device.

The different modes allow different access to the conﬁguration bits, test memory, and boot ROM. Table 7-1 lists which modes can access which areas in memory. Test Memor y and Boot Memory are not required for normal operation of the device. Care should be taken to ensure that no unintended branches occur to these areas.

FIGURE 7-1: PROGRAM MEMORY MAP

AND STACK

PC<15:0>

Stack Level 1

•

Stack Level 16

Reset Vector INT Pin Interrupt Vector Timer0 Interrupt Vector

T0CKI Pin Interrupt Vector Peripheral Interrupt Vector

FOSC0

FOSC1 WDTPS0 WDTPS1

PM0

Reserved

PM1

Reserved

•

Conﬁguration Memory

Space

User Memory

Space

(1)

CALL, RETURN RETFIE, RETLW

0000h

0008h 0010h

0020h 0021h

0018h

FDFFh FE00h

FE01h FE02h FE03h FE04h FE05h FE06h FE07h

FE0Fh

Test EPROM

Boot ROM

FE10h FF5Fh FF60h

FFFFh

1FFFh

3FFFh

(PIC17C752)

(PIC17C756)

Reserved

PM2

FE08h

Note 1: User memory space may be internal, external, or

both. The memory conﬁguration depends on the processor mode.

FE0Eh

BODEN

FE0Dh

PIC17C75X

DS30264A-page 40 Preliminary  1997 Microchip Technology Inc.

TABLE 7-1: MODE MEMORY ACCESS

Operating

Mode

Internal

Program

Memory

Conﬁguration Bits,

Test Memory,

Boot ROM

Microprocessor No Access No Access Microcontroller Access Access

Extended Microcontroller

Access No Access

Protected Microcontroller

Access Access

The PIC17C75X can operate in modes where the program memory is off-chip. They are the microprocessor and extended microcontroller modes. The microprocessor mode is the default for an unprogrammed device.

Regardless of the processor mode, data memory is always on-chip.

FIGURE 7-2: MEMORY MAP IN DIFFERENT MODES

Microprocessor

Mode

0000h

FFFFh

External Program Memory

2000h

FFFFh

0000h

01FFFh

On-chip Program Memory

Extended Microcontroller Mode

Microcontroller

Modes

0000h

01FFFh

2000h

FE00h

FFFFh

ON-CHIP ON-CHIP ON-CHIP

OFF-CHIP ON-CHIP OFF-CHIP ON-CHIP OFF-CHIP ON-CHIP

PROGRAM SPACEDATA SPACE

Conﬁg. Bits

Test Memory

Boot ROM

PIC17C752

0000h

FFFFh

External Program Memory

FFFFh

0000h

3FFFh

4000h

FE00h

FFFFh

OFF-CHIP ON-CHIP OFF-CHIP ON-CHIP OFF-CHIP ON-CHIP

Conﬁg. Bits

Test Memory

Boot ROM

PROGRAM SPACEDATA SPACE

ON-CHIPON-CHIP

00h

FFh 1FFh

120h

ON-CHIP

3FFFh

4000h

PIC17C756

On-chip Program Memory

2FFh

220h

3FFh

320h

00h

FFh 1FFh

120h

2FFh

220h

3FFh

320h

00h

FFh 1FFh

120h

2FFh

220h

3FFh

320h

00h

FFh 1FFh

120h

00h

FFh 1FFh

120h

00h

FFh 1FFh

120h

 1997 Microchip Technology Inc. Preliminary DS30264A-page 41

PIC17C75X

7.1.2 EXTERNAL MEMORY INTERFACE When either microprocessor or extended microcontrol-

ler mode is selected, PORTC, P ORTD and PORTE are conﬁgured as the system bus. P ORTC and PORTD are the multiplexed address/data bus and PORTE<2:0> is for the control signals. External components are needed to demultiplex the address and data. This can be done as shown in Figure 7-4. The waveforms of address and data are shown in Figure 7-3. For complete timings, please refer to the electrical speciﬁcation section.

FIGURE 7-3: EXTERNAL PROGRAM

MEMORY ACCESS WAVEFORMS

The system bus requires that there is no bus conﬂict (minimal leakage), so the output value (address) will be capacitively held at the desired value.

As the speed of the processor increases, external EPROM memory with faster access time must be used. T ab le 7-2 lists external memory speed requirements for a given PIC17C75X device frequency.

Q1 Q2 Q4Q3Q1 Q2 Q4

<15:0>

ALE

'1'

Read cycle

Write cycle

Address out Data in

Address out

Data out

In extended microcontroller mode, when the device is executing out of internal memory, the control signals will continue to be active. That is, they indicate the action that is occurring in the internal memory. The external memory access is ignored.

This following selection is for use with Microchip EPROMs. For interfacing to other manufacturers memory, please refer to the electrical speciﬁcations of the desired PIC17C75X device, as well as the desired memory device to ensure compatibility.

TABLE 7-2: EPROM MEMORY ACCESS

TIME ORDERING SUFFIX

PIC17C75X

Oscillator

Frequency

Instruction

Cycle

Time (T

CY)

EPROM Sufﬁx

PIC17C752 PIC17C756

8 MHz 500 ns -25 16 MHz 250 ns -15 20 MHz 200 ns -10 25 MHz 160 ns -70 33 MHz 121 ns (1)

Note 1: The access times for this requires the use of

fast SRAMs.

FIGURE 7-4: TYPICAL EXTERNAL PROGRAM MEMORY CONNECTION DIAGRAM

AD7-AD0

PIC17CXXX

AD15-AD8

ALE

I/O

(1)

AD15-AD0

373

Memory

(MSB)

Ax-A0 D7-D0

A15-A0

Memory

(LSB)

Ax-A0 D7-D0

373

138

(1)

OE OE

WR WR

(2)(2)

Note 1: Use of I/O pins is only required for paged memory.

2: This signal is unused for ROM and EPROM devices.

PIC17C75X

DS30264A-page 42 Preliminary  1997 Microchip Technology Inc.

7.2 Data Memory Organization

Data memory is partitioned into two areas. The ﬁrst is the General Purpose Registers (GPR) area, while the second is the Special Function Registers (SFR) area. The SFRs control and give the status for the operation of the device.

Portions of data memory are banked, this occurs in both areas. The GPR area is banked to allow greater than 232 bytes of general purpose RAM.

Banking requires the use of control bits for bank selection. These control bits are located in the Bank Select Register (BSR). If an access is made to the unbanked region, the BSR bits are ignored. Figure 7-5 shows the data memory map organization.

Instructions MOVPF and MOVFP provide the means to move values from the peripheral area (“P”) to any location in the register file (“F”), and vice-versa. The deﬁnition of the “P” range is from 0h to 1Fh, while the “F” range is 0h to FFh. The “P” range has six more locations than peripheral registers which can be used as General Purpose Registers. This can be useful in some applications where variables need to be copied to other locations in the general purpose RAM (such as saving status information during an interrupt).

The entire data memory can be accessed either directly or indirectly through ﬁle select registers FSR0 and FSR1 (Section 7.4). Indirect addressing uses the appropriate control bits of the BSR for accesses into the banked areas of data memory. The BSR is explained in greater detail in Section 7.8.

7.2.1 GENERAL PURPOSE REGISTER (GPR) All devices have some amount of GPR area. The GPRs

are 8-bits wide. When the GPR area is greater than 232, it must be banked to allow access to the additional memory space.

All the PIC17C75X devices have banked memory in the GPR area. To facilitate switching between these banks, the MOVLR bank instruction has been added to the instruction set. GPRs are not initialized by a Power-on Reset and are unchanged on all other resets .

7.2.2 SPECIAL FUNCTION REGISTERS (SFR) The SFRs are used by the CPU and peripheral func-

tions to control the operation of the device (Figure 7-5). These registers are static RAM.

The SFRs can be classiﬁed into two sets, those associated with the “core” function and those related to the peripheral functions. Those registers related to the “core” are described here, while those related to a peripheral feature are described in the section for each peripheral feature.

The peripheral registers are in the banked portion of memory, while the core registers are in the unbanked region. To facilitate switching between the peripheral banks, the MOVLB bank instruction has been provided.

 1997 Microchip Technology Inc. Preliminary DS30264A-page 43

PIC17C75X

FIGURE 7-5: PIC17C75X REGISTER FILE MAP

Addr Unbanked

00h

INDF0

01h

FSR0

02h

PCL

03h

PCLATH

04h

ALUSTA

05h

T0STA

06h

CPUSTA

07h

INTSTA

08h

INDF1

09h

FSR1

0Ah

WREG

0Bh

TMR0L

0Ch

TMR0H

0Dh

TBLPTRL

0Eh

TBLPTRH

0Fh

BSR

Bank 0 Bank 1

(1)

Bank 2

(1)

Bank 3

(1)

Bank 4

(1)

Bank 5

(1)

Bank 6

(1)

Bank 7

(1)

10h

PORTA DDRC TMR1 PW1DCL PIR2 DDRF SSPADD PW3DCL

11h

DDRB PORTC TMR2 PW2DCL PIE2 PORTF SSPCON1 PW3DCH

12h

PORTB DDRD TMR3L PW1DCH

—

DDRG SSPCON2 CA3L

13h

RCSTA1 PORTD TMR3H PW2DCH RCSTA2 PORTG SSPSTAT CA3H

14h

RCREG1 DDRE PR1 CA2L RCREG2 ADCON0 SSPBUF CA4L

15h

TXSTA1 PORTE PR2 CA2H TXSTA2 ADCON1

—

CA4H

16h

TXREG1 PIR1 PR3L/CA1L TCON1 TXREG2 ADRESL

—

TCON3

17h

SPBRG1 PIE1 PR3H/CA1H TCON2 SPBRG2 ADRESH

— —

Unbanked

18h

PRODL

19h

PRODH

1Ah 1Fh

General

Purpose

RAM

Bank 0

(2)

Bank 1

(2)

Bank 2

(2, 3)

Bank 3

(2, 3)

20h

FFh

General

Purpose

RAM

General Purpose

RAM

General

Purpose

RAM

General Purpose

RAM

Note 1: SFR ﬁle locations 10h - 17h are banked. The lower nibble of the BSR speciﬁes the bank. All

unbanked SFRs ignore the Bank Select Register (BSR) bits.

2: General Purpose Registers (GPR) locations 20h - FFh, 120h - 1FFh, 220h - 2FFh, and 320h - 3FFh

are banked. The upper nibble of the BSR speciﬁes this bank. All other GPRs ignore the Bank Select Register (BSR) bits.

3: These RAM banks are not implemented on the PIC17C752. Reading any register in this bank reads

‘0’s

PIC17C75X

DS30264A-page 44 Preliminary  1997 Microchip Technology Inc.

TABLE 7-3: SPECIAL FUNCTION REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on

all other

resets (3)

Unbanked

00h INDF0 Uses contents of FSR0 to address data memory (not a physical register) ---- ---- ---- ---01h FSR0 Indirect data memory address pointer 0 xxxx xxxx uuuu uuuu 02h PCL Low order 8-bits of PC 0000 0000 0000 0000

03h

(1)

PCLATH Holding register for upper 8-bits of PC

0000 0000 uuuu uuuu

04h ALUSTA FS3 FS2 FS1 FS0 OV Z DC C 1111 xxxx 1111 uuuu 05h T0STA INTEDG T0SE T0CS T0PS3 T0PS2 T0PS1 T0PS0

— 0000 000- 0000 000-

06h

(2)

CPUSTA

— — STKAV GLINTD TO PD POR BOR --11 1100 --11 qquu

07h INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000 08h INDF1 Uses contents of FSR1 to address data memory (not a physical register) ---- ---- ---- ---09h FSR1 Indirect data memory address pointer 1 xxxx xxxx uuuu uuuu 0Ah WREG Working register xxxx xxxx uuuu uuuu 0Bh TMR0L TMR0 register; low byte xxxx xxxx uuuu uuuu 0Ch TMR0H TMR0 register; high byte xxxx xxxx uuuu uuuu 0Dh TBLPTRL Low byte of program memory table pointer 0000 0000 0000 0000 0Eh TBLPTRH High byte of program memory table pointer 0000 0000 0000 0000 0Fh BSR Bank select register 0000 0000 0000 0000

Bank 0

10h

PORTA RBPU

—

RA5/TX1/

CK1

RA4/RX1/

DT1

RA3/SDI/

SDA

RA2/SS

SCL

RA1/T0CKI RA0/INT 0-xx xxxx 0-uu uuuu 11h DDRB Data direction register for PORTB 1111 1111 1111 1111 12h PORTB

RB7/ SDO

RB6/

SCK

RB5/

TCLK3

RB4/

TCLK12

RB3/

PWM2

RB2/

PWM1

RB1/

CAP2

RB0/

CAP1

xxxx xxxx uuuu uuuu

13h RCSTA1 SPEN RX9 SREN CREN

— FERR OERR RX9D 0000 -00x 0000 -00u 14h RCREG1 Serial port receive register xxxx xxxx uuuu uuuu 15h TXSTA1 CSRC TX9 TXEN SYNC

— — TRMT TX9D 0000 --1x 0000 --1u 16h TXREG1 Serial Port Transmit Register (for USART1) xxxx xxxx uuuu uuuu 17h SPBRG1 Baud Rate Generator Register (for USART1) xxxx xxxx uuuu uuuu

Bank 1

10h DDRC Data direction register for PORTC 1111 1111 1111 1111 11h PORTC

RC7/

AD7

RC6/

AD6

RC5/

AD5

RC4/

AD4

RC3/

AD3

RC2/

AD2

RC1/

AD1

RC0/

AD0

xxxx xxxx uuuu uuuu

12h DDRD Data direction register for PORTD 1111 1111 1111 1111 13h PORTD

RD7/ AD15

RD6/

AD14

RD5/

AD13

RD4/

AD12

RD3/

AD11

RD2/

AD10

RD1/

AD9

RD0/

AD8

xxxx xxxx uuuu uuuu

14h DDRE Data direction register for PORTE ---- 1111 ---- 1111 15h

PORTE

— — — —

RE3/

CAP4

RE2/WR

RE1/OE RE0/ALE ---- xxxx ---- uuuu

16h PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010 17h PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q - value depends on condition. Shaded cells are unimplemented, read as '0'. Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose contents are updated

from or transferred to the upper byte of the program counter.

2: The T

O and PD status bits in CPUSTA are not affected by a MCLR reset.

3: Other (non power-up) resets include: external reset through MCLR

and Watchdog Timer Reset.

 1997 Microchip Technology Inc. Preliminary DS30264A-page 45

PIC17C75X

Bank 2

10h TMR1 Timer1’s register xxxx xxxx uuuu uuuu 11h TMR2 Timer2’s register xxxx xxxx uuuu uuuu 12h TMR3L Timer3’s register; low byte xxxx xxxx uuuu uuuu 13h TMR3H Timer3’s register; high byte xxxx xxxx uuuu uuuu 14h PR1 Timer1’s period register xxxx xxxx uuuu uuuu 15h PR2 Timer2’s period register xxxx xxxx uuuu uuuu 16h PR3L/CA1L Timer3’s period register - low byte/capture1 register; low byte xxxx xxxx uuuu uuuu 17h PR3H/CA1H Timer3’s period register - high byte/capture1 register; high byte xxxx xxxx uuuu uuuu

Bank 3

10h PW1DCL DC1 DC0

— — — — — — xx-- ---- uu-- ----

11h PW2DCL DC1 DC0 TM2PW2

— — — — — xx0- ---- uu0- ---- 12h PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu 13h PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu 14h CA2L Capture2 low byte xxxx xxxx uuuu uuuu 15h CA2H Capture2 high byte xxxx xxxx uuuu uuuu 16h TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000 17h

TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3

TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000 Bank 4: 10h PIR2 SSPIF BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010 11h PIE2 SSPIE BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000 12h Unimplemented — — — — — — — — ---- ---- ---- ---13h RCSTA2 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u 14h RCREG2 Serial Port Receive Register for USART2 xxxx xxxx uuuu uuuu 15h TXSTA2 CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u 16h TXREG2 Serial Port Transmit Register for USART2 xxxx xxxx uuuu uuuu 17h SPBRG2 Baud Rate Generator for USART2 xxxx xxxx uuuu uuuu Bank 5: 10h DDRF Data Direction Register for PORTF 1111 1111 1111 1111 11h PORTF RF7/

AN11

RF6/

AN10

RF5/

AN9

RF4/

AN8

RF3/

AN7

RF2/ AN6

RF1/ AN5

RF0/ AN4

0000 0000 0000 0000

12h DDRG Data Direction Register for PORTG 1111 1111 1111 1111 13h PORTG RG7/

TX2/CK2

RG6/

RX2/DT2

RG5/

PWM3

RG4/

CAP3

RG3/

AN0

RG2/

AN1

RG1/

AN2

RG0/

AN3

xxxx 0000 uuuu 0000

14h ADCON0 CHS3 CHS2 CHS1 CHS0

— GO/DONE — ADON 0000 -0-0 0000 -0-0 15h ADCON1 ADCS1 ADCS0 ADFM — PCFG3 PCFG2 PCFG1 PCFG0 000- 0000 000- 0000 16h ADRESL A/D Result Register low byte xxxx xxxx uuuu uuuu 17h ADRESH A/D Result Register high byte xxxx xxxx uuuu uuuu

TABLE 7-3: SPECIAL FUNCTION REGISTERS (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on

all other

resets (3)

from or transferred to the upper byte of the program counter.

2: The T

O and PD status bits in CPUSTA are not affected by a MCLR reset.

3: Other (non power-up) resets include: external reset through MCLR

and Watchdog Timer Reset.

PIC17C75X

DS30264A-page 46 Preliminary  1997 Microchip Technology Inc.

Bank 6: 10h SSPADD SSP Address register in I2C slave mode. SSP baud rate reload register in I2C master mode. 0000 0000 0000 0000 11h SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 12h SSPCON2 GCEN AKSTAT AKDT AKEN RCEN PEN RSEN SEN 0000 0000 0000 0000 13h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000 14h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 15h Unimplemented — — — — — — — — ---- ---- ---- ---16h Unimplemented

— — — — — — — — ---- ---- ---- ---17h Unimplemented — — — — — — — — ---- ---- ---- ---Bank 7: 10h PW3DCL DC1 DC0 TM2PW3 - - - - - xx0- ---- uu0- ---11h PW3DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu 12h CA3L Capture3 low byte xxxx xxxx uuuu uuuu 13h CA3H Capture3 high byte xxxx xxxx uuuu uuuu 14h CA4L Capture4 low byte xxxx xxxx uuuu uuuu 15h CA4H Capture4 high byte xxxx xxxx uuuu uuuu 16h TCON3 — CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000 17h Unimplemented — — — — — — — — ---- ---- ---- --- Unbanked

18h

(5)

PRODL Low Byte of 16-bit Product (8 x 8 Hardware Multiply)

xxxx xxxx uuuu uuuu

19h

(5)

PRODH High Byte of 16-bit Product (8 x 8 Hardware Multiply)

xxxx xxxx uuuu uuuu

TABLE 7-3: SPECIAL FUNCTION REGISTERS (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on

all other

resets (3)

from or transferred to the upper byte of the program counter.

2: The T

O and PD status bits in CPUSTA are not affected by a MCLR reset.

3: Other (non power-up) resets include: external reset through MCLR

and Watchdog Timer Reset.

 1997 Microchip Technology Inc. Preliminary DS30264A-page 47

PIC17C75X

7.2.2.1 ALU STATUS REGISTER (ALUSTA) The ALUSTA register contains the status bits of the

Arithmetic and Logic Unit and the mode control bits for the indirect addressing register.

As with all the other registers, the ALUSTA register can be the destination for any instruction. If the ALUSTA register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the ALUSTA register as destination may be different than intended.

For example, CLRF ALUSTA will clear the upper four bits and set the Z bit. This leaves the ALUSTA register as 0000u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions be used to alter the ALUSTA register because these instructions do not

affect any status bit. To see how other instructions affect the status bits, see the “Instruction Set Summary.”

The Arithmetic and Logic Unit (ALU) is capable of carrying out arithmetic or logical operations on two operands or a single operand. All single operand instructions operate either on the WREG register or the given file register. For two operand instructions, one of the operands is the WREG register and the other one is either a ﬁle register or an 8-bit immediate constant.

Note 3: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

Note 4: The overﬂow bit will be set if the 2’s com-

plement result exceeds +127 or is less than -128.

FIGURE 7-6: ALUSTA REGISTER (ADDRESS: 04h, UNBANKED)

R/W - 1 R/W - 1 R/W - 1 R/W - 1 R/W - x R/W - x R/W - x R/W - x

FS3 FS2 FS1 FS0 OV Z DC C

R = Readable bit W = Writable bit

-n = Value at POR reset (x = unknown)

bit7 bit0

bit 7-6: FS3:FS2: FSR1 Mode Select bits

00 = Post auto-decrement FSR1 value 01 = Post auto-increment FSR1 value 1x = FSR1 value does not change

bit 5-4: FS1:FS0: FSR0 Mode Select bits

00 = Post auto-decrement FSR0 value 01 = Post auto-increment FSR0 value 1x = FSR0 value does not change

bit 3: OV: Overﬂow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overﬂow of the 7-bit magnitude, which causes the sign bit (bit7) to change state. 1 =Overﬂow occurred for signed arithmetic, (in this arithmetic operation) 0 =No overﬂow occurred

bit 2: Z: Zero bit

1 =The result of an arithmetic or logic operation is zero 0 =The results of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borro

w bit For ADDWF and ADDLW instructions. 1 =A carry-out from the 4th low order bit of the result occurred 0 =No carry-out from the 4th low order bit of the result Note: For borrow the polarity is reversed.

bit 0: C: carry/borro

w bit For ADDWF and ADDLW instructions. 1 =A carry-out from the most signiﬁcant bit of the result occurred Note that a subtraction is executed by adding the two’s complement of the second operand. For rotate (RRCF, RLCF) instructions, this bit is loaded with either the high or low order bit of the source register. 0 =No carry-out from the most signiﬁcant bit of the result Note: For borrow the polarity is reversed.

PIC17C75X

DS30264A-page 48 Preliminary  1997 Microchip Technology Inc.

7.2.2.2 CPU STATUS REGISTER (CPUSTA) The CPUSTA register contains the status and control

bits for the CPU. This register has a bit that is used to globally enable/disable interrupts. If only a speciﬁc interrupt is desired to be enabled/disabled, please refer to the INTerrupt STAtus (INTSTA) register and the Peripheral Interrupt Enable (PIE) registers. The CPUSTA register also indicates if the stack is available and contains the Power-down (PD

) and Time-out (TO)

bits. The T

O, PD, and STKAV bits are not writable. These bits are set and cleared according to device logic. Therefore, the result of an instruction with the CPUSTA register as destination may be different than intended.

The POR

bit allows the differentiation between a

Power-on Reset, external MCLR

reset, or a WDT

Reset. The BOR

bit indicates if a Brown-out Reset

occured.

Note 1: The BOR status bit is a don’t care and is

not necessarily predictable if the brown-out circuit is disabled (when the BODEN bit in the Conﬁguration word is programmed).

FIGURE 7-7: CPUSTA REGISTER (ADDRESS: 06h, UNBANKED)

U - 0 U - 0 R - 1 R/W - 1 R - 1 R - 1 R/W - 0 R/W - 0

— — STKAV GLINTD TO PD POR BOR

R = Readable bit W = Writable bit U = Unimplemented bit, Read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-6: Unimplemented: Read as '0' bit 5: STKAV: Stack Available bit

This bit indicates that the 4-bit stack pointer value is Fh, or has rolled ov er from Fh → 0h (stac k ov erﬂow). 1 =Stack is available 0 =Stack is full, or a stack overﬂow may have occurred (Once this bit has been cleared by a

stack overﬂow, only a device reset will set this bit)

bit 4: GLINTD: Global Interrupt Disable bit

This bit disables all interrupts. When enabling interrupts, only the sources with their enable bits set can cause an interrupt. 1 =Disable all interrupts 0 =Enables all un-masked interrupts

bit 3: T

O: WDT Time-out Status bit 1 =After power-up or by a CLRWDT instruction 0 =A Watchdog Timer time-out occurred

bit 2: PD

: Power-down Status bit 1 =After power-up or by the CLRWDT instruction 0 =By execution of the SLEEP instruction

bit 1: POR

: Power-on Reset Status bit 1 =No Power-on Reset occurred 0 =A Power-on Reset occurred (must be set by software after a Power-on Reset occurs)

bit 0: BOR

: Brown-out Reset Status bit 1 =No Brown-out Reset occurred 0 =A Brown-out Reset occurred (must be set by software after a Brown-out Reset occurs)

 1997 Microchip Technology Inc. Preliminary DS30264A-page 49

PIC17C75X

7.2.2.3 TMR0 STATUS/CONTROL REGISTER (T0STA)

This register contains various control bits. Bit7 (INTEDG) is used to control the edge upon which a signal on the RA0/INT pin will set the RA0/INT interrupt ﬂag. The other bits conﬁgure the Timer0 prescaler and clock source.

FIGURE 7-8: T0STA REGISTER (ADDRESS: 05h, UNBANKED)

R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 U - 0

INTEDG T0SE T0CS T0PS3 T0PS2 T0PS1 T0PS0

—

R = Readable bit W = Writable bit U = Unimplemented, reads as ‘0’

-n = Value at POR reset

bit7 bit0

bit 7: INTEDG: RA0/INT Pin Interrupt Edge Select bit

This bit selects the edge upon which the interrupt is detected. 1 =Rising edge of RA0/INT pin generates interrupt 0 =Falling edge of RA0/INT pin generates interrupt

bit 6: T0SE: Timer0 Clock Input Edge Select bit

This bit selects the edge upon which TMR0 will increment. When

T0CS = 0 (External Clock) 1 =Rising edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt 0 =Falling edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt When

T0CS = 1 (Internal Clock) Don’t care

bit 5: T0CS: Timer0 Clock Source Select bit

This bit selects the clock source for Timer0. 1 =Internal instruction clock cycle (T

CY)

0 =External clock input on the T0CKI pin

bit 4-1: T0PS3:T0PS0: Timer0 Prescale Selection bits

These bits select the prescale value for Timer0.

bit 0: Unimplemented: Read as '0'

T0PS3:T0PS0 Prescale V alue

0000 0001 0010 0011 0100 0101 0110 0111 1xxx

1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256

PIC17C75X

DS30264A-page 50 Preliminary  1997 Microchip Technology Inc.

7.3 Stack Operation

PIC17C75X devices have a 16 x 16-bit hardw are stack (Figure 7-1). The stac k is not part of either the program or data memory space, and the stack pointer is neither readable nor writable. The PC (Program Counter) is “PUSHed” onto the stack when a CALL or LCALL instruction is executed or an interrupt is acknowledged. The stack is “POP ed” in the e v ent of a RETURN, RETLW, or a RETFIE instruction execution. PCLATH is not affected by a “PUSH” or a “POP” operation.

The stack operates as a circular buffer, with the stack pointer initialized to '0' after all resets. There is a stack available bit (STKAV) to allow software to ensure that the stack has not overﬂowed. The STKAV bit is set after a device reset. When the stack pointer equals Fh, STKAV is cleared. When the stack pointer rolls over from Fh to 0h, the STKAV bit will be held clear until a device reset.

After the device is “PUSHed” sixteen times (without a “POP”), the seventeenth push overwrites the value from the ﬁrst push. The eighteenth push overwrites the second push (and so on).

Note 1: There is not a status bit for stack under-

ﬂow. The STKAV bit can be used to detect the underﬂow which results in the stack pointer being at the top of stack.

Note 2: There are no instruction mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instruc- tions, or the vectoring to an interrupt vector.

Note 3: After a reset, if a “POP” operation occurs

before a “PUSH” oper ation, the STKAV bit will be cleared. This will appear as if the stack is full (underﬂow has occurred). If a “PUSH” operation occurs next (before another “POP”), the STKAV bit will be locked clear. Only a device reset will cause this bit to set.

7.4 Indirect Addressing

Indirect addressing is a mode of addressing data memory where the data memory address in the instruction is not ﬁxed. That is, the register that is to be read or written can be modiﬁed by the program. This can be useful for data tables in the data memory. Figure 7-9 shows the operation of indirect addressing. This shows the moving of the value to the data memory address speciﬁed by the value of the FSR register.

Example 7-1 shows the use of indirect addressing to clear RAM in a minimum number of instructions. A similar concept could be used to move a deﬁned number of bytes (block) of data to the USART transmit register (TXREG). The starting address of the block of data to be transmitted could easily be modiﬁed by the program.

FIGURE 7-9: INDIRECT ADDRESSING

Opcode Address

File = INDFx

FSR

Instruction Executed

Instruction Fetched

RAM

Opcode

File

 1997 Microchip Technology Inc. Preliminary DS30264A-page 51

PIC17C75X

7.4.1 INDIRECT ADDRESSING REGISTERS The PIC17C75X has four registers for indirect

addressing. These registers are:

• INDF0 and FSR0

• INDF1 and FSR1 Registers INDF0 and INDF1 are not physically imple-

mented. Reading or writing to these registers activates indirect addressing, with the value in the corresponding FSR register being the address of the data. The FSR is an 8-bit register and allows addressing anywhere in the 256-byte data memory address range. For banked memory, the bank of memor y accessed is speciﬁed by the value in the BSR.

If ﬁle INDF0 (or INDF1) itself is read indirectly via an FSR, all '0's are read (Zero bit is set). Similarly, if INDF0 (or INDF1) is written to indirectly, the operation will be equivalent to a NOP, and the status bits are not affected.

7.4.2 INDIRECT ADDRESSING OPERATION The indirect addressing capability has been enhanced

over that of the PIC16CXX family. There are two control bits associated with each FSR register. These two bits conﬁgure the FSR register to:

• Auto-decrement the value (address) in the FSR after an indirect access

• Auto-increment the value (address) in the FSR after an indirect access

• No change to the value (address) in the FSR after an indirect access

These control bits are located in the ALUSTA register. The FSR1 register is controlled by the FS3:FS2 bits and FSR0 is controlled by the FS1:FS0 bits.

When using the auto-increment or auto-decrement features, the effect on the FSR is not reﬂected in the ALUSTA register. For example, if the indirect address causes the FSR to equal '0', the Z bit will not be set.

If the FSR register contains a value of 0h, an indirect read will read 0h (Zero bit is set) while an indirect write will be equivalent to a NOP (status bits are not affected).

Indirect addressing allows single cycle data transfers within the entire data space. This is possible with the use of the MOVPF and MOVFP instructions, where either 'p' or 'f' is speciﬁed as INDF0 (or INDF1).

If the source or destination of the indirect address is in banked memory, the location accessed will be determined by the value in the BSR.

A simple program to clear RAM from 20h - FFh is shown in Example 7-1.

EXAMPLE 7-1: INDIRECT ADDRESSING

7.5 T

able Pointer (TBLPTRL and

TBLPTRH)

File registers TBLPTRL and TBLPTRH form a 16-bit pointer to address the 64K program memory space. The table pointer is used by instructions TABLWT and TABLRD.

The TABLRD and the TABLWT instructions allow transfer of data between program and data space. The table pointer serves as the 16-bit address of the data word within the program memory. For a more complete description of these registers and the operation of Table Reads and Table Writes, see Section 8.0.

7.6 Table Latch (TBLATH, TBLATL)

The table latch (TBLAT) is a 16-bit register, with TBLATH and TBLATL referring to the high and low bytes of the register. It is not mapped into data or program memory. The table latch is used as a temporary holding latch during data transfer between program and data memory (see TABLRD, TABLWT, TLRD and TLWT instruction descriptions). For a more complete description of these registers and the operation of Table Reads and Table Writes, see Section 8.0.

MOVLW 0x20 ; MOVWF FSR0 ; FSR0 = 20h BCF ALUSTA, FS1 ; Increment FSR BSF ALUSTA, FS0 ; after access BCF ALUSTA, C ; C = 0 MOVLW END_RAM + 1 ; LP CLRF INDF0 ; Addr(FSR) = 0 CPFSEQ FSR0 ; FSR0 = END_RAM+1? GOTO LP ; NO, clear next : ; YES, All RAM is : ; cleared

PIC17C75X

DS30264A-page 52 Preliminary  1997 Microchip Technology Inc.

7.7 Program Counter Module

The Program Counter (PC) is a 16-bit register. PCL, the low byte of the PC, is mapped in the data memory. PCL is readable and writable just as is any other register. PCH is the high byte of the PC and is not directly addressable. Since PCH is not mapped in data or program memory, an 8-bit register PCLATH (PC high latch) is used as a holding latch for the high byte of the PC. PCLATH is mapped into data memor y. The user can read or write PCH through PCLATH.

The 16-bit wide PC is incremented after each instruction fetch during Q1 unless:

• Modiﬁed by a GOTO, CALL, LCALL, RETURN, RETLW, or RETFIE instruction

• Modiﬁed by an interrupt response

• Due to destination write to PCL by an instruction

“Skips” are equivalent to a forced NOP cycle at the skipped address.

Figure 7-10 and Figure 7-11 show the operation of the program counter for various situations.

FIGURE 7-10: PROGRAM COUNTER

OPERATION

FIGURE 7-11: PROGRAM COUNTER USING

THE CALL AND GOTO INSTRUCTIONS

Internal data bus <8>

PCLATH

PCH PCL

15 0

12 8 7 0

PC<15:13>

PCLATH

Opcode

PCH

PCL

1315

Using Figure 7-10, the operations of the PC and PCLATH for different instructions are as follows:

a) LCALL

instructions:

An 8-bit destination address is provided in the instruction (opcode). PCLATH is unchanged.

PCLATH → PCH Opcode<7:0> → PCL

b) Read instr

uctions on PCL: Any instruction that reads PCL. PCL → data bus → ALU or destination PCH → PCLATH

c) Wr

ite instructions on PCL: Any instruction that writes to PCL. 8-bit data → data bus → PCL PCLATH → PCH

d) Read-Modify-Wr

ite instructions on PCL:

Any instruction that does a read-write-modify operation on PCL, such as ADDWF PCL.

Read: PCL → data bus → ALU Write: 8-bit result → data bus → PCL

PCLATH → PCH

e) RETURN

instruction:

Stack<MRU> → PC<15:0>

Using Figure 7-11, the operation of the PC and PCLATH for GOTO and CALL instructions is as follows:

CALL, GOTO instructions: A 13-bit destination address is provided in the

instruction (opcode). Opcode<12:0> → PC<12:0> PC<15:13> → PCLATH<7:5> Opcode<12:8> → PCLATH<4:0>

The read-modify-write only affects the PCL with the result. PCH is loaded with the value in the PCLATH. For example, ADDWF PCL will result in a jump within the current page. If PC = 03F0h, WREG = 30h and PCLATH = 03h before instruction, PC = 0320h after the instruction. To accomplish a true 16-bit computed jump, the user needs to compute the 16-bit destination address, write the high byte to PCLATH and then write the low value to PCL.

The following PC related operations do not change PCLATH:

a) LCALL, RETLW, and RETFIE instructions. b) Interrupt vector is forced onto the PC. c) Read-modify-write instructions on PCL (e.g.

BSF PCL).

 1997 Microchip Technology Inc. Preliminary DS30264A-page 53

PIC17C75X

7.8 Bank Select Register (BSR)

The BSR is used to switch between banks in the data memory area (Figure 7-12). In the PIC17C752, and PIC17C756 devices, the entire byte is implemented. The lower nibble is used to select the peripheral register bank. The upper nibble is used to select the general purpose memory bank.

All the Special Function Registers (SFRs) are mapped into the data memory space. In order to accommodate the large number of registers, a banking scheme has been used. A segment of the SFRs, from address 10h to address 17h, is banked. The low er nibble of the bank select register (BSR) selects the currently active “peripheral bank.” Effort has been made to group the peripheral registers of related functionality in one bank. However, it will still be necessar y to switch from bank to bank in order to address all peripherals related to a single task. To assist this, a MOVLB bank instruction has been included in the instruction set.

The need for a large general purpose memory space dictated a general purpose RAM banking scheme. The upper nibble of the BSR selects the currently active general purpose RAM bank. To assist this, a MOVLR bank instruction has been provided in the instruction set.

If the currently selected bank is not implemented (such as Bank 13), any read will read all '0's. Any write is completed to the bit bucket and the ALU status bits will be set/cleared as appropriate.

Note: Registers in Bank 15 in the Special Func-

tion Register area, are reserved for Microchip use. Reading of registers in this bank may cause random values to be read.

FIGURE 7-12: BSR OPERATION

7430

10h 17h

BSR

0 123 8 15

• • •

20h FFh

• • •

(1)

(2)

Bank 15Bank 8

Bank 3Bank 2Bank 1Bank 0

012

Bank 2Bank 1Bank 0

Bank 15

SFR Banks

GPR Banks

Address Range

Note 1: Only Banks 0 through 7 are implemented. Selection of an unimplemented bank is not recommended.

Bank 15 is reserved for Microchip use, reading of registers in this bank may cause random values to be read.

2: Bank 0 and Bank 1 are implemented for the PIC17C752, and Banks 0 through 3 are implemented for the PIC17C756.

Selection of an unimplemented bank is not recommended.

Bank 3

Bank 4

4 56 7

Bank 7Bank 6Bank 5Bank 4

(Peripheral)

(RAM)

PIC17C75X

DS30264A-page 54 Preliminary  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. Preliminary DS30264A-page 55

PIC17C75X

8.0 TABLE READS AND TABLE WRITES

The PIC17C75X has four instructions that allow the processor to move data from the data memory space to the program memory space, and vice versa. Since the program memory space is 16-bits wide and the data memory space is 8-bits wide, two operations are required to move 16-bit values to/from the data memory.

The TLWT t,f and TABLWT t,i,f instructions are used to write data from the data memory space to the program memory space. The TLRD t,f and TABLRD t,i,f instructions are used to write data from the program memory space to the data memory space.

The program memory can be internal or external. For the program memory access to be external, the device needs to be operating in extended microcontroller or microprocessor mode.

Figure 8-1 through Figure 8-4 show the operation of these four instructions.

FIGURE 8-1: TLWT INSTRUCTION

OPERATION

TABLE POINTER

TABLE LATCH (16-bit)

PROGRAM MEMORY

DATA

MEMORY

TBLPTRH

TBLPTRL

TABLATH TABLATL

TLWT 1,f TLWT 0,f

Note 1: 8-bit value, from register 'f', loaded into the

high or low byte in TABLAT (16-bit).

FIGURE 8-2: TABLWT INSTRUCTION

OPERATION

TABLE POINTER

TABLE LATCH (16-bit)

PROGRAM MEMORY

DATA

MEMORY

TBLPTRH

TBLPTRL

TABLATH TABLATL

TABLWT 1,i,f TABLWT 0,i,f

Prog-Mem (TBLPTR)

Note 1: 8-bit value, from register 'f', loaded into the

high or low byte in TABLAT (16-bit).

2: 16-bit TABLAT value written to address

Program Memory (TBLPTR).

3: If “i” = 1, then TBLPTR = TBLPTR + 1,

If “i” = 0, then TBLPTR is unchanged.

PIC17C75X

DS30264A-page 56 Preliminary  1997 Microchip Technology Inc.

FIGURE 8-3: TLRD INSTRUCTION

OPERATION

TABLE POINTER

TABLE LATCH (16-bit)

PROGRAM MEMORY

DATA

MEMORY

TBLPTRH TBLPTRL

TABLATH TABLATL

TLRD 1,f

TLRD 0,f

Note 1: 8-bit value, from TABLAT (16-bit) high or

low byte, loaded into register 'f'.

FIGURE 8-4: TABLRD INSTRUCTION

OPERATION

TABLE POINTER

TABLE LATCH (16-bit)

PROGRAM MEMORY

DATA

MEMORY

TBLPTRH

TBLPTRL

TABLATH TABLATL

TABLRD 1,i,f

TABLRD 0,i,f

Prog-Mem (TBLPTR)

Note 1: 8-bit value, from TABLAT (16-bit) high or

low byte, loaded into register 'f'.

2: 16-bit value at Program Memory (TBLPTR)

loaded into TABLAT register.

3: If “i” = 1, then TBLPTR = TBLPTR + 1,

If “i” = 0, then TBLPTR is unchanged.

 1997 Microchip Technology Inc. Preliminary DS30264A-page 57

PIC17C75X

8.1 Table Writes to Internal Memory

A table write operation to internal memory causes a long write operation. The long write is necessary for programming the internal EPROM. Instruction execution is halted while in a long write cycle. The long write will be terminated by any enabled interrupt. To ensure that the EPROM location has been well programmed, a minimum programming time is required (see speciﬁcation #D114). Having only one interrupt enabled to terminate the long write ensures that no unintentional interrupts will prematurely terminate the long write.

The sequence of events for programming an internal program memory location should be:

1. Disable all interrupt sources, except the source

to terminate EPROM program write.

2. Raise MCLR

/VPP pin to the programming volt-

age.

3. Clear the WDT.

4. Do the table write. The interrupt will terminate

the long write.

5. Verify the memory location (table read).

Note 1: Programming requirements must be

met. See timing speciﬁcation in electrical speciﬁcations for the desired device. Violating these speciﬁcations (including temperature) may result in EPROM locations that are not fully programmed and may lose their state over time.

Note 2: If the V

PP requirement is not met, the

table write is a 2 cycle write and the program memory is unchanged.

8.1.1 TERMINATING LONG WRITES An interrupt source or reset are the only events that

terminate a long write operation. Terminating the long write from an interrupt source requires that the interrupt enable and ﬂag bits are set. The GLINTD bit only enables the vectoring to the interrupt address.

If the T0CKI, RA0/INT, or TMR0 interrupt source is used to terminate the long write; the interrupt ﬂag, of the highest priority enabled interrupt, will terminate the long write and automatically be cleared.

If a peripheral interrupt source is used to terminate the long write, the interrupt enable and ﬂag bits must be set. The interrupt ﬂag will not be automatically cleared upon the vectoring to the interrupt vector address.

The GLINTD bit determines whether the program will branch to the interrupt vector when the long write is terminated. If GLINTD is clear, the program will vector, if GLINTD is set, the program will not vector to the interrupt address.

Note 1: If an interrupt is pending, the TABLWT is

aborted (an NOP is executed). The highest priority pending interrupt, from the T0CKI, RA0/INT, or TMR0 sources that is enabled, has its ﬂag cleared.

Note 2: If the interrupt is not being used for the

program write timing, the interrupt should be disabled. This will ensure that the interrupt is not lost, nor will it terminate the long write prematurely.

TABLE 8-1: INTERRUPT - TABLE WRITE INTERACTION

Interrupt

Source

GLINTD

Enable

Bit

Flag

Bit

Action

RA0/INT , TMR0, T0CKI

0 1 1

1 0 1

0 x 1

Terminate long table write (to internal program memory), branch to interrupt vector (branch clears ﬂag bit). None None Terminate table write, do not branch to interrupt vector (ﬂag is automatically cleared).

Peripheral 0

0 1 1

1 1 0 1

1 0 x 1

Terminate table write, branch to interrupt vector. None None Terminate table write, do not branch to interrupt vector (ﬂag remains set).

PIC17C75X

DS30264A-page 58 Preliminary  1997 Microchip Technology Inc.

8.2 Table Writes to External Memory

Table writes to external memor y are always two-cycle instructions. The second cycle writes the data to the external memory location. The sequence of events for an external memory write are the same for an internal write.

Note: If an interrupt is pending or occurs during

the TABLWT, the two cycle table write completes. The RA0/INT, TMR0, or T0CKI interrupt ﬂag is automatically cleared or the pending peripheral interrupt is acknowledged.

8.2.2 TABLE WRITE CODE The “i” operand of the TABLWT instruction can specify

that the value in the 16-bit TBLPTR register is automatically incremented (for the next write). In Example 8-1, the TBLPTR register is not automatically incremented.

EXAMPLE 8-1: TABLE WRITE

CLRWDT ; Clear WDT MOVLW HIGH (TBL_ADDR) ; Load the Table MOVWF TBLPTRH ; address MOVLW LOW (TBL_ADDR) ; MOVWF TBLPTRL ; MOVLW HIGH (DATA) ; Load HI byte TLWT 1, WREG ; in TABLATH MOVLW LOW (DATA) ; Load LO byte TABLWT 0,0,WREG ; in TABLATH ; and write to ; program memory ; (Ext. SRAM)

FIGURE 8-5: TABLWT WRITE TIMING (EXTERNAL MEMORY)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

AD15:AD0

Instruction fetched

Instruction executed

ALE

TABLWT

INST (PC+1)

INST (PC-1)

TABLWT cycle1 TABLWT cycle2

INST (PC+2)

Data write cycle

'1'

PC PC+1 TBL PC+2Data out

INST (PC+1)

Note: If external write, and GLINTD = '1', and Enable bit = '1', then when '1' → Flag bit, Do table write.

The highest pending interrupt is cleared.

 1997 Microchip Technology Inc. Preliminary DS30264A-page 59

PIC17C75X

FIGURE 8-6: CONSECUTIVE TABLWT WRITE TIMING (EXTERNAL MEMORY)

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

AD15:AD0

Instruction fetched

Instruction executed

ALE

TABLWT1 TABLWT2 INST (PC+2)

INST (PC-1)

TABLWT1 cycle1

TABLWT1 cycle2 TABLWT2 cycle1

TABLWT2 cycle2

Data write cycle

INST (PC+3)

PC+1

TBL1

PC+2

TBL2

PC+3

Data out 1 Data out 2

INST (PC+2)

PIC17C75X

DS30264A-page 60 Preliminary  1997 Microchip Technology Inc.

8.3 Table Reads

The table read allows the program memory to be read. This allows constants to be stored in the program memory space, and retrieved into data memory when needed. Example 8-2 reads the 16-bit value at program memory address TBLPTR. After the dummy byte has been read from the TABLATH, the TABLATH is loaded with the 16-bit data from program memory address TBLPTR + 1. The ﬁrst read loads the data into the latch, and can be considered a dummy read (unknown data loaded into 'f'). INDF0 should be conﬁgured for either auto-increment or auto-decrement.

EXAMPLE 8-2: TABLE READ

MOVLW HIGH (TBL_ADDR) ; Load the Table MOVWF TBLPTRH ; address MOVLW LOW (TBL_ADDR) ; MOVWF TBLPTRL ; TABLRD 0,0,DUMMY ; Dummy read, ; Updates TABLATH TLRD 1, INDF0 ; Read HI byte ; of TABLATH TABLRD 0,1,INDF0 ; Read LO byte ; of TABLATH and ; Update TABLATH

FIGURE 8-7: TABLRD TIMING

FIGURE 8-8: TABLRD TIMING (CONSECUTIVE TABLRD INSTRUCTIONS)

Q1 Q2

AD15:AD0

Instruction fetched

Instruction executed

ALE

TABLRD INST (PC+1)

INST (PC+2)

INST (PC-1)

TABLRD cycle1

TABLRD cycle2 INST (PC+1) Data read cycle

PC PC+1 TBL Data in

PC+2

'1'

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

AD15:AD0

Instruction fetched

Instruction executed

TABLRD1

TABLRD2

INST (PC+2) INST (PC+3)

INST (PC+2)

ALE

INST (PC-1) TABLRD1 cycle1 TABLRD1 cycle2 TABLRD2 cycle1

TABLRD2 cycle2

Data read cycle Data read cycle

'1'

PC+1

PC+2

PC+3

TBL1

Data in 1

TBL2 Data in 2

 1997 Microchip Technology Inc. Preliminary DS30264A-page 61

PIC17C75X

9.0 HARDWARE MULTIPLIER

All PIC17C75X devices have an 8 x 8 hardware multiplier included in the ALU of the device. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that giv es a 16-bit result. The result is stored into the 16-bit PRODuct register (PRODH:PRODL). The multiplier does not affect any ﬂags in the ALUSTA register.

Making the 8 x 8 multiplier execute in a single cycle gives the following advantages:

• Higher computational throughput

• Reduces code size requirements for multiply algo-

rithms

The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors.

Table 9-1 shows a performance comparison between PIC17CXXX devices using the single cycle hardware multiply, and performing the same function without the hardware multiply.

Example 9-1 shows the sequence to do an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register.

Example 9-2 shows the sequence to do an 8 x 8 signed multiply. To account for the sign bits of the arguments, each argument’s most signiﬁcant bit (MSb) is tested and the appropriate subtractions are done.

EXAMPLE 9-1: 8 x 8 UNSIGNED MULTIPLY

ROUTINE

EXAMPLE 9-2: 8 x 8 SIGNED MULTIPLY

ROUTINE

MOVFP ARG1, WREG ; MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL

MOVFP ARG1, WREG MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL BTFSC ARG2, SB ; Test Sign Bit SUBWF PRODH, F ; PRODH = PRODH ; - ARG1 MOVFP ARG2, WREG BTFSC ARG1, SB ; Test Sign Bit SUBWF PRODH, F ; PRODH = PRODH ; - ARG2

TABLE 9-1: PERFORMANCE COMPARISON

Routine Multiply Method

Program Memory

(Words)

Cycles (Max)

Time

@ 33 MHz

8 x 8 unsigned Without hardware multiply 13 69 8.364 µs

Hardware multiply 1 1 0.121 µs

8 x 8 signed Without hardware multiply — — —

Hardware multiply 6 6 0.727 µs

16 x 16 unsigned Without hardware multiply 21 242 29.333 µs

Hardware multiply 24 24 2.91 µs

16 x 16 signed Without hardware multiply 52 254 30.788 µs

Hardware multiply 36 36 4.36 µs

PIC17C75X

DS30264A-page 62 Preliminary  1997 Microchip Technology Inc.

Example 9-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in 4 registers RES3:RES0.

EQUATION 9-1: 16 x 16 UNSIGNED

MULTIPLICATION ALGORITHM

RES3:RES0 = ARG1H:ARG1L • ARG2H:ARG2L

= (ARG1H • ARG2H • 2

(ARG1H • ARG2L • 2

(ARG1L • ARG2H • 2

(ARG1L • ARG2L)

EXAMPLE 9-3: 16 x 16 UNSIGNED

MULTIPLY ROUTINE

 1997 Microchip Technology Inc. Preliminary DS30264A-page 63

PIC17C75X

Example 9-4 shows the sequence to do an 16 x 16 signed multiply. Equation 9-2 shows the algorithm used. The 32-bit result is stored in four registers RES3:RES0. To account for the sign bits of the arguments, each argument pairs most signiﬁcant bit (MSb) is tested and the appropriate subtractions are done.

EQUATION 9-2: 16 x 16 SIGNED

MULTIPLICATION ALGORITHM

RES3:RES0

= ARG1H:ARG1L • ARG2H:ARG2L = (ARG1H • ARG2H • 2

(ARG1H • ARG2L • 2

(ARG1L • ARG2H • 2

(ARG1L • ARG2L) + (-1 • ARG2H<7> • ARG1H:ARG1L • 2

(-1 • ARG1H<7> • ARG2H:ARG2L • 2

)

EXAMPLE 9-4: 16 x 16 SIGNED MULTIPLY

ROUTINE

MOVFP ARG1L, WREG MULWF ARG2L ; ARG1L * ARG2L -> ; PRODH:PRODL MOVPF PRODH, RES1 ; MOVPF PRODL, RES0 ; ; MOVFP ARG1H, WREG MULWF ARG2H ; ARG1H * ARG2H -> ; PRODH:PRODL MOVPF PRODH, RES3 ; MOVPF PRODL, RES2 ; ; MOVFP ARG1L, WREG MULWF ARG2H ; ARG1L * ARG2H -> ; PRODH:PRODL MOVFP PRODL, WREG ; ADDWF RES1, F ; Add cross MOVFP PRODH, WREG ; products ADDWFC RES2, F ; CLRF WREG, F ; ADDWFC RES3, F ; ; MOVFP ARG1H, WREG ; MULWF ARG2L ; ARG1H * ARG2L -> ; PRODH:PRODL MOVFP PRODL, WREG ; ADDWF RES1, F ; Add cross MOVFP PRODH, WREG ; products ADDWFC RES2, F ; CLRF WREG, F ; ADDWFC RES3, F ; ; BTFSS ARG2H, 7 ; ARG2H:ARG2L neg? GOTO SIGN_ARG1 ; no, check ARG1 MOVFP ARG1L, WREG ; SUBWF RES2 ; MOVFP ARG1H, WREG ; SUBWFB RES3 ; SIGN_ARG1 BTFSS ARG1H, 7 ; ARG1H:ARG1L neg? GOTO CONT_CODE ; no, done MOVFP ARG2L, WREG ; SUBWF RES2 ; MOVFP ARG2H, WREG ; SUBWFB RES3 ; CONT_CODE :

PIC17C75X

DS30264A-page 64 Preliminary  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. Preliminary DS30264A-page 65

PIC17C75X

10.0 I/O PORTS

PIC17C75X devices have seven I/O ports, PORTA through PORTG. PORTB through PORTG have a corresponding Data Direction Register (DDR), which is used to conﬁgure the port pins as inputs or outputs. These seven ports are made up of 50 I/O pins. Some of these ports pins are multiplexed with alternate functions.

PORTC, PORTD, and PORTE are multiplexed with the system bus. These pins are conﬁgured as the system bus when the device’ s conﬁguration bits are selected to Microprocessor or Extended Microcontroller modes. In the two other microcontroller modes, these pins are general purpose I/O.

PORTA, PORTB, PORTE<3>, PORTF and PORTG are multiplexed with the peripheral features of the device. These peripheral features are:

• Timer modules

• Capture modules

• PWM modules

• USART/SCI modules

• SSP Module

• A/D Module

• External Interrupt pin

When some of these peripheral modules are turned on, the port pin will automatically conﬁgure to the alternate function. The modules that do this are:

• PWM module

• SSP module

• USART/SCI module

When a pin is automatically conﬁgured as an output by a peripheral module, the pins data direction (DDR) bit is unknown. After disabling the peripheral module, the user should re-initialize the DDR bit to the desired conﬁguration.

The other peripheral modules (which require an input) must have their data direction bit conﬁgured appropriately.

Note: A pin that is a peripheral input, can be con-

ﬁgured as an output (DDRx<y> is cleared). The peripheral events will be determined by the action output on the port pin.

10.1 PORTA Register

PORTA is a 6-bit wide latch. PORTA does not have a corresponding Data Direction Register (DDR).

Reading PORTA reads the status of the pins. The RA1 pin is multiplexed with TMR0 clock input, RA2

and RA3 are multiplexed with the SSP functions, and RA4 and RA5 are multiplexed with the USART1 functions. The control of RA2, RA3, RA4 and RA5 as outputs are automatically conﬁgured by the their multiplexed peripheral module.

10.1.1 USING RA2, RA3 AS OUTPUTS The RA2 and RA3 pins are open drain outputs. To use

the RA2 and/or the RA3 pin(s) as output(s), simply write to the PORTA register the desired value. A '0' will cause the pin to drive low, while a '1' will cause the pin to ﬂoat (hi-impedance). An external pull-up resistor should be used to pull the pin high. Writes to the RA2 and RA3 pins will not affect the other PORTA pins.

FIGURE 10-1: RA0 AND RA1 BLOCK

DIAGRAM

Note: When using the RA2 or RA3 pin(s) as out-

put(s), read-modify-write instructions (such as BCF , BSF , BTG) on PORTA are not recommended. Such operations read the port pins, do the desired operation, and then write this value to the data latch. This may inadvertently cause the RA2 or RA3 pins to switch from input to output (or vice-versa). To avoid this possibility use a shadow register for PORTA. Do the bit operations on this shadow register and then move it to PORTA.

Note: I/O pins have protection diodes to VDD and VSS.

DATA BUS

RD_PORTA

(Q2)

PIC17C75X

DS30264A-page 66 Preliminary  1997 Microchip Technology Inc.

Example 10-1 shows an instruction sequence to initialize PORTA. The Bank Select Register (BSR) must be selected to Bank 0 for the port to be initialized. The following example uses the MOVLB instruction to load the BSR register for bank selection.

EXAMPLE 10-1: INITIALIZING PORTA

FIGURE 10-2: RA2 BLOCK DIAGRAM

MOVLB 0 ; Select Bank 0 MOVLW 0xF3 ; MOVPF PORTA ; Initialize PORTA ; RA<3:2> are output low ; RA<5:4> and RA<1:0> ; are inputs ; (outputs floating)

Note: I/O pin has protection diodes to VSS.

Data Bus

WR_PORTA

(Q4)

RD_PORTA

(Q2)

Peripheral data in

I2C Mode enable

CL out

FIGURE 10-3: RA3 BLOCK DIAGRAM

FIGURE 10-4: RA4 AND RA5 BLOCK

DIAGRAM

Note: I/O pin has protection diodes to VSS.

Data Bus

WR_PORTA

(Q4)

RD_PORTA

(Q2)

Peripheral data in

SDA out

SSP Mode

“1”

Note: I/O pins have protection diodes to VDD and VSS.

Data Bus

RD_PORTA

(Q2)

Serial port output signals

Serial port input signal

= SPEN,SYNC,TXEN, CREN, SREN for RA4

= SPEN (SYNC+SYNC,CSRC) for RA5

 1997 Microchip Technology Inc. Preliminary DS30264A-page 67

PIC17C75X

TABLE 10-1: PORTA FUNCTIONS

TABLE 10-2: REGISTERS/BITS ASSOCIATED WITH PORTA

Name Bit0

Buffer

Type

Function

RA0/INT bit0 ST Input or external interrupt input. RA1/T0CKI bit1 ST Input or clock input to the TMR0 timer/counter, and/or an external interrupt

input.

RA2/SS

/SCL bit2 ST Input/Output or slave select input for the SPI or clock input for the I2C bus.

Output is open drain type.

RA3/SDI/SDA bit3 ST

Input/Output or data input for the SPI or data for the I

C bus.

Output is open drain type.

RA4/RX1/DT1 bit4 ST Input/Output or USART1 Asynchronous Receive or

USART1 Synchronous Data.

RA5/TX1/CK1 bit5 ST Input/Output or USART1 Asynchronous Transmit or

USART1 Synchronous Clock.

RBPU

bit7 — Control bit for PORTB weak pull-ups.

Legend: ST = Schmitt Trigger input.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on

all other

resets

(Note1)

10h, Bank 0 PORTA

RBPU —

RA5/

TX1/CK1

RA4/

RX1/DT1

RA3/

SDI/SDA

RA2/

/SCL

RA1/T0CKI RA0/INT

0-xx xxxx 0-uu uuuu

05h, Unbanked T0STA INTEDG T0SE

T0CS PS3 PS2 PS1 PS0 — 0000 000- 0000 000-

13h, Bank 0 RCSTA1 SPEN

RC9 SREN CREN — FERR OERR RC9D 0000 -00x 0000 -00u

15h, Bank 0 TXSTA1 CSRC

TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u

Legend: x = unknown, u = unchanged, - = unimplemented reads as '0'. Shaded cells are not used by PORTA. Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

PIC17C75X

DS30264A-page 68 Preliminary  1997 Microchip Technology Inc.

10.2 PORTB and DDRB Registers

PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is DDRB. A '1' in DDRB conﬁgures the corresponding port pin as an input. A '0' in the DDRB register conﬁgures the corresponding port pin as an output. Reading PORTB reads the status of the pins, whereas writing to it will write to the port latch.

Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is done by clearing the RBPU

(PORTA<7>) bit. The weak pull-up is automatically turned off when the port pin is conﬁgured as an output. The pull-ups are enabled on any reset.

PORTB also has an interrupt on change feature. Only pins conﬁgured as inputs can cause this interrupt to occur (i.e. any RB7:RB0 pin conﬁgured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB0) are compared with the value in the PORTB data latch. The “mismatch” outputs of RB7:RB0 are OR’ed together to set the PORTB Interrupt Flag bit, RBIF (PIR1<7>).

This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt by:

a) Read-Write PORTB (such as; MOVPF PORTB,

PORTB). This will end mismatch condition.

b) Then, clear the RBIF bit. A mismatch condition will continue to set the RBIF bit.

Reading then writing PORTB will end the mismatch condition, and allow the RBIF bit to be cleared.

This interrupt on mismatch feature, together with software conﬁgurable pull-ups on this port, allows easy interface to a keypad and make it possible for wake-up on key-depression. For an example, refer to Application Note AN552, “Implementing Wake-up on Keystroke.”

The interrupt on change feature is recommended for wake-up on operations where PORTB is only used for the interrupt on change feature and key depression operations.

FIGURE 10-5: BLOCK DIAGRAM OF RB5:RB4 AND RB1:RB0 PORT PINS

Note: I/O pins have protection diodes to VDD and VSS.

Data Bus

Weak Pull-Up

Port Input Latch

Port Data

WR_PORTB (Q4)

WR_DDRB (Q4)

RD_PORTB (Q2)

RD_DDRB (Q2)

RBIF

RBPU

Match Signal from other port pins

(PORTA<7>)

Peripheral Data in

 1997 Microchip Technology Inc. Preliminary DS30264A-page 69

PIC17C75X

Example 10-2 shows an instruction sequence to initialize PORTB. The Bank Select Register (BSR) must be selected to Bank 0 for the port to be initialized. The following example uses the MOVLB instruction to load the BSR register for bank selection.

EXAMPLE 10-2: INITIALIZING PORTB

MOVLB 0 ; Select Bank 0 CLRF PORTB ; Initialize PORTB by clearing ; output data latches MOVLW 0xCF ; Value used to initialize ; data direction MOVWF DDRB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs

FIGURE 10-6: BLOCK DIAGRAM OF RB3:RB2 PORT PINS

Note: I/O pins have protection diodes to VDD and Vss.

Data Bus

Weak Pull-Up

Port Input Latch

Port Data

Peripheral_enable

Peripheral_output

WR_PORTB (Q4)

WR_DDRB (Q4)

RD_PORTB (Q2)

RD_DDRB (Q2)

RBIF

RBPU

Match Signal from other port pins

(PORTA<7>)

Peripheral Data in

PIC17C75X

DS30264A-page 70 Preliminary  1997 Microchip Technology Inc.

FIGURE 10-7: BLOCK DIAGRAM OF RB6 PORT PIN

FIGURE 10-8: BLOCK DIAGRAM OF RB7 PORT PIN

Note: I/O pins have protection diodes to VDD and Vss.

Data Bus

Weak Pull-Up

Port Data

SPI output enable

SPI output

WR_PORTB (Q4)

WR_DDRB (Q4)

RD_PORTB (Q2)

RD_DDRB (Q2)

RBIF

RBPU

Match Signal from other port pins

(PORTA<7>)

Peripheral Data in

Note: I/O pins have protection diodes to VDD and Vss.

Data Bus

Weak Pull-Up

Port Data

SPI output enable

SPI output

WR_PORTB (Q4)

WR_DDRB (Q4)

RD_PORTB (Q2)

RD_DDRB (Q2)

RBIF

RBPU

Match Signal from other port pins

(PORTA<7>)

Peripheral Data in

SS output disable

 1997 Microchip Technology Inc. Preliminary DS30264A-page 71

PIC17C75X

TABLE 10-3: PORTB FUNCTIONS

TABLE 10-4: REGISTERS/BITS ASSOCIATED WITH PORTB

Name Bit Buffer Type Function

RB0/CAP1 bit0 ST Input/Output or the Capture1 input pin. Software programmable weak

pull-up and interrupt on change features.

RB1/CAP2 bit1 ST Input/Output or the Capture2 input pin. Software programmable weak

pull-up and interrupt on change features.

RB2/PWM1 bit2 ST Input/Output or the PWM1 output pin. Software progr ammable weak pull-up

and interrupt on change features.

RB3/PWM2 bit3 ST Input/Output or the PWM2 output pin. Software progr ammable weak pull-up

and interrupt on change features.

RB4/TCLK12 bit4 ST Input/Output or the external clock input to Timer1 and Timer2. Software

programmable weak pull-up and interrupt on change features.

RB5/TCLK3 bit5 ST Input/Output or the external clock input to Timer3. Software programmable

weak pull-up and interrupt on change features.

RB6/SCK bit6 ST Input/Output or the master/slave clock for the SPI. Software programmable

weak pull-up and interrupt on change features.

RB7/SDO bit7 ST Input/Output or data output for the SPI. Software programmable weak

pull-up and interrupt on change features.

Legend: ST = Schmitt Trigger input.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on

all other

resets

(Note1)

12h PORTB

RB7/ SDO

RB6/ SCK

RB5/

TCLK3

RB4/

TCLK12

RB3/

PWM2

RB2/

PWM1

RB1/

CAP2

RB0/

CAP1

xxxx xxxx uuuu uuuu

11h, Bank 0 DDRB Data direction register for PORTB 1111 1111 1111 1111

10h, Bank 0 PORTA RBPU

—

RA5/

TX1/CK1

RA4/

RX1/DT1

RA3/

SDI/SDA

RA2/

/SCL

RA1/T0CKI RA0/INT

0-xx xxxx 0-uu uuuu

06h, Unbanked CPUSTA

— — STKAV GLINTD TO PD POR BOR --11 1100 --11 qq11

07h, Unbanked INTSTA PEIF

T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000

16h, Bank 1 PIR1 RBIF

TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF 0000 0010 0000 0010

17h, Bank 1 PIE1 RBIE

TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000

16h, Bank 3 TCON1

CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000

17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = Value depends on condition.

Shaded cells are not used by PORTB.

Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

PIC17C75X

DS30264A-page 72 Preliminary  1997 Microchip Technology Inc.

10.3 PORTC and DDRC Registers

PORTC is an 8-bit bi-directional port. The corresponding data direction register is DDRC. A '1' in DDRC conﬁgures the corresponding port pin as an input. A '0' in the DDRC register conﬁgures the corresponding port pin as an output. Reading PORTC reads the status of the pins, whereas writing to it will write to the port latch. PORTC is multiplexed with the system bus. When operating as the system bus, PORTC is the low order byte of the address/data bus (AD7:AD0). The timing for the system bus is shown in the Electrical Characteristics section.

Note: This por t is conﬁgured as the system bus

when the device’s conﬁguration bits are selected to Microprocessor or Extended Microcontroller modes. In the two other microcontroller modes, this port is a general purpose I/O.

Example 10-3 shows an instruction sequence to initialize PORTC. The Bank Select Register (BSR) must be selected to Bank 1 for the port to be initialized. The following example uses the MOVLB instruction to load the BSR register for bank selection.

EXAMPLE 10-3: INITIALIZING PORTC

MOVLB 1 ; Select Bank 1 CLRF PORTC ; Initialize PORTC data

;

latches before setting

; the data direction register

MOVLW 0xCF ; Value used to initialize

; data direction

MOVWF DDRC ; Set RC<3:0> as inputs

;

RC<5:4> as outputs

; RC<7:6> as inputs

FIGURE 10-9: BLOCK DIAGRAM OF RC7:RC0 PORT PINS

Note: I/O pins have protection diodes to VDD and Vss.

TTL

0 1

Input Buffer

Port

Data

to D_Bus → IR

INSTRUCTION READ

Data Bus

RD_PORTC

WR_PORTC

RD_DDRC

WR_DDRC

EX_EN

DATA/ADDR_OUT

DRV_SYS

SYS BUS Control

 1997 Microchip Technology Inc. Preliminary DS30264A-page 73

PIC17C75X

TABLE 10-5: PORTC FUNCTIONS

TABLE 10-6: REGISTERS/BITS ASSOCIATED WITH PORTC

Name Bit Buffer Type Function

RC0/AD0 bit0 TTL Input/Output or system bus address/data pin. RC1/AD1 bit1 TTL Input/Output or system bus address/data pin. RC2/AD2 bit2 TTL Input/Output or system bus address/data pin. RC3/AD3 bit3 TTL Input/Output or system bus address/data pin. RC4/AD4 bit4 TTL Input/Output or system bus address/data pin. RC5/AD5 bit5 TTL Input/Output or system bus address/data pin. RC6/AD6 bit6 TTL Input/Output or system bus address/data pin. RC7/AD7 bit7 TTL Input/Output or system bus address/data pin. Legend: TTL = TTL input.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on all

other resets

(Note1)

11h, Bank 1 PORTC

RC7/

AD7

RC6/

AD6

RC5/

AD5

RC4/

AD4

RC3/

AD3

RC2/

AD2

RC1/

AD1

RC0/

AD0

xxxx xxxx uuuu uuuu

10h, Bank 1 DDRC Data direction register for PORTC 1111 1111 1111 1111

Legend: x = unknown, u = unchanged. Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

PIC17C75X

DS30264A-page 74 Preliminary  1997 Microchip Technology Inc.

10.4 PORTD and DDRD Registers

PORTD is an 8-bit bi-directional port. The corresponding data direction register is DDRD. A '1' in DDRD conﬁgures the corresponding port pin as an input. A '0' in the DDRD register conﬁgures the corresponding port pin as an output. Reading PORTD reads the status of the pins, whereas writing to it will write to the port latch. PORTD is multiplexed with the system bus. When operating as the system bus, PORTD is the high order byte of the address/data bus (AD15:AD8). The timing for the system bus is shown in the Electrical Characteristics section.

Note: This por t is conﬁgured as the system bus

when the device’s conﬁguration bits are selected to Microprocessor or Extended Microcontroller modes. In the two other microcontroller modes, this port is a general purpose I/O.

Example 10-4 shows an instruction sequence to initialize PORTD. The Bank Select Register (BSR) must be selected to Bank 1 for the port to be initialized. The following example uses the MOVLB instruction to load the BSR register for bank selection.

EXAMPLE 10-4: INITIALIZING PORTD

MOVLB 1 ; Select Bank 1 CLRF PORTD ; Initialize PORTD data

;

latches before setting

; the data direction register

MOVLW 0xCF ; Value used to initialize

; data direction

MOVWF DDRD ; Set RD<3:0> as inputs

;

RD<5:4> as outputs

; RD<7:6> as inputs

FIGURE 10-10: BLOCK DIAGRAM OF RD7:RD0 PORT PINS (IN I/O PORT MODE)

Note: I/O pins have protection diodes to VDD and Vss.

TTL

0 1

Input Buffer

Port

Data

to D_Bus → IR

INSTRUCTION READ

Data Bus

RD_PORTD

WR_PORTD

RD_DDRD

WR_DDRD

EX_EN

DATA/ADDR_OUT

DRV_SYS

SYS BUS Control

 1997 Microchip Technology Inc. Preliminary DS30264A-page 75

PIC17C75X

TABLE 10-7: PORTD FUNCTIONS

TABLE 10-8: REGISTERS/BITS ASSOCIATED WITH PORTD

Name Bit Buffer Type Function

RD0/AD8 bit0 TTL Input/Output or system bus address/data pin. RD1/AD9 bit1 TTL Input/Output or system bus address/data pin. RD2/AD10 bit2 TTL Input/Output or system bus address/data pin. RD3/AD11 bit3 TTL Input/Output or system bus address/data pin. RD4/AD12 bit4 TTL Input/Output or system bus address/data pin. RD5/AD13 bit5 TTL Input/Output or system bus address/data pin. RD6/AD14 bit6 TTL Input/Output or system bus address/data pin. RD7/AD15 bit7 TTL Input/Output or system bus address/data pin. Legend: TTL = TTL input.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on all

other resets

(Note1)

13h, Bank 1 PORTD

RD7/

AD15

RD6/ AD14

RD5/

AD13

RD4/

AD12

RD3/

AD11

RD2/

AD10

RD1/

AD9

RD0/

AD8

xxxx xxxx uuuu uuuu

12h, Bank 1 DDRD Data direction register for PORTD 1111 1111 1111 1111

Legend: x = unknown, u = unchanged. Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

PIC17C75X

DS30264A-page 76 Preliminary  1997 Microchip Technology Inc.

10.5 PORTE and DDRE Register

PORTE is a 4-bit bi-directional port. The corresponding data direction register is DDRE. A '1' in DDRE conﬁgures the corresponding port pin as an input. A '0' in the DDRE register conﬁgures the corresponding port pin as an output. Reading PORTE reads the status of the pins, whereas writing to it will write to the port latch. PORTE is multiplexed with the system bus. When operating as the system bus, PORTE contains the control signals for the address/data bus (AD15:AD0). These control signals are Address Latch Enable (ALE), Output Enable (OE

), and Write (WR). The control sig-

nals OE

and WR are active low signals. The timing for the system bus is shown in the Electrical Characteristics section.

Note: Three pins of this por t are conﬁgured as

the system bus when the device’s conﬁguration bits are selected to Microprocessor or Extended Microcontroller modes. The other pin is a general purpose I/O or Capture4 pin. In the two other microcontroller modes, RE2:RE0 are general purpose I/O pins.

Example 10-5 shows an instruction sequence to initialize PORTE. The Bank Select Register (BSR) must be selected to Bank 1 for the port to be initialized. The following example uses the MOVLB instruction to load the BSR register for bank selection.

EXAMPLE 10-5: INITIALIZING PORTE

MOVLB 1 ; Select Bank 1 CLRF PORTE ; Initialize PORTE data ; latches before setting ; the data direction ; register MOVLW 0x03 ; Value used to initialize ; data direction MOVWF DDRE ; Set RE<1:0> as inputs ; RE<3:2> as outputs ; RE<7:4> are always ; read as '0'

FIGURE 10-11: BLOCK DIAGRAM OF RE2:RE0 (IN I/O PORT MODE)

Note: I/O pins have protection diodes to VDD and Vss.

TTL

0 1

Input Buffer

Port

Data

Data Bus

RD_PORTE

WR_PORTE

RD_DDRE

WR_DDRE

EX_EN

CNTL

DRV_SYS

SYS BUS Control

 1997 Microchip Technology Inc. Preliminary DS30264A-page 77

PIC17C75X

FIGURE 10-12: BLOCK DIAGRAM OF RE3/CAP4 PORT PIN

TABLE 10-9: PORTE FUNCTIONS

TABLE 10-10: REGISTERS/BITS ASSOCIATED WITH PORTE

Name Bit Buffer Type Function

RE0/ALE bit0 TTL Input/Output or system bus Address Latch Enable (ALE) control pin. RE1/OE

bit1 TTL Input/Output or system bus Output Enable (OE) control pin.

RE2/WR

bit2 TTL Input/Output or system bus Write (WR) control pin. RE3/CAP4 bit3 ST Input/Output or Capture4 input pin Legend: TTL = TTL input. ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on,

POR,

BOR

Value on all

other resets

(Note1)

15h, Bank 1 PORTE

— — — — RE3/CAP4 RE2/WR RE1/OE RE0/ALE ---- xxxx ---- uuuu

14h, Bank 1 DDRE Data direction register for PORTE ---- 1111 ---- 1111 14h, Bank 7 CA4L Capture4 low byte xxxx xxxx uuuu uuuu 15h, Bank 7 CA4H Capture4 high byte xxxx xxxx uuuu uuuu 16h, Bank 7 TCON3

— CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE. Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

Note: I/O pin has protection diodes to VDD and Vss.

Port

Data

Data Bus

RD_PORTE

WR_PORTE

RD_DDRE

WR_DDRE

Peripheral In

PIC17C75X

DS30264A-page 78 Preliminary  1997 Microchip Technology Inc.

10.6 PORTF and DDRF Registers

PORTF is an 8-bit wide bi-directional port. The corresponding data direction register is DDRF. A '1' in DDRF conﬁgures the corresponding port pin as an input. A '0' in the DDRF register conﬁgures the corresponding port pin as an output. Reading PORTF reads the status of the pins, whereas writing to them will write to the respective port latch.

All eight bits of PORTF are multiplexed with 8 of the 12 channels of the 10-bit A/D converter.

Upon reset the entire Port is automatically conﬁgured as analog inputs, and must be conﬁgured in software to be a digital I/O.

Example 10-6 shows an instruction sequence to initialize PORTF. The Bank Select Register (BSR) must be selected to Bank 5 for the port to be initialized. The following example uses the MOVLB instruction to load the BSR register for bank selection.

EXAMPLE 10-6: INITIALIZING PORTF

MOVLB 5 ; Select Bank 5 MOVLW 0x0E ; Configure PORTF as MOVPF ADCON1 ; Digital CLRF PORTF ; Initialize PORTF data ; latches before setting ; the data direction ; register MOVLW 0x03 ; Value used to initialize ; data direction MOVWF DDRF ; Set RF<1:0> as inputs ; RF<7:2> as outputs

FIGURE 10-13: BLOCK DIAGRAM OF RF7:RF0

Data bus

WR PORTF

WR DDRF

RD PORT

Data Latch

DDRF Latch

I/O pin

PCFG3:PCFG0

ST input buffer

VDD

RD DDRF

To other pads

VAN

CHS3:CHS0

To other pads

 1997 Microchip Technology Inc. Preliminary DS30264A-page 79

PIC17C75X

TABLE 10-11: PORTF FUNCTIONS

TABLE 10-12: REGISTERS/BITS ASSOCIATED WITH PORTF

Name Bit Buffer Type Function

RF0/AN4

bit0

Input/Output or analog input 4

RF1/AN5 bit1 ST

Input/Output or analog input 5

RF2/AN6 bit2 ST

Input/Output or analog input 6

RF3/AN7 bit3 ST

Input/Output or analog input 7

RF4/AN8 bit4 ST

Input/Output or analog input 8

RF5/AN9 bit5 ST

Input/Output or analog input 9

RF6/AN10 bit6 ST

Input/Output or analog input 10

RF7/AN11 bit7 ST

Input/Output or analog input 11

Legend: ST = Schmitt Trigger input.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on,

POR,

BOR

Value on all

other resets

(Note1)

10h, Bank 5 DDRF Data Direction Register for PORTF 1111 1111 1111 1111 11h, Bank 5 PORTF RF7/

AN11

RF6/

AN10

RF5/

AN9

RF4/ AN8

RF3/ AN7

RF2/ AN6

RF1/ AN5

RF0/ AN4

0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTF. Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

PIC17C75X

DS30264A-page 80 Preliminary  1997 Microchip Technology Inc.

10.7 PORTG and DDRG Registers

PORTG is an 8-bit wide bi-directional port. The corresponding data direction register is DDRG. A '1' in DDRG conﬁgures the corresponding port pin as an input. A '0' in the DDRG register conﬁgures the corresponding port pin as an output. Reading PORTG reads the status of the pins, whereas writing to them will write to the respective port latch.

The lower four bits of POR TG are m ultiplexed with four of the 12 channels of the 10-bit A/D converter.

The remaining bits of PORTG are multiplexed with peripheral output and inputs. RG4 is multiplexed with the CAP3 input, RG5 is multiplexed with the PWM3 output, RG6 and RG7 are multiplexed with the USART2 functions.

Upon reset the entire Port is automatically conﬁgured as analog inputs, and must be conﬁgured in software to be a digital I/O.

Example 10-7 shows the instruction sequence to initialize PORTG. The Bank Select Register (BSR) must be selected to Bank 5 for the port to be initialized. The following example uses the MOVLB instruction to load the BSR register for bank selection.

EXAMPLE 10-7: INITIALIZING PORTG

MOVLB 5 ; Select Bank 5 MOVLW 0x0E ; Configure PORTG as MOVPF ADCON1 ; digital CLRF PORTG ; Initialize PORTG data ; latches before setting ; the data direction ; register MOVLW 0x03 ; Value used to initialize ; data direction MOVWF DDRG ; Set RG<1:0> as inputs ; RG<7:2> as outputs

FIGURE 10-14: BLOCK DIAGRAM OF RG3:RG0

Data bus

WR PORTG

WR DDRG

RD PORT

Data Latch

DDRG Latch

I/O pin

PCFG3:PCFG0

ST input buffer

VDD

RD DDRG

To other pads

VAN

CHS3:CHS0

To other pads

 1997 Microchip Technology Inc. Preliminary DS30264A-page 81

PIC17C75X

FIGURE 10-15: RG4 BLOCK DIAGRAM

FIGURE 10-16: RG7:RG5 BLOCK DIAGRAM

Note: I/O pin has protection diodes to VDD and Vss.

Data Bus

RD_PORTG

WR_PORTG

RD_DDRG

WR_DDRG

Peripheral Data In

VDD

Note: I/O pins have protection diodes to VDD and Vss.

1 0

Port

Data

Data Bus

RD_PORTG

WR_PORTG

RD_DDRG

WR_DDRG

OUTPUT

OUTPUT ENABLE

Peripheral Data In

PIC17C75X

DS30264A-page 82 Preliminary  1997 Microchip Technology Inc.

TABLE 10-13: PORTG FUNCTIONS

TABLE 10-14: REGISTERS/BITS ASSOCIATED WITH PORTG

Name Bit Buffer Type Function

RG0/AN3

bit0

Input/Output or analog input 3.

RG1/AN2 bit1 ST

Input/Output or analog input 2.

RG2/AN1/V

REF- bit2 ST

Input/Output or analog input 1 or the ground reference voltage

RG3/AN0/V

REF+ bit3 ST

Input/Output or analog input 0 or the positive reference voltage

RG4/CAP3 bit4 ST

RG4 can also be the Capture3 input pin.

RG5/PWM3 bit5 ST

RG5 can also be the PWM3 output pin.

RG6/RX2/DT2 bit6 ST

RG6 can also be selected as the USART2 (SCI) Asynchronous Receive or USART2 (SCI) Synchronous Data.

RG7/TX2/CK2 bit7 ST

RG7 can also be selected as the USART2 (SCI) Asynchronous Transmit or USART2 (SCI) Synchronous Clock.

Legend: ST = Schmitt Trigger input.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on,

POR, BOR

Value on all

other resets

(Note1)

12h, Bank 5 DDRG Data Direction Register for PORTG 1111 1111 1111 1111 13h, Bank 5 PORTG RG7/

TX2/CK2

RG6/

RX2/DT2

RG5/

PWM3

RG4/

CAP3

RG3/

AN0

RG2/

AN1

RG1/

AN2

RG0/

AN3

xxxx 0000 uuuu 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTG. Note 1: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.

 1997 Microchip Technology Inc. Preliminary DS30264A-page 83

PIC17C75X

10.8 I/O Programming Considerations

10.8.1 BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a

read followed by a write operation. For example, the BCF and BSF instructions read the register into the CPU, execute the bit operation, and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs deﬁned. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (e.g. bit0) and it is deﬁned as an input at this time, the input signal present on the pin itself would be read into the CPU and re-written to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown.

Reading a port reads the values of the por t pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (BCF, BSF, BTG, etc.) on a port, the value of the port pins is read, the desired operation is performed with this value, and the value is then written to the port latch.

Example 10-8 shows the effect of two sequential read-modify-write instructions on an I/O port.

EXAMPLE 10-8: READ MODIFY WRITE

INSTRUCTIONS ON AN I/O PORT

10.8.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 10-17). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before executing the instruction that reads the values on that I/O port. Otherwise, the pre vious state of that pin may be read into the CPU rather than the “ne w” state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.

; Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs ; PORTB<7:6> have pull-ups and are ; not connected to other circuitry ; ; PORT latch PORT pins ; ---------- --------; BCF PORTB, 7 ; 01pp pppp 11pp pppp BCF PORTB, 6 ; 10pp pppp 11pp pppp

BCF DDRB, 7 ; 10pp pppp 11pp pppp BCF DDRB, 6 ; 10pp pppp 10pp pppp ; ; Note that the user may have expected the ; pin values to be 00pp pppp. The 2nd BCF ; caused RB7 to be latched as the pin value ; (High).

Note: A pin actively outputting a Low or High

should not be driven from external devices in order to change the level on this pin (i.e. “wired-or”, “wired-and”). The resulting high output currents may damage the device.

FIGURE 10-17: SUCCESSIVE I/O OPERATION

PC PC + 1 PC + 2

PC + 3

Q1 Q2

Instruction

fetched

RB7:RB0

MOVWF PORTB

write to PORTB

NOP

Port pin sampled here

NOP

MOVF PORTB,W

Instruction

executed

MOVWF PORTB

write to PORTB

NOPMOVF PORTB,W

Note: This example shows a write to PORTB

followed by a read from PORTB. Note that: data setup time = (0.25TCY - TPD) where TCY = instruction cycle

TPD = propagation delay

Therefore, at higher clock frequencies, a write followed by a read may be problematic.

PIC17C75X

DS30264A-page 84 Preliminary  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. Preliminary DS30264A-page 85

PIC17C75X

11.0 OVERVIEW OF TIMER RESOURCES

The PIC17C75X has four timer modules. Each module can generate an interrupt to indicate that an event has occurred. These timers are called:

• Timer0 - 16-bit timer with programmable 8-bit

prescaler

• Timer1 - 8-bit timer

• Timer2 - 8-bit timer

• Timer3 - 16-bit timer

For enhanced time-base functionality, four input Captures and three Pulse Width Modulation (PWM) outputs are possible. The PWMs use the Timer1 and Timer2 resources and the input Captures use the Timer3 resource.

11.1 Timer0 Overview

The Timer0 module is a simple 16-bit ov erﬂo w counter. The clock source can be either the internal system clock (Fosc/4) or an external clock.

When Timer0 uses an external clock source, it has the ﬂexibility to allow user selection of the incrementing edge, rising or falling.

The Timer0 module also has a programmable prescaler. The PS3:PS0 bits (T0STA<4:1>) determine the prescale value. TMR0 can increment at the following rates: 1:1, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64, 1:128, 1:256.

Synchronization of the external clock occurs after the prescaler. When the prescaler is used, the external clock frequency may be higher then the device’s frequency. The maximum external frequency, on the T0CKI pin, is 50 MHz, given the high and low time requirements of the clock.

11.2 Timer1 Overview

The Timer1 module is an 8-bit timer/counter with an 8-bit period register (PR1). When the TMR1 value rolls over from the period match value to 0h, the TMR1IF ﬂag is set, and an interrupt will be generated if enabled. In counter mode, the clock comes from the RB4/TCLK12 pin, which can also be selected to be the clock for the Timer2 module.

TMR1 can be concatenated with TMR2 to form a 16-bit timer. The TMR1 register is the LSB and TMR2 is the MSB. When in the 16-bit timer mode, there is a corresponding 16-bit period register (PR2:PR1). When the TMR2:TMR1 value rolls over from the period match value to 0h, the TMR1IF ﬂag is set, and an interrupt will be generated if enabled.

11.3 Timer2 Overview

The Timer2 module is an 8-bit timer/counter with an 8-bit period register (PR2). When the TMR2 value rolls over from the period match value to 0h, the TMR2IF ﬂag is set, and an interrupt will be generated if enabled. In counter mode, the clock comes from the RB4/TCLK12 pin, which can also provide the clock for the Timer1 module.

TMR2 can be concatenated with TMR1 to form a 16-bit timer. The TMR2 register is the MSB and TMR1 is the LSB. When in the 16-bit timer mode, there is a corresponding 16-bit period register (PR2:PR1). When the TMR2:TMR1 value rolls over from the period match value to 0h, the TMR1IF ﬂag is set, and an interrupt will be generated if enabled.

11.4 Timer3 Overview

The Timer3 module is a 16-bit timer/counter with a 16-bit period register. When the TMR3H:TMR3L value rolls over to 0h, the TMR3IF bit is set and an interrupt will be generated if enabled. In counter mode, the clock comes from the RB5/TCLK3 pin.

When operating in the four capture mode, the period registers become the second (of four) 16-bit capture registers.

11.5 Role of the Timer/Counters

The timer modules are general purpose, but have dedicated resources associated with them. TImer1 and Timer2 are the time-bases for the three Pulse Width Modulation (PWM) outputs, while Timer3 is the time-base for the four input captures.

PIC17C75X

DS30264A-page 86 Preliminary  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. Preliminary DS30264A-page 87

PIC17C75X

12.0 TIMER0

The Timer0 module consists of a 16-bit timer/counter, TMR0. The high byte is register TMR0H and the low byte is register TMR0L. A software programmable 8-bit prescaler makes Timer0 an effective 24-bit overﬂow timer. The clock source is software programmable as either the internal instruction clock or an external clock on the RA1/T0CKI pin. The control bits for this module are in register T0STA (Figure 12-1).

FIGURE 12-1: T0STA REGISTER (ADDRESS: 05h, UNBANKED)

R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 U - 0

INTEDG T0SE T0CS T0PS3 T0PS2 T0PS1 T0PS0

—

R = Readable bit W = Writable bit U = Unimplemented, Read as '0'

-n = Value at POR reset

bit7 bit0

bit 7: INTEDG: RA0/INT Pin Interrupt Edge Select bit

This bit selects the edge upon which the interrupt is detected 1 =Rising edge of RA0/INT pin generates interrupt 0 =Falling edge of RA0/INT pin generates interrupt

bit 6: T0SE: Timer0 Clock Input Edge Select bit

This bit selects the edge upon which TMR0 will increment When

T0CS = 0 (External Clock) 1 =Rising edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt 0 =Falling edge of RA1/T0CKI pin increments TMR0 and/or generates a T0CKIF interrupt When

T0CS = 1 (Internal Clock) Don’t care

bit 5: T0CS: Timer0 Clock Source Select bit

This bit selects the clock source for TMR0. 1 =Internal instruction clock cycle (T

CY)

0 =External Clock input on the T0CKI pin

bit 4-1: T0PS3:T0PS0: Timer0 Prescale Selection bits

These bits select the prescale value for TMR0.

bit 0: Unimplemented: Read as '0'

T0PS3:T0PS0 Prescale V alue

0000 0001 0010 0011 0100 0101 0110 0111 1xxx

1:1 1:2 1:4

1:8 1:16 1:32 1:64

1:128 1:256

PIC17C75X

DS30264A-page 88 Preliminary  1997 Microchip Technology Inc.

12.1 Timer0 Operation

When the T0CS (T0STA<5>) bit is set, TMR0 increments on the internal clock. When T0CS is clear, TMR0 increments on the external clock (RA1/T0CKI pin). The external clock edge can be selected in software. When the T0SE (T0STA<6>) bit is set, the timer will increment on the rising edge of the RA1/T0CKI pin. When T0SE is clear, the timer will increment on the falling edge of the RA1/T0CKI pin. The prescaler can be programmed to introduce a prescale of 1:1 to 1:256. The timer increments from 0000h to FFFFh and rolls over to 0000h. On overﬂow, the TMR0 Interrupt Flag bit (T0IF) is set. The TMR0 interrupt can be masked by clearing the corresponding TMR0 Interrupt Enable bit (T0IE). The TMR0 Interrupt Flag bit (T0IF) is automatically cleared when vectoring to the TMR0 interrupt vector.

12.2 Using Timer0 with External Clock

When an external clock input is used for Timer0, it is synchronized with the internal phase clocks. Figure 12-3 shows the synchronization of the external clock. This synchronization is done after the prescaler. The output of the prescaler (PSOUT) is sampled twice in every instruction cycle to detect a rising or a falling edge. The timing requirements for the external clock are detailed in the electrical speciﬁcation section.

12.2.1 DELAY FROM EXTERNAL CLOCK EDGE Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the external clock edge occurs to the time TMR0 is actually incremented. Figure 12-3 shows that this delay is between 3T

OSC and 7TOSC. Thus, for example, mea-

suring the interval between two edges (e.g. period) will be accurate within ±4T

OSC (±121 ns @ 33 MHz).

FIGURE 12-2: TIMER0 MODULE BLOCK DIAGRAM

FIGURE 12-3: TMR0 TIMING WITH EXTERNAL CLOCK (INCREMENT ON FALLING EDGE)

RA1/T0CKI

Synchronization

Prescaler (8 stage

async ripple counter)

T0SE

(T0STA<6>)

Fosc/4

T0CS

(T0STA<5>)

T0PS3:T0PS0 (T0STA<4:1>)

Q2 Q4

0 1

TMR0H<8> TMR0L<8>

Interrupt on overﬂow

sets T0IF

(INTST A<5>)

PSOUT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Prescaler

output

(PSOUT)

Sampled

Prescaler

output

Increment

TMR0

T0 T0 + 1 T0 + 2

(note 3)

(note 2)

Note 1: The delay from the T0CKI edge to the TMR0 increment is 3Tosc to 7Tosc.

2: ↑ = PSOUT is sampled here.

3: The PSOUT high time is too short and is missed by the sampling circuit.

(note 1)

 1997 Microchip Technology Inc. Preliminary DS30264A-page 89

PIC17C75X

12.3 Read/Write Consideration for TMR0

Although TMR0 is a 16-bit timer/counter, only 8-bits at a time can be read or written during a single instruction cycle. Care must be taken during any read or write.

12.3.1 READING 16-BIT VALUE The problem in reading the entire 16-bit value is that

after reading the low (or high) byte, its value may change from FFh to 00h.

Example 12-1 shows a 16-bit read. To ensure a proper read, interrupts must be disabled during this routine.

EXAMPLE 12-1: 16-BIT READ

MOVPF TMR0L, TMPLO ;read low tmr0 MOVPF TMR0H, TMPHI ;read high tmr0 MOVFP TMPLO, WREG ;tmplo −> wreg CPFSLT TMR0L ;tmr0l < wreg? RETURN ;no then return MOVPF TMR0L, TMPLO ;read low tmr0 MOVPF TMR0H, TMPHI ;read high tmr0 RETURN ;return

12.3.2 WRITING A 16-BIT VALUE TO TMR0 Since writing to either TMR0L or TMR0H will eff ectiv ely

inhibit increment of that half of the TMR0 in the next cycle (following write), but not inhibit increment of the other half, the user must write to TMR0L ﬁrst and TMR0H second in two consecutive instructions, as shown in Example 12-2. The interrupt must be disabled. Any write to either TMR0L or TMR0H clears the prescaler.

EXAMPLE 12-2: 16-BIT WRITE

12.4 Prescaler

Assignments

Timer0 has an 8-bit prescaler. The prescaler assignment is fully under software control; i.e., it can be changed “on the ﬂy” during program execution. When changing the prescaler assignment, clearing the prescaler is recommended before changing assignment. The value of the prescaler is “unknown,” and assigning a value that is less then the present value makes it difﬁcult to take this unknown time into account.

BSF CPUSTA, GLINTD ; Disable interrupts MOVFP RAM_L, TMR0L ; MOVFP RAM_H, TMR0H ; BCF CPUSTA, GLINTD ; Done, enable ; interrupts

FIGURE 12-4: TMR0 TIMING: WRITE HIGH OR LOW BYTE

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

AD15:AD0

ALE

TMR0L

TMR0H

MOVFP W,TMR0L

Write to TMR0L

MOVFP TMR0L,W

Read TMR0L

(Value = NT0)

MOVFP TMR0L,W

Read TMR0L

(Value = NT0)

MOVFP TMR0L,W

Read TMR0L

(Value = NT0 +1)

T0 T0+1 New T0 (NT0) New T0+1

PC+1 PC+2 PC+3 PC+4

Fetch

Instruction

executed

PIC17C75X

DS30264A-page 90 Preliminary  1997 Microchip Technology Inc.

FIGURE 12-5: TMR0 READ/WRITE IN TIMER MODE

TABLE 12-1: REGISTERS/BITS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on all

other resets

(Note1)

05h, Unbanked T0STA

INTEDG T0SE T0CS T0PS3 T0PS2 T0PS1 T0PS0 — 0000 000- 0000 000- 06h, Unbanked CPUSTA — — STKAV GLINTD TO PD POR BOR --11 1100 --11 qq11 07h, Unbanked INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000 0Bh, Unbanked TMR0L TMR0 register; low byte xxxx xxxx uuuu uuuu 0Ch, Unbanked TMR0H TMR0 register; high byte xxxx xxxx uuuu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', q - value depends on condition, Shaded cells are not used by Timer0. Note 1: Other (non power-up) resets include: external reset through MCLR

and the Watchdog Timer Reset.

Instruction

executed

MOVFP

DATAL,TMR0L

Write TMR0L

MOVFP

DATAH,TMR0H

Write TMR0H

MOVPF

TMR0L,W

Read TMR0L

MOVPF

TMR0L,W

Read TMR0L

MOVPF

TMR0L,W

Read TMR0L

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

AD15:AD0

ALE

WR_TRM0L

WR_TMR0H

RD_TMR0L

TMR0H

TMR0L

57 58

In this example, old TMR0 value is 12FEh, new value of AB56h is written.

Instruction

fetched

MOVFP

DATAL,TMR0L

Write TMR0L

MOVFP

DATAH,TMR0H

Write TMR0H

MOVPF

TMR0L,W

Read TMR0L

MOVPF

TMR0L,W

Read TMR0L

MOVPF

TMR0L,W

Read TMR0L

MOVPF

TMR0L,W

Read TMR0L

Previously Fetched Instruction

 1997 Microchip Technology Inc. Preliminary DS30264A-page 91

PIC17C75X

13.0 TIMER1, TIMER2, TIMER3, PWMS AND CAPTURES

The PIC17C75X has a wealth of timers and time-based functions to ease the implementation of control applications. These time-base functions include three PWM outputs and four Capture inputs.

Timer1 and Timer2 are two 8-bit incrementing timers, each with an 8-bit period register (PR1 and PR2 respectively) and separate overﬂow interrupt ﬂags. Timer1 and Timer2 can operate either as timers (increment on internal Fosc/4 clock) or as counters (increment on falling edge of external clock on pin RB4/TCLK12). They are also software conﬁgurable to operate as a single 16-bit timer/counter. These timers are also used as the time-base for the PWM (Pulse Width Modulation) modules.

Timer3 is a 16-bit timer/counter which uses the TMR3H and TMR3L registers. Timer3 also has two additional registers (PR3H/CA1H: PR3L/CA1L) that are conﬁgurable as a 16-bit period register or a 16-bit capture register. TMR3 can be software conﬁgured to increment from the internal system clock (F

OSC/4) or from

an external signal on the RB5/TCLK3 pin. Timer3 is the time-base for all of the 16-bit captures.

Six other registers comprise the Capture2, Capture3, and Capture4 registers (CA2H:CA2L, CA3H:CA3L, and CA4H:CA4L).

Figure 13-1, Figure 13-2, and Figure 13-3 are the control registers for the operation of Timer1, Timer2, and Timer3, as well as PWM1, PWM2, PWM3, Capture1, Capture2, Capture3, and Capture4.

Table 13-1 shows the Timer resource requirements for these time-base functions. Each timer is an open resource so that multiple functions may operate with it.

TABLE 13-1: TIME-BASE FUNCTION /

RESOURCE REQUIREMENTS

Time-base Function Timer Resource

PWM1 Timer1 PWM2 Timer1 or Timer2 PWM3 Timer1 or Timer2 Capture1 Timer3 Capture2 Timer3 Capture3 Timer3 Capture4 Timer3

FIGURE 13-1: TCON1 REGISTER (ADDRESS: 16h, BANK 3)

R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0

CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS

R = Readable bit W = Writable bit

-n = Value at POR reset

bit7 bit0 bit 7-6: CA2ED1:CA2ED0: Capture2 Mode Select bits

00 = Capture on every falling edge 01 = Capture on every rising edge 10 = Capture on every 4th rising edge 11 = Capture on every 16th rising edge

bit 5-4: CA1ED1:CA1ED0: Capture1 Mode Select bits

00 = Capture on every falling edge 01 = Capture on every rising edge 10 = Capture on every 4th rising edge 11 = Capture on every 16th rising edge

bit 3: T16: Timer2:Timer1 Mode Select bit

1 =Timer2 and Timer1 form a 16-bit timer 0 =Timer2 and Timer1 are two 8-bit timers

bit 2: TMR3CS: Timer3 Clock Source Select bit

1 =TMR3 increments off the falling edge of the RB5/TCLK3 pin 0 =TMR3 increments off the internal clock

bit 1: TMR2CS: Timer2 Clock Source Select bit

1 =TMR2 increments off the falling edge of the RB4/TCLK12 pin 0 =TMR2 increments off the internal clock

bit 0: TMR1CS: Timer1 Clock Source Select bit

1 =TMR1 increments off the falling edge of the RB4/TCLK12 pin 0 =TMR1 increments off the internal clock

PIC17C75X

DS30264A-page 92 Preliminary  1997 Microchip Technology Inc.

FIGURE 13-2: TCON2 REGISTER (ADDRESS: 17h, BANK 3)

R - 0 R - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0

CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3

TMR3ON TMR2ON TMR1ON

R = Readable bit W = Writable bit

-n = Value at POR reset

bit7 bit0 bit 7: CA2OVF: Capture2 Overﬂow Status bit

This bit indicates that the capture value had not been read from the capture register pair (CA2H:CA2L) before the next capture e vent occurred. The capture register retains the oldest unread capture value (last capture before overﬂow). Subsequent capture events will not update the capture register with the TMR3 value until the capture register has been read (both bytes). 1 =Overﬂow occurred on Capture2 register 0 =No overﬂow occurred on Capture2 register

bit 6: CA1OVF: Capture1 Overﬂow Status bit

This bit indicates that the capture value had not been read from the capture register pair (PR3H/CA1H:PR3L/CA1L) before the next capture event occurred. The capture register retains the oldest unread capture value (last capture before overﬂow). Subsequent capture events will not update the capture register with the TMR3 value until the capture register has been read (both bytes). 1 =Overﬂow occurred on Capture1 register 0 =No overﬂow occurred on Capture1 register

bit 5: PWM2ON: PWM2 On bit

1 =PWM2 is enabled (The RB3/PWM2 pin ignores the state of the DDRB<3> bit) 0 =PWM2 is disabled (The RB3/PWM2 pin uses the state of the DDRB<3> bit for data direction)

bit 4: PWM1ON: PWM1 On bit

1 =PWM1 is enabled (The RB2/PWM1 pin ignores the state of the DDRB<2> bit) 0 =PWM1 is disabled (The RB2/PWM1 pin uses the state of the DDRB<2> bit for data direction)

bit 3: CA1/PR3

: CA1/PR3 Register Mode Select bit 1 =Enables Capture1 (PR3H/CA1H:PR3L/CA1L is the Capture1 register. Timer3 runs without a period register) 0 =Enables the Period register (PR3H/CA1H:PR3L/CA1L is the Period register for Timer3)

bit 2: TMR3ON: Timer3 On bit

1 =Starts Timer3 0 =Stops Timer3

bit 1: TMR2ON: Timer2 On bit

This bit controls the incrementing of the TMR2 register. When TMR2:TMR1 form the 16-bit timer (T16 is set), TMR2ON must be set. This allows the MSB of the timer to increment. 1 =Starts Timer2 (Must be enabled if the T16 bit (TCON1<3>) is set) 0 =Stops Timer2

bit 0: TMR1ON: Timer1 On bit

When

T16 is set (in 16-bit Timer Mode) 1 =Starts 16-bit TMR2:TMR1 0 =Stops 16-bit TMR2:TMR1

When

T16 is clear (in 8-bit Timer Mode) 1 =Starts 8-bit Timer1 0 =Stops 8-bit Timer1

 1997 Microchip Technology Inc. Preliminary DS30264A-page 93

PIC17C75X

FIGURE 13-3: TCON3 REGISTER (ADDRESS: 16h, BANK 7)

U-0 R - 0 R - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0 R/W - 0

- CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON

R = Readable bit W = Writable bit U = Unimplemented bit, Reads as ‘0’

-n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as ‘0’ bit 6: CA4OVF: Capture4 Overﬂow Status bit

This bit indicates that the capture value had not been read from the capture register pair (CA4H:CA4L) before the next capture event occurred. The capture register retains the oldest unread capture value (last capture before overﬂow). Subsequent capture events will not update the capture register with the TMR3 value until the capture register has been read (both bytes). 1 =Overﬂow occurred on Capture4 registers 0 =No overﬂow occurred on Capture4 registers

bit 5: CA3OVF: Capture3 Overﬂow Status bit

This bit indicates that the capture value had not been read from the capture register pair (CA3H:CA3L) before the next capture event occurred. The capture register retains the oldest unread capture value (last capture before overﬂow). Subsequent capture events will not update the capture register with the TMR3 value until the capture register has been read (both bytes). 1 =Overﬂow occurred on Capture3 registers 0 =No overﬂow occurred on Capture3 registers

bit 4-3: CA4ED1:CA4ED0: Capture4 Mode Select bits

00 = Capture on every falling edge 01 = Capture on every rising edge 10 = Capture on every 4th rising edge 11 = Capture on every 16th rising edge

bit 2-1: CA3ED1:CA3ED0: Capture3 Mode Select bits

00 = Capture on every falling edge 01 = Capture on every rising edge 10 = Capture on every 4th rising edge 11 = Capture on every 16th rising edge

bit 0: PWM3ON: PWM3 On bit

1 =PWM3 is enabled (The RG5/PWM3 pin ignores the state of the DDRG<5> bit) 0 =PWM3 is disabled (The RG5/PWM3 pin uses the state of the DDRG<5> bit for data direction)

PIC17C75X

DS30264A-page 94 Preliminary  1997 Microchip Technology Inc.

13.1 Timer1 and Timer2

13.1.1 TIMER1, TIMER2 IN 8-BIT MODE Both Timer1 and Timer2 will operate in 8-bit mode

when the T16 bit is clear . These two timers can be independently conﬁgured to increment from the internal instruction cycle clock (T

CY) or from an external clock

source on the RB4/TCLK12 pin. The timer cloc k source is conﬁgured by the TMRxCS bit (x = 1 for Timer1 or = 2 for Timer2). When TMRxCS is clear, the clock source is internal and increments once every instruction cycle (Fosc/4). When TMRxCS is set, the clock source is the RB4/TCLK12 pin, and the counters will increment on every falling edge of the RB4/TCLK12 pin.

The timer increments from 00h until it equals the Period register (PRx). It then resets to 00h at the next increment cycle. The timer interrupt ﬂag is set when the timer is reset. TMR1 and TMR2 have individual interrupt ﬂag bits. The TMR1 interrupt ﬂag bit is latched into TMR1IF, and the TMR2 interrupt ﬂag bit is latched into TMR2IF.

Each timer also has a corresponding interrupt enable bit (TMRxIE). The timer interrupt can be enabled/disabled by setting/clearing this bit. For peripheral interrupts to be enabled, the Peripheral Interrupt Enable bit must be set (PEIE = '1') and global interrupt must be enabled (GLINTD = '0').

The timers can be turned on and off under software control. When the timer on control bit (TMRxON) is set, the timer increments from the clock source. When TMRxON is cleared, the timer is turned off and cannot cause the timer interrupt ﬂag to be set.

13.1.1.1 EXTERNAL CLOCK INPUT FOR TIMER1 AND TIMER2

When TMRxCS is set, the clock source is the RB4/TCLK12 pin, and the counter will increment on every falling edge on the RB4/TCLK12 pin. The TCLK12 input is synchronized with internal phase clocks. This causes a delay from the time a f alling edge appears on TCLK12 to the time TMR1 or TMR2 is actually incremented. For the external clock input timing requirements, see the Electrical Speciﬁcation section.

FIGURE 13-4: TIMER1 AND TIMER2 IN TWO 8-BIT TIMER/COUNTER MODE

Fosc/4

RB4/TCLK12

TMR1ON (TCON2<0>)

TMR1CS (TCON1<0>)

TMR1

PR1

Reset

Equal

Set TMR1IF (PIR1<4>)

Comparator<8>Comparator x8

Fosc/4

TMR2ON (TCON2<1>)

TMR2CS (TCON1<1>)

TMR2

PR2

Reset

Equal

Set TMR2IF (PIR1<5>)

Comparator<8>Comparator x8

 1997 Microchip Technology Inc. Preliminary DS30264A-page 95

PIC17C75X

13.1.2 TIMER1 AND TIMER2 IN 16-BIT MODE To select 16-bit mode, set the T16 bit. In this mode

TMR2 and TMR1 are concatenated to form a 16-bit timer (TMR2:TMR1). The 16-bit timer increments until it matches the 16-bit period register (PR2:PR1). On the following timer clock, the timer value is reset to 0h, and the TMR1IF bit is set.

When selecting the clock source for the16-bit timer , the TMR1CS bit controls the entire 16-bit timer and TMR2CS is a “don’t care”, however ensure that TMR2ON is set (allows TMR2 to increment). When TMR1CS is clear, the timer increments once every instruction cycle (Fosc/4). When TMR1CS is set, the timer increments on every falling edge of the RB4/TCLK12 pin. For the 16-bit timer to increment, both TMR1ON and TMR2ON bits must be set (Table 13-2).

TABLE 13-2: TURNING ON 16-BIT TIMER

T16 TMR2ON TMR1ON Result

11 116-bit timer

(TMR2:TMR1) ON

10 1Only TMR1 increments 1x 016-bit timer OFF 01 1Timers in 8-bit mode

13.1.2.1 EXTERNAL CLOCK INPUT FOR TMR2:TMR1

When TMR1CS is set, the 16-bit TMR2:TMR1 increments on the falling edge of clock input TCLK12. The input on the RB4/TCLK12 pin is sampled and synchronized by the internal phase clocks twice every instruction cycle. This causes a delay from the time a falling edge appears on RB4/TCLK12 to the time TMR2:TMR1 is actually incremented. For the external clock input timing requirements, see the Electrical Speciﬁcation section.

FIGURE 13-5: TMR2 AND TMR1 IN 16-BIT TIMER/COUNTER MODE

RB4/TCLK12

Fosc/4

TMR1ON (TCON2<0>)

TMR1CS (TCON1<0>)

TMR1 x 8

PR1 x 8

Reset

Equal

Set Interrupt TMR1IF

(PIR1<4>)

Comparator<8>

Comparator x16

TMR2 x 8

PR2 x 8

MSB LSB

PIC17C75X

DS30264A-page 96 Preliminary  1997 Microchip Technology Inc.

TABLE 13-3: SUMMARY OF TIMER1 AND TIMER2 REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on all

other resets

(Note1)

16h, Bank 3 TCON1

CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000

17h, Bank 3 TCON2

CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000

16h, Bank 7 TCON3 — CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000 10h, Bank 2 TMR1 Timer1’s register xxxx xxxx uuuu uuuu 11h, Bank 2 TMR2 Timer2’s register xxxx xxxx uuuu uuuu 16h, Bank 1 PIR1

RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF 0000 0010 0000 0010

17h, Bank 1 PIE1

RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000

07h, Unbanked INTSTA PEIF

T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000

06h, Unbanked CPUSTA — — STKAV GLINTD TO PD POR BOR --11 1100 --11 qq11 14h, Bank 2 PR1 Timer1 period register xxxx xxxx uuuu uuuu 15h, Bank 2 PR2 Timer2 period register xxxx xxxx uuuu uuuu 10h, Bank 3 PW1DCL DC1 DC0

— — — — — — xx-- ---- uu-- ----

11h, Bank 3 PW2DCL DC1 DC0 TM2PW2

— — — — — xx0- ---- uu0- ----

10h, Bank 7 PW3DCL DC1 DC0 TM2PW3

— — — — — xx0- ---- uu0- ---- 12h, Bank 3 PW1DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu 13h, Bank 3 PW2DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu 11h, Bank 7 PW3DCH DC9 DC8 DC7 DC6 DC5 DC4 DC3 DC2 xxxx xxxx uuuu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented read as a '0', q - value depends on condition,

shaded cells are not used by Timer1 or Timer2.

Note 1: Other (non power-up) resets include: external reset through MCLR

and WDT Timer Reset.

 1997 Microchip Technology Inc. Preliminary DS30264A-page 97

PIC17C75X

13.1.3 USING PULSE WIDTH MODULATION (PWM) OUTPUTS WITH TIMER1 AND TIMER2

Three high speed pulse width modulation (PWM) outputs are provided. The PWM1 output uses Timer1 as its time-base, while PWM2 and PWM3 may independently be software conﬁgured to use either Timer1 or Timer2 as the time-base. The PWM outputs are on the RB2/PWM1, RB3/PWM2, and RG5/PWM3 pins.

Each PWM output has a maximum resolution of 10-bits. At 10-bit resolution, the PWM output frequency is 32.2 kHz (@ 32 MHz clock) and at 8-bit resolution the PWM output frequency is 128.9 kHz. The duty cycle of the output can vary from 0% to 100%.

Figure 13-6 shows a simpliﬁed block diagram of a PWM module.

The duty cycle registers are double buffered for glitch free operation. Figure 13-7 shows how a glitch could occur if the duty cycle registers were not double buffered.

The user needs to set the PWM1ON bit (TCON2<4>) to enable the PWM1 output. When the PWM1ON bit is set, the RB2/PWM1 pin is conﬁgured as PWM1 output and forced as an output irrespective of the data direction bit (DDRB<2>). When the PWM1ON bit is clear, the pin behaves as a port pin and its direction is controlled by its data direction bit (DDRB<2>). Similarly, the PWM2ON (TCON2<5>) bit controls the conﬁguration of the RB3/PWM2 pin and the PWM3ON (TCON3<0>) bit controls the conﬁguration of the RG5/PWM3 pin.

FIGURE 13-6: SIMPLIFIED PWM BLOCK

DIAGRAM

PWxDCH

Duty Cycle registers

PWxDCL<7:6>

Clear Timer, PWMx pin and Latch D.C.

(Slave)

Comparator

TMRx

Comparator

PRy

(Note 1)

RSQ

PWMxON

PWMx

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock

or 2 bits of the prescaler to create 10-bit time-base.

Read

Write

FIGURE 13-7: PWM OUTPUT

010203040 0

PWM output

Timer interrupt

Write new PWM value

Timer interrupt new PWM value transferred to slave

Note The dotted line shows PWM output if duty cycle registers were not double buffered.

If the new duty cycle is written after the timer has passed that value, then the PWM does not reset at all during the current cycle causing a “glitch”.

In this example, PWM period = 50. Old duty cycle is 30. New duty cycle value is 10.

PIC17C75X

DS30264A-page 98 Preliminary  1997 Microchip Technology Inc.

13.1.3.1 PWM PERIODS The period of the PWM1 output is determined by

Timer1 and its period register (PR1). The period of the PWM2 and PWM3 outputs can be individually software conﬁgured to use either Timer1 or Timer2 as the time-base. For PWM2, when TM2PW2 bit (PW2DCL<5>) is clear, the time-base is determined by TMR1 and PR1, and when TM2PW2 is set, the time-base is determined by Timer2 and PR2. For PWM3, when TM2PW3 bit (PW3DCL<5>) is clear, the time-base is determined by TMR1 and PR1, and when TM2PW3 is set, the time-base is determined by Timer2 and PR2.

Running two different PWM outputs on two different timers allows different PWM periods. Running all PWMs from Timer1 allows the best use of resources b y freeing Timer2 to operate as an 8-bit timer. Timer1 and Timer2 can not be used as a 16-bit timer if any PWM is being used.

The PWM periods can be calculated as follows:

period of PWM1 = [(PR1) + 1] x 4T

OSC

period of PWM2 = [(PR1) + 1] x 4TOSC or

[(PR2) + 1] x 4T

OSC

period of PWM3 = [(PR1) + 1] x 4TOSC or

[(PR2) + 1] x 4T

OSC

The duty cycle of PWMx is determined by the 10-bit value DCx<9:0>. The upper 8-bits are from register PWxDCH and the lower 2-bits are from PWxDCL<7:6> (PWxDCH:PWxDCL<7:6>). Table 13-4 shows the maximum PWM frequency (F

PWM) given the value in

the period register. The number of bits of resolution that the PWM can

achieve depends on the operation frequency of the device as well as the PWM frequency (F

PWM).

Maximum PWM resolution (bits) for a given PWM frequency:

where: F

PWM = 1 / period of PWM

The PWMx duty cycle is as follows:

PWMx Duty Cycle =(DCx) x T

OSC

where DCx represents the 10-bit value from PWxDCH:PWxDCL.

log

(

FPWM

log (2)

OSC

)

bits

If DCx = 0, then the duty cycle is zero. If PRx = PWxDCH, then the PWM output will be low for one to four Q-clock (depending on the state of the PWxDCL<7:6> bits). For a Duty Cycle to be 100%, the PWxDCH value must be greater then the PRx value.

The duty cycle registers for both PWM outputs are double buffered. When the user writes to these registers, they are stored in master latches. When TMR1 (or TMR2) overﬂows and a new PWM period begins, the master latch values are transferred to the sla v e latches and the PWMx pin is forced high.

The user should also avoid any "read-modify-write" operations on the duty cycle registers, such as: ADDWF PW1DCH. This may cause duty cycle outputs that are unpredictable.

TABLE 13-4: PWM FREQUENCY vs.

RESOLUTION AT 33 MHz

13.1.3.2 PWM INTERRUPTS The PWM modules makes use of the TMR1 and/or

TMR2 interrupts. A timer interrupt is generated when TMR1 or TMR2 equals its period register and on the following increment is cleared to zero. This interrupt also marks the beginning of a PWM cycle. The user can write new duty cycle values before the timer roll-over. The TMR1 interrupt is latched into the TMR1IF bit and the TMR2 interrupt is latched into the TMR2IF bit. These ﬂags must be cleared in software.

Note: For PW1DCH, PW1DCL, PW2DCH,

PW2DCL, PW3DCH and PW3DCL registers, a write operation writes to the "master latches" while a read operation reads the "slave latches". As a result, the user may not read back what was just written to the duty cycle registers.

PWM

Frequency

Frequency (kHz)

32.2 64.5 90.66 128.9 515.6

PRx Value 0xFF 0x7F 0x5A 0x3F 0x0F High

Resolution

10-bit 9-bit 8.5-bit 8-bit 6-bit

Standard Resolution

8-bit 7-bit 6.5-bit 6-bit 4-bit

 1997 Microchip Technology Inc. Preliminary DS30264A-page 99

PIC17C75X

13.1.3.3 EXTERNAL CLOCK SOURCE

The PWMs will operate regardless of the clock source of the timer. The use of an external clock has ramiﬁcations that must be understood. Because the external TCLK12 input is synchronized internally (sampled once per instruction cycle), the time TCLK12 changes to the time the timer increments will vary by as much as 1T

(one instruction cycle). This will cause jitter in the duty cycle as well as the period of the PWM output.

This jitter will be ±1T

CY, unless the external clock is

synchronized with the processor clock. Use of one of the PWM outputs as the clock source to the TCLK12 input, will supply a synchronized clock.

In general, when using an external clock source for PWM, its frequency should be much less than the device frequency (Fosc).

13.1.3.3.1 MAX RESOLUTION/FREQUENCY FOR EXTERNAL CLOCK INPUT

The use of an external clock for the PWM time-base (Timer1 or Timer2) limits the PWM output to a maximum resolution of 8-bits. The PWxDCL<7:6> bits must be kept cleared. Use of any other value will distort the PWM output. All resolutions are supported when internal clock mode is selected. The maximum attainable frequency is also lower. This is a result of the timing requirements of an external clock input for a timer (see the Electrical Speciﬁcation section). The maximum PWM frequency, when the timers clock source is the RB4/TCLK12 pin, as shown in Table 13-4 (standard resolution mode).

TABLE 13-5: REGISTERS/BITS ASSOCIATED WITH PWM

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

POR,

BOR

Value on all

other

resets

(Note1)

16h, Bank 3 TCON1

CA2ED1 CA2ED0 CA1ED1 CA1ED0 T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000 17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000 16h, Bank 7 TCON3 — CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON -000 0000 -000 0000

10h, Bank 2 TMR1 Timer1’s register xxxx xxxx uuuu uuuu 11h, Bank 2 TMR2 Timer2’s register xxxx xxxx uuuu uuuu 16h, Bank 1 PIR1

RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF 0000 0010 0000 0010

17h, Bank 1 PIE1

RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000

07h, Unbanked INTSTA PEIF

T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000

— — — — — — xx-- ---- uu-- ----

11h, Bank 3 PW2DCL DC1 DC0 TM2PW2

— — — — — xx0- ---- uu0- ----

10h, Bank 7 PW3DCL DC1 DC0 TM2PW3

Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends on conditions,

shaded cells are not used by PWM Module.

Note 1: Other (non power-up) resets include: external reset through MCLR

and WDT Timer Reset.

PIC17C75X

DS30264A-page 100 Preliminary  1997 Microchip Technology Inc.

13.2 Timer3

Timer3 is a 16-bit timer consisting of the TMR3H and TMR3L registers. TMR3H is the high byte of the timer and TMR3L is the low byte. This timer has an associated 16-bit period register (PR3H/CA1H:PR3L/CA1L). This period register can be software conﬁgured to be a another 16-bit capture register.

When the TMR3CS bit (TCON1<2>) is clear, the timer increments every instruction cycle (Fosc/4). When TMR3CS is set, the counter increments on every falling edge of the RB5/TCLK3 pin. In either mode, the TMR3ON bit must be set for the timer/counter to increment. When TMR3ON is clear, the timer will not increment or set ﬂag bit TMR3IF.

Timer3 has two modes of operation, depending on the CA1/PR3

bit (TCON2<3>). These modes are:

• Three capture and one period register mode

• Four capture register mode The PIC17C75X has up to four 16-bit capture registers

that capture the 16-bit value of TMR3 when events are detected on capture pins. There are four capture pins

(RB0/CAP1, RB1/CAP2, RG4/CAP3, and RE3/CAP4), one for each capture register pair . The capture pins are multiplexed with the I/O pins. An event can be:

• A rising edge

• A falling edge

• Every 4th rising edge

• Every 16th rising edge Each 16-bit capture register has an interrupt ﬂag asso-

ciated with it. The ﬂag is set when a capture is made. The capture modules are truly part of the Timer3 block. Figure 13-8 and Figure 13-9 show the block diagrams for the two modes of operation.

13.2.1 THREE CAPTURE AND ONE PERIOD REGISTER MODE

In this mode registers PR3H/CA1H and PR3L/CA1L constitute a 16-bit period register. A block diagram is shown in Figure 13-8. The timer increments until it equals the period register and then resets to 0000h on the next timer clock. TMR3 Interrupt Flag bit (TMR3IF) is set at this point. This interrupt can be disabled by clearing the TMR3 Interrupt Enable bit (TMR3IE). TMR3IF must be cleared in software.

FIGURE 13-8: TIMER3 WITH THREE CAPTURE AND ONE PERIOD REGISTER BLOCK DIAGRAM

PR3H/CA1H

TMR3H

Comparator<8>

Fosc/4

TMR3ON

Reset

Equal

Comparator x16

RB5/TCLK3

Set TMR3IF

TMR3CS

PR3L/CA1L

TMR3L

CA2H CA2L

RB1/CAP2

Edge select,

Prescaler select

Set CA2IF

Capture2

CA2ED1: CA2ED0 (TCON1<7:6>)

(TCON2<2>)

(TCON1<2>)

(PIR1<3>)

(PIR1<6>)

Enable

CA3H CA3L

RG4/CAP3

Edge select,

Prescaler select

Set CA3IF

Capture3

CA3ED1: CA3ED0 (TCON3<2:1>)

(PIR2<2>)

Enable

CA4H CA4L

RE3/CAP4

Edge select,

Prescaler select

Set CA4IF

Capture4

CA4ED1: CA4ED0 (TCON3<4:3>)

(PIR2<3>)

Enable

Microchip Technology Inc PIC17C752-08-PT, PIC17C752-08-SP, PIC17C752-08I-JW, PIC17C752-08I-L, PIC17C752-08I-P Datasheet

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