Microchip Technology Inc PIC16LF77-I-P Datasheet

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 2000 Microchip Technology Inc. Advance Information DS30325A-page 1

PIC16F7X

Devices Included in this Data Sheet:

Microcontroller Core Features:

• High-performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program branches which are two cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• Up to 8K x 14 words of FLASH Program M em ory, Up to 368 x 8 bytes of Data Memory (RAM)

• Pinout compatible to the PIC16C73B/74B/76/77

• Pinout compatible to the PIC16F873/874/876/877

• Interrupt capability (up to 12 sources)

• Eight level deep hardware stack

• Direct, Indirect and Relative Addressing modes

• Power-o n Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC oscillator for relia ble operation

• Programmable code protection

• Power saving SLEEP mode

• Selectable oscillator options

• Low power, high speed CMO S F LASH tech no log y

• Fully static design

• In-Circuit Serial Programming (ICSP) via two pins

• Processor read access to program memory

• Wide operating voltage range: 2.0V to 5.5V

• High Sink/Source Current: 25 mA

• Industrial temperature range

• Low power consumption:

- < 2 mA typical @ 5V, 4 MHz

-20 µA typical @ 3V, 32 kHz

-< 1 µA typical standby current

Pin Diagram

Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler, can be incremented during SLEEP via external crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler

• Two Capture, Compare , PWM modules

- Capture is 16-bit, max. resolution is 12.5 ns

- Compare is 16-bit, max. resolution is 200 ns

- PWM max. resolution is 10-bit

• 8-bit multi-channel Analog-to-Digital converter

• Synchronous Serial Port (SSP) with SPI



(Master

mode) and I

2C

(Slave)

• Universal Synchronous Asynchronous Receiver Transmitter (USART/SCI)

• Parallel Slave Port (PSP) 8-bits wide, with external RD

, WR and CS controls (40/44-pin only)

• Brown-out detection circuitry for Brown-out Reset (BOR)

•PIC16F73

•PIC16F74

•PIC16F76

•PIC16F77

RB7 RB6 RB5 RB4 RB3 RB2

RB1 RB0/INT V

VSS RD7/PSP7 RD6/PSP6

RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2

MCLR/VPP

RA0/AN0 RA1/AN1

RA2/AN2

RA3/AN3/V

REF

RA4/T0CKI

RA5/AN4/SS

RE0/RD/AN5

RE1/WR/AN6

RE2/CS

/AN7

VDD VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RD0/PSP0 RD1/PSP1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21

PIC16F77/74

PDIP

28/40-Pin 8-Bit CMOS FLASH Microcontrollers

PIC16F7X

DS30325A-page 2 Advance Information  2000 Microchip Technology Inc.

Pin Diagrams

PIC16F76/73

10 11

2 3 4 5 6

12 13 14

22 21

MCLR/VPP

RA0/AN0 RA1/AN1 RA2/AN2

RA3/AN3/V

REF

RA4/T0CKI

RA5/AN4/SS

VSS

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

RC2/CCP1

RC3/SCK/SCL

RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0/INT V

VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA

10 11 12 13 14 15 16 17

181920212223242526

65432

PIC16F77

RA4/T0CKI

RA5/AN4/SS

RE0/RD/AN5

OSC1/CLKIN

OSC2/CLKOUT

RC0/T1OSO/T1CK1

RE1/WR

/AN6

RE2/CS

/AN7

VSS

RB3 RB2 RB1 RB0/INT V

VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

MCLR

/VPP

RB7

RB6

RB5

RB4

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2

10 11

2 3 4 5 6

1819202122

121314

4443424140

363435

PIC16F77

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

MCLR

/VPP

RB7

RB6

RB5

RB4

RC6/TX/CK

RC5/SDO

RC4/SDI/SDA

RD3/PSP3

RD2/PSP2

RD1/PSP1

RD0/PSP0

RC3/SCK/SCL

RC2/CCP1

RC1/T1OSI/CCP2

NC RC0/T1OSO/T1CKI OSC2/CLKOUT OSC1/CLKIN V

VDD RE2/AN7/CS RE1/AN6/WR RE0/AN5/RD RA5/AN4/SS RA4/T0CKI

RC7/RX/DT

RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7

VDD

RB0/INT

RB1 RB2 RB3

PLCC

QFP

DIP, SOIC, SSOP

PIC16F74

 2000 Microchip Technology Inc. Advance Information DS30325A-page 3

PIC16F7X

Key Features

PICmicro™ Mid-Range Reference Manual

(DS33023)

PIC16F73 PIC16F74 PIC16F76 PIC16F77

Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz RESETS (and Delays) POR, BOR

(PWRT, OST)

POR, BOR

(PWRT, OST)

POR, BOR

(PWRT, OST)

POR, BOR

(PWRT, OST)

FLASH Program Memory (14-bit words, 100 E/W cycles)

4K 4K 8K 8K

Data Memory (bytes) 192 192 368 368 Interrupts 11 12 11 12 I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E Timers 3333 Capture/Compare/PWM Modules 2 2 2 2 Serial Communications SSP, USART SSP, USART SSP, USART SSP, USART Parallel Communications — PSP — PSP

8-bit Analog-to-Digital Module 5 Input Channels 8 Input Channels 5 Input Channels 8 Input Channels Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions

PIC16F7X

DS30325A-page 4 Advance Information  2000 Microchip Technology Inc.

Table of Contents

1.0 Device Overview............................................................................................................................................................5

2.0 Memory Organization .................................................................................................................................................. 11

3.0 I/O Ports............ ...........................................................................................................................................................29

4.0 Reading Program Memory........................................................................................... .... .... ........................................41

5.0 Timer0 Module.............................................................................................................................................................45

6.0 Timer1 Module.............................................................................................................................................................49

7.0 Timer2 Module.............................................................................................................................................................53

8.0 Capture/Compare/PWM Modules................................................................................................................................55

9.0 Synchronous Serial Port (SSP) Module.......................................................................................................................61

10.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ......................................................................73

11.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................... 89

12.0 Special Featur e s of th e CPU.................. ................................................................. ....................................................95

13.0 Instruction Set Summary ...........................................................................................................................................111

14.0 Development Support................................................................................................................................................119

15.0 Electrical Characteristics ........................................................................................................................................... 125

16.0 DC and AC Characteristics Graphs and Tables ........................................................................................................147

17.0 Packaging Infor mation................................................................................................. ..............................................149

Appendix A: Revision History.........................................................................................................................................................157

Appendix B: Device Differences.....................................................................................................................................................157

Appendix C: Conversion Considerations .................................................................... .... .. .. .... ....... .. .............................................. 157

Index ..................................................................................................................................................................................................159

On-Line Support.................................................................... .... .. .... ......... .. .... .... .. ......... .. ...................................................................165

Reader Response.............................................................................................................................................................................. 166

PIC16F7X Product Identification System...........................................................................................................................................167

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with t he best documentation possible to ensure successful us e of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax t he Reader Response Form in the back of this data sheet to (480) 786-

7578. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:

http://www.microchip.com

You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies.

To determine if an errata sheet exists for a particular device, please check with one of the following:

• Microchip’s Worldwide Web site; http://www.microchip.com

• Your local Microchip sales office (see last page)

• The Microchip Corporate Literature Center; U.S. FAX: (480) 786-7277

When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.

Customer Notification System

 2000 Microchip Technology Inc. Advance Information DS30325A-page 5

PIC16F7X

1.0 DEVICE OVERVIEW

This document contains device specific information. Additional information m ay be found in the PICm ic ro™ Mid-Range Reference Manual (DS33023), which may be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The Reference Manual should be considered a complementary documen t to thi s dat a she et, and is hig hly re commended reading for a better understanding of the device architecture and operation of the peripheral modules.

There are four devices (PIC16F73, PIC16F74, PIC16F76 an d PIC16F 77) co vered by this da ta sheet . The PIC16F76/73 dev ices are available in 28-pin pack ages and the PIC16F77/74 devices are available in 40-pin packages. The 28-pin devices do not have a Parallel Slave Port implemented.

The following two figures are device block diagrams sorted by pin number; 28-pin for Figure 1-1 and 40-pin for Figure 1-2. The 28-pin and 40-pin pinouts are liste d in Table 1-1 and Table 1-2, respectively.

FIGURE 1-1: PIC16F73 AND PIC16F76 BLOCK DIAGRAM

FLASH

Program

Memory

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr

RAM Addr (1)

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN OSC2/CLKOUT

MCLR

VDD, VSS

PORTA

PORTB

PORTC

RA4/T0CKI RA5/AN4/SS

RB0/INT

RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1

RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT

Brown-out

Reset

Note 1: Higher order bits are from the STATUS register.

USART

CCP1,2

Synchronous

8-bit A/DTimer0 Timer1 Timer2

Serial Port

RA3/AN3/VREF

RA2/AN2/

RA1/AN1

RA0/AN0

RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD

Device

Program

FLASH

Data Memory

PIC16F73 4K 192 Bytes PIC16F76 8K 368 Bytes

PIC16F7X

DS30325A-page 6 Advance Information  2000 Microchip Technology Inc.

FIGURE 1-2: PIC16F74 AND PIC16F77 BLOCK DIAGRAM

FLASH

Program

Memory

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr

RAM Addr (1)

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN OSC2/CLKOUT

MCLR

VDD, VSS

PORTA

PORTB

PORTC

PORTD

PORTE

RA4/T0CKI RA5/AN4/SS

RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT

RE0/AN5/RD RE1/AN6/WR

RE2/AN7/CS

Brown-out

Reset

Note 1: Higher order bits are from the STATUS register.

USART

CCP1,2

Synchronous

8-bit A/DTimer0 Timer1 Timer2

Serial Port

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

Parallel Slave Port

RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD

Device

Program

FLASH

Data Memory

PIC16F74 4K 192 Bytes PIC16F77 8K 368 Bytes

RD0/PSP0 RD1/PSP1 RD2/PSP2

RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7

 2000 Microchip Technology Inc. Advance Information DS30325A-page 7

PIC16F7X

T ABLE 1-1: PIC16F73 AND PIC16F76 PINOUT DESCRIPTION

Pin Name

DIP

Pin#

SSOP

SOIC

Pin#

I/O/P Type

Buffer

Type

Description

OSC1/CLKIN 9 9 I ST/CMOS

(3)

Oscillator crystal input/external clock sour ce input.

OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in Crys-

tal Oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denote s the ins tr uctio n cycle rate.

MCLR

/VPP 1 1 I/P ST Master clear (RESET) input or programming voltage input or High

Voltage Test mode control. This pin is a n ac tive low RESET to the device.

PORTA is a bi-directional I/O port. RA0/AN0 2 2 I/O TTL RA0 can also be analog input0. RA1/AN1 3 3 I/O TTL RA1 can also be analog input1. RA2/AN2 4 4 I/O TTL RA2 can also be analog input2. RA3/AN3/V

REF 5 5 I/O TTL RA3 can also be analog input3 or analog reference voltage.

RA4/T0CKI 6 6 I/O ST RA4 ca n also be th e clock input t o the T ime r0 module. Ou tput

is open drain type.

RA5/SS/

AN4 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the

synchronous serial port.

PORTB is a bi-directio nal I/O port. PORTB can be software

programmed for internal weak pull-up on all inputs. RB0/INT 21 21 I/O

TTL/ST

(1)

RB0 can also be the external interrupt pin.

RB1 22 22 I/O TTL RB2 23 23 I/O TTL RB3 24 24 I/O TTL RB4 25 25 I/O TTL Interrupt-on-change pin. RB5 26 26 I/O TTL Interrupt-on-change pin. RB6 27 27 I/O

TTL/ST

(2)

Interrupt-on-change pin or Serial programming clock.

RB7 28 28 I/O

TTL/ST

(2)

Interrupt-on-change pi n or Serial programming data.

PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock

input.

RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Time r1 oscillator i nput or Capture2 in put/

Compare2 output/P WM2 output.

RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Comp are1 outpu t/PWM1

output.

RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/ou tput f or

both SPI and I

C modes.

RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or

Data I/O (I

C mode). RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or

Synchronous Clock.

RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or

Synchronous Data.

SS 8, 19 8, 19 P — Ground reference for logic and I/O pins.

DD 20 20 P — Positive supply for logic and I/O pins.

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

PIC16F7X

DS30325A-page 8 Advance Information  2000 Microchip Technology Inc.

TABLE 1-2: PIC16F74 AND PIC16F77 PINOUT DESCRIPTION

Pin Name

DIP

Pin#

PLCC

Pin#

QFP Pin#

I/O/P Type

Buffer

Type

Description

OSC1/CLKIN 13 14 30 I

ST/CMOS

(4)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in

Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.

MCLR

/VPP 1 2 18 I/P ST Master clear (RESET) input or programming voltage input or

High Voltage Test mode control. This pin is an activ e low RESET to the device.

PORTA is a bi-directiona l I/ O po r t. RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input0. RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input1. RA2/AN2 4 5 21 I/O TTL RA2 can also be analog input2. RA3/AN3/V

REF 5 6 22 I/O TTL RA3 can also be analog input3 or analog reference

voltage.

RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/

counter. Output is open drain type.

RA5/SS/

AN4 7 8 24 I/O TTL RA5 can also be analog input4 or the slave select for the

synchronous serial port.

PORTB is a bi-directional I/O port. PORTB can be software

programmed for internal weak pul l-up on all inputs. RB0/INT 33 36 8 I/O

TTL/ST

(1)

RB0 can also be the external interrupt pin.

RB1 3 4 37 9 I/O TTL RB2 35 38 10 I/O TTL RB3 36 39 11 I/O TTL RB4 37 41 14 I/O TTL Interrupt-on-change pin. RB5 38 42 15 I/O TTL Interrupt-on-change pin. RB6 3 9 43 16 I/O

TTL/ST

(2)

Interrupt-on-change pin or Serial programming clock.

RB7 4 0 44 17 I/O

TTL/ST

(2)

Interrupt-on-change pin or Serial programming data.

PORTC is a bi-dir ec t i on al I/O port. RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1

clock input.

RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2

input/Compare2 output/PWM2 output.

RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/

PWM1 output.

RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchrono us ser ial cl ock input /output

for both SPI and I

C modes.

RC4/SDI/SDA 23 25 42 I/ O ST RC4 can also be the SP I D ata In (S PI mo d e) or

Data I/O (I

C mode). RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or

Synchronous Clock.

RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or

Synchronous Data.

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.

This buffer is a Schmitt Trigger input when used in Serial Programming mode.

3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Para llel Slave

Port mode (for interfacing to a microprocessor bus).

4: This buffer is a Schmitt Trigger input when conf igured in RC Oscillator mode and a CMOS input otherwise.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 9

PIC16F7X

PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microproces sor bus.

RD0/PSP0

19 21 38 I/O

ST/TTL

(3)

RD1/PSP1 20 22 39 I/O

ST/TTL

(3)

RD2/PSP2 21 23 40 I/O

ST/TTL

(3)

RD3/PSP3 22 24 41 I/O

ST/TTL

(3)

RD4/PSP4 27 30 2 I/O

ST/TTL

(3)

RD5/PSP5 28 31 3 I/O

ST/TTL

(3)

RD6/PSP6 29 32 4 I/O

ST/TTL

(3)

RD7/PSP7 30 33 5 I/O

ST/TTL

(3)

PORTE is a bi-directional I/ O port .

RE0/RD

/AN5 8925I/O

ST/TTL

(3)

RE0 can also be read control for the p ar allel slave port , or analog input5.

RE1/WR

/AN6 91026I/O

ST/TTL

(3)

RE1 can also be write cont rol for t he p a rallel s lave por t, o r analog input6.

RE2/CS

/AN7 10 11 27 I/O

ST/TTL

(3)

RE2 can also be select control for the parallel slave port, or analog input7.

SS 12,31 13,34 6,29 P — G r ound reference for logic and I/O pins.

DD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins.

— 1,17,28,4012,13,

33,34

— These pins are not internally connected. These pins should be

left unconnected.

T ABLE 1-2: PIC16F74 AND PIC16F77 PINOUT DESCRIPTION (CONTINUED)

Pin Name

DIP

Pin#

PLCC

Pin#

QFP Pin#

I/O/P Type

Buffer

Type

Description

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.

This buffer is a Schmitt Trigger input when used in Serial Programming mode.

3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave

Port mode (for interfacing to a microprocessor bus).

4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.

PIC16F7X

DS30325A-page 10 Advance Information  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. Advance Information DS30325A-page 11

PIC16F7X

2.0 MEMORY ORGANIZATION

There are two memory blocks in each of these PICmicro

MCUs. The Program Memory and Data Memory have separate buses so that concurrent access can oc cur and is detailed in this section. T he Program Mem ory can be read i ntern ally by user co de (see Section 4.0).

Additional informa tion on devi ce memory may be found in the PICmicro Mid-Range Reference Manual, (DS33023).

2.1 Program Memory Organization

The PIC16F7X devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. The PIC16 F77 /76 d evic es ha ve 8K x 14 wo rds of FLASH program memory and the PIC16F73/74 devices have 4K x 14. Ac cess ing a lo cati on ab ove t he physically implemented address will cause a wraparound.

The RESET Ve ctor is at 0000h an d the Interrup t V ector is at 0004h.

FIGURE 2-1: PIC16F77/76 PROGRAM

MEMORY MAP AND STACK

FIGURE 2-2: PIC16F74/73 PROGRAM

MEMORY MAP AND STACK

PC<12:0>

0000h

0004h

0005h

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-Chip

CALL, RETURN RETFIE, RETLW

1FFFh

Stack Level 2

Program

Memory

Page 0

Page 1

Page 2

Page 3

07FFh

0800h

0FFFh

1000h

17FFh

1800h

PC<12:0>

0000h

0004h

0005h

Stack Level 1

Stack Level 8

RESET Vector

Interrupt Vector

On-Chip

CALL, RETURN RETFIE, RETLW

1FFFh

Stack Level 2

Program Memory

Page 0

Page 1

07FFh

0800h

0FFFh

1000h

PIC16F7X

DS30325A-page 12 Advance Information  2000 Microchip Technology Inc.

2.2 Dat a Memory Organization

The Data Memory is partitioned into multiple banks, which contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits.

Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are Genera l Purpose Registers, implemented as static RAM. All implemented banks contain Special Function Registers. Some frequently used Special Function Registers from one bank may be mirrored in another bank for code reduction and quicker access.

2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be acces sed either directly, or indi-

rectly, through the File Select Register FSR.

RP1:RP0 Bank

00 0 01 1 10 2 11 3

 2000 Microchip Technology Inc. Advance Information DS30325A-page 13

PIC16F7X

FIGURE 2-3: PIC16F77/76 REGISTER F IL E MAP

Indirect addr.(*)

TMR0

PCL

ST ATUS

FSR

PORTA PORTB PORTC

PCLATH INTCON

PIR1

TMR1L TMR1H T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

OPTION_REG

PCL

ST ATUS

FSR TRISA TRISB TRISC

PCLATH INTCON

PIE1

PCON

PR2

SSPSTA T

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh

20h

A0h

7Fh

FFh

Bank 0

Bank 1

Unimplemented data memory locations, read as ’0’.

* Not a physical register.

Note 1: These registers are not impleme nte d on 28-pin devi ce s.

File

Address

Indirect addr.(*)

PCL

ST ATUS

FSR

PCLATH INTCON

PCL

STATUS

FSR

PCLATH INTCON

100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh

180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh

120h

1A0h

17Fh

1FFh

Bank 2

Bank 3

Indirect addr .(*)

PORTD

(1)

PORTE

(1)

TRISD

(1)

TRISE

(1)

TMR0

OPTION_REG

PIR2

PIE2

RCST A

TXREG

RCREG

CCPR2L

CCPR2H

CCP2CON

ADRES

ADCON0

TXSTA

SPBRG

ADCON1

General Purpose Register

1EFh 1F0h

accesses 70h - 7Fh

EFh F0h

accesses

70h-7Fh

16Fh 170h

accesses

70h-7Fh

General

Purpose Register

General Purpose Register

TRISB

PORTB

96 Bytes

80 Bytes 80 Bytes 80 Bytes

16 Bytes

PMDATA

PMADR

PMCON1

PMDATH

PMADRH

File

Address

File

Address

File

Address

SSPADD

PIC16F7X

DS30325A-page 14 Advance Information  2000 Microchip Technology Inc.

FIGURE 2-4: PIC16F74/73 REGISTER F IL E MAP

Indirect addr.(*)

TMR0

PCL

STATUS

FSR PORTA PORTB

PORTC

PCLATH INTCON

PIR1

TMR1L TMR1H T1CON

TMR2

T2CON

SSPBUF

SSPCON

CCPR1L

CCPR1H

CCP1CON

OPTION_REG

PCL

STATUS

FSR TRISA TRISB TRISC

PCLATH INTCON

PIE1

PCON

PR2

SSPSTA T

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh

20h

A0h

7Fh

FFh

Bank 0

Bank 1

File

Address

Indirect addr.(*)

PCL

ST ATUS

FSR

PCLATH INTCON

PCL

ST ATUS

FSR

PCLATH INTCON

100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh

180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh

17Fh

1FFh

Bank 2

Bank 3

Indirect addr.(*)

PORTD

(1)

PORTE

(1)

TRISD

(1)

TRISE

(1)

TMR0

OPTION_REG

PIR2

PIE2

RCST A TXREG

RCREG CCPR2L CCPR2H

CCP2CON

ADRES

ADCON0

TXSTA

SPBRG

ADCON1

General

Purpose Register

General Purpose Register

1EFh 1F0h

accesses

A0h - FFh

16Fh 170h

accesses

20h-7Fh

TRISB

PORTB

96 Bytes

10Ch 10Dh 10Eh 10Fh 110h

18Ch 18Dh 18Eh 18Fh 190h

PMDATA

PMADR

PMCON1

PMDATH PMADRH

Unimplemented data memory locations, read as ’0’.

* Not a physical register.

Note 1: These registers are not implemented on 28-pin devices.

120h

1A0h

File

Address

File

Address

File

Address

SSPADD

 2000 Microchip Technology Inc. Advance Information DS30325A-page 15

PIC16F7X

2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by

the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1.

The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral feature section.

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on

all other

RESETS

(2)

Bank 0

00h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000 0000 0000

01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu 02h

(4)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

03h

(4)

STATUS IRP RP1 RP0 TO PD ZDCC

0001 1xxx 000q quuu

04h

(4)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

05h PORTA — — PORT A Data Latch when written: PORTA pins when read

--0x 0000 --0u 0000

06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu

08h

(5)

PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu

09h

(5)

PORTE — — — — — RE2 RE1 RE0

---- -xxx ---- -uuu

0Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

0Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

0Ch PIR1

PSPIF

(3)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

0Dh PIR2 — — — — — — — CCP2IF

---- ---0 ---- ---0

0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

--00 0000 --uu uuuu

11h TMR2 Timer2 Module’s Register

0000 0000 0000 0000

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

-000 0000 -000 0000

13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register

xxxx xxxx uuuu uuuu

14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

0000 0000 0000 0000

15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB)

xxxx xxxx uuuu uuuu

17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0

--00 0000 --00 0000

18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D

0000 -00x 0000 -00x

19h TXREG USART Transmit Data Register

0000 0000 0000 0000

1Ah RCREG USART Receive Data Register

0000 0000 0000 0000

1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0

--00 0000 --00 0000

1Eh ADRES A/D Result Register Byte

xxxx xxxx uuuu uuuu

1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0

GO/

DONE

— ADON 0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ' 0', r = reserved.

Shaded locations are unimplem ented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose

contents are transf erred to the upper byte of the pr ogram counter.

2: Other (non power-up) RESETS include external RESET through MCLR

and Watchdog Timer Reset.

3: Bits PSPI E and PSPIF are re se r v e d on the 28-pin devi ces; always ma intain these bits cle a r. 4: These registers can be addressed from any bank. 5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’. 6: This bit always reads as a ‘1’.

PIC16F7X

DS30325A-page 16 Advance Information  2000 Microchip Technology Inc.

Bank 1

80h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000 0000 0000

81h

OPTION_ REG

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

82h

(4)

PCL Program Counter’s (PC) Least Significant Byte

0000 0000 0000 0000

83h

(4)

STATUS IRP RP1 RP0 TO PD ZDCC

0001 1xxx 000q quuu

84h

(4)

FSR Indirect data memory address pointer

xxxx xxxx uuuu uuuu

85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register

1111 1111 1111 1111

87h TRISC PORTC Data Direction Register

1111 1111 1111 1111

88h

(5)

TRISD PORTD Data Direction Register

1111 1111 1111 1111

89h

(5)

TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits

0000 -111 0000 -111

8Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

8Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

8Ch PIE1

PSPIE

(3)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

0000 0000 0000 0000

8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 8Eh PCON — — — — — — POR BOR

---- --qq ---- --uu

8Fh — Unimplemented

— —

90h — Unimplemented

— —

91h — Unimplemented

— —

92h PR2 Timer2 Period Register 1111 1111 1111 1111 93h SSPADD

Synchronous Serial Port (I

C mode) Address Register

0000 0000 0000 0000

94h SSPSTAT SMP CKE D/A PSR/WUA BF

0000 0000 0000 0000

95h — Unimplemented

— —

96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D

0000 -010 0000 -010

99h SPBRG Baud Rate Generator Register

0000 0000 0000 0000

9Ah — Unimplemented

— —

9Bh — Unimplemented

— —

9Ch — Unimplemented

— —

9Dh — Unimplemented — — 9Eh — Unimplemented

— —

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0

---- -000 ---- -000

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on

all other

RESETS

(2)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ' 0', r = reserved.

Shaded locations are unimplem ented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose

contents are transferred to the upper byte of the program counter.

2: Other (non power-up) RESETS include external RESET through MCLR

and Watchdog Timer Reset.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 17

PIC16F7X

Bank 2

100h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000 0000 0000

101h TMR0 Timer0 Module’s Register

xxxx xxxx uuuu uuuu

102h

(4)

PCL Program Counter's (PC) Least Significant Byte

0000 0000 0000 0000

103h

(4)

STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu

104h

(4)

FSR Indirect Data Memory Address Pointer

xxxx xxxx uuuu uuuu

105h — Unimplemented

— —

106h PORTB PORTB Data Latch when written: PORTB pins when read

xxxx xxxx uuuu uuuu

107h — Unimplemented

— —

108h — Unimplemented

— —

109h — Unimplemented — — 10Ah

(1,4)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

10Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

10Ch PMDATA Data Register Low Byte xxxx xxxx uuuu uuuu 10Dh PMADR Address Register Low Byte

xxxx xxxx uuuu uuuu

10Eh PMDATH — — Data Register High Byte

xxxx xxxx uuuu uuuu

10Fh PMADRH — — — Address Register High Byte

xxxx xxxx uuuu uuuu

Bank 3

180h

(4)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register)

0000 0000 0000 0000

181h

OPTION_ REG

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

1111 1111 1111 1111

182h

(4)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

183h

(4)

STATUS IRP RP1 RP0 TO PD Z DC C

0001 1xxx 000q quuu

184h

(4)

FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu

185h — Unimplemented

— —

186h TRISB PORTB Data Direction Register

1111 1111 1111 1111

187h — Unimplemented — — 188h — Unimplemented

— —

189h — Unimplemented

— —

18Ah

(1,4)

PCLATH — — —

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

18Bh

(4)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

18Ch PMCON1

—

(6)

— — — — — — RD

1--- ---0 1--- ---0

18Dh — Unimplemented — — 18Eh — Reserved maintain clear 0000 0000 0000 0000 18Fh — Reserved maintain clear

0000 0000 0000 0000

TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on

all other

RESETS

(2)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ' 0', r = reserved.

Shaded locations are unimplem ented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose

contents are transf erred to the upper byte of the pr ogram counter.

2: Other (non power-up) RESETS include external RESET through MCLR

and Watchdog Timer Reset.

PIC16F7X

DS30325A-page 18 Advance Information  2000 Microchip Technology Inc.

2.2.2.1 STATUS Register The STATUS register contains the arithmetic status of

the ALU, the RESET statu s and the b ank sele ct bit s for data memory.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, or C bits, then the wri te to these thre e bit s is disabled. These bit s are set or cleared ac cording to the device logic. Furthermore, the TO

and PD bits are not writable, therefore, the result of an instruction with the STATUS r egister as des tination may be different than intended.

For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This le aves the STATUS register as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, or DC bits from the STATUS register. For other in s tru ct i o ns not aff ec t ing a n y s tat us b its, s ee the "Instruction Set Summary."

Note 1: The C and DC bits operate as a borrow

and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO

PD ZDCC

bit 7 bit 0

bit 7 IRP: Register Bank Select bit (used fo r indirect addressing)

1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh)

bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes

bit 4 TO

: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

(for borrow

the polarity is reversed)

1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result

bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)

1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred

Note: For borrow

, the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2000 Microchip Technology Inc. Advance Information DS30325A-page 19

PIC16F7X

2.2.2.2 OPTION_REG Register The OPTION_REG register is a readable and writable

register , which cont ains various contr ol bits to conf igure the TMR0 prescaler/WDT postscaler (single assignable register k nown als o as th e presca ler), the Externa l INT Interrupt, TMR0 and the w eak pul l-up s on POR TB.

Note: To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to the Watchdog Timer.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RBPU

: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values

bit 6 INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin

bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin 0 = Internal in struction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Bit Value TMR0 Rate WDT Rate

PIC16F7X

DS30325A-page 20 Advance Information  2000 Microchip Technology Inc.

2.2.2.3 INTCON Register The INTCON register is a readable and writable regis-

ter, which contains various enable and flag bits for the TMR0 register overflow, RB Port change and External RB0/INT pin interrupts.

Note: Interrupt flag bits are set whe n an in terru pt

condition occurs, re gar dless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF

bit 7 bit 0

bit 7 GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts 0 = Disables all interr upts

bit 6 PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts

bit 5 T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4 INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt

bit 3 RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt

bit 2 T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow

bit 1 INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur

bit 0 RBIF: RB Port Change Interrupt Flag bit

A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared.

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2000 Microchip Technology Inc. Advance Information DS30325A-page 21

PIC16F7X

2.2.2.4 PIE1 Register The PIE1 register cont ains the ind ividual enable b its for

the peripheral interrupts.

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

bit 7 bit 0

bit 7 PSPIE

(1)

: Parallel Slave Port Read/Write Interrupt Enable bit

1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt

bit 6 ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D converter interrupt 0 = Disables the A/D converter interrupt

bit 5 RCIE: USART Receive Interrupt Enable bit

1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt

bit 4 TXIE: USART Transmit Interrupt Enable bit

1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt

bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt 0 = Disables the SSP interrupt

bit 2 CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt

bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt

bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt

Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear.

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F7X

DS30325A-page 22 Advance Information  2000 Microchip Technology Inc.

2.2.2.5 PIR1 Register The PIR1 register contains the individual flag bits for

the peripheral interrupts.

Note: Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should en sure the approp riate interrup t bits are cle ar pri or to en ab li ng an i nte rru pt.

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0

PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

bit 7 bit 0

bit 7 PSPIF

(1)

: Parallel Slave Port Read/Write Interrupt Flag bit

1 = A read or a write operatio n has taken place (must be cleare d in softwa r e) 0 = No read or write has occur red

bit 6 ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed 0 = The A/D conversion is not complete

bit 5 RCIF: USART Receive Interrupt Flag bit

1 = The USART receive buffer is full 0 = The USART receive buffer is empty

bit 4 TXIF: USART Transmit Interrupt Flag bit

1 = The USART transmit buffer is empty 0 = The USART transmit buffer is full

bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag

1 = The SSP interrupt condition has occ urre d, and mu st be cle ared in software before

returning from the Interrup t Se rv ic e Routine. The conditions that w ill set th is bi t are: SPI

A transmission/recept i on has taken place. I

C Slave A transmission/recept i on has taken place. I

C Master A transmission/recept i on has taken place. The initiated START condition was completed by the SSP module. The initiated STOP condition was completed by the SSP module. The initiated Restart condition was completed by the SSP module. The initiated Acknowledge condition was completed by the SSP module. A START condition occurred while the SSP module was idle (Multi-master system). A STOP condition occurred while the SSP module was idle (Multi-master system).

0 = No SSP interrupt c ondition has occurred.

bit 2 CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register ca pt ur e occurred (must be cleared i n software) 0 = No TMR1 register capt ur e oc curred

Compare Mode

1 = A TMR1 register co m pare m at ch occurred (must be cleared i n softw ar e) 0 = No TMR1 register compare match occurred

PWM Mode Unused in this mode

bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bi t

1 = TMR2 to PR2 match oc cur re d ( m ust be cleared in software) 0 = No TMR2 to PR2 match occurred

bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register over flow ed (must be cleared in softwa re ) 0 = TMR1 register did no t over f lo w

Note 1: PSPIF is reserved on 28-pin devi ces ; a lwa ys ma in tain this bi t cle ar.

Legend: R = Readable bit W = Writable bit U = Unimplemented b it, rea d as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is clear ed x = Bit is unknown

 2000 Microchip Technology Inc. Advance Information DS30325A-page 23

PIC16F7X

2.2.2.6 PIE2 Register The PIE2 register cont ains the ind ividual enable b its for

the CCP2 peripheral interrupt.

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — CCP2IE

bit 7 bit 0

bit 7-1 Unimplemented: Read as ’0’ bit 0 CCP2IE: CCP2 Interrupt Enable bit

1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F7X

DS30325A-page 24 Advance Information  2000 Microchip Technology Inc.

2.2.2.7 PIR2 Register The PIR2 register contains the flag bits for the CCP2

interrupt.

Note: Interrupt flag bits are set whe n an in terru pt

U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0

— — — — — — — CCP2IF

bit 7 bit 0

bit 7-1 Unimplemented: Read as '0' bit 0 CCP2IF: CCP2 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred

Compare Mode

1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred

PWM Mode Unused

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2000 Microchip Technology Inc. Advance Information DS30325A-page 25

PIC16F7X

2.2.2.8 PCON Register The Power Control (PCON) register contains flag bits

to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR

Reset.

Note: BOR is unknown on POR. It mus t be set by

the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurre d. The BOR st atus bit is a don’t care and is not predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the configuration word).

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1

— — — — — — POR BOR

bit 7 bit 0

bit 7-2 Unimplemented: Read as '0' bit 1 POR

: Power-on Reset Status bit

1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0 BOR: Brown-out Reset Status bit

1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F7X

DS30325A-page 26 Advance Information  2000 Microchip Technology Inc.

2.3 PCL and PCLATH

The program counter (PC) is 13-bits wid e. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLA TH reg ister. On any RESET, the up per bi t s of the PC will be cleared. Fig ure2-5 shows the two situations for the loading of th e PC. The up per ex ample in the fi gure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH). The lower exam pl e i n th e fi gure shows how the PC is load ed during a CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 2-5: LOADING OF PC IN

DIFFERENT SITUATIONS

2.3.1 COMPUTED GOTO A computed GOTO is accomplish ed b y a dding an offset

to the progr am counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercise d if the t able loca tion c rosse s a PCL memory boundary (each 256 byte block). Refer to the application note, “Implementing a Table Read" (AN556).

2.3.2 STACK The PIC16F7X family has an 8 -level de ep x 13-bi t wide

hardware s tack. The stack space is not part of either program or data space and the stack pointer is not readable or writabl e. The PC is PU SHed onto th e stac k when a CALL instruction is executed, or an interrupt causes a branch. The st ac k is POPed in the ev en t of a RETURN,RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buf fer . This means that after the st ack h as be en PU SHed ei ght ti mes, th e nin th push overwrites the v alue tha t was stor ed fro m the first push. The tenth push ov erw ri tes the second push (and so on).

2.4 Program Memory Paging

PIC16F7X devices are cap able of add ressing a co ntinuous 8K word block of program memory. The CALL and GOTO instructions provide only 11 bits of address to allow branching within any 2K program memory page. When doing a CALL or GOTO instruction , the upper 2 bits of the address are provided by PCLATH<4:3>. When doing a CALL or GOTO instruct ion , th e us er m us t ensure that t he page select bits are progra mmed so that the desired prog ram memory pa ge is addre ssed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack. Therefore, manipulation of the PCLATH<4:3> bits are not required for the return instructions (whi ch POPs the address from the stack).

Example 2-1 shows the calling of a subroutine in page 1 of the prog ram memory. This example assumes that PCLATH is saved and restored by the Interrupt Service Routine

(if interrupts are used).

EXAMPLE 2-1: CALL OF A SUBROUTINE IN

PAGE 1 FROM PAGE 0

ORG 0x500 BCF PCLATH,4 BSF PCLATH,3 ;Select page 1 (800h-FFFh) CALL SUB1_P1 ;Call subroutine in : ;page 1 (800h-FFFh) : ORG 0x900 ;page 1 (800h-FFFh)

SUB1_P1

: ;called subroutine : ;page 1 (800h-FFFh) : RETURN ;return to Call subroutine

;in page 0 (000h-7FFh)

12 8 7 0

PCLATH<4:0>

PCLATH

Instruction with

ALU

GOTO,CALL

Opcode <10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

PCLATH

PCH PCL

PCL as Destination

Note 1: There are no status bits to indicate stack

overflow or stack underflow conditions.

2: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW and RETFIE instructions or th e vectoring to an interrupt address.

Note: The contents of the PCLATH are

unchanged after a RETURN or RETFIE instruction is executed. The user must setup the PCLATH for any subsequent CALLS or GOTOS.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 27

PIC16F7X

2.5 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physica l register. Addressing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruc tion using the INDF register actual ly accesses the register pointed to by the File Sele ct Register, FSR. Reading the INDF register itself indirectly (FSR = ’0’) will read 00h. Writing to the INDF register indirectly result s in a no-operation (althoug h s t atu s bits may be affected ). An eff ective 9- bit add ress is obt ained by concatenating the 8 -bit FSR regi ster and the IRP bit (STATU S<7>), as shown in Figure 2-6.

A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2.

EXAMPLE 2-2: INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer movwf FSR ;to RAM

NEXT clrf INDF ;clear INDF register

incf FSR,F ;inc pointer btfss FSR,4 ;all done? goto NEXT ;no clear next

CONTINUE

: ;yes continue

FIGURE 2-6: DIRECT/INDIRECT ADDRESSING

Note 1: For register file map detail see Figure 2-3.

Data Memory

(1)

Indirect AddressingDirect Addressing

bank select location select

RP1:RP0 6

from opcode

IRP FSR register

bank select

location select

00 01 10 11

Bank 0 Bank 1 B ank 2 Bank 3

FFh

80h

7Fh

00h

17Fh

100h

1FFh

180h

PIC16F7X

DS30325A-page 28 Advance Information  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. Advance Information DS30325A-page 29

PIC16F7X

3.0 I/O P ORTS

Some pins for th ese I/O ports are mul tiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

Additional inform atio n o n I / O ports may be f oun d i n th e PICmicro™ Mid-Range Reference Manual, (DS33023).

3.1 PORTA and the TRISA Register

PORTA is a 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a TRISA bit (=1) will make t he co rrespon ding POR TA pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISA bit (=0) will make the correspondin g PORTA pin an output (i.e., put the contents of the output latch on the selected pin).

Reading the PORTA register reads the status of the pins, whereas writing to i t will wri te to th e po rt lat ch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are read, the value is modified and then written to the port data latch.

Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain outpu t. All other PORTA pins have TTL input levels and full CMOS output drivers.

Other PORTA pins are multiplexed with analog inputs and analog V

REF input. The operation of each pin is

selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1).

The TRISA register controls the direction of the RA pins, even when they ar e be ing us ed as ana lo g inp uts. The user must ensure the bit s in the TRISA regi ster are maintained set, when using them as analog inputs.

EXAMPLE 3-1: INITIALIZING PORTA

BCF STATUS, RP0 ; BCF STATUS, RP1 ; Bank0 CLRF PORTA ; Initialize PORTA by

; clearing output

; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0x06 ; Configure all pins MOVWF ADCON1 ; as digital inputs MOVLW 0xCF ; Value used to

; initialize data

; direction MOVWF TRISA ; Set RA<3:0> as inputs

; RA<5:4> as outputs

; TRISA<7:6> are always

; read as ’0’.

FIGURE 3-1: BLOCK DIAGRAM OF

RA3:RA0 AND RA5 PINS

FIGURE 3-2: BLOCK DIAGRAM OF RA4/

T0CKI PIN

Note: On a Power-on Reset, these pins a re con-

figured as analog inputs and read as '0'.

Data Bus

WR Port

WR TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

VDD

I/O pin

(1)

Note 1: I/O pins have protection diodes to VDD and VSS.

Analog Input Mode

TTL Input Buffer

To A/D Converter

Data Bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt Trigger Input Buffer

I/O pin

(1)

TMR0 clock input

Note 1: I/O pin has protection diodes to VSS only.

PIC16F7X

DS30325A-page 30 Advance Information  2000 Microchip Technology Inc.

TABLE 3-1: PORTA FUNCTIONS

TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit# Buffer Function

RA0/AN0 bit0 TTL Input/output or analog input. RA1/AN1 bit1 TTL Input/output or analog input. RA2/AN2 bit2 TTL Input/output or analog input. RA3/AN3/V

REF bit3 TTL Input/output or analog input or VREF.

RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type. RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input. Legend: TTL = TTL input, ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other

RESETS

05h PORTA

— — RA5 RA4 RA3 RA2 RA1 RA0

--0x 0000 --0u 0000

85h TRISA — — PORTA Data Direction Register

--11 1111 --11 1111

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0

---- -000 ---- -000

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.

Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of

the following modes where PCFG2:PCFG0 = 100, 101, 11x.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 31

PIC16F7X

3.2 P ORTB and the TRISB Register

PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (=1) will make the correspo nding POR TB pi n an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISB bit (=0) will make the corresponding POR TB pin an output (i.e., put the contents of the output latch on the selected pin).

Each of the PORTB pins has a we ak inte rnal pul l-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU

(OPTION_REG<7>). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset.

FIGURE 3-3: BLOCK DIAGRAM OF

RB3:RB0 PINS

Four of PORTB’s pins , RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear flag bit RBIF. A mismatch c ond it i on w i ll cont i n ue t o s et fl ag bi t RB IF.

Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared.

The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature.

This interrupt on mismatch feature, together with software configureable pull-ups on these four pins, allow easy interface to a keypad and make it possible for wake-up on key depression. Refer to the Embedded Control Handbook, “Implementing Wake-Up on Key Stroke” (AN552).

RB0/INT is an ext ernal i nterrupt input pin a nd is confi gured using the INTEDG bit (OPTION_REG<6>).

RB0/INT is discussed in detail in Section 12.10.1.

FIGURE 3-4: BLOCK DIAGRAM OF

RB7:RB4 PINS

Data Latch

RBPU

(2)

Data Bus

WR Port

WR TRIS

RD TRIS

RD Port

Weak Pull-up

RD Port

RB0/INT

I/O

(1)

TTL Input Buffer

Schmitt Trigger Buffer

TRIS Latch

Note 1: I/O pins have diode protection to V

DD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU

bit (OPTION_REG<7>).

Data Latch

From other

RBPU

(2)

I/O

Data Bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

Weak Pull-up

RD Port

Latch

TTL Input Buffer

(1)

Buffer

RB7:RB6 in Serial Programming mode

Note 1: I/O pins have diode protection to V

DD and VSS.

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the RBPU

bit (OPTION_REG<7>).

PIC16F7X

DS30325A-page 32 Advance Information  2000 Microchip Technology Inc.

TABLE 3-3: PORTB FUNCTIONS

TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Name Bit# Buffer Function

RB0/INT bit0 TTL/ST

(1)

Input/output pin or external interrupt input. Internal software

programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt-o n-change) . Internal soft ware progra mmable

weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt-o n-change) . Internal soft ware progra mmable

weak pull-up. RB6 bit6 TTL/ST

(2)

Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST

(2)

Input/output pin (with interrupt-on-change).

Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Val ue on :

POR, BOR

Value on all

other

RESETS

06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB 1 RB0

xxxx xxxx uuuu uuuu

86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h, 181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 33

PIC16F7X

3.3 P ORTC and the TRISC Register

PORTC is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corres ponding POR TC pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISC bit (=0) will make the corresponding PO RTC pin an output (i.e., p ut the contents of the output latch on the selected pin).

PORTC is multip lexed with s everal periphe ral function s (Table 3-5). PORTC pins have Schmitt Trigger input buffers.

When enabling peripheral functions, care should be taken in defining TRIS bit s fo r each POR T C pi n. Som e peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. Since the TRIS bit override is in effect while the peripheral is enabled, read-modifywrite instru ctions (BSF, BCF, XORWF) with TRISC as destination shoul d be avoided. The us er should refer to the corresponding peripheral section for the correct TRIS bit settings.

FIGURE 3-5: PORTC BLOCK DIAGRAM

(PERIPHERAL OUTPUT OVERRIDE)

TABLE 3-5: PORTC FUNCTIONS

TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC

Port/Peripheral Select

(2)

Data Bus

WR Port

WR TRIS

Data Latch

TRIS Latch

RD TRIS

Schmitt Trigger

QD Q

Peripheral Data Out

QD Q

VSS

Port

Peripheral OE

(3)

Peripheral Input

Note 1: I/O pins have diode protection to V

DD and VSS.

2: Port/Peripheral select signal selects between port data

and peripheral output.

3: Peripheral OE (output enable) is only activated if

peripheral select is active.

I/O

(1)

Name Bit# Buffer Type Function

RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI/CCP2 bit1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/

Compare2 output/PWM2 output. RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/C omp are1 ou tput/PWM1 output. RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I

modes. RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or Data I/O (I

C mode). RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output. RC6/TX/CK bit6 ST Input/output port pin or USART Asynchronous Transmit or

Synchronous Clock.

RC7/RX/DT bit7 ST Input/output port pin or USART Asynchronous Receive or

Synchronous Data.

Legend: ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on

all other RESETS

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0

xxxx xxxx uuuu uuuu

87h TRISC PORTC Data Direction Register

1111 1111 1111 1111

Legend: x = unknown, u = unchanged

PIC16F7X

DS30325A-page 34 Advance Information  2000 Microchip Technology Inc.

3.4 PORTD and TRISD Registers

This section is not applicable to the PIC16F73 or PIC16F76.

PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is in dividually co nfigureable as an in put or output.

PORTD can be configured as an 8-bit wide microprocessor port (parallel slave p ort) by setting c ontrol bit PSPMODE (TRISE<4>). In this mode, the input buf fers are TTL.

FIGURE 3-6: PORTD BLOCK DIAGRAM (IN

I/O PORT MODE)

TABLE 3-7: PORTD FUNCTIONS

TABLE 3-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Data Bus

WR Port

WR TRIS

RD Port

Data Latch

TRIS Latch

RD TRIS

Schmitt Trigger Input Buffer

I/O pin

(1)

Note 1: I/O pins have protection diodes to Vdd and Vss.

Name Bit# Buffer Type Function

RD0/PSP0 bit0

ST/TTL

(1)

Input/output port pin or parallel slave port bit0

RD1/PSP1 bit1

ST/TTL

(1)

Input/output port pin or parallel slave port bit1

RD2/PSP2 bit2

ST/TTL

(1)

Input/output port pin or parallel slave port bit2

RD3/PSP3 bit3

ST/TTL

(1)

Input/output port pin or parallel slave port bit3

RD4/PSP4 bit4

ST/TTL

(1)

Input/output port pin or parallel slave port bit4

RD5/PSP5 bit5

ST/TTL

(1)

Input/output port pin or parallel slave port bit5

RD6/PSP6 bit6

ST/TTL

(1)

Input/output port pin or parallel slave port bit6

RD7/PSP7 bit7

ST/TTL

(1)

Input/output port pin or parallel slave port bit7

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on all

other

RESETS

08h PORTD RD7 RD6 RD5 R D4 RD3 RD2 RD1 RD0

xxxx xxxx uuuu uuuu

88h TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction bits 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 35

PIC16F7X

3.5 PORTE and TRISE Register

This section is not applicable to the PIC16F73 or PIC16F76.

PORTE has three pins, RE0/RD

/AN5, RE1/WR/AN6

and RE2/CS

/AN7, which are indivi dua ll y configureable as inputs or outputs. These pins have Schmitt Trigger input buffers.

I/O PORTE becomes control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs). Ensure ADC ON1 is configure d for digital I/O. In this mode, the input buffers are TTL.

PORTE pins are multiplexed with analog inputs. When selected as an anal og input, thes e pins will re ad as ’0’s.

TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs.

FIGURE 3-7: PORTE BLOCK DIAGRAM (IN

I/O PORT MODE)

Note: On a Power-on Reset, these pins a re con-

figured as analog inputs and read as ‘0’.

Data Bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt Trigger Input Buffer

I/O pin

(1)

Note 1: I/O pins have protection diodes to Vdd and Vss.

PIC16F7X

DS30325A-page 36 Advance Information  2000 Microchip Technology Inc.

R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE

— bit2 bit1 bit0

bit 7 bit 0

bit 7 Parallel Slave Port Status/Control Bits

IBF: Input Buffer Full Status bit

1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received

bit 6 OBF: Output Buffer Full Status bit

1 = The output buffer still holds a previously written word 0 = The output buffer has been read

bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode)

1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred

bit 4 PSPMODE: Parallel Slave Port Mode Select bit

1 = Parallel Slave Port mode 0 = General Purpose I/O mode

bit 3 Unimplemented: Read as '0' bit 2 PORTE Data Direction Bits

Bit2: Direction Control bit for pin RE2/CS/AN7

1 = Input 0 = Output

bit 1 Bit1: Direction Control bit for pin RE1/WR/AN6

1 = Input 0 = Output

bit 0 Bit0: Direction Control bit for pin RE0/RD/AN5

1 = Input 0 = Output

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2000 Microchip Technology Inc. Advance Information DS30325A-page 37

PIC16F7X

TABLE 3-9: PORTE FUNCTIONS

TABLE 3-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE

Name Bit# Buffer Type Function

RE0/RD/AN5 bit0 ST/TTL

(1)

Input/output port pin or read co ntrol input in Parall el Slave Port mode or analog input: RD

1 =Idle 0 = Read operation. Con t en t s of PORTD register outpu t to PO RTD I/O

pins (if chip selected).

RE1/WR

/AN6 bit1 ST/TTL

(1)

Input/output port pin or write control input in Parallel Slave Port mode or analog input: WR

1 =Idle 0 =Write operation. Value of PORTD I/O pins latched into PORTD

RE2/CS

/AN7 bit2 ST/TTL

(1)

Input/output port pin or chip select control input in Parallel Slave Port mode or analog input: CS

1 = Device is not selected 0 = Device is selected

Legend: ST = Schmitt Trigger input, TTL = TTL input

Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port mode.

Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Val ue on :

POR, BOR

Value on all

other

RESETS

09h PORTE

— — — — — RE 2 RE1 RE0 ---- -xxx ---- -uuu

89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE.

PIC16F7X

DS30325A-page 38 Advance Information  2000 Microchip Technology Inc.

3.6 Parallel Slave Port

The Parallel Slave Port is not implemented on the PIC16F73 or PIC16F76.

PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port when control bit PSPMODE (TRISE<4>) is set. I n Sl av e mo de, it is asynchronousl y readable and writa ble by the ex ternal world throu gh RD control input pin RE0/RD and WR control input pin RE1/WR

It can directly interface to an 8-bit micr op roc essor data bus. The external mic roproc essor can read or w rite th e PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD

to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as input s (set). The A/D port configuration bits PCFG3:PCFG0 (ADCON1<3:0>) must be set to configure pins RE2:RE0 as digital I/O.

There are actually two 8-bit latches. One for data output and one for data input. The user writes 8-bit data to the PORTD data la tch and reads dat a from the port pin latch (note that they have the same address). In this mode, the TRISD registe r is ignore d, since the ext ernal device is controlling the direction of data flow.

A write to the PSP occurs when both the CS

and WR lines are first detected low. When either the CS or WR lines become high (l evel triggered) , the Input Buffe r Full (IBF) status flag bit (TRISE<7>) is set on the Q 4 cloc k cycle, following the next Q2 cycle, to signal the write is complete (Figure 3-9). The interrupt flag bit PSPIF (PIR1<7>) is also set on the same Q4 clock cycle. IBF can only be cleare d by reading the POR TD i nput latch. The Input Buffer Overflow (IBOV) status flag bit (TRISE<5>) is set if a second write to the PSP is attempted w hen the pre vious byte has not bee n read out of the b uffer.

A read from the PSP occurs when both the CS

and RD lines are first detected low. The Output Buffer Full (OBF) status flag bit (TRISE<6>) is cleared immediately (Figure 3-10) indicating that the PORTD latch is waiting to be read by the ext ernal bus. Whe n eithe r the CS

or RD pin becomes high ( level triggered), the interrupt flag bit PSPIF is set on the Q4 clock cycle, following the next Q2 cycle, indicating that the read is complete. OBF remains low until data is written to PORTD by the user firmware.

When not in PSP mode, the IBF an d O BF b its are held clear. However, if flag bit IBOV was previously set, it must be cleared in firmware.

An interrupt is generated and latched into flag bit PSPIF when a read or write operation is completed. PSPIF must be cleared by the us er in fi rmware and th e interrupt can be disabled by clearing the interrupt enable bit PSPIE (PIE1<7>).

FIGURE 3-8: PORTD AND PORTE BLOCK

DIAGRAM (PARALLEL SLAVE PORT)

Data Bus

WR Port

RDx

Port

One bit of PORTD

Set Interrupt Flag PSPIF (PIR1<7>)

Read

Chip Select

Write

Note: I/O pin has protection diodes to V

DD and VSS.

TTL

 2000 Microchip Technology Inc. Advance Information DS30325A-page 39

PIC16F7X

FIGURE 3-9: PARALLEL SLAVE PORT WRITE WAVEFORMS

FIGURE 3-10: PARALLEL SLAVE PORT READ WAVEFORMS

TABLE 3-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Q1 Q2 Q3 Q4CSQ1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

WR RD

IBF

OBF

PSPIF

PORTD<7:0>

Q1 Q2 Q3 Q4CSQ1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

IBF

PSPIF

OBF

PORTD<7:0>

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other

RESETS

08h PORTD Port data latch when written: Port pins when read

xxxx xxxx uuuu uuuu

09h PORTE — — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Da ta Di re ction Bits 0000 -111 0000 -111

0Ch PIR1

PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch PIE1

PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.

PIC16F7X

DS30325A-page 40 Advance Information  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. Advance Information DS30325A-page 41

PIC16F7X

4.0 READING PROGRAM MEMORY

The FLASH Program Memory is readable during normal operation over the entire V

DD range. It is indirectly

addressed through Special Function R egisters ( SFR). Up to 14-bit numbers can be stored in memory for use as calibration param eters, serial nu mbers, packe d 7-bit ASCII, etc. Execu ting a p rogram mem ory locati on containing data that forms an invalid instruction results in a NOP.

There are five SFRs used to read the program and memory. These registers are:

• PMCON1

• PMDATA

• PMDATH

• PMADR

• PMADRH

The program memory allows word reads. Program memory access allows for checksum calculation and reading calibration t abl es .

When interfacing to the program memory block, the PMDATH:PMDATA registers form a two byte word, which holds the 14-bit data for reads. The PMADRH:PMADR registers form a two byte word, which holds the 13-bit address of the FLASH location being accessed. These devices can have up to 8K words of program FLASH, with an address range from 0h to 3FFFh. The unused upper bits in both the PMDATH and PMADRH registers are not implemented and read as “0’s”.

4.1 PMADR

The address registers can address up to a maxim um of 8K words of program FLASH.

When selecting a program address value, the MSByte of the address is written to the PMADRH register and the LSByte is written to the PMADR regi ster . The upper MSbits of PMADRH must always be clear.

4.2 PMCON1 Register

PMCON1 is the control register for memory accesses. The control bit RD initiates read operations. This bit

cannot be cleared, only set, in sof twa re. It is cl eare d in hardware at the completion of the read operation.

R-1 U-0 U-0 U-0 U-x U-0 U-0 R/S-0

— — — — — — — RD

bit 7 bit 0

bit 7 Reserved: Read as ‘1’ bit 6-1 Unimplemented: Read as '0' bit 0 RD: Read Control bit

1 = Initiates a FLASH read, RD is cleared in hardware. The RD bit can only be set (not cleared) in software. 0 = Does not initiate a FLASH read

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F7X

DS30325A-page 42 Advance Information  2000 Microchip Technology Inc.

4.3 Reading the FLASH Program Memory

A program memory location may be read by wri ting two bytes of the address to the PMADR and PMADRH registers and then setting control bit RD (PMCON1<0>). Once the read control bit is set, the microcontroller will use the next two instruction cycl es to read the data. The

data is available in the PMDATA and PMDATH registers after the second NOP instruction. Therefore, it can be read as two bytes in the following instructions. The PMDATA and PMDATH registers will hold this value until another read operation.

EXAMPLE 4-1: FLASH PROGRAM READ

BSF STATUS, RP1 ;

BCF STATUS, RP0 ; Bank 2

MOVF ADDRH, W ;

MOVWF PMADRH ; MSByte of Program Address to read

MOVF ADDRL, W ;

MOVWF PMADR ; LSByte of Program Address to read

BSF STATUS, RP0 ; Bank 3

Required BSF PMCON1, RD ; EEPROM Read

Sequence

NOP ; memory is read in the next two cycles after BSF PMCON1,RD

NOP ;

BCF STATUS, RP0 ; Bank 2

MOVF PMDATA, W ; W = LSByte of Program PMDATA

MOVF PMDATH, W ; W = MSByte of Program PMDATA

 2000 Microchip Technology Inc. Advance Information DS30325A-page 43

PIC16F7X

4.4 Operation During Code Protect

FLASH program memory has its own code protect mechanism. External Read and Write operations are disabled if this mechanism is enabled.

The microcontroller can read and execute instructions out of the internal FLASH program memory, regardless of the state of the code protect configuration bits.

TABLE 4-1: REGISTERS ASSOCIATED WITH PROGRAM FLASH

AddressNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0

Value on:

POR,

BOR

Value on all other RESETS

10Dh PMADR Address Regis ter Low Byte

xxxx xxxx uuuu uuuu

10Fh PMADRH — — — Address Register High Byte

xxxx xxxx uuuu uuuu

10Ch PMDATA Data Register Low Byte

xxxx xxxx uuuu uuuu

10Eh PMDATH — — Data Register High Byte

xxxx xxxx uuuu uuuu

18Ch PMCON1 —

(1)

— — — — — — RD

1--- ---0 1--- ---0

Legend: x = unknown, u = unchang ed, r = re serv ed, - = unimplemented read as ’0’. Shaded cells are not used during FLASH access.

Note 1: This bit always reads as a ‘1’.

PIC16F7X

DS30325A-page 44 Advance Information  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. Advance Information DS30325A-page 45

PIC16F7X

5.0 TIMER0 MODULE

The Timer0 module timer/counter has the following features:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overflow from FFh to 00h

• Edge select for external clock

Figure 5-1 is a block diagram of th e T imer0 module and the prescaler shared with the WDT.

Additional information on the Timer0 module is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023).

Timer mode is selected by clearing bit T0CS (OPTION_REG<5>). In Timer mode, the Timer0 module will increment ev ery ins tru cti on c y cle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section5.2.

The prescaler is mutually exclusively shared between the Timer0 mo du le and t he W a tchdo g Timer . The prescaler is not readabl e or w rit able. Sectio n 5.3 details the operation of the prescaler.

5.1 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit T0IF (INTCON<2>). The interrupt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in softw are by the T imer0 mo dule Interrupt Service Routine, before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut off during SLEEP.

FIGURE 5-1: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

RA4/T0CKI

T0SE

U X

CLKOUT (= F

OSC/4)

SYNC

Cycles

TMR0 reg

8-bit Prescaler

8 - to - 1MUX

M U

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

PSA

WDT Enable bit

M U

Data Bus

Set Flag bit T0IF

on Overflow

PSA

T0CS

PRESCALER

PIC16F7X

DS30325A-page 46 Advance Information  2000 Microchip Technology Inc.

5.2 Using Timer0 with an External Clock

When no pres caler is us ed, t he ex ternal clock inpu t is the same as the prescaler outp ut. Th e synch ron iz atio n of T0CKI, with the internal phase clocks, is accomplished by sampli ng the prescale r output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary f or T 0 CK I t o be hi g h f or a t le as t 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical specification of the desired device.

5.3 Prescaler

There is only on e presca ler avai lable, w hich i s mutuall y exclusively sha red between the T imer0 mod ule and the Watchdog Timer. A prescaler assignment for the

Timer0 m odule means that t here is no presc aler fo r the Watchdog Timer, and vice-versa. This prescaler is not readable or writable (see Figure 5-1).

The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and pre scale ratio.

When assigned to the Timer0 module, all instructions writing to the TMR0 register ( e.g. CLRF

1, MOVWF 1,

BSF

1,x.. ..etc.) will clear the pre scaler . When assi gned

to WDT, a CLRWDT instru ction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable.

Note: Writing to TMR0 when the prescaler is

assigned to T imer0, will clear the pre scaler count but will not change the prescaler assignment.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0

bit 7 bit 0

bit 7 RBPU bit 6 INTEDG bit 5 T0CS: TMR0 Clock Source Select bit

1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

bit 4 T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin

bit 3 PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0 PS2:PS0: Prescaler Rate Select bits

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Bit Value TMR0 Rate WDT Rate

Note: To avoid an unintended device RESET, the instruction sequence shown in the

PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) must be executed when changing the pres caler assign ment from T imer0 to the WDT. This sequence must be followed even if the W DT is disabled.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 47

PIC16F7X

T ABLE 5-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on all

other

RESETS

01h,101h TMR0 Timer0 Module’s Register

xxxx xxxx uuuu uuuu

0Bh,8Bh, 10Bh,18Bh

INTCON GIE PEIE T0IE

INTE RB IE T0IF INTF RBIF 0000 000x 0000 000u

81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

PIC16F7X

DS30325A-page 48 Advance Information  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. Advance Information DS30325A-page 49

PIC16F7X

6.0 TIMER1 MODULE

The Timer1 mod ule is a 16-bi t tim er/c ou nter c onsis tin g of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000 h. The TMR1 Interrupt , if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).

Timer1 can operate in one of two modes:

• As a timer

• As a counter

The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>).

In Timer mode, Timer1 increments every instruction cycle. In Counter mode, it increments on every rising edge of the external clock input.

Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0> ) .

Timer1 also has an internal “RESET input”. This RESET can be generated by either of the two CCP modules (Section 8.0). Register 6-1 shows the Timer1 Control register.

When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored and these pins read as ‘0’.

Additional information on timer modules is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023).

U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON

bit 7 bit 0

bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits

11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value

bit 3 T1OSCEN: Timer1 Oscillator Enable Control bit

1 = Oscillator is enabled 0 = Oscillator is shut off (The oscillator inverter is turned off to eliminate power drain)

bit 2 T1SYNC

: Timer1 External Clock Input Sync hro ni zat ion Control bit

TMR1CS = 1

1 = Do not synchronize external clock input 0 = Synchronize external clock input

TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.

bit 1 TMR1CS: Timer1 Clock Source Select bit

1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4)

bit 0 TMR1ON: Timer1 On bit

1 = Enables Timer1 0 = Stops Timer1

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F7X

DS30325A-page 50 Advance Information  2000 Microchip Technology Inc.

6.1 Timer1 Operation in Timer Mode

Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect, since the internal clock is always in sync.

6.2 Timer1 Counter Operation

Timer1 may operate in Asynchronous or Synchronous mode, depending on the setting of the TMR1CS bit.

When Timer1 is being incremented via an external source, increment s occur on a rising edg e. After T imer1 is enabled in Coun ter mode, the module must fi rst have a falling edge before the counter begins to increment.

FIGURE 6-1: TIMER1 INCREMENTING EDGE

6.3 Timer1 Operation in Synchronized

Counter Mode

Counter mode is selected by setting bit TMR1CS. In this mode, the timer increm ents on every rising edg e of clock input on pin RC1/T1OSI/CCP2, when bit T1OSCEN is set, or on pin R C0/T1 OSO/T 1CKI, w hen bit T1OSCEN is cleared.

If T1SYNC

is cleared, the n the externa l clock input is synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The prescaler stage is an asynchronous ripple counter.

In this configuration, during SLEEP mode, Timer1 will not increment even if the external clock is present, since the synchronization circuit is shut off. The prescaler however, will continue to increment.

FIGURE 6-2: TIMER1 BLOCK DIAGRAM

T1CKI (Default high)

T1CKI (Default low)

Note: Arrows indicate counter increments.

TMR1H

TMR1L

T1OSC

T1SYNC

TMR1CS

T1CKPS1:T1CKPS0

Q Clock

T1OSCEN

Enable

Oscillator

(1)

Fosc/4

Internal Clock

TMR1ON

On/Off

Prescaler

1, 2, 4, 8

Synchronize

det

Synchronized

Clock Input

RC0/T1OSO/T1CKI

RC1/T1OSI/CCP2

(2)

Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.

2: For the PIC16F73/76, the Schmitt Trigger is not implemented in External Clock mode.

Set Flag bit TMR1IF on Overflow

TMR1

(2)

 2000 Microchip Technology Inc. Advance Information DS30325A-page 51

PIC16F7X

6.4 Timer1 Operation in Asynchronous Counter Mode

If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow, which will wake-up the processor. However, special precautions in software are needed to read/write the time r (Section 6.4.1).

In Asynchronous Counter mode, Timer1 can not be used as a time base for capture or comp are operations.

6.4.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE

Reading TMR1H or TMR1L, while the timer is running from an external asynchronous clock, will guarantee a valid read (taken care of in hardware). However, the user should keep i n mind that r eadin g the 16-bit time r in two 8-bit values itself, poses certain problems since the timer may overflow between the reads.

For writes, it is recomm ended that the us er simply stop the timer and write the desired values. A write contention may occur by writing to the timer registers, while the register is incrementing. This may produce an unpredictable value in the timer re gister.

Reading the 16-bit value requires some care. Examples 12-2 and 12-3 i n the PICmicro™ Mid -R ang e MC U Family Reference Manual (DS33023) show how to read and write Timer1 when it is running in Asynchronous mode.

6.5 Timer1 Oscillator

A crystal oscillator ci rcuit is built-in betwee n pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T 1CON<3>). The oscill ator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for use with a 32 kHz crystal. Table 6-1 shows the capacitor selection for the Timer1 oscillator.

The Timer1 oscillator is identical to the LP oscillator. The user must provide a so f tw ar e tim e de lay to en sure proper oscillator start-up.

T ABLE 6-1: CAPACITOR SELECTION FOR

THE TIMER1 OSCILLATOR

6.6 Resetting Timer1 using a CCP Trigger Output

If the CCP1 or CCP2 module is config ured in C omp are mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1.

Timer1 mu st be confi gured fo r either T ime r or Synchr onized Counter mode, to t a ke adv antage of this feature. If Timer1 is running in Asynchronous Counter mode, this RESET operation may not work.

In the event that a write to Timer1 coincides with a special event trigger from CCP1 or CCP2, the write will take precedence.

In this mode of ope ration, the CCPRxH:C CPRx L regis ter pair effectively becomes the period register for Timer1.

6.7 Resetting of Timer1 Register Pair (TMR1H, TMR1L)

TMR1H and TMR1L regist ers are not reset to 00h on a POR, or any other RESET, except by the CCP1 and CCP2 special event triggers.

T1CON register is rese t to 00h on a Powe r-on Reset or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other RESETS, the register is unaffected.

6.8 Timer1 Prescaler

The prescaler counter is cleared on writes to the TMR1H or TMR1L registers.

Osc Ty pe Freq C1 C2

LP 32 kHz 33 pF 33 pF

100 kHz 15 pF 15 pF 200 kHz 15 pF 15 pF

These values are for design guidance only.

Crystals Tested:

32.768 kHz Epson C-001R32.768K-A ± 20 PPM 100 kHz Epson C-2 100.00 KC-P ± 20 PPM 200 kHz STD XTL 200.000 kHz ± 20 PPM Note 1: Higher capacitanc e increases the s tability of

the oscillator , but also inc reases the star t-up time.

2: Since each resonator/crystal has its own

characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.

Note: The special event triggers from the CCP1

and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1<0>).

PIC16F7X

DS30325A-page 52 Advance Information  2000 Microchip Technology Inc.

TABLE 6-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on

all other

RESETS

0Bh,8Bh, 10Bh,18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch PIE1 PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS 0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 53

PIC16F7X

7.0 TIMER2 MODULE

Timer2 is an 8-bit timer with a prescaler and a postscaler . It c an be used as the PWM time base f or the PWM mode of the CCP module(s). The TMR2 register is readable and writable, and is cleared on any device RESET.

The input clock (F

OSC/4) has a prescale option of 1:1,

1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>).

The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon RESET.

The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)).

Timer2 ca n be sh ut off by clearing con trol bit TMR2ON (T2CON<2>) to minimize power consumption.

the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023).

7.1 Timer2 Prescaler and Postscaler

The prescaler and postscaler counters are cleared when any of the following occurs:

• a write to the TMR2 register

• a write to the T2CON register

• any device RESET (POR, MCLR

Reset, WDT

Reset or BOR)

TMR2 is not cleared when T2CON is written.

7.2 Output of TMR2

The output of TMR2 (before the post scaler) is fed to the SSP module, which optionally uses it to generate shift clock.

FIGURE 7-1: TIMER2 BLOCK DIAGRAM

Comparator

TMR2

Sets Flag

TMR2 reg

Output

(1)

Reset

Postscaler

Prescaler

PR2 reg

OSC/4

1:1 1:16

1:1, 1:4, 1:16

bit TMR2IF

Note 1: TMR2 register output can be software selected by the

SSP module as a baud clock.

T2OUTPS3:

T2OUTPS0

T2CKPS1:

T2CKPS0

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

bit 7 bit 0

bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits

0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale

•

1111 = 1:16 Postscale

bit 2 TMR2ON: Timer2 On bit

1 = Timer2 is on 0 = Timer2 is off

bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits

00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F7X

DS30325A-page 54 Advance Information  2000 Microchip Technology Inc.

TABLE 7-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on all other RESETS

0Bh,8Bh, 10Bh,18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

0Ch PIR1 PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

0000 0000 0000 0000

8Ch PIE1 PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

0000 0000 0000 0000

11h TMR2 Timer2 Module’s Register

0000 0000 0000 0000

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

-000 0000 -000 0000

92h PR2 Timer2 Period Registe r

1111 1111 1111 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 55

PIC16F7X

8.0 CAPTURE/COMPARE/PWM MODULES

Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a:

• 16-bit Capture registe r

• 16-bit Compare register

• PWM Master/Slave Duty Cycle register

Both the CCP1 and CCP2 modules are identical in operation, with the e xception being the operation of the special event trigg er. Table 8-1 and Ta ble8-2 show the resources and interactions of the CCP module(s). In the following sections, the operation of a CCP module is described with respect to CCP1. CCP2 operates the same as CCP1, except where noted.

8.1 CCP1 Module

Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. The special event trigger is generated by a compare match and will reset Timer1.

8.2 CCP2 Module

Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP2CON register controls the operation of CCP2. The special event trigger is generated by a compare match and will reset Timer1 and start an A/D conversion (if the A/D module is enabled).

Additional information on CCP modules is available in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) and in Appli cation N ote 594 , “Using the CCP Modules” (DS00594).

TABLE 8-1: CCP MODE - TIMER

RESOURCES REQUIRED

TABLE 8-2: INTERACTION OF TWO CCP MODULES

CCP Mode Timer Resource

Capture

Compare

PWM

Timer1 Timer1 Timer2

CCPx Mode CCPy Mode Interaction

Capture Capture Same TMR1 time base. Capture Compare The compare should be configured for the special event trigger, which clears TMR1. Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1. PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt). PWM Capture None. PWM Compare None.

PIC16F7X

DS30325A-page 56 Advance Information  2000 Microchip Technology Inc.

U-0 U-0 R/W-0 R/W-0 R/W -0 R/W-0 R/W-0 R/W-0

— — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0

bit 7 bit 0

bit 7-6 Unimplemented: Read as '0' bit 5-4 CCPxX:CCPxY: PWM Least Sign ifi can t bit s

Capture Mode: Unused

Compare Mode: Unused

PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.

bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits

0000 = Capture/Compare/PWM disabled (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set,

CCPx pin is unaffected) 1011 = Compare mode, trigger special event ( CCPxIF bit is set, CCPx pin is unaffected); CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled) 11xx = PWM mode

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2000 Microchip Technology Inc. Advance Information DS30325A-page 57

PIC16F7X

8.3 Capture Mode

In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 r egister wh en an eve nt occurs on pin RC2/CCP1. An even t is defined as on e of the following and is configured by CCPxCON<3:0>:

• Every falling edge

• Every rising edge

• Every 4th rising edge

• Every 16th rising edge

An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. The interrupt flag must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value is overwritten by the new captured value.

8.3.1 CCP PIN CONFIGURATION

In Capture mode, the RC 2/ CCP 1 pin sh oul d b e co nfi gured as an in put by setting the TRISC<2> bit.

FIGURE 8-1: CAPTURE MODE OPERATION

BLOCK DIAGRAM

8.3.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchro-

nized Counter mode for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work.

8.3.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture

interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode.

8.3.4 CCP PRESCALER There are four prescaler settings, specified by bits

CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any RESET will clear the prescaler counter.

Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared, therefore, the first cap ture may be from a non-zero prescaler. Example8-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt.

EXAMPLE 8-1: CHANGING BETWEEN

CAPTURE PRESCALERS

CLRF CCP1CON ;Turn CCP module off MOVLW NEW_CAPT_PS ;Load the W reg with

; the new prescaler ; move value and CCP ON

MOVWF CCP1CON ;Load CCP1CON with this

; value

Note: If the RC2/CCP1 pin is configured as an

output, a write to the port can cause a capture condition.

CCPR1H CCPR1L

TMR1H TMR1L

Set Flag bit CCP1IF

(PIR1<2>)

Capture Enable

Q’s

CCP1CON<3:0>

RC2/CCP1

Prescaler ÷ 1, 4, 16

and

edge detect

PIC16F7X

DS30325A-page 58 Advance Information  2000 Microchip Technology Inc.

8.4 Compare Mode

In Compare mo de, th e 16- bit CCP R1 re gist er valu e is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/C CP 1 pin is:

• Driven high

• Driven low

• Remains unchanged

The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the same time, interrupt flag bit CCP1IF is set.

FIGURE 8-2: COMPARE MODE OPERATION

BLOCK DIAGRAM

8.4.1 CCP PIN CONFIGURATION The user must configure the RC2/CCP1 pin as an out-

put by clearing the TRISC<2> bit.

8.4.2 TIMER1 MODE SELECTION Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work.

8.4.3 SOFTWARE INTERRUPT MODE When Generate Softwa re Interrupt mode is c hosen, the

CCP1 pin is not affected. The CCPIF bit is set causing a CCP interrupt (if enabled).

8.4.4 SPECIAL EVENT TRIGGER In this mode, an intern al ha rdwar e trigg er is gene rated,

which may be used to initiate an action. The special event trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to effectively be a 16- bit progra mmable perio d register for Timer1.

The special event trigger output of CCP2 resets the TMR1 register pai r and starts an A/D conv ersi on (if the A/D module is enabled).

8.5 PWM Mode (PWM)

In Pulse Width Mo dulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output.

Figure 8-3 shows a simplified block diagram of the CCP module in PWM mode.

For a step-by-step proc edure on how to set up the CC P module for PWM operation, see Section8.5.3.

FIGURE 8-3: SIMPLIFIED PWM BLOCK

DIAGRAM

Note: Clearing the CCP1CON register will force

the RC2/CCP1 compare outp ut latch to the default low level. This is not the PORTC I/O data latch.

CCPR1H CCPR1L

TMR1H TMR1L

Comparator

Output

Logic

Special Event Trigger

Set Flag bit CCP1IF (PIR1<2>)

Match

RC2/CCP1

TRISC<2>

CCP1CON<3:0> Mode Select

Output Enable

Special event trigger will:

reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>).

Note: The special event trigger from the CCP1

and CCP2 modules will not set interrupt flag bit TMR1IF (PIR1<0>).

Note: Clearing the CCP1CON register will force

the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty Cycle Registers

CCP1CON<5:4>

Clear Timer, CCP1 pin and latch D.C.

TRISC<2>

RC2/CCP1

Note 1: 8-bit timer is concatenated with 2-bit internal Q clock

or 2 bits of the prescaler to create 10-bit time base.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 59

PIC16F7X

A PWM output (Figure 8-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period).

FIGURE 8-4: PWM OUTPUT

8.5.1 PWM PERIOD

The PWM period is spec ified by writi ng to th e PR2 re gister. The PWM period can be calculated using the following formula:

PWM period = [(PR2) + 1] • 4 • T

OSC •

(TMR2 prescale value)

PWM frequency is defined as 1 / [PWM period]. When TMR2 is eq ual to PR2, t he followi ng three ev ents

occur on the next incremen t cycle:

• TMR2 is cleared

• The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin w ill not be set )

• The PWM duty cycle is lat ched from CC PR1L into

CCPR1H

8.5.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit re sol ut i on is av ai l abl e. T he CCP R1 L c on tai ns the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time:

PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •

Tosc • (TMR2 prescale value)

CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read only register.

The CCPR1H register and a 2-bit internal latch are used to double buffer th e PWM duty cycle. Thi s doubl e buffering is essential for glitchless PWM operation.

When the CCPR1H and 2-bit latch match TMR2 concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 presc aler, the CCP1 pin is cleared.

Maximum PWM resolution (bits) for a given PWM frequency:

8.5.3 SET-UP FOR PWM OPERATION The following steps should be taken when configuring

the CCP module for PWM operation:

1. Set the PW M period by writing to t he PR2 regis ter .

2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits.

3. Make the CCP1 pin an output by clearing the TRISC<2> bit.

4. Set the TMR2 prescale value and enab le Time r2 by writing to T2CON.

5. Configure the CCP1 module for PWM operatio n.

T ABLE 8-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

Note: The Timer2 postscaler (s ee Se cti on 8.3) is

not used in the determination of the PWM frequency . T he posts caler coul d be used to have a servo update rate at a different frequency than the PWM output.

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

TMR2

RESET

TMR2

RESET

Note: If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be cleared.

log(

FPWM

log(2)

OSC

)

bits

Resolution

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz

Timer Prescale (1, 4, 16) 16 4 1 1 1 1 PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10 8 7 5.5

PIC16F7X

DS30325A-page 60 Advance Information  2000 Microchip Technology Inc.

TABLE 8-4: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

TABLE 8-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Val ue on :

POR,

BOR

Val ue on

all other

RESETS

0Bh,8Bh, 10Bh,18Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0 8Ch PIE1 PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0 87h TRISC PORTC Data Direction Regis ter 1111 1111 1111 1111 0Eh TMR1L Holding register for the Least Sign ificant By te of th e 16-bit TMR1 r egister xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu 15h CCPR1L Capture/Compare/PWM register1 ( LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 1Bh CCPR2L Capture/Compare /PWM register 2 (LSB) xxxx xxxx uuuu uuuu 1Ch CCPR2H Capture/Compare/PWM register2 (MSB) xxxx xxxx uuuu uuuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by Capture and Timer1.

Note 1: The PSP is not implemented on the PIC16F73/76; always maintain these bits clear.

Add ress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on

all other

RESETS

0Bh,8Bh, 10Bh,18B h

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF

0000 000x 0000 000u

0Ch PIR1 PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF

0000 0000 0000 0000

0Dh PIR2 — — — — — — — CCP2IF

---- ---0 ---- ---0

8Ch PIE1 PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE

0000 0000 0000 0000

8Dh PIE2 — — — — — — — CCP2IE

---- ---0 ---- ---0

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111

11h TMR2 Timer2 module’s register

0000 0000 0000 0000

92h PR2 Timer2 module’s period register

1111 1111 1111 1111

12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0

-000 0000 -000 0000

15h CCPR1L Capture/Compare/PWM register1 (LSB)

xxxx xxxx uuuu uuuu

16h CCPR1H Capture/Compare/PWM register1 (MSB)

xxxx xxxx uuuu uuuu

17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0

--00 0000 --00 0000

1Bh CCPR2L Capture/Compare/PWM register2 (LSB)

xxxx xxxx uuuu uuuu

1Ch CCPR2H Capture/Comp are/PWM r egiste r2 (MSB)

xxxx xxxx uuuu uuuu

1Dh CCP2C O N — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0

--00 0000 --00 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as ’0’. Shaded cells are not used by PWM and Timer2.

Note 1:

Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 61

PIC16F7X

9.0 SYNCHRONOUS SERIAL PORT (SSP) MODULE

9.1 SSP Module Overview

The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D conv erte rs, et c. The SSP m odu le can operate in one of two modes:

• Serial Peripheral Interface (SPI)

• Inter-Integrated Circuit (I

An overview of I

C operations and additional information on the SSP module can be found in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023).

Refer to Application Note AN578, “Use of the SSP

Module in the I

C Multi-Master Environment.”

9.2 SPI Mode

This section contains register definitions and operational characteristics of the SPI module. Additional information on the SPI module can be found in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023A).

SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. To accomplish communication, typically three pins are used:

• Serial Data Out (SDO) RC5/SDO

• Serial Data In (SDI) RC4/SDI/SDA

• Serial Clock (SCK) RC3/SCK/SCL

Additionally, a fourth pin may be used when in a Slave mode of operation:

• Slave Select (SS

) RA5/SS/AN4

When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) and SSPSTAT<7:6>. These control bits allow the following to be specified:

• Master mode (SCK is the clock output)

• Slave mode (SCK is the clock input)

• Clock Polarity (Idle state of SCK)

• Clock edge (output data on rising/falling edge of

SCK)

• Clock Rate (Master mode only)

• Slave Select mode (Slave mode only)

PIC16F7X

DS30325A-page 62 Advance Information  2000 Microchip Technology Inc.

R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0

SMP CKE D/A

PSR/WUA BF

bit 7 bit 0

bit 7 SMP: SPI Data Input Sample Phase

SPI Master mode:

1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire

)

SPI Slave

mode:

SMP must be cleared when SPI is used in Slave mode I

C mode:

This bit must be maintained clear

bit 6 CKE: SPI Clock Edge Select (Figure 9-2, Figure 9-3, and Figure 9-4)

SPI

mode:

CKP = 0

1 = Data transmitted on rising edge of SCK (Microwire® alternate) 0 = Data transmitted on falling edge of SCK

CKP = 1

1 = Data transmitted on falling edge of SCK (Microwire® default) 0 = Data transmitted on rising edge of SCK

I2 C mode: This bit must be maintained clear

bit 5 D/A

: Data/Address bit (I2C mode only)

1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address

bit 4 P: STOP bit (I

C mode only) This bit is cleared when the SSP module is disabled, or when the START bit is detected last. SSPEN is cleared.

1 = Indicates that a STOP bit has been detected last (this bit is ’0’ on RESET) 0 = STOP bit was not detected last

bit 3 S: START bit (I

C mode only) This bit is cleared when the SSP module is disabled, or when the STOP bit is detected last. SSPEN is cleared.

1 = Indicates that a START bit has been detected last (this bit is ’0’ on RESET) 0 = START bit was not detected last

bit 2 R/W

: Read/Write bit Information (I2C mode only) This bit holds the R/W bit informat ion follo wing the las t addres s match . This bit is only valid from the address match to the next START bit, STOP bit, or ACK

bit. 1 = Read 0 = Write

bit 1 UA: Update Address (10-bit I

C mode only)

1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated

bit 0 BF: B uffer Full Status bit

Receive (SPI and I

C modes):

1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty

Transmit (I

C mode only):

1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2000 Microchip Technology Inc. Advance Information DS30325A-page 63

PIC16F7X

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0

bit 7 bit 0

bit 7 WCOL: Write Collision Detect bit

1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision

bit 6 SSPOV: Receive Overflow Indicator bit

In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow

In I

C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care" in Transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow

bit 5 SSPEN: Synchronous Serial Port Enable bit

In SPI mode:

1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins

In I2 C mode:

1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins

In both modes, when enabled, these pins must be properly configured as input or output.

bit 4 CKP: Clock Polarity Select bit

In SPI mode:

1 = Idle state for clock is a high level (Microwire® default) 0 = Idle state for clock is a low level (Microwire

alternate)

In I

C mode: SCK release control

1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.)

bit 3-0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits

0000 = SPI Master mode, clock = F

OSC/4

0001 = SPI Master mode, clock = F

OSC/16

0010 = SPI Master mode, clock = F

OSC/64

0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS

pin control enabled.

0101 = SPI Slave mode, clock = SCK pin. SS

pin control disabled. SS can be used as I/O pin.

0110 = I

C Slave mode, 7-bit address

0111 = I

C Slave mode, 10-bit address

1011 = I

C firmware controlled Master mode (slave idle)

1110 = I

C Slave mode, 7-bit address with START and STOP bit interrupts enabled

1111 = I

C Slave mode, 10-bit address with START and STOP bit interrupts enabled

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F7X

DS30325A-page 64 Advance Information  2000 Microchip Technology Inc.

FIGURE 9-1: SSP BLOCK DIAGRAM

(SPI MODE)

To enable the serial port, SSP enable bit, SSPEN (SSPCON<5>) must be set. T o reset or rec onfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, an d the n s et bi t SSPEN. Th is config ures the SDI, SDO, SCK, and SS

pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appropriately programmed. That is:

• SDI must have TRISC<4> set

• SDO must have TRISC<5> cleared

• SCK (Master mode) must have TRISC<3>

cleared

• SCK (Slave mode) must have TRISC<3> set

• SS

must have TRISA<5> set and ADCON must

be configured such that RA5 is a digital I/O

Read Write

Internal

Data Bus

RC4/SDI/SDA

RC5/SDO

RA5/SS/AN4

RC3/SCK/

SSPSR reg

SSPBUF reg

SSPM3:SSPM0

bit0

Shift

Clock

Control Enable

Edge

Select

Clock Select

TMR2 Output

Prescaler

4, 16, 64

TRISC<3>

Edge

Select

SCL

Note 1: When the SPI is in Slave mode with SS pin

control enabled, (SSPCON<3:0> = 0100) the SPI module will reset if the SS pin is set to V

DD.

2: If the SPI is used in Slave mode with

CKE = '1', then the SS pin control m ust be enabled.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 65

PIC16F7X

FIGURE 9-2: SPI MODE TIMING, MASTER MODE

FIGURE 9-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0)

FIGURE 9-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1)

SCK (CKP = 0,

SDI (SMP = 0)

SSPIF

bit7

bit6 bit5

bit4

bit3

bit2

bit1 bit0

SDI (SMP = 1)

SCK (CKP = 0,

SCK (CKP = 1,

SDO

bit7

bit7 bit0

bit0

CKE = 0)

CKE = 1)

CKE = 0)

CKE = 1)

SCK (CKP = 0)

SDI (SMP = 0)

SSPIF

bit7

bit6 bit5

bit4

bit3

bit2

bit1 bit0

SCK (CKP = 1)

SDO

bit7 bit0

SS (optional)

SCK (CKP = 0)

SDI (SMP = 0)

SSPIF

bit7

bit6 bit5

bit4

bit3

bit2

bit1 bit0

SCK (CKP = 1)

SDO

bit7 bit0

PIC16F7X

DS30325A-page 66 Advance Information  2000 Microchip Technology Inc.

TABLE 9-1: REGISTERS ASSOCIATED WITH SPI OPERATION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all other RESETS

0Bh,8Bh. 10Bh,18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch PIE1 PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 67

PIC16F7X

9.3 SSP I2 C Operation

The SSP module in I2C mode, fully implements all slave functions, except general call support, and provides interrupts on ST ART and STOP bit s in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing.

Two pin s are used for dat a transfer . These are th e RC3/ SCK/SCL pin, which is the clock (SCL), and the RC4/ SDI/SDA pi n, which i s the data (SDA). T he user must configure these pins as inputs or outputs through the TRISC<4:3> bits.

The SSP module functions a re enabl ed by settin g SSP enable bit SSPEN (SSPCON<5>).

FIGURE 9-5: SSP BLOCK DIAGRAM

C MODE)

The SSP module has five registers for I2C operation. These are the:

• SSP Control Register (SSPCON)

• SSP Status Register (SSPSTAT)

• Serial Receive/Transmit Buffer (SSPBUF)

• SSP Shift Register (SSPSR) - Not directl y ac c essi ble

• SSP Address Register (SSPADD)

The SSPCON register allows control of the I

C operation. Four mode selection bits (SSPCON<3:0>) allow one of the following I

C modes to be selected:

• I

C Slave mode (7-bit address)

• I

C Slave mode (10-bit address)

• I2C Slave mode (7-bit address), with START and

STOP bit interrupts enabled to support firmware Master mode

• I

C Slave mode (10-bit address) , with ST AR T and STOP bit interrupts enabled to support firmware Master mode

• I

C START and STOP bit interrupts enabled to support firmware Master mode, Slave is idle

Selection of any I

C mode, with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. Pull-up resistors must be provided externally to the SCL a nd SDA pi ns for prop er operation of the I

C module.

Additional information on SSP I

C operation can be found in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023A).

9.3.1 SLAVE MODE In Slave mode, the SCL and SDA pins must be confi g-

ured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when required (slave-transmitter).

When an address is matched, or the data transfer af ter an address match is received, the hardware automatically will generate the acknowledge (ACK

) pulse, and then load the SSPBUF register with th e re cei ved v alu e currently in the SSPSR register.

There are certain conditions that will cause the SSP module not to give this ACK

pulse. They include (either

or both): a) The buffer full bit BF (SSPSTAT<0>) was set

before the transfer was received.

b) The overflow bit SSPOV (SSPCON<6>) was set

before the transfer was received.

In this case, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR1<3>) is set. Table 9-2 shows what happens when a data transfer byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where user software d id no t pr operly clear th e ove rflow cond ition. Flag bit BF is cleared by read ing the SSPBUF register while bit SSPOV is cleared through software.

The SCL clock input must have a minimum high and low for proper operati on. The hi gh and low times of the I

C specification, as well as the requirements o f the SSP module, are shown in timing parameter #100 and parameter #101.

Read Write

SSPSR reg

Match Detect

SSPADD reg

START and

STOP bit Dete c t

SSPBUF reg

Internal Data Bus

Addr Match

Set, RESET

S, P bits

(SSPSTAT reg)

RC3/SCK/SCL

RC4/

Shift

Clock

MSb

SDI/

LSb

SDA

PIC16F7X

DS30325A-page 68 Advance Information  2000 Microchip Technology Inc.

9.3.1.1 Addressing Once the SSP module has been enabled, it waits for a

ST ART conditi on to occu r. Following the START cond ition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur:

a) The SSPSR register value is loaded into the

SSPBUF register. b) The buffer full bit, BF is set. c) An ACK

pulse is generated.

d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set

(interrupt is genera ted if e nabled ) - on the fallin g

edge of the ninth SCL pulse. In 10-bit address mode, two address bytes need to be

received by the slave (Figure 9-7). The five Most Significant bits (MSbs) of the first address byte specify if this is a 10 -bit addr ess. Bit R/W

(SSPSTAT<2>) must specify a write so the s la ve d ev ice will receive the se cond address byte. For a 10-bit address, the first byte would equal ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit address is as follows, with steps 7 - 9 for slave-transmitter:

1. Receive first (high) byte of address (bits SSPIF, BF, and bit UA (SSPSTAT<1>) are set).

2. Update the SSPADD register with second (low) byte of address (clears bit UA and releases the SCL line).

3. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.

4. Receive second (low) byte of address (bits SSPIF, BF, and UA are set).

5. Update the SSP ADD re gister w ith the f irst (hig h) byte of address, if ma tch releases SCL line, this will clear bit UA.

6. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.

7. Receive Repeated START condition.

8. Receive first (high) byte of address (bits SSPIF and BF are set).

9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF.

TABLE 9-2: DATA TRANSFER RECEIVED BYTE ACTIONS

Status Bits as Data

Transfer is Received

SSPSR → SSPBUF

Generate ACK

Pulse

Set bit SSPIF

(SSP Interrupt occurs

if enabled)

BF SSPOV

00 Yes Yes Yes 10 No No Yes 11 No No Yes 0 1 No No Yes

Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 69

PIC16F7X

9.3.1.2 Reception When the R/W

bit of the address byte is clear and an

address match occurs, the R/W

bit of the SSPSTAT register is cleare d. The re ceive d addre ss is loa ded in to the SSPBUF register.

When the address byte overflow condition exists, then no Acknowledge (ACK

) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set, or bit SSPOV (SSPCON<6>) is set. This is an error condition due to the user’s firmware.

An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in sof tware. The SSPSTAT register is used to determine the status of the byte.

FIGURE 9-6: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

D3D4

D6D7

A7 A6 A5 A4

A3 A2 A1SDA

SCL

1234

123

Bus Master terminates transfer

Bit SSPOV is set because the SSPBUF register is still full.

Cleared in software

SSPBUF register is read

ACK

Receiving Data

D3D4

D6D7

ACK

R/W=0

Receiving Address

SSPIF (PIR1<3>)

BF (SSPSTAT<0>)

SSPOV (SSPCON<6>)

ACK

ACK is not sent.

PIC16F7X

DS30325A-page 70 Advance Information  2000 Microchip Technology Inc.

9.3.1.3 Transmission When the R/W

bit of the inco ming add ress byte i s set

and an address match occurs, the R/W

bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK

pulse will be sent on the ninth bit, and pin RC3/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. The n, pin RC3/SCK/SCL shou ld be enabled by setting bit CKP (SSPCON<4>). The master must monitor the SCL pin prior to asse rtin g an other clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 9-7).

An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and the SSPSTAT register is used to determine the status of the byte. Flag bit SSPIF is set on the falling edge of the ninth clock pulse.

As a slave-transmi tte r, the ACK

pulse from the masterreceiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line was high (not ACK), then the data transfer is com plete. When th e ACK

is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave then moni tors for another occ urrence of the START bit. If the SDA line was low (ACK

), the transmit data must be load ed into the SSPBUF register, which also loads the SSPSR register. Then pin RC3/SCK/SCL should be enabled by setting bit CKP.

FIGURE 9-7: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

SDA

SCL

SSPIF (PIR1<3>) BF (SSPST AT<0>)

CKP (SSPCON<4>)

A7 A6 A5 A4 A3 A2 A1 ACK

D7 D6 D5 D4 D3 D2 D1 D0

ACK

Transmitting DataR/W = 1Receiving Address

123456789 123456789

Cleared in software

SSPBUF is written in software

From SSP Interrupt Service Routine

Set bit after writing to SSPBUF

Data in sampled

SCL held low while CPU

responds to SSPIF

(the SSPBUF must be written-to before the CKP bit can be set)

 2000 Microchip Technology Inc. Advance Information DS30325A-page 71

PIC16F7X

9.3.2 MASTER MODE Master mode of operation is supported in firmware

using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and ST AR T ( S) bits are cleare d from a RESET or when th e SSP module is disabled. The ST OP (P) and ST ART (S) bits will toggle based on the START and STOP conditions. Control of the I

C bus may be taken when the P bit is set, or th e bus is idle and bo th the S and P b its a re clear.

In Master mode, the SCL and SDA lines are manipulated by clearing the c orresp onding TRISC<4 :3> bit(s ). The output level is always low, irrespective of the value(s) in PORT C< 4:3 >. So wh en transmitting data, a ’1’ data bit must have the TRISC<4> bit set (input) and a ’0’ dat a bit mus t hav e th e TRISC <4> bit c lea red (o utput). The same scenario is true for the SCL li ne with the TRISC<3> bit. Pull-up resistors must be provided externally to the SCL and SDA pins for proper operation of the I

C module.

The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt will occur if enabled):

• START condition

• STOP condition

• Data transfer byte transmitted/received

Master mode of operation can be done with either the Slave mode idle (SSPM3:SSPM0 = 1011), or with the Slave active. When both Master and Slave modes are enabled, the software needs to differentiate the source(s) of the interrupt.

9.3.3 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the

detection of the START and STOP conditions, allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a RESET or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I

C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idl e an d both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs.

In Multi-Master operation, the SDA line must be monitored to see if the signal level is the expected output level. This check only needs to be done when a high level is output. If a h igh level is expect ed and a low leve l is present , the device need s to release th e SDA and SCL lines (set TRISC<4:3>). There are two stages where this arbitration can be lost, these are:

• Address Transfer

• Data Transfer

When the slave log ic is enab led, th e sla ve co ntinue s to receive. If arbitration was los t during the address transfer stage, communication to the device may be in progress. If addressed, an ACK

pulse will be generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at a later time.

TABLE 9-3: REGISTERS ASSOCIATED WITH I2C OPERATION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other

RESETS

0Bh, 8Bh, 10Bh,18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

8Ch PIE1 PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 94h SSPSTAT SMP

(2)

CKE

(2)

D/A PSR/WUA BF 0000 0000 0000 0000 87h TRISC PORTC Data Direction register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as ’0’. Shaded cells are not used by SSP module in I2C mode.

Note 1: PSPIF and PSPIE are reserved on the PIC16F73/76; always maintain these bits clear.

2: M aintain these bits clear in I

C mode.

PIC16F7X

DS30325A-page 72 Advance Information  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. Advance Information DS30325A-page 73

PIC16F7X

10.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER T RANSMITTER (USART)

The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules . (USA RT is als o know n as a Se rial Communications Interface or SCI.) The USART can be configured as a full duplex asynchronous system that can communicate with pe ripheral devices , such as CRT t erminals and perso nal comp uters, or it can be configure d as a half duplex s yn chr onous system that can co mm unicate with peripheral devices, such as A/D or D/A integrated circuits, serial EEPROMs, etc.

The USART can be configured in the following modes:

• Asynchronous (full duplex)

• Synchronous - Master (half duplex)

• Synchronous - Slave (half duplex)

Bit SPEN (RCSTA<7>) and bits TRISC<7:6> have to be set in order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter.

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0

CSRC TX9 TXEN SYNC — BRGH TRMT TX9D

bit 7 bit 0

bit 7 CSRC: Clock Source Select bit

Asynchronous mode: Don’t care

Synchronous mode:

1 = Master mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source)

bit 6 TX9: 9-bit Transmit Enable bit

1 = Selects 9-bit transmission 0 = Selects 8-bit transmission

bit 5 TXEN: Transmit Enable bit

1 = Transmit enabled 0 = Transmit disabled

Note: SREN/CREN overrides TXEN in SYNC mode.

bit 4 SYNC: USART Mode Select bit

1 = Synchronous mode 0 = Asynchronous mode

bit 3 Unimplemented: Read as '0' bit 2 BRGH: High Baud Rate Select bit

Asynchronous mode:

1 = High speed 0 = Low speed

Synchronous mode: Unused in this mode

bit 1 TRMT: Transmit Shift Register Status bit

1 = TSR empty 0 = TSR full

bit 0 TX9D: 9th bit of transmit data. Can be parity bit.

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F7X

DS30325A-page 74 Advance Information  2000 Microchip Technology Inc.

R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R-0 R-x

SPEN RX9 SREN CREN

— FERR OERR RX9D

bit 7 bit 0

bit 7 SPEN: Serial Port Enable bit

1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled

bit 6 RX9: 9-bit Receive Enable bit

1 = Selects 9-bit reception 0 = Selects 8-bit reception

bit 5 SREN: Single Receive Enable bit

Asynchronous mode: Don’t care

Synchronous mode - Master:

1 = Enables single receive 0 = Disables single receive

This bit is cleared after reception is complete. Synchronous mode - Slave:

Don’t care

bit 4 CREN: Continuous Receive Enabl e bit

Asynchronous mode:

1 = Enables continuous receive 0 = Disables continuous receive

Synchronous mode:

1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive

bit 3 Unimplemented: Read as '0' bit 2 FERR: Framing Error bit

1 = Framing error (Can be updated by reading RCREG register and receive next valid byte) 0 = No framing error

bit 1 OERR: Overrun Error bit

1 = Overrun error (Can be cleared by clearing bit CREN) 0 = No overrun error

bit 0 RX9D: 9th bit of Received Data

Can be parity bit (parity to be calculated by firmware)

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

 2000 Microchip Technology Inc. Advance Information DS30325A-page 75

PIC16F7X

10.1 USART Baud Rate Generator (BRG)

The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit BRGH is ignored. Table 10-1 shows the formula for computation of the baud rate for differen t US ART modes which only appl y in Master mode (internal clock).

Given the desired b aud rate an d Fosc, the n earest in teger value for the SPBRG register can be calculated using the formula in Table 10-1. From this, the error in baud rate can be determined.

It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the F

OSC/(16(X + 1)) equation can reduce the

baud rate error in some cases. Writing a new value to the SPBRG register causes the

BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate.

10.1.1 SAMPLING The data on the RC7/RX/D T pin is sampled three times

by a majority detect circuit to determine if a high or a low level is present at the RX pin.

TABLE 10-1: BAUD RATE FORMULA

TABLE 10-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR

SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed)

0 1

(Asynchronous) Baud Rate = F

OSC/(64(X+1))

(Synchronous) Baud Rate = F

OSC/(4(X+1))

Baud Rate= F

OSC/(16(X+1))

N/A

X = value in SPBRG (0 to 255)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other

RESETS

98h TXSTA

CSRC TX9 TXEN SYNC — BRGH TRMT TX9D

0000 -010 0000 -010

18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D

0000 -00x 0000 -00x

99h SPBRG Baud Rate Generator Register

0000 0000 0000 0000

Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG.

PIC16F7X

DS30325A-page 76 Advance Information  2000 Microchip Technology Inc.

TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)

BAUD

RATE

(K)

OSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz

KBAUD%ERROR

SPBRG VALUE

(DECIMAL)

KBAUD%ERROR

SPBRG

VALUE

(DECIMAL)

KBAUD%ERROR

SPBRG

VALUE

(DECIMAL)

0.3 - - - - - - - - -

1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129

2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64

9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15

19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7

28.8 31.250 8.51 9 27.778 3.55 8 31.250 8.51 4

33.6 34.722 3.34 8 35.714 6.29 6 31.250 6.99 4

57.6 62.500 8.51 4 62.500 8.51 3 52.083 9.58 2 HIGH 1.221 - 255 0.977 - 255 0.610 - 255 LOW 312.500 - 0 250.000 - 0 156.250 - 0

BAUD

RATE

(K)

OSC = 4 MHz FOSC = 3.6864 MHz

KBAUD

ERROR

SPBRG

VALUE

(DECIMAL) KBAUD

ERROR

SPBRG

VALUE

(DECIMAL)

0.3 0.300 0 207 0.301 0.33 185

1.2 1.202 0.17 51 1.216 1.33 46

2.4 2.404 0.17 25 2.432 1.33 22

9.6 8.929 6.99 6 9.322 2.90 5

19.2 20.833 8.51 2 18.643 2.90 2

28.8 31.250 8.51 1 - - -

33.6 - - - - - -

57.6 62.500 8.51 0 55.930 2.90 0 HIGH 0.244 - 255 0.218 - 255 LOW 62.500 - 0 55.930 - 0

TABLE 10-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)

BAUD

RATE

(K)

OSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz

KBAUD%ERROR

SPBRG

VALUE

(DECIMAL)

KBAUD%ERROR

SPBRG

VALUE

(DECIMAL)

KBAUD%ERROR

SPBRG

VALUE

(DECIMAL)

0.3---------

1.2---------

2.4 - - - - - - 2.441 1.71 255

9.6 9.615 0.16 129 9.615 0.16 103 9.615 0.16 64

19.2 19.231 0.16 64 19.231 0.16 51 19.531 1.72 31

28.8 29.070 0.94 42 29.412 2.13 33 28.409 1.36 21

33.6 33.784 0.55 36 33.333 0.79 29 32.895 2.10 18

57.6 59.524 3.34 20 58.824 2.13 16 56.818 1.36 10 HIGH 4.883 - 255 3.906 - 255 2.441 - 255 LOW 1250.000 - 0 1000.000 0 625.000 - 0

BAUD

RATE

(K)

OSC = 4 MHz FOSC = 3.6864 MHz

KBAUD

ERROR

SPBRG

VALUE

(DECIMAL) KBAUD

ERROR

SPBRG

VALUE

(DECIMAL)

0.3 - - - - - -

1.2 1.202 0.17 207 1.203 0.25 185

2.4 2.404 0.17 103 2.406 0.25 92

9.6 9.615 0.16 25 9.727 1.32 22

19.2 19.231 0.16 12 18.643 2.90 11

28.8 27.798 3.55 8 27.965 2.90 7

33.6 35.714 6.29 6 31.960 4.88 6

57.6 62.500 8.51 3 55.930 2.90 3 HIGH 0.977 - 255 0.874 - 255 LOW 250.000 - 0 273.722 - 0

 2000 Microchip Technology Inc. Advance Information DS30325A-page 77

PIC16F7X

10.2 USART Asynchronous Mode

In this mode, the USART uses standard non-return-tozero (NRZ) format (one START bit, eight or nine data bits, and one STOP bit). The most common data format is 8-bits. An on-chip, dedicated, 8-bit baud rate generator can be used to derive st and ard baud rate freque ncies from the oscillator. The USART transmits and receives the LSb first. The USART’s transmitter and receiver are functionally independent, but use the same data forma t an d b aud rate. The baud rate gen erator produces a clock either x16 or x64 of the bit shift rate, depending on bit BRGH (TXST A<2>). Pari ty is not supported by the hardware, but can be imple mente d in software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP.

Asynchronous mode is selected by clearing bit SYNC (TXSTA<4>).

The USART Asynchronous module consists of the following important elements:

• Baud Rate Generator

• Sampling Circuit

• Asynchronous Transmitter

• Asynchronous Receiver

10.2.1 USART ASYNCHRONOUS TRANSMITTER The USART transmitter block diagram is shown in

Figure 10-1. The heart of t he trans mitte r is the t ransm it (serial) shift register (TSR). The shif t register obta ins its data from the read/write transmit buffer, TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one T

CY), the TXR EG re giste r i s em pty and

flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE

(PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bi t TX IE an d cann ot be cl ear ed in software. It will reset only wh en ne w dat a is loa ded i nto th e TXREG register . While flag bi t TXIF indicates the st atus of the TXREG register, another bit TRMT (TXSTA<1>) shows the status of the TSR register. Status bit TRMT is a read only bi t, w h ic h i s se t w he n the TSR r egi ste r i s empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty.

Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data and the baud rate generator (BRG) has produced a shift clock (Figure10-2). The transmission can also be started by first loading the TXREG register and then setting enable bit TXEN. Normally, w hen transmission is first started, the TSR register is empty. At that point, transfer to the TXREG register will result in an immediate transfe r to TSR, result ing in an empty TXR EG. A back-to-back transfer is thus possible (Figure 10-3). Clearing enable bit TXEN during a transmission will cause the transmis s ion to be ab orte d a nd w il l re se t th e transmitter. As a result, the RC6/TX/CK pin will revert to hi-impedance.

In order to select 9-bit transmission, transmit bit TX9 (TXSTA<6>) should be set and the ninth bit should be written to TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the TXREG register. This is because a data write to the TXREG register can result in an immediate tra nsfer of the dat a to the TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit may be loaded in the TSR register.

FIGURE 10-1: USART TRANSMIT BLOCK DIAGRAM

Note 1: The TSR register is not mapped in data

memory, so it is not available to the user.

2: Flag bit TXIF is set when enable bit TXEN

is set. TXIF is cleared by loading TXREG.

TXIF

TXIE

Interrupt

TXEN

Baud Rate CLK

SPBRG

Baud Rate Generator

TX9D

MSb

LSb

Data Bus

TXREG register

TSR Register

(8)

TX9

TRMT

SPEN

RC6/TX/CK pin

Pin Buffer and Control

• • •

PIC16F7X

DS30325A-page 78 Advance Information  2000 Microchip Technology Inc.

Steps to follow when setting up an Asynchronous Transmission:

1. Initialize the SPBRG register for the appropria te baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 10.1)

2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN.

3. If interrupts are desired, then set en able bit TXIE.

4. If 9-bit transmission is desired, then set transmit bit TX9.

5. Enable the transmission by setting bit TXEN, which will also set bit TXIF.

6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D.

7. Load data to the TXREG register (starts transmission).

8. If using interrupts, ensure that GIE and PIE in the INTCON register are set.

FIGURE 10-2: ASYNCHRONOUS MASTER TRANSMISSION

FIGURE 10-3: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK)

TABLE 10-5: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Address Name

Bit 7

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bi t 1 Bi t 0

Val ue on :

POR,

BOR

Val ue on all other RESETS

0Bh, 8Bh, 10Bh,18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP 1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h T XRE G USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for asynchronous transmission.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.

Word 1

STOP Bit

Word 1 Transmit Shift Reg

STAR T Bit Bit 0 Bit 1 Bit 7/8

Write to TXREG

Word 1 BRG Output (Shift Clock)

RC6/TX/CK (pin)

TXIF bit (Transmit Buffer Reg. Empty Flag)

TRMT bit (Transmit Shift Reg. Empty Flag)

Transmit Shift Reg.

Write to TXREG

BRG Output (Shift Clock )

RC6/TX/CK (pin)

TXIF bit (Interrupt Reg. Flag)

TRMT bit (Transmit Shift Reg. Empty Flag)

Word 1

Word 2

Word 1

Word 2

START Bit

STOP Bit

START Bit

Transmit Shift Reg.

Word 1

Word 2

Bit 0 Bit 1

Bit 7/8 Bit 0

Note: This timing diagram shows two consecutive transmissions.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 79

PIC16F7X

10.2.2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 10-4.

The data is received on th e R C7/RX/D T p in an d dri ve s the data recovery block. The data recovery block is actually a high sp ee d s hifter operating at x 16 tim es the baud rate, whereas the main receive serial shif ter operates at the bit rate, or at F

OSC.

Once Asynchronous mode is selected, reception is enabled by setting bit CREN (RCSTA<4>).

The heart of the receive r is the receive (s erial) shif t register (RSR). After sampling the STOP bit, the received data in the RSR is tra nsferred to the R CREG register (if it is empty). If the transfer is complete, flag bit RCIF (PIR1<5>) i s set. T he actu al i nt erru pt c an b e en abl ed/ disabled by setting/clearing enable bit RCIE (PIE1<5>). Flag bit RCIF is a read only bit which is cleared by the hardware. It is cleared when the RCREG register has been read and is empty. The RCREG is a double buffered register (i.e., it is a two deep FIFO). It

is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting to the RSR register. On the detection of the STOP bit of the third byte, if the RCREG register is still full, the overrun error bit OE RR (RCST A<1>) will be set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Overrun bit OERR has to be cle ared in sof twar e. This is don e by resetting the receive logic (C REN is cleared and then s et). If bit O ERR is s et, tran sfers from the RSR register to the RCREG register are inhibited and no further data will be received, therefore, it is essential to clear error bit OERR if it is set. Framing error bit FERR (RCSTA<2>) is set if a STOP bit is detected as clear. Bit FERR and the 9th receive bit are buffered the sa me way as the receiv e data. Reading the RCREG will load bits RX9D and FERR with new values, therefore, it is e ss ent ial for the us er to re ad th e RCSTA register before

reading RCREG register, in

order not to lose the old FERR and RX9D information .

FIGURE 10-4: USART RECEIVE BLOCK DIAGRAM

FIGURE 10-5: ASYNCHRON OUS RECEPTION

x64 Baud Rate CLK

SPBRG

Baud Rate Generator

RC7/RX/DT

Pin Buffer and Control

SPEN

Data Recovery

CREN

OERR

FERR

RSR Register

MSb

LSb

RX9D

RCREG Register

FIFO

Interrupt

RCIF

RCIE

Data Bus

STOP

START

(8)

RX9

• • •

FOSC

÷64 ÷16

START

bit

bit7/8

bit1bit0

bit7/8 bit0STOP

bit

START

bit

START

bit

bit7/8

STOP

bit

RX (pin)

reg Rcv Buffer reg

Rcv Shift

Read Rcv Buffer reg RCREG

RCIF (Interrupt Flag)

OERR bit CREN

WORD 1 RCREG

WORD 2 RCREG

STOP

bit

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,

causing the OERR (overrun) bit to be set. An overrun error indicates an error in user firmware.

PIC16F7X

DS30325A-page 80 Advance Information  2000 Microchip Technology Inc.

Steps to follow when setting up an Asynchronous Reception:

1. Initialize the SPBRG register for the appropria te baud rate. If a high speed baud rate is desired, set bit BRGH (Section 10.1).

2. Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN.

3. If interrupts are desired, then set enable bit RCIE.

4. If 9-bit reception is desired, then set bit RX9.

5. Enable the reception by setting bit CREN.

6. Flag bit RCIF will be set when reception is com plete and an interru pt will be g enerated i f enable bit RCIE is set.

7. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception.

8. Read the 8-bit received data by reading the RCREG register.

9. If any error occurred, clear the error by clearing enable bit CREN.

10. If using interrupts, ensure that GIE and PIE in the INTCON register are set.

TABLE 10-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all other RESETS

0Bh, 8Bh, 10Bh,18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA S PE N RX9 SRE N CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE

(1)

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 81

PIC16F7X

FIGURE 10-6: USART RECEIVE BLOCK DIAGRAM

TABLE 10-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

x64 Baud Rat e CLK

SPBRG

Baud Rate Generator

RC7/RX/DT

Pin Buffer and Control

SPEN

Data Recovery

CREN

OERR

FERR

RSR Register

MSb

LSb

RX9D

RCREG Register

FIFO

Interrupt

RCIF

RCIE

Data Bus

STOP

START

(8)

RX9

• • •

FOSC

÷64 ÷16

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on

all other

RESETS

0Bh, 8Bh, 10Bh,18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG B aud Rate Generat or Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.

PIC16F7X

DS30325A-page 82 Advance Information  2000 Microchip Technology Inc.

10.3 USART Synchronous Master Mode

In Synchronous Ma ster mode, the dat a is trans mitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transm itting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indic ates that the pr ocessor transmit s the master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA<7>).

10.3.1 USART SYNCHRONOUS MASTER TRANSMISSION

The USART transmitter block diagram is shown in Figure 10-6. The heart of t he trans mitte r is the t ransm it (serial) shift register (TSR). The shif t register obta ins its data from the read/write transmit buffer register TXREG. The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one Tcycle), the TXREG is empty and interrupt bit TXIF (PIR1<4>) is set. The interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset o nly when ne w dat a i s loa ded into the TXREG register . While fla g bit TXIF indicates th e status of the TXREG re gi st e r, another b it TR MT (T XS TA<1>) shows the status of the TSR register. TRMT is a read only bit which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR regis ter is empty. The TSR is not mapped in data memory, so it is not available to the user.

Transmission is enabled by setting enable bit TXEN (TXSTA<5>). The actual transmission will not occur until the TXREG register has been loaded with data. The first data bit will be shifted out on th e next available rising edge of the clock on the CK line. Data out is stable around the falling edge of the synchronous clock (Figure 10-7). The transmission can also be started by first loading the TXREG register and then setting bit TXEN (Figure 10-8). This is advantageous when slow baud rates are selected, since the BRG is kept in RESET when bits TXEN, CREN and SREN are clear. Setting enable bit TXEN will start the BRG, creating a shift clock i mmediate ly. Normally , when transm issi on is first started, the TSR register is empty, so a transfer to the TXREG register will re su lt i n an im med ia te transfer to TSR resulting in an empty TXREG. Back-to-back transfers are possible.

Clearing enable bit TXEN during a transmission will cause the transmis s ion to be ab orte d a nd w il l re se t th e transmitter. The DT and CK pins will revert to hiimpedance. If eithe r bit CRE N or bit SREN is se t during a transmission, the transm issi on is abor ted and the DT pin reverts to a hi-impedance state (for a reception). The CK pin will remain an output if bit CSRC is set (internal clock). The transmitter logic, however, is not reset, although it i s disconnected from t he pins. In order to reset the transmitter, the user has to clear bit TXEN. If bit SREN is set (to i nterrupt an on-goin g transmiss ion and receive a si ngle word), then af ter the single wo rd is received, bit SREN will be cleared and the serial port will revert back to transmitting, since bit TXEN is still set. The DT line will immediately switch from hiimpedance r eceiv e mode t o transm it and start dri ving. To avoid this, bit TXEN should be cleared.

In order to select 9-bit transmission, the TX9 (TXSTA<6>) bit should be set and the ninth bit should be written to bit TX9D (TXSTA<0>). The ninth bit must be written before writing the 8-bit data to the TXREG register . This is because a dat a write to the TXREG ca n result in an immediate transfer of the data to the TSR register (if the TSR i s empty). If the TSR was empty and the TXREG was written before writing the “new” TX9D, the “present” value of bit TX9D is loaded.

Steps to follow when setting up a Synchronous Master Transmission:

1. Initialize the SPBRG register for the appropria te baud rate (Section 10.1).

2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC.

3. If interrupts are desired, set enable bit TXIE.

4. If 9-bit transmission is desired, set bit TX9.

5. Enable the transmission by setting bit TXEN.

6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D.

7. Start transmissi on by loading da ta to the TXREG register.

8. If using interrupts, ensure that GIE and PIE in the INTCON register are set.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 83

PIC16F7X

TABLE 10-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

FIGURE 10-7: SYNCHRONOUS TRANSMISS ION

FIGURE 10-8: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Val ue on :

POR, BOR

Value on all

other

RESETS

0Bh, 8Bh, 10Bh,18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000

Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for synchronous master transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.

bit 0 bit 1 bit 7

Word 1

Q1Q2Q3Q4Q1 Q2Q3 Q4Q1Q2Q3Q4Q1 Q2Q3Q4Q1Q2 Q3Q4 Q3Q4 Q1Q2Q3Q4Q1Q2Q3Q4 Q1Q2Q3Q4Q1 Q2Q3 Q4Q1Q2Q3 Q4Q1 Q2Q3 Q4

bit 2 bit 0 bit 1 bit 7

RC7/RX/DT pin

RC6/TX/CK pin

Write to TXREG reg

TXIF bit

(Interrupt Flag)

TRMT

TXEN bit

’1’ ’1’

Note: Sync Master mode; SPBRG = ’0’. Continuous transmission of two 8-bit words.

Word 2

TRMT bit

Write Word1

Write Word2

RC7/RX/DT pin

RC6/TX/CK pin

Write to

TXREG reg

TXIF bit

TRMT bit

bit0

bit1

bit2

bit6 bit7

TXEN bit

PIC16F7X

DS30325A-page 84 Advance Information  2000 Microchip Technology Inc.

10.3.2 USART SYNCHRONOUS MASTER RECEPTION

Once synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCST A<5>), or enable bit CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, then only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, CREN takes precedence. After clocking the last bit, the received data in the Receive Shift Register (RSR) is transferred to the RCREG register (if it is empty). When the transfer is complete, interrupt flag bit RCIF (PIR1<5>) is set. The actual interrupt can be enabled/ disabled by setting/clearing enable bit RCIE (PIE1<5>). Flag bit RCIF is a read only bit, which is reset by the hardware. In this case, it is reset when the RCREG register has been read and is empty. The RCREG is a double buffered register (i.e., it is a two deep FIFO). It is possible for two bytes of data to be received and transferred to the RCREG FIFO and a third byte to begin shifting into the RSR register. On the clocking of the last bit of the third byte, if the RCREG register is still full, then overrun error bit OERR (RCSTA<1>) is set. The word in the RSR will be lost. The RCREG register can be read twice to retrieve the two bytes in the FIFO. Bit OERR has to be cleared in software (by clearing bit CREN). If bit OERR is set, transfers from the RSR to the RCREG are inhibited, so it is essential to clear bit OERR if it is set. The ninth receive bit is buffered the same way as the

receive data. Reading the RCREG register will load bit RX9D with a new value, therefore, it is essential for the user to read the RCSTA register before readin g RCREG , in order not to lose the old RX9D information.

Steps to follow when setting up a Synchronous Master Reception:

1. Initialize the SPBRG register for the appropria te baud rate (Section 10.1).

2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC.

3. Ensure bits CREN and SREN are clear.

4. If interrupts are desired, then set enable bit RCIE.

5. If 9-bit reception is desired, then set bit RX9.

6. If a single reception is required, set bit SREN. For continuous reception set bit CREN.

7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set.

8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception.

9. Read the 8-bit received data by reading the RCREG register.

10. If any error occurred, clear the error by clearing bit CREN.

11. If using interrupts, ensure that GIE and PIE in the INTCON register are set.

TABLE 10-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on all

other

RESETS

0Bh, 8Bh, 10Bh,18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for synchronous master reception.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 85

PIC16F7X

FIGURE 10-9: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

CREN bit

RC7/RX/DT pin

RC6/TX/CK pin

Write to bit SREN

SREN bit

RCIF bit (interrupt)

Read RXREG

Note: Timing diagram demonstrates SYNC Master mode with bit SREN = ’1’ and bit BRG = ’0’.

Q3Q4 Q1 Q2Q3 Q4 Q1Q2 Q3Q4Q2 Q1Q2Q3 Q4Q1 Q2Q3 Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4 Q1 Q2Q3 Q4

’0’

bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7

’0’

Q1Q2 Q3 Q4

PIC16F7X

DS30325A-page 86 Advance Information  2000 Microchip Technology Inc.

10.4 USART Synchronous Slave Mode

Synchronous Slave mode differs from the Master mode, in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>).

10.4.1 USART SYNCHRONOUS SLAVE TRANSMIT

The operation of the Synchronous Master and Slave modes are ide ntical except in the case of the SLEEP mode.

If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur:

a) The first word will immediately transfer to the

TSR register and transmit. b) The second word will remain in TXREG register. c) Flag bit TXIF will not be set. d) When the first wo rd has been s hifted o ut of TSR,

the TXREG register will transfer the second

word to the TSR and flag bit TXIF will now be

set. e) If enable bit TXIE is set, the interrupt will wake

the chip from SLEEP and if the global interrupt

is enabled, the program will branch to the inter-

rupt vector (0004h). Steps to follow when setting up a Synchronous Slave

Transmission:

1. Enable the synchronous slave serial p ort by set-

ting bits SYNC and SPEN and clearing bit

CSRC.

2. Clear bits CREN and SREN.

3. If interrupts are desired, then set enable bit

TXIE.

4. If 9-bit transmission is desired, then set bit TX9.

5. Enable the transmission by setting enable bit

TXEN.

6. If 9-bit transmission is selected, the ninth bit

should be loaded in bit TX9D.

7. Start transmissi on by loading d ata to the TXREG

8. If using interru pts, ensure that GIE and PIE in

the INTCON register are set.

10.4.2 USART SYNCHRONOUS SLAVE RECEPTION

The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode. Bit SREN is a “don't care” in Slav e mod e.

If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP. On completely receiving the word, the RSR register will transfer the data to the RCREG register and if enable bit RCIE bit is set, the interrup t generated will wake the chip from SLEEP. If the global interrupt is enabled, the program w ill br anch to the int errupt v ector (0004h).

Steps to follow when setting up a Synchronous Slave Reception:

1. Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit CSRC.

2. If interrupts are desired, set enable bit RCIE.

3. If 9-bit reception is desired, set bit RX9.

4. To enable reception, set enable bit CREN.

5. Flag bit RCIF will be set when reception is com -

plete and an interrupt will be generated, if enable bit RCIE was set.

6. Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred during reception.

7. Read the 8-bit received data by reading the

RCREG register.

8. If any error occurred, clear the error by clearing

bit CREN.

9. If using interrupts, ensure that GIE and PIE in

the INTCON register are set.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 87

PIC16F7X

TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

TABLE 10-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other

RESETS

0Bh, 8Bh, 10Bh,18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX 9 SREN CREN ADDEN FERR OERR RX9D 0000 000x 0000 000x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Regist er 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices; always maintain these bits clear.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 B it 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on all

other

RESETS

0Bh, 8Bh, 10Bh,18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch PIR1 PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX 9D 0000 000x 0000 000x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76 devices, always maintain these bits clear.

PIC16F7X

DS30325A-page 88 Advance Information  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. Advance Information DS30325A-page 89

PIC16F7X

11.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE

The 8-bit analog-to-digital (A/D) converter module has five inputs for the PIC16F73/76 and eight for the PIC16F74/77.

The A/D allows conversi on of an anal og inp ut si gnal to a corresponding 8-bit digital number. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device’s positive supply voltage (V

DD), or the

voltage level on the RA3/AN3/V

REF pin.

The A/D converter has a unique feature of being able to operate while the d evice is in SLEEP mode. To operate in SLEEP, the A/D conversion clock must be derived from the A/D’s internal RC oscillator.

The A/D module ha s three registers. Thes e registers are:

• A/D Result Register (ADRES)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

The ADCON0 register, shown in Register 11-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 11-2, configures the functions of the port pins. The port pins can be configured as analog input s (RA3 can also be a voltag e reference), or as digital I/O.

Additional informa tion on usi ng the A/D module can be found in the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) and in Application Note, AN546.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON

bit 7 bit 0

bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits

00 = FOSC/2 01 = F

OSC/8

10 = F

OSC/32

11 = F

RC (clock derived from the internal A/D module RC oscillator)

bit 5-3 CHS2:CHS0: Analog Channel Select bits

000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4) 101 = channel 5, (RE0/AN5)

(1)

110 = channel 6, (RE1/AN6)

(1)

111 = channel 7, (RE2/AN7)

(1)

bit 2 GO/DONE: A/D Conversion Status bit

If ADON = 1:

1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when

the A/D conversion is complete) bit 1 Unimplemented: Read as '0' bit 0 ADON: A/D On bit

1 = A/D converter module is operating

0 = A/D converter module is shutoff and consumes no operating current

Note 1: A/D channels 5, 6 and 7 are implemented on the PIC16F74/77 only.

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

PIC16F7X

DS30325A-page 90 Advance Information  2000 Microchip Technology Inc.

U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0

— — — — — PCFG2 PCFG1 PCFG0

bit 7 bit 0

bit 7-3 Unimplemented: Read as '0' bit 2-0 PCFG2:PCFG0: A/D Port Configuration Control bits

Note 1: RE0, RE1 and RE2 are implemented on the PIC16F74/77 only.

Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown

A = Analog input D = Digital I/O

PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 RE0

(1)

RE1

(1)

RE2

(1)

VREF

000 AAAAAAAAVDD 001 AAAAVREF AAARA3 010 AAAAADDDV

011 AAAAVREF DDDRA3 100 AADDADDDVDD 101 AADDVREF DDDRA3 11x DDDDDDDDV

 2000 Microchip Technology Inc. Advance Information DS30325A-page 91

PIC16F7X

The following steps should be followed for doing an A/D conversion:

1. Configure the A/D module:

• Configure analog pins / voltage reference / and digital I/O (ADCON1 )

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

2. Configure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set PEIE bit

• Set GIE bit

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE

bit (ADCON0)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE

bit to be cleared

(interrupts disabled)

• Waiting for the A/D interrupt

6. Read A/D result register (ADRES), clear bit ADIF if required.

7. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as T

AD. A minimum wait of 2TAD is

required before next acquisition starts.

FIGURE 11-1: A/D BLOCK DIAGRAM

(Input Voltage)

VREF

(Reference

Voltage)

PCFG2:PCFG0

CHS2:CHS0

000 or 010 or 100 or

001 or 011 or

101

RE2/AN7

(1)

RE1/AN6

(1)

RE0/AN5

(1)

RA5/AN4

RA3/AN3/V

REF

RA2/AN2

RA1/AN1

RA0/AN0

111

110

101

100

011

010

001

000

A/D

Converter

Note 1: Not available on PIC16F73/76.

11x

PIC16F7X

DS30325A-page 92 Advance Information  2000 Microchip Technology Inc.

11.1 A/D Acquisition Requirements

For the A/D co nverter to meet its s pecified accuracy, the charge holding capacitor (C

HOLD) must be allowed

to fully charge to the input channel voltage level. The analog input model is shown in Figure 11-2. The source impedance (R

S) and the internal s ampling switch (RSS)

impedance directly affect the time required to charge the capacitor C

HOLD. The sampling switch (RSS)

impedance varies over the device voltage (V

DD),

Figure 11-2. The source impedance affects the offset voltage at the analog input (due to pin leakage curre nt).

The maximum recommended impedance for analog sources is 10 kΩ. After the analog input ch annel is

selected (changed), the acquisition must pass before the conversion can be started.

To calculate the minimum acquisition time, T

ACQ, see

the PICmicro™ Mid-Range MCU Family Reference Manual (DS33023A). In ge neral, howev er , giv en a max of 10kΩ a nd at a temp erature of 100°C, T

ACQ will be no

more than 16µsec.

FIGURE 11-2: ANALOG INPUT MODEL

TABLE 11-1: T

AD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))

CPIN

ANx

5 pF

VT = 0.6V

T = 0.6V

I leakage

IC ≤ 1k

Sampling Switch

CHOLD = DAC Capacitance

Sampling Switch

5V 4V 3V 2V

567891011

(kΩ)

VDD

= 51.2 pF

± 500 nA

Legend CPIN

VT I leakage

SS C

HOLD

= input capacitance = threshold voltage = leakage current at the pin due to

= interconnect resistance = sampling switch = sample/hold capacitance (from DAC)

various junctions

AD Clock Source (TAD) Maximum Device Frequency

Operation ADCS1:ADCS0 Max.

OSC 00 1.25 MHz

8TOSC 01 5 MHz

32T

OSC 10 20 MHz

(1, 2, 3)

11 (Note 1)

Note 1: The RC source has a typical TAD time of 4 µs but can vary between 2-6 µs.

2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only

recommended for SLEEP operation.

3: For extended voltage devices (LC), please refer to the Electrical Specifications section.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 93

PIC16F7X

11.2 Selecting the A/D Conversion Clock

The A/D conversion time per bit is defined as TAD. The A/D conversi on requires 9.0T

AD per 8-bit conversion.

The source of the A/D conversion clock is software selectable. The four possible options for TAD are:

• 2T

OSC

• 8TOSC

• 32T OSC

• Internal RC oscillator (2-6 µs)

For correct A/D conversions, the A/D conversion clock (T

AD) must be selected to ensure a minimum TAD time

of 1.6 µs.

11.3 Configuring Analog Port Pins

The ADCON1, TRISA and TRISE registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (V

OH or VOL) will be

converted. The A/D operation is independent of the state of the

CHS2:CHS0 bits and the TRIS bits.

11.4 A/D Conversions

Clearing the GO/DONE bit during a conversion will abort the current conversion. The ADRES register will NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed conversion (or the last value wr itten to the AD RES register). After the A/D conversion is aborted, a 2T

AD wait

is required before the next acquisition is started. After this 2T

AD wait, an acquisition is a utomatically s tarted on

the selected channel. The GO/DONE

bit can then be

set to start the conversion.

11.5 A/D Operation During SLEEP

The A/D module can ope rate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from th e convers ion. When th e conversion is completed, the GO/DONE

bit will be clea red, and the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from SLEEP . If the A/D interru pt is not enabled , the A/D module will then be turned off, although the ADON bit will remain set.

When the A/D clock s ource is anothe r cloc k option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A /D m odule to b e turn ed of f, though the ADON bit will remain set.

Turning off the A/D places the A/D modu le in its lowest current consumption state.

11.6 Effects of a RESET

A device RESET forces all registers to their RESET state. The A/D module is disabled and any conversion in progress is aborted. All A/D inp ut pins are confi gured as analog inputs.

The ADRES register will contain unknown data after a Power-on Reset.

11.7 Use of the CCP Trigger

An A/D conversion can be st arted by the “special event trigger” of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as 1011 and th at th e A/D m od ule is ena ble d (ADON bit is set). When the trigger occurs, the GO/DONE

bit will be set, s tarting t he A/D co nversi on, and the Timer1 counter will be reset to zero. Timer1 is reset to automatical ly rep eat th e A/D ac quisi tion perio d with minimal sof tware overh ead (moving the ADRES to the desired location). The appropriate analog input channel must be s elected an d the minim um acqu isition done before the “special event trigger” sets the GO/DONE

bit (starts a conversion). If the A/D module is not enabled (ADON is cleared),

then the “special event t rigger” will be i gnored by the A/D module, but will still reset the Timer1 counter.

Note 1: When reading the port register, all pins

configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input wi ll not affect the co nv ersion accuracy.

2: Analog levels on any pin that is defined a s

a digital input, but not as an analog input, may cause the input buffer to consume current that is ou t of the devices specif ication.

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

Note: For the A/D module to operate in SLEEP,

the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To perform an A/D conversion in SLEEP, ensure the SLEEP instruction immediately follows the instruction that sets the GO/DONE

bit.

PIC16F7X

DS30325A-page 94 Advance Information  2000 Microchip Technology Inc.

TABLE 11-2: SUMMARY OF A/D REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Val ue on :

POR,

BOR

Value on all

other

RESETS

0Bh,8Bh, 10Bh,18Bh

INTCON GIE PEIE

T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch

PIR1

PSPIF

(1)

ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000

0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0

8Ch

PIE1

PSPIE

(1)

ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000

8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0

1Eh

ADRES A/D Result Register

xxxx xxxx uuuu uuuu

1Fh

ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE

— ADON 0000 00-0 0000 00-0

9Fh

ADCON1

— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000

05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0

--0x 0000 --0u 0000

85h TRISA — — PORTA Data Direction Register

--11 1111 --11 1111

09h PORTE

(2)

— — — — —

RE2 RE1 RE0

---- -xxx ---- -uuu

89h TRISE

(2)

IBF OBF IBOV PSPMODE

—

PORTE Data Direction Bits

0000 -111 0000 -111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.

Note 1: Bits PSPIE and PSPIF are reserved on the PIC16F73/76; always maintain these bits clear.

These registers are reserved on the PIC16F73/76.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 95

PIC16F7X

12.0 SPECIAL FEATURES OF THE CPU

These devices h ave a host of fea tures intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes an d offer code protecti on. T hes e a re:

• Oscillator S election

• RESET

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code Protection

• ID Locations

• In-Circuit Serial Programming

These devices have a Watchdog Timer, which can be shut off only through configuration bits. It runs off its own RC oscillator for added reliability.

There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay of 72 ms (nominal) on power-up on ly. It is designed to keep the p art in RESET while the power supply stabilizes. With these two timers on-chip, mo st app lic ati on s n eed no external RESET circuitry.

SLEEP mode is designed to offer a very low current power-down mode. The user can w ake-up from SLEEP through external RESET, Watchdog T imer W ake-up, or through an interrupt.

Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of configuration bits are used to select various options.

Additional information on special features is available in the PICmicro™ Mid-Range Reference Manual, (DS33023).

12.1 Configuration Bits

The configuration bit s can be program med (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. These bits are mapped in program memory location 2007h.

The user will note that address 2007h is beyond the user program memory space, which can be accessed only during programming.

PIC16F7X

DS30325A-page 96 Advance Information  2000 Microchip Technology Inc.

— — — — — — —

BODEN

—

CP0 PWRTE WDTE F0SC1 F0SC0

bit13 bit0

bit 13-7: Unimplemented: Read as ‘1’ bit 6: BODEN: Brown-out Reset Enable bit

(1)

1 = BOR enabled 0 = BOR disabled

bit 5: Unimplemented: Read as ‘1’ bit 4 CP0: Flash Program Memory Code Protection bit

1 = Code protection off 0 = All memory locations code protected

bit 3: PWRTE: Power-up Timer Enable bit

(1)

1 = PWRT disabled 0 = PWRT enabled

bit 2: WDTE: Watchdog Timer Enable bit

1 = WDT enabled 0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator

Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT), regardless of the value of bit PWRTE

Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled.

 2000 Microchip Technology Inc. Advance Information DS30325A-page 97

PIC16F7X

12.2 Oscillator Configurations

12.2.1 OSCILLATOR TYPES

The PIC16F7X can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC Resistor/Capacitor

12.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS

In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure12-1). The PIC16F7X oscillator desi gn requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers specifications. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/CLKIN pin (Figure 12-2). See Table 15-1 for valid external clock frequencies.

FIGURE 12-1: CRYSTAL/CERAMIC

RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)

FIGURE 12-2: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP OSC CONFIGURATION)

TABLE 12-1: CERAMIC RESONATORS

Note 1: See Table 12-1 and Table 12-2 for recom-

mended values of C1 and C2.

2: A series resistor (RS) may be required for AT

strip cut crystals.

3: RF varies with the crystal chosen.

(1)

C2(1)

XTAL

OSC2

OSC1

RF(3)

SLEEP

logic

PIC16F7X

(2)

internal

Ranges Tested:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

68 - 100 pF

15 - 68 pF 15 - 68 pF

68 - 100 pF

15 - 68 pF 15 - 68 pF

HS 8.0 MHz

16.0 MHz

10 - 68 pF 10 - 22 pF

These values are for design gu idance only . See notes at bottom of page.

Resonators Used:

455 kHz Panasonic EFO-A455K04B ± 0.3%

2.0 MHz Murata Erie CSA2.00MG ± 0.5%

4.0 MHz Murata Erie CSA4.00MG ± 0.5%

8.0 MHz Murata Erie CSA8.00MT ± 0.5%

16.0 MHz Murata Erie CSA16.00MX ± 0.5% All resonators used did not have built-in capacitors.

OSC1

OSC2

Open

Clock from ext. system

PIC16F7X

DS30325A-page 98 Advance Information  2000 Microchip Technology Inc.

TABLE 12-2: CAPACITOR SELECTION FOR

CRYSTAL OSCILLATOR

12.2.3 RC OSCILLATOR For timing insensitive applications, the “RC” device

option offers additi ona l cos t sav in gs . The RC osc il lator frequency is a functio n of t he s upp ly vo ltage, the resistor (R

EXT) and capacitor (CEXT) values, and the operat-

ing temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low C

EXT values. The user also needs to take into account

variation d ue t o t ole ranc e of ex ter nal R an d C c ompo nents used. Figure12-3 shows how the R/C combination is connected to the PIC16F7X.

FIGURE 12-3: RC OSCILLATOR MODE

Osc Type

Crystal

Freq

Cap. Range

Cap.

Range

LP 32 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 200 kHz 47-68 pF 47-68 pF

1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF

HS 4 MHz 15 pF 15 pF

8 MHz 15-33 pF 15-33 pF

20 MHz 15-33 pF 15-33 pF

These values are for design gui dance only . See notes at bottom of page.

Crystals Used

32 kHz Epson C-001R32.768K-A ± 20 PPM 200 kHz STD XTL 200.000KHz ± 20 PPM 1 MHz ECS ECS-10-13-1 ± 50 PPM 4 MHz ECS ECS-40-20-1 ± 50 PPM 8 MHz EPSON CA-301 8.000M-C ± 30 PPM 20 MHz EPSON CA-301 20.000M-C ± 30 PPM

Note 1: Higher capacitance increases the stability

of oscillator, but also increases the startup time.

2: Since each resonator/crystal has its own

characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.

3: Rs may be required in HS mode, as well

as XT mode, to avoid overdriving crystals with low drive level specification.

4: When migrating from other PICmicro

devices, oscillato r per form anc e s hou ld be verified.

OSC2/CLKOUT

CEXT

REXT

PIC16F7X

OSC1

OSC/4

Internal

Clock

VDD

VSS

Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ

EXT > 20pF

 2000 Microchip Technology Inc. Advance Information DS30325A-page 99

PIC16F7X

12.3 RESET

The PIC16F7X differentiates between various kinds of RESET:

• Power-on Reset (POR)

• MCLR

Reset during normal operation

• MCLR

Reset during SLEEP

• WDT Reset (during normal operation)

• WDT Wake-up (during SLEEP)

• Brown-out Reset (BOR)

Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged in any other RESET. Most other registers are reset to a “RESET state” on Power-on Reset (POR), on the MCLR

and WDT Reset, on MCLR Reset during

SLEEP, and Brown-out Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The TO

and PD bits are set or cleared differently in different RESET situations, as indicated in Table 12-4. These bits are used in software to determine the nature of the RESET. See Table 12-6 for a full description of RESET states of all registers.

A simplified block diagram of the on-chip RESET circuit is shown in Figure 12-4.

These devices have a MCLR

noise filter in the MCLR Reset path. The filter will detect and ignore small pulses.

It should be noted that a WDT Reset does not drive MCLR

pin low.

FIGURE 12-4: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

RESET

MCLR

VDD

OSC1

WDT

Module

DD rise

detect

OST/PWRT

On-chip RC OSC

WDT Time-out

Power-on Reset

OST

10-bit Ripple counter

PWRT

Chip_Reset

10-bit Ripple counter

Reset

Enable OST

Enable PWRT

SLEEP

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

Brown-out

Reset

BODEN

(1)

PIC16F7X

DS30325A-page 100 Advance Information  2000 Microchip Technology Inc.

12.4 Power-on Reset (POR)

A Power-on Reset pulse is generated on-chip when V

DD rise is detected (in the range of 1.2V - 1.7V). To

take advantage of the POR, tie the MCLR

pin direc tly

(or through a resistor) to V

DD. This will eliminate exter-

nal RC component s usua lly ne eded to c reate a Po weron Reset. A maximum rise time for VDD is specified. See Electrical Specifications for details.

When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature,...) must be met to en su re operation. If these cond itions are not met, the de vice must be held in RESET until the operating conditions are met. Brown-out Reset may be used to meet the start-up conditions. For additional information, refer to Application Note, AN007, “Power-up Trouble Shooting”, (DS00007).

12.5 Power-up Timer (PWRT)

The Power-up Timer provides a fixed 72 ms nominal time-out on power-up only from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in RESET as long as the PWRT is active. The PWRT’s t ime delay allows V

DD to rise to an accept-

able level. A configuration bit is provided to enable/ disable the PWRT.

The power-up time dela y will vary f rom chip to chi p due to V

DD, temperature and process variation. See DC

parameters for details (T

PWRT, parameter #33).

12.6 Oscillator Start-up Timer (OST)

The Oscillator Start-up Timer (OST) provides 1024 oscillator cycles (from OSC1 input) delay after the PWRT delay is over (if enabled). This helps to ensure that the crystal oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.

12.7 Brown-out Reset (BOR)

The configuration bit, BODEN, can enable or disable the Brown-out Reset circuit. If V

DD falls below VBOR

(parameter D005, about 4V) for longer than TBOR (parameter #35, about 10 0 µS), the brown-out situation will reset the device. If V

DD falls below VBOR for less

than T

BOR, a RESET may not occur.

Once the brown-out occurs, the device will remain in Brown-out Reset until VDD rises above VBOR. The Power-up Timer then keeps the device in RESET for T

PWRT (parameter #33, abou t 72mS). If V DD should fall

below V

BOR during TPWRT, the Brown-out Reset pro-

cess will restart when V

DD rises above VBOR, with the

Power-up Timer Reset. The Power-up Timer is always enabled when the Brown-out Reset circuit is enabled, regardless of the state of the PWRT configuration bit.

12.8 Time-out Sequence

On power-up, the time-out seque nce is as follows: The PWRT delay starts (if enabled) when a POR Reset occurs. Then OST starts counting 1024 oscillator cycles when PWRT ends (LP, XT, HS). When the OST ends, the device comes out of RESET.

If MCLR

is kept low long enough, the time-outs will

expire. Bringing MCLR

high will begin execution immediately. This is useful for testing purposes or to synchronize more than one PIC16F7X device operating in parallel.

Table 12-5 shows the RESET conditions for the STATUS, PCON and PC registers, while Table 12-6 shows the RESET conditions for all the registers.

12.9 Power Control/Status Register

(PCON)

The Power Control/Status Register, PCON, has up to two bits depending upon the device.

Bit0 is Brown-out Reset Status bit, BOR

. Bit BOR is unknown on a Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if bit BOR

cleared, indicating a Brown-out Reset occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpred ict able and ther efore, not valid at any time.

Bit1 is POR

(Power-on Reset St atus bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset.

Microchip Technology Inc PIC16LF77-I-P Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual