Microchip Technology Inc PIC16HV540-04I-P, PIC16HV540-04I-SO, PIC16HV540-20I-P, PIC16HV540-20I-SO, PIC16HV540-20I-SS Datasheet



1998 Microchip Technology Inc.

Preliminary

DS40197A-page 1

PIC16HV540

High-Performance RISC CPU:

• Only 33 single word instructions to learn

• All instructions are single cycle (200 ns) except for
program branches which are two-cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• 12-bit wide instructions

• 8-bit wide data path

• Seven special function hardware registers

• Four-level deep hardware stack

• Direct, indirect and relative addressing modes for
data and instructions

Peripheral Features:

• 8-bit real time clock/counter (TMR0) with 8-bit
programmable prescaler

• Power-On Reset (POR)

• Brown-Out Protection

• Device Reset Timer (DRT) with short
RC-oscillator start up time

• Programmable Watchdog Timer (WDT) with its
own on-chip RC oscillator for reliable operation

• Sleep Timer

• 8 High Voltage I/O

• 4 Regulated I/O

• Wake up from SLEEP on pin change

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options:

- RC: Low-cost RC oscillator

- XT: Standard crystal/resonator

- HS: High speed crystal/resonator

- LP: Power saving, low frequency crystal

• Glitch filtering on MCLR

and pin change inputs

= Enhanced Features

Device Pins I/O EPROM RAM

PIC16HV540 18 12 512 25

CMOS Tec hnology:

• Selectable on-chip 3V/5V Regulator

• Low-power, high-speed CMOS EPROM
technology

• Fully static design

• Wide-operating voltage range:

- 3.5V to 15V

• Temperature range:

- Commercial: 0°C to 70°C

- Industrial: -40°C to 85°C

• Low-power consumption

- < 2 mA typical @ 5V, 4 MHz

- 15 µA typical @ 3V, 32 kHz

- < 4.5 µA typical standby current @ 15V (with

WDT disabled), 0°C to 70°C

Enhanced PIC16C54 EPROM-Based 8-Bit CMOS Microcontroller

With On-Chip Voltage Regulator

Pin Configurations

PDIP, SOIC, Windowed CERDIP

18
17
16
15
14
13
12
11
10

• 1
2
3
4
5
6
7
8
9

RA2
RA3

T0CKI

MCLR/VPP

VSS
RB0
RB1
RB2
RB3

RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
VDD
RB7
RB6
RB5
RB4

PIC16HV540

RA1
RA0
OSC1/CLKIN
OSC2/CLKOUT
V

DD

VDD
RB7
RB6
RB5
RB4

RA2
RA3

T0CKI

MCLR

/VPP

VSS

VSS
RB0
RB1
RB2
RB3

•1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

SSOP

PIC16HV540

✯

✯

✯

✯

✯
✯
✯

✯

✯

PIC16HV540

DS40197A-page 2

Preliminary



1998 Microchip Technology Inc.

1.0 GENERAL DESCRIPTION

The PIC16HV540 from Microchip Technology is a
low-cost, high-performance, 8-bit, fully-static,
EPROM-based CMOS microcontroller. It is pin and soft­ware compatible with the PIC16C5X family of devices. It
employs a RISC architecture with only 33 single word/sin­gle cycle instructions. All instructions are single cycle
except for program branches which take two cycles. The
PIC16HV540 delivers performance an order of magnitude
higher than its competitors in the same price category. The
12-bit wide instructions are highly orthogonal resulting in
2:1 code compression over other 8-bit microcontrollers in
its class. The easy-to-use and easy-to-remember instruc­tion set reduces development time significantly.

The PIC16HV540 is the first One-Time-Programmable
(OTP) microcontroller with an on-chip 3 Volt and 5 V olt reg­ulator. This eliminates the need for an external regulator in
many applications powered from 9 Volt or 12 Volt batteries
or unregulated 6 Volt, 9 V olt or 12 Volt mains adapters. The
PIC16HV540 is ideally suited for applications that require
very low standby current at high voltages. These typically
require expensive low current regulators .

The PIC16HV540 is equipped with special features that
reduce system cost and power requirements. The
Power-On Reset (POR) and Device Reset Timer (DRT)
eliminate the need for external reset circuitry . There are f our
oscillator configurations to choose from, including the
power-saving LP (Low Power) oscillator, cost saving RC
oscillator, and XT and HS f or crystal oscillators. Power sav­ing SLEEP mode, Watchdog Timer and code protection
features improve system cost, po wer and reliability.

The UV erasable CERDIP packaged versions are ideal for
code development, while the cost-eff ective OTP v ersions are
suitable for production in any v olume. The customer can take
full advantage of Microchip’s price leadership in O TP micro­controllers while benefiting from the OTP’ s fle xibility.

The PIC16HV540 will in future be supported by a
full-featured macro assembler, a software simulator, an
in-circuit emulator, a ‘C’ compiler, fuzzy logic support
tools, a low-cost dev elopment programmer , and a full f ea­tured programmer. All the tools are suppor ted on IBM



PC and compatible machines. Functions that correspond
to the PIC16C54 (such as assembly and programming)
can utilize existing tools.

1.1 Applications

The PIC16HV540 fits perfectly in low-power battery appli­cations such as CO and smoke detection, toys, games,
security systems and automobile modules. The EPROM
technology makes customizing of application programs
(transmitter codes, receiver frequencies, etc.) extremely
fast and convenient. The small footprint package, for
through hole or surface mounting, make this microcontrol­ler perfect for applications with space limitations.
Low-cost, low-power, high-performance, ease of use and
I/O flexibility make the PIC16HV540 very versatile e ven in
areas where no microcontroller use has been considered
before (e.g., timer functions, replacement of “glue” logic in
larger systems, coprocessor applications).

1.2 Enhanced Features

1.2.1 REGULATED I/O PORTA INDEPENDENT
OF CORE REGULATOR

PORTA I/O pads and OSC2 output are powered by the
regulated internal voltage VIO. A maximum of 10mA per
output is allowed, or a total of 40mA. The core itself is
powered from the independently regulated supply
V

REG

.

1.2.2 HIGH VOLTAGE I/O PORTB

All eight PORTB I/Os are high voltage I/O. The inputs
will tolerate input voltages as high as the VDD and out­puts will swing from VSS to the VDD. The input threshold
voltages vary with supply voltage. (See DC character­istics.)

1.2.3 WAKE UP ON PIN CHANGE ON PORTB [0:3]

Four of the PORTB inputs latch the status of the pin at
the onset of sleep mode. A level change on the inputs
resets the device, implementing wak e up on pin change
(via warm reset). The PC bit in the status register is
reset to indicate that a pin change caused the reset
condition. Any pin change (glitch insensitive) of the
opposite level of the initial value wakes up the device.
This option can be enabled/disabled in OPTION2 reg­ister. (See OPTION2 register, Figure 4-3.)

1.2.4 WAKE UP ON PIN CHANGE WITH A
SLOWLY-RISING VOLTAGE ON PORTB [7]

PORTB [7] also implements wake up from sleep, how­ever this input is specifically adapted so that a slowly

rising

voltage does not cause excessive power con­sumption. This input can be used with external RC cir­cuits for long sleep periods without using the internal
timer and prescaler. This option is also enabled/dis­abled in OPTION2 register. (The enable/disable bit is
shared with the other 4 wake up inputs.) The ne w w ake
up status bit in the status register is also shared with
the other four wake up inputs.

1.2.5 LOW-VOLTAGE (BROWN-OUT)

DETECTION

A low voltage (Brown-out) detect circuit optionally
resets the device at a voltage level higher than that at
which Brown-out events occur. The nominal trip volt­ages are 3.1 Volt (for 5 Volt operation) and 2.2 Volt (for
3 Volt operation), respectively. The core remains in the
reset state as long as this condition holds (as if a MCLR
external reset was given). The Brown-out trip level is
user selectable, with built-in interlocks. The Brown-out
detector is disabled at power-up and is activated by
clearing the appropriate bit (BE) in OPTION2 register.

1.2.6 INCREASED STACK DEPTH
The stack depth is 4 levels to allow modular program

implementation by using functions and subroutines.



1998 Microchip Technology Inc.

Preliminary

DS40197A-page 3

PIC16HV540

1.2.7 ENHANCED WATCHDOG TIMER (WDT)
OPERATION

The WDT is enabled b y setting FUSE 2 in the configuration
word. The WDT setting is latched and the fuse disabled
during SLEEP mode to reduce current consumption.

If the WDT is disabled by FUSE 2, it can be enabled/dis­abled under program control using bit 4 in OPTION2
(SWE). The software WDT control is disab led at power-up .

The current consumption of the on-chip oscillator (used
for the watchdog, oscillator startup timer and sleep
timer) is less than 1µA (typical) at 3 Volt operation.

1.2.8 REDUCED EXTERNAL RC OSCILLATOR
STARTUP TIME

If the RC oscillator option is selected in the Configura­tion word (FOSC1=1 and FOSCO=1) the oscillator
startup time is 1.0 ms nominal instead of 18 ms nomi­nal. This is applicable after power-up (POR), either
WDT interrupt or wake-up, external reset on MCLR

,

WPC (wake on pin change) and Brown-out.

1.2.9 LOW-VOLTAGE OPERATION OF THE
ENTIRE CPU DURING SLEEP

The voltage regulator can automatically lower the volt­age to the core from 5 Volt to 3 V olt during sleep, result­ing in reduced current consumption. This is an option
bit in OPTION2 register.

1.2.10 GLITCH FILTERS ON WAKEUP PINS AND
MCLR

Glitch sensitive inputs for wak eup on pin change are fil­tered to reduce susceptibility to interference. A similar
filter reduces false reset on MCLR.

1.2.11 PROGRAMMABLE CLOCK GENERATOR

When used in RC mode the CLKOUT pin can be used
as a programmable clock output. The output is con­nected to TMR0, bit 0 and by setting the prescaler,
clock out frequencies of CLKIN/8 to CLKIN/1024 can
be generated. The CLKOUT pin can also be used as a
general purpose output by modifying to TMR0, bit 0.

TABLE 1-1: PIC16HV540 DEVICE

PIC16HV540

Clock

Maximum Frequency (MHz) 20

Memory

EPROM Program Memory 512
RAM Data Memory (bytes) 25

Peripherals

Timer Module(s) TMR0

Packages

I/O Pins 12
Voltage Range (Volts) 3.5V-15V
Number of Instructions 33
Packages 18-pin DIP

SOIC

20-pin SSOP

All PICmicro



devices have Power-on Reset, selectable

WDT, selectable code protect and high I/O current capability.

2.0 PIC16HV540 DEVICE
VARIETIES

A variety of frequency ranges and packaging options
are available. When placing orders, please use the
PIC16HV540 Product Identification System at the back
of this data sheet to specify the correct part number.

2.1 UV Erasab

le Devices

The UV erasable versions, offered in CERDIP pack­ages, are optimal for prototype development and pilot
programs.

UV erasable devices can be progr ammed for an y of the
four oscillator configurations. Microchip's PICSTART



and PRO MATE programmers both support program­ming of the PIC16HV540. Third party programmers
also are available; refer to Literature Number DS00104
for a list of sources.

2.2 One-Time-Pr

ogrammable (OTP)

Devices

The availability of OTP devices is especially useful for
customers expecting frequent code changes and
updates.

The OTP devices, packaged in plastic packages, per­mit the user to program them once. In addition to the
program memory, the configuration bits must be pro­grammed.

2.3 Quic

k-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for fac­tory production orders. This ser vice is made available
for users who choose not to program a medium to high
quantity of units and whose code patterns have stabi­lized. The devices are identical to the OTP devices but
with all EPROM locations and configuration bit options
already programmed by the factory. Certain code and
prototype verification procedures apply before produc­tion shipments are available. Please contact your
Microchip Technology sales office for more details.

2.4 Serializ

ed
Quick-Turnaround-Production
(SQTP) Devices

Microchip offers the unique programming service where
a few user-defined locations in each device are pro­grammed with different serial numbers. The serial num­bers may be random, pseudo-random or sequential.

Serial programming allows each device to have a
unique number which can serve as an entry code,
password or ID number.

PIC16HV540

DS40197A-page 4

Preliminary



1998 Microchip Technology Inc.

3.0 ARCHITECTURAL OVERVIEW

FIGURE 3-1: PIC16HV540 BLOCK DIAGRAM

This section provides information on the architecture of the PIC16HV540. For information on operation of the periph­erals, electrical specifications, etc., please refer to the PIC16C5X data sheet (DS30453).

WDT
TIME
OUT

8

ST ACK 1

EPROM

512 X 12

INSTRUCTION

REGISTER

INSTRUCTION

DECODER

WA TCH-

DOG

CONFIGURA TION W ORD

OSCILLA T OR/

TIMING &

CONTROL

GENERAL
PURPOSE
REGISTER

FILE

(SRAM)

25 Bytes

WDT/TMR0

PRESCALER

OPTION

“OPTION”

“SLEEP”

“CODE

PROTECT”

“OSC

SELECT”

DIRECT ADDRESS

TMR0

FROM W

FROM W

“TRIS 5”

“TRIS 6”

FSR

TRISA PORTA

TRISB PORT

T0CKI

PIN

9-11

9-11

12

12

8

W

4

4

4

DATA BUS

8

8

8

8

ALU

STATUS

FROM W

CLKOUT

8

9

6

5

5-7

OSC1 OSC2 MCLR

LITERALS

PC

“DISABLE”

2

RA3:RA0

RB7:RB0

DIRECT RAM

ADDRESS

8

HIGH VOLTAGE

TRANSLA TION

VREG

3V/5V

Regulator

VDD

ST ACK 2
ST ACK 3
ST ACK 4

“TRIS 7”

FROM W

6

OPTION2

3V/5V

Regulator

BOD

BL/BE

RL/SL

VIO

PC

(PIN CHANGE)

WPC

4
RB3 : RB0

FILTER

RB7

SWE (OPTION2 REGISTER)



1998 Microchip Technology Inc.

Preliminary

DS40197A-page 5

PIC16HV540

TABLE 3-1: PINOUT DESCRIPTION - PIC16HV540

Name

DIP, SOIC

No.

SSOP

No.

I/O/P
Type

Input

Levels

Description

RA0
RA1
RA2
RA3

17
18

1
2

19
20

1
2

I/O
I/O
I/O
I/O

TTL
TTL
TTL
TTL

Independently regulated Bi-directional I/O port — V

IO

RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7

6
7
8

9
10
11
12
13

7
8

9
10
11
12
13
14

I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O

TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL

High-voltage Bi-directional I/O port.
Sourced from V

DD

.

T0CKI 3 3 I ST Clock input to Timer 0. Must be tied to VSS or V

DD,

if not in

use, to reduce current consumption.

MCLR/

V

PP

4 4 I ST Master clear (reset) input/programming voltage input. This

pin is an active low reset to the device. Voltage on the
MCLR

/V

PP

pin must not exceed VDD to avoid unintended

entering of programming mode.

OSC1/CLKIN 16 18 I ST Oscillator crystal input/external clock source input.

OSC2/CLKOUT 15 17 O — Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.

V

DD

14 15,16 P — Positive supply.

V

SS

5 5,6 P — Ground reference.

Legend: I = input, O = output, I/O = input/output,

P = power, — = Not Used, TTL = TTL input,
ST = Schmitt Trigger input

Wake up on
pin change.

Wake up on SLOW
rising pin change.

PIC16HV540

DS40197A-page 6

Preliminary



1998 Microchip Technology Inc.

4.0 MEMORY ORGANIZATION

FIGURE 4-1: PIC16HV540 PROGRAM

MEMORY MAP AND STACK

PC<8:0>

Stack Level 1
Stack Level 2

User Memory

Space

CALL, RETLW

9

000h

1FFh

Reset Vector

0FFh
100h

On-chip
Program
Memory

Stack Level 3
Stack Level 4

FIGURE 4-2: PIC16HV540 REGISTER FILE

MAP

File Address

00h
01h
02h
03h
04h
05h
06h
07h

1Fh

INDF

(1)

TMR0

PCL

STATUS

FSR
PORTA
PORTB

General

Purpose

Registers

Note 1: Not a physical register.

0Fh
10h

08h

TRISA
TRISB

OPTION2

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-On

Reset

Value on

MCLR

and

WDT Reset

N/A TRIS I/O control registers (TRISA, TRISB)

1111 1111 1111 1111

N/A OPTION Contains control bits to configure Timer0 and Timer0/WDT prescaler

--11 1111 --11 1111

N/A OPTION2 Contains control bits to configure pin changes, software enabled WDT,

xx11 1111 xx11 1111

regulation and brown-out

00h INDF Uses contents of FSR to address data memory (not a physical register)

xxxx xxxx uuuu uuuu

01h TMR0 8-bit real-time clock/counter

xxxx xxxx uuuu uuuu

02h

(1)

PCL Low order 8 bits of PC

1111 1111 1111 1111

03h STATUS PCF PA1 PA0 T

O PD ZDCC

1001 1xxx 100q quuu

04h FSR Indirect data memory address pointer

1xxx xxxx 1uuu uuuu

05h PORTA ————RA3RA2RA1RA0

---- xxxx ---- uuuu

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0

xxxx xxxx uuuu uuuu

Legend: Shaded boxes = unimplemented or unused, – = unimplemented, read as '0' (if applicable)

x

= unknown, u = unchanged, q = value depends on condition.

Note 1: The upper b yte of the Program Counter is not directly accessib le . See Section 4.5 of the PIC16C5X data sheet (DS30453)

for an explanation of how to access these bits.

2: File address 07h is a general purpose register on the PIC16HV540.

3: PCF This bit is set to 1 after power up-reset (POR) or sleep command.
4: PCF This bit is set to 0 after a wake up on pin change event.



1998 Microchip Technology Inc.

Preliminary

DS40197A-page 7

PIC16HV540

Figure 4-3: OPTION2 REGISTER (TRIS 07h)

U-0 U-0 W-1 W-1 W-1 W-1 W-1 W-1

- - WPC SWE RL SL BL BE W = Writable bit
U = Unimplemented bit

-n = Value at POR reset

bit7 6 5 4 3 2 1 0

bit 7-6:

Unimplemented.

bit 5:

WPC

: Wake up on pin change
1 = Disabled
0 = Enabled

bit 4:

SWE

: Software WDT enable
1 = Disabled
0 = Enabled

bit 3:

RL

: Regulated voltage level select bit
1 = 5 Volt
0 = 3 Volt

bit 2:

SL

: Sleep voltage level select bit
1 = RL bit setting
0 = 3 Volt

bit 1:

BL

: Brown-out voltage level select bit
1 = RL bit setting, but SL during sleep
0 = 3 Volt

bit 0:

BE

: Brown-out enabled
1 = Disabled
0 = Enabled

PIC16HV540

DS40197A-page 8

Preliminary



1998 Microchip Technology Inc.

5.0 INSTRUCTION SET SUMMARY

Each PIC16HV540 instruction is a 12-bit word divided into
an OPCODE, which specifies the instruction type, and one
or more operands which further specify the operation of
the instruction. The PIC16HV540 instruction set summary
in Table 5-2 groups the instructions into byte-oriented,
bit-oriented, and literal and control operations. Table 5-1
shows the opcode field descriptions.

For

byte-oriented

instructions, 'f' represents a file register
designator and 'd' represents a destination designator. The
file register designator is used to specify which one of the
32 file registers is to be used by the instruction.

The destination designator specifies where the result
of the operation is to be placed. If 'd' is '0', the result is
placed in the W register. If 'd' is '1', the result is placed
in the file register specified in the instruction.

For

bit-oriented

instructions, 'b' represents a bit field
designator which selects the number of the bit affected
by the operation, while 'f' represents the number of the
file in which the bit is located.

For

literal and control

operations, 'k' represents an

8 or 9-bit constant or literal value.

TABLE 5-1: OPCODE FIELD

DESCRIPTIONS

Field Description

f

Register file address (0x00 to 0x7F)

W

Working register (accumulator)

b

Bit address within an 8-bit file register

k

Literal field, constant data or label

x

Don't care location (= 0 or 1)
The assembler will generate code with x = 0. It is
the recommended form of use for compatibility
with all Microchip software tools.

d

Destination select;

d = 0 (store result in W)
d = 1 (store result in file register 'f')

Default is d = 1

label

Label name

TOS

Top of Stack

PC Program Counter

WDT Watchdog Timer Counter

TO

Time-Out bit

PD Power-Down bit

dest

Destination, either the W register or the specified
register file location

[ ]

Options

( )

Contents

→

Assigned to

< >

Register bit field

∈

In the set of

i

talics

User defined term (font is courier)

All instructions are executed within one single
instruction cycle, unless a conditional test is true or the
program counter is changed as a result of an
instruction. In this case, the execution takes two
instruction cycles. One instruction cycle consists of
four oscillator periods. Thus, for an oscillator frequency
of 4 MHz, the normal instruction execution time is 1 µs.
If a conditional test is true or the program counter is
changed as a result of an instruction, the instruction
execution time is 2 µs.

Figure 5-1 shows the three general formats that the
instructions can have. All examples in the figure use the
following format to represent a hexadecimal number:

0xhhh

where 'h' signifies a hexadecimal digit.

FIGURE 5-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented file register operations

11 6 5 4 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f
f = 5-bit file register address

Bit-oriented file register operations

11 8 7 5 4 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address
f = 5-bit file register address

Literal and control operations (except GOTO)

11 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Literal and control operations - GOTO instruction

11 9 8 0

OPCODE k (literal)

k = 9-bit immediate value

 1998 Microchip Technology Inc. Preliminary DS40197A-page 9

PIC16HV540

TABLE 5-2: INSTRUCTION SET SUMMARY

Mnemonic,

Operands Description Cycles

12-Bit Opcode

Status

Affected NotesMSb LSb

ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF

f,d
f,d
f
–
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
–
f, d
f, d
f, d
f, d
f, d

Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate left f through Carry
Rotate right f through Carry
Subtract W from f
Swap f
Exclusive OR W with f

1
1
1
1
1
1

1(2)

1

1(2)

1
1
1
1
1
1
1
1
1

0001
0001
0000
0000
0010
0000
0010
0010
0011
0001
0010
0000
0000
0011
0011
0000
0011
0001

11df
01df
011f
0100
01df
11df
11df
10df
11df
00df
00df
001f
0000
01df
00df
10df
10df
10df

ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff

C,DC,Z

Z
Z
Z
Z
Z

None

Z

None

Z

Z
None
None

C

C

C,DC,Z

None

Z

1,2,4

2,4

4

2,4
2,4
2,4
2,4
2,4
2,4
1,4

2,4
2,4

1,2,4

2,4
2,4

BIT-ORIENTED FILE REGISTER OPERATIONS
BCF

BSF
BTFSC
BTFSS

f, b
f, b
f, b
f, b

Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set

1

1
1 (2)
1 (2)

0100
0101
0110
0111

bbbf
bbbf
bbbf
bbbf

ffff
ffff
ffff
ffff

None
None
None
None

2,4
2,4

LITERAL AND CONTROL OPERATIONS
ANDLW

CALL
CLRWDT
GOTO
IORLW
MOVLW
OPTION
RETLW
SLEEP
TRIS
XORLW

k
k
k
k
k
k
k
k
–
f
k

AND literal with W
Call subroutine
Clear Watchdog Timer
Unconditional branch
Inclusive OR Literal with W
Move Literal to W
Load OPTION register
Return, place Literal in W
Go into standby mode
Load TRIS register
Exclusive OR Literal to W

1

2

1

2

1

1

1

2

1

1

1

1110
1001
0000
101k
1101
1100
0000
1000
0000
0000
1111

kkkk
kkkk
0000
kkkk
kkkk
kkkk
0000
kkkk
0000
0000
kkkk

kkkk
kkkk
0100
kkkk
kkkk
kkkk
0010
kkkk
0011
0fff
kkkk

Z

None

T

O, PD

None

Z
None
None
None

T

O, PD

None

Z

1

3

Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO.

(See individual device data sheets, Memory Section/Indirect Data Addressing, INDF and FSR Registers)

2: When an I/O register is modified as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven
low by an external device , the data will be written back with a '0'.

3: The instruction TRIS f, where f = 5 or 6 causes the contents of the W register to be written to the tristate

latches of PORTA or B respectively . A '1' forces the pin to a hi-impedance state and disables the output buffers .

4: If this instruction is executed on the TMR0 register (and, where applicable , d = 1), the prescaler will be cleared

(if assigned to TMR0).

PIC16HV540

DS40197A-page 10 Preliminary  1998 Microchip Technology Inc.

ADDWF Add W and f

Syntax: [

label

] ADDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]
Operation: (W) + (f) → (dest)
Status Affected: C, DC, Z
Encoding:

0001 11df ffff

Description:

Add the contents of the W register and

register 'f'. If 'd' is 0 the result is stored

in the W register . If 'd' is '1' the result is

stored back in register 'f'

.
Words: 1
Cycles: 1
Example:

ADDWF FSR, 0

Before Instruction

W = 0x17
FSR = 0xC2

After Instruction

W = 0xD9
FSR = 0xC2

ANDLW And literal with W

Syntax: [

label

] ANDLW k
Operands: 0 ≤ k ≤ 255
Operation: (W).AND. (k) → (W)
Status Affected: Z
Encoding:

1110 kkkk kkkk

Description:

The contents of the W register are
AND’ed with the eight-bit literal 'k'. The
result is placed in the W register

.
Words: 1
Cycles: 1
Example:

ANDLW 0x5F

Before Instruction

W = 0xA3

After Instruction

W = 0x03

ANDWF AND W with f

Syntax: [

label

] ANDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]
Operation: (W) .AND. (f) → (dest)
Status Affected: Z
Encoding:

0001 01df ffff

Description:

The contents of the W register are

AND’ed with register 'f'. If 'd' is 0 the

result is stored in the W register . If 'd' is

'1' the result is stored back in register 'f'

.
Words: 1
Cycles: 1
Example:

ANDWF FSR, 1

Before Instruction

W = 0x17
FSR = 0xC2

After Instruction

W = 0x17
FSR = 0x02

BCF Bit Clear f

Syntax: [

label

] BCF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7
Operation: 0 → (f<b>)
Status Affected: None
Encoding:

0100 bbbf ffff

Description:

Bit 'b' in register 'f' is cleared.

Words: 1
Cycles: 1
Example:

BCF FLAG_REG, 7

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

 1998 Microchip Technology Inc. Preliminary DS40197A-page 11

PIC16HV540

BSF Bit Set f

Syntax: [

label

] BSF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7
Operation: 1 → (f<b>)
Status Affected: None
Encoding:

0101 bbbf ffff

Description:

Bit 'b' in register 'f' is set.

Words: 1
Cycles: 1
Example:

BSF FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

BTFSC Bit Test f, Skip if Clear

Syntax: [

label

] BTFSC f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7
Operation: skip if (f<b>) = 0
Status Affected: None
Encoding: 0110

bbbf ffff

Description:

If bit 'b' in register 'f' is 0 then the next

instruction is skipped.

If bit 'b' is 0 then the next instruction

fetched during the current instruction

execution is discarded, and an NOP is

executed instead, making this a 2 cycle

instruction.

Words: 1
Cycles: 1(2)
Example:

HERE

FALSE

TRUE

BTFSC
GOTO

•

•

•

FLAG,1
PROCESS_CODE

Before Instruction

PC = address (HERE)

After Instruction

if FLAG<1> = 0,
PC = address (TRUE);
if FLAG<1> = 1,
PC = address(FALSE)

BTFSS Bit Test f, Skip if Set

Syntax: [

label

] BTFSS f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b < 7
Operation: skip if (f<b>) = 1
Status Affected: None
Encoding:

0111 bbbf ffff

Description:

If bit 'b' in register 'f' is '1' then the next

instruction is skipped.

If bit 'b' is '1', then the next instruction

fetched during the current instruction

execution, is discarded and an NOP is

executed instead, making this a 2 cycle

instruction.

Words: 1
Cycles: 1(2)
Example:

HERE BTFSS FLAG,1

FALSE GOTO PROCESS_CODE

TRUE •

•

•

Before Instruction

PC = address (HERE)

After Instruction

If FLAG<1> = 0,
PC = address (FALSE);
if FLAG<1> = 1,
PC = address (TRUE)