Microchip Technology Inc PIC16F77-I-P, PIC16F74-I-P Datasheet
PIC16F7X
28/40-Pin 8-Bit CMOS FLASH Microcontrollers
Devices Included in this Data Sheet:
•PIC16F73
•PIC16F74
•PIC16F76
•PIC16F77
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• Up to 8K x 14 words of FLASH Progr am Mem ory,
Up to 368 x 8 bytes of Data Memory (RAM)
• Pinout compatible to the PIC16C73B/74B/76/77
• Pinout compatible to the PIC16F873/874/876/877
• Interrupt capability (up to 12 sources)
• Eight level deep hardware stack
• Direct, Indirect and Relative Addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable opera tion
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low power, high speed C MOS F LASH tech no log y
• Fully static design
• In-Circuit Serial Programming (ICSP) via two
pins
• Processor read access to program memory
• Wide operating voltage range: 2.0V to 5.5V
• High Sink/Source Current: 25 mA
• Industrial temperature range
• Low power consumption:
- < 2 mA typical @ 5V, 4 MHz
-20 µA typical @ 3V, 32 kHz
-< 1 µA typical standby current
Pin Diagram
PDIP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
REF
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
RE1/WR/AN6
/AN7
RE2/CS
VDD
VSS
OSC1/CLKIN
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PIC16F77/74
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
V
DD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during SLEEP via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Two Capture, Compare, PWM modul es
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 8-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with SPI
mode) and I
2C
(Slave)
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Parallel Slave Port (PSP) 8-bits wide, with
external RD
, WR and CS controls (40/44-pin only)
• Brown-out detection circuitry for
Brown-out Reset (BOR)
(Master
2000 Microchip Technology Inc. Advance Information DS30325A-page 1
PIC16F7X
Pin Diagrams
DIP, SOIC, SSOP
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC3/SCK/SCL
REF
RA4/T0CKI
RA5/AN4/SS
VSS
RC2/CCP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIC16F76/73
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
V
DD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
/VPP
PLCC
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
MCLR
NC
RB7
RB6
RB5
RB4
NC
RA4/T0CKI
RA5/AN4/SS
RE0/RD/AN5
RE1/WR
/AN6
RE2/CS
/AN7
V
DD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CK1
NC
65432
7
8
9
10
11
12
13
14
15
16
17
181920212223242526
1
44
PIC16F77
PIC16F74
40
41
42
43
39
38
37
36
35
34
33
32
31
30
29
27
28
RB3
RB2
RB1
RB0/INT
V
DD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
V
VDD
RB0/INT
RB1
RB2
RB3
NC
RC5/SDO
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
QFP
SS
RC6/TX/CK
4443424140
1
2
3
4
5
6
7
8
9
10
11
121314
NC
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
39
PIC16F77
PIC16F74
16
17
15
NC
RB4
RB5
RB7
RB6
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
363435
37
38
1819202122
/VPP
RA2/AN2
RA1/AN1
RA0/AN0
MCLR
NC
33
32
31
30
29
28
27
26
25
24
23
RA3/AN3/VREF
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
SS
V
VDD
RE2/AN7/CS
RE1/AN6/WR
RE0/AN5/RD
RA5/AN4/SS
RA4/T0CKI
RC2/CCP1
RC3/SCK/SCL
RC1/T1OSI/CCP2
RC6/TX/CK
RC4/SDI/SDA
DS30325A-page 2 Advance Information 2000 Microchip Technology Inc.
PIC16F7X
PICmicro™ Mid-Range Reference Manual
Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz
RESETS (and Delays) POR, BOR
FLASH Program Memory
(14-bit words, 100 E/W cycles)
Data Memory (bytes) 192 192 368 368
Interrupts 11 12 11 12
I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E
Timers 3333
Capture/Compare/PWM Modules 2 2 2 2
Serial Communications SSP, USART SSP, USART SSP, USART SSP, USART
Parallel Communications — PSP — PSP
8-bit Analog-to-Digital Module 5 Input Channels 8 Input Channels 5 Input Channels 8 Input Channels
Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions
Key Features
(DS33023)
PIC16F73 PIC16F74 PIC16F76 PIC16F77
POR, BOR
(PWRT, OST)
4K 4K 8K 8K
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
2000 Microchip Technology Inc. Advance Information DS30325A-page 3
PIC16F7X
Table of Contents
1.0 Device Overview............................................................................................................................................................5
2.0 Memory Organization .................................................................................................................................................. 11
3.0 I/O Ports............ ............ ............. ............. ............ ............. ............ ............. ............. .. .................................................... 29
4.0 Reading Program Memory............................................................................................... .... ........................................41
5.0 Timer0 Module.............................................................................................................................................................45
6.0 Timer1 Module.............................................................................................................................................................49
7.0 Timer2 Module.............................................................................................................................................................53
8.0 Capture/Compare/PWM Modules................................................................. .... ....... .... .... .. .... ......................................55
9.0 Synchronous Serial Port (SSP) Module.......................................................................................................................61
10.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ......................................................................73
11.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................... 89
12.0 Special Featur e s of th e CPU........................................... ............ ............. ............. ...................................................... 95
13.0 Instruction Set Summary ...........................................................................................................................................111
14.0 Development Support................................................................................................................................................ 119
15.0 Electrical Characteristics ........................................................................................................................................... 125
16.0 DC and AC Characteristics Graphs and Tables ........................................................................................................147
17.0 Packaging Information................................ ............ ............. ............. ............ ............. ................................................149
Appendix A: Revision History.........................................................................................................................................................157
Appendix B: Device Differences.....................................................................................................................................................157
Appendix C: Conversion Considerations .................................................................... .. .. .... .. ....... .. ................................................157
Index .................................................................................................................................................................................................. 159
On-Line Support........................................................................ .... .... ....... .... .. .... .... ....... .... ................................................................. 165
Reader Response..............................................................................................................................................................................166
PIC16F7X Product Identification System. .......................................................................................................................................... 167
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with t he best documen tation possible to ensure successf ul use of your Mic rochip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined
and enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department
via E-mail at docerrors@mail.m ic rochip.com or fax the Reader Response Form in the back of this data sheet to (480) 786-
7578. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (480) 786-7277
When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using.
Customer Notification System
Register on our web site at www.microchip.com/cn to receive the most current information on all of our products.
DS30325A-page 4 Advance Information 2000 Microchip Technology Inc.
PIC16F7X
1.0 DEVICE OVERVIEW
This document contains device specific information.
Additional information m ay be found in the PICm ic ro™
Mid-Range Reference Manual (DS33023), which may
be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The
Reference Manual should be considered a complementary documen t to thi s dat a she et, and is hig hly re commended reading for a better understanding of the
device architecture and operation of the peripheral
There are four devices (PIC16F73, PIC16F74,
PIC16F76 an d PIC1 6F77) co vered by this data sheet .
The PIC16F76/73 dev ices are availab le in 28 -pin p ackages and the PIC16F77/74 devices are available in
40-pin packages. The 28-pin devices do not have a
Parallel Slave Port implemented.
The following two figures are device block diagrams
sorted by pin number; 28-pin for Figure 1-1 and 40-pin
for Figure 1-2. The 28-pin and 40-pin pinouts are li sted
in Table 1-1 and Table 1-2, respectively.
modules.
FIGURE 1-1: PIC16F73 AND PIC16F76 BLOCK DIAGRAM
Program
Bus
Program
FLASH
FLASH
Program
Memory
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
Data Memory
13
Program Counter
8 Level Stack
(13-bit)
Direct Addr
8
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
RAM Addr (1)
7
8
Data Bus
3
RAM
File
Registers
9
Addr MUX
8
FSR reg
STATUS reg
MUX
ALU
W reg
Device
PIC16F73 4K 192 Bytes
PIC16F76 8K 368 Bytes
OSC1/CLKIN
OSC2/CLKOUT
8
Indirect
Addr
PORTA
PORTB
PORTC
RA0/AN0
RA1/AN1
RA2/AN2/
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
MCLR
VDD, VSS
8-bit A/DTimer0 Timer1 Timer2
CCP1,2
Note 1: Higher order bits are from the STATUS register.
Synchronous
Serial Port
USART
2000 Microchip Technology Inc. Advance Information DS30325A-page 5
PIC16F7X
FIGURE 1-2: PIC16F74 AND PIC16F77 BLOCK DIAGRAM
Device
Program
FLASH
Data Memory
PIC16F74 4K 192 Bytes
PIC16F77 8K 368 Bytes
13
Program Counter
Direct Addr
8
Start-up Timer
MCLR
Program
Bus
OSC1/CLKIN
OSC2/CLKOUT
FLASH
Program
Memory
14
Instruction reg
Instruction
Decode &
Control
Timing
Generation
8 Level Stack
(13-bit)
Power-up
Timer
Oscillator
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
VDD, VSS
RAM Addr (1)
7
8
Data Bus
RAM
File
Registers
Addr MUX
FSR reg
STATUS reg
3
ALU
W reg
Parallel Slave Port
9
8
MUX
8
Indirect
Addr
PORTA
PORTB
PORTC
PORTD
PORTE
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/AN4/SS
RB0/INT
RB1
RB2
RB3/PGM
RB4
RB5
RB6/PGC
RB7/PGD
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD0/PSP0
RD1/PSP1
RD2/PSP2
RD3/PSP3
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
RE0/AN5/RD
RE1/AN6/WR
RE2/AN7/CS
8-bit A/DTimer0 Timer1 Timer2
CCP1,2
Note 1: Higher order bits are from the STATUS register.
Synchronous
Serial Port
USART
DS30325A-page 6 Advance Information 2000 Microchip Technology Inc.
TABLE 1-1: PIC16F73 AND PIC16F76 PINOUT DESCRIPTION
PIC16F7X
Pin Name
OSC1/CLKIN 9 9 I ST/CMOS OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connec ts to crystal or resonator in Crys-
MCLR
/VPP 1 1 I/P ST Master clear (RESET) input or programming voltage input or High
RA0/AN0 2 2 I/O TTL RA0 can also be analog input0. RA1/AN1 3 3 I/O TTL RA1 can also be analog input1. RA2/AN2 4 4 I/O TTL RA2 can also be analog input2. RA3/AN3/V RA4/T0CKI 6 6 I/O ST RA4 ca n also be th e cloc k input t o the T ime r0 module. Ou tput
RA5/SS/
RB0/INT 21 21 I/O RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3 24 24 I/O TTL
RB4 25 25 I/O TTL Interrupt-on-change pin.
RB5 26 26 I/O TTL Interrupt-on-change pin.
RB6 27 27 I/O
RB7 28 28 I/O
RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock
RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Time r1 oscillator i nput or Capture2 in put/
RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Comp are1 outpu t/PWM1
RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchr onous seri al clock inpu t/ou tput for
RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or
RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or
V
SS 8, 19 8, 19 P — Ground reference for logic and I/O pins.
V
DD 20 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
REF 5 5 I/O TTL RA3 can also be analog input3 or analog ref erence voltage.
AN4 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the
2: This buffer is a Schmitt Tri gger input when used in Serial Programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input ot herwise.
DIP
Pin#
— = Not used TTL = TTL input ST = Schmitt Trigger input
SSOP
SOIC
Pin#
I/O/P
Type
Buffer
Type
TTL/ST
TTL/ST
TTL/ST
Description
(3)
Oscillator crystal input/external clock source input.
tal Oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT
which has 1/4 the frequency of OSC1, and deno tes t he instr uctio n
cycle rate.
Voltage Test mode control. This pin is an active low RESET to the
device.
PORTA is a bi-directional I/O port.
is open drain type.
synchronous serial port.
PORTB is a bi-directio nal I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
(2)
(2)
RB0 can also be the external interrupt pin.
Interrupt-on-change pi n or Serial programming clock.
Interrupt-on-change pi n or Serial programming data.
PORTC is a bi-directional I/O port.
input.
Compare2 output/PWM2 output.
output.
both SPI and I
Data I/O (I
Synchronous Clock.
Synchronous Data.
2
C modes.
2
C mode).
2000 Microchip Technology Inc. Advance Information DS30325A-page 7
PIC16F7X
TABLE 1-2: PIC16F74 AND PIC16F77 PINOUT DESCRIPTION
DIP
Pin Name
OSC1/CLKIN 13 14 30 I OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in
MCLR
/VPP 1 2 18 I/P ST Master clear (RESET) input or programming v oltage input or
RA0/AN0 2 3 19 I/O TTL RA0 can also be analog input0. RA1/AN1 3 4 20 I/O TTL RA1 can also be analog input1. RA2/AN2 4 5 21 I/O TTL RA2 can also be analog input2. RA3/AN3/V
RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/
RA5/SS/
RB0/INT 33 36 8 I/O RB1 34 37 9 I/O TTL
RB2 35 38 10 I/O TTL
RB3 36 39 11 I/O TTL
RB4 37 41 14 I/O TTL Interrupt-on-change pin.
RB5 38 42 15 I/O TTL Interrupt-on-change pin.
RB6 39 43 16 I/O
RB7 40 44 17 I/O
RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1
RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2
RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/
RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchrono us ser ial c lock input /out put
RC4/SDI/SDA 23 25 42 I/ O ST RC4 can also be the SP I D ata In (SPI mo d e) or
RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or
RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or
Legend: I = input O = output I/O = input/output P = power
REF 5 6 22 I/O TTL RA3 can also be analog input3 or analog reference
AN4 7 8 24 I/O TTL RA5 can also be analog input4 or the slave select for the
Pin#
PLCC
Pin#
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
2:
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave
Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
QFP
Pin#
I/O/P
Type
Buffer
Type
ST/CMOS
TTL/ST
TTL/ST
TTL/ST
Description
(4)
Oscillator crystal input/external clock source input.
Crystal Oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
High Voltage Test mode control. This pin is an active low
RESET to the device.
PORTA is a bi-directiona l I/O po r t.
voltage.
counter. Output is open drain type.
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
(1)
(2)
(2)
RB0 can also be the external interrupt pin.
Interrupt-on-change pin or Serial programming clock.
Interrupt-on-change pin or Serial programming data.
PORTC is a bi-dir ec t i onal I/O port.
clock input.
input/Compare2 output/PWM2 output.
PWM1 output.
2
C mode).
2
C modes.
for both SPI and I
Data I/O (I
Synchronous Clock.
Synchronous Data.
DS30325A-page 8 Advance Information 2000 Microchip Technology Inc.
PIC16F7X
TABLE 1-2: PIC16F74 AND PIC16F77 PINOUT DESCRIPTION (CONTINUED)
DIP
Pin Name
RD0/PSP0 RD1/PSP1 20 22 39 I/O RD2/PSP2 21 23 40 I/O RD3/PSP3 22 24 41 I/O RD4/PSP4 27 30 2 I/O RD5/PSP5 28 31 3 I/O RD6/PSP6 29 32 4 I/O RD7/PSP7 30 33 5 I/O
RE0/RD
/AN5 8925I/O
RE1/WR
/AN6 91026I/O
RE2/CS
/AN7 10 11 27 I/O
V
SS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins.
V
DD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins.
NC
Legend: I = input O = output I/O = input/output P = power
PLCC
Pin#
— = Not used TTL = TTL input ST = Schmitt Trigger input
Pin#
19 21 38 I/O
— 1,17,28,4012,13,
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2:
This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave
Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when conf igured in RC Oscillator mode and a CMOS input otherwise.
QFP
Pin#
33,34
I/O/P
Type
Buffer
Type
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
ST/TTL
— These pins are not internally connected. These pins should be
Description
PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus.
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
PORTE is a bi-directional I/ O port.
(3)
(3)
(3)
RE0 can also be read control for the p ar allel slave port, or
analog input5.
RE1 can also be write cont rol for t he p a ralle l slave por t, or
analog input6.
RE2 can also be select control for the parallel slave port,
or analog input7.
left unconnect ed.
2000 Microchip Technology Inc. Advance Information DS30325A-page 9
PIC16F7X
NOTES:
DS30325A-page 10 Advance Information 2000 Microchip Technology Inc.
PIC16F7X
2.0 MEMORY ORGANIZATION
There are two memory blocks in each of these
PICmicro
Memory have separate buses so that concurrent
access can oc cur and is detailed in this section. The
Program Mem ory can be read i ntern ally by user co de
(see Section 4.0).
Additional informa tion on devi ce memory may be found
in the PICmicro Mid-Range Reference Manual,
(DS33023).
2.1 Program Memory Organization
The PIC16F7X devices have a 13-bit program counter
capable of addressing an 8K x 14 program memory
space. The PIC 16F77 /7 6 devic es have 8K x 14 wo rds
of FLASH program memory and the PIC16F73/74
devices have 4K x 14. Ac cess ing a lo cati on ab ove t he
physically implemented address will cause a wraparound.
The RESET Ve ctor is at 0000h an d the Interrup t V ector
is at 0004h.
FIGURE 2-1: PIC16F77/76 PROGRAM
®
MCUs. The Program Memory and Data
MEMORY MAP AND STACK
PC<12:0>
FIGURE 2-2: PIC16F74/73 PROGRAM
MEMORY MAP AND STACK
PC<12:0>
CALL, RETURN
RETFIE, RETLW
On-Chip
Program
Memory
Stack Level 1
Stack Level 2
Stack Level 8
RESET Vector
Interrupt Vector
Page 0
Page 1
13
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
CALL, RETURN
RETFIE, RETLW
On-Chip
Program
Memory
Stack Level 1
Stack Level 2
Stack Level 8
Reset Vector
Interrupt Vector
Page 0
Page 1
Page 2
Page 3
13
1FFFh
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
17FFh
1800h
1FFFh
2000 Microchip Technology Inc. Advance Information DS30325A-page 11
PIC16F7X
2.2 Data Memory Organization
The Data Memory is partitioned into multiple banks,
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 (STATUS<6>)
and RP0 (STATUS<5>) are the bank select bits.
RP1:RP0 Bank
00 0
01 1
10 2
11 3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are Gener al Purpose Registers, implemented as
static RAM. All implemented banks contain Special
Function Registers. Some frequently used Special
Function Registers from one bank may be mirrored in
another bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER FILE The register file can be acces sed either directly, or indi-
rectly, through the File Select Register FSR.
DS30325A-page 12 Advance Information 2000 Microchip Technology Inc.
FIGURE 2-3: PIC16F77/76 REGIST ER FIL E MAP
PIC16F7X
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
CCP1CON
CCP2CON
(1)
(1)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
ADRES
ADCON0
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
(1)
TRISD
(1)
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
PMDATA
PMADR
PMDATH
PMADRH
General
Purpose
Register
16 Bytes
File
Address
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h
Indirect addr .(*)
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
PMCON1
General
Purpose
Register
16 Bytes
File
Address
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh
1A0h
General
Purpose
Register
96 Bytes
7Fh
Bank 0
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
Note 1: These registers are not impleme nte d on 28-pin devi ces.
2000 Microchip Technology Inc. Advance Information DS30325A-page 13
General
Purpose
Register
80 Bytes 80 Bytes 80 Bytes
accesses
70h-7Fh
Bank 1
EFh
F0h
FFh
General
Purpose
Register
accesses
70h-7Fh
Bank 2
16Fh
170h
17Fh
General
Purpose
Register
accesses
70h - 7Fh
Bank 3
1EFh
1F0h
1FFh
PIC16F7X
FIGURE 2-4: PIC16F74/73 REGIST ER FIL E MAP
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
PORTE
SSPCON
CCPR1H
CCP1CON
CCP2CON
(1)
(1)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
CCPR1L
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
ADRES
ADCON0
File
Address
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
(1)
TRISD
(1)
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1
File
Address
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTB
PCLATH
INTCON
PMDATA
PMADR
PMDATH
PMADRH
File
Address
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
120h
Indirect addr.(*)
OPTION_REG
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
PMCON1
File
Address
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
1A0h
General
Purpose
Register
96 Bytes
7Fh
Bank 0
Unimplemented data memory locations, read as ’0’.
* Not a physical register.
Note 1: These registers are not implemented on 28-pin devices.
DS30325A-page 14 Advance Information 2000 Microchip Technology Inc.
General
Purpose
Register
96 Bytes
Bank 1
FFh
accesses
20h-7Fh
Bank 2
16Fh
170h
17Fh
accesses
A0h - FFh
1EFh
1F0h
1FFh
Bank 3
PIC16F7X
2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
given in Table 2-1.
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Bank 0
(4)
00h
01h TMR0 Timer0 Module’s Register xxxx xxxx uuuu uuuu
02h
03h
04h
05h PORTA — — PORTA Data Latch when written: PORTA pins when read
06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h
09h
0Ah
0Bh
0Ch PIR1
0Dh PIR2 — — — — — — — CCP2IF
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 Register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
11h TMR2 Timer2 Module’s Register
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB)
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0
18h RCSTA SPEN R X9 SREN CREN — FERR OERR RX9D
19h TXREG USART Transmit Data Register
1Ah RCREG USART Receive Data Register
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0
1Eh ADRES A/D Result Register Byte
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0
Legend: x = unknown, u = unchanged, q = value depe nds on condition, - = unimplemented read as '0', r = reserved.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
INDF Addressing this location uses contents of FSR to address data memory (not a physical register)
(4)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(4)
STATUS IRP RP1 RP0 TO PD ZDCC
(4)
FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
(5)
PORTD PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
(5)
PORTE — — — — — RE2 RE1 RE0
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
(4)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
(3)
PSPIF
Shaded locations are unimple mented, read as ‘0’.
contents are tran sf erred to the upper byte of the pr ogram counter.
2: Other (non power-up) RESETS include external RESET through MCLR
3: Bits PSPI E an d PSPIF are reser v e d on the 28-pin dev i ce s ; al w ays maintain th es e bi ts cle a r.
4: These registers can be addressed from any ban k.
5: PORTD, PORTE, TRISD, and TRISE are not physically implement ed on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
GO/
DONE
and Watchdog Timer Reset.
— ADON 0000 00-0 0000 00-0
0000 0000 0000 0000
0001 1xxx 000q quuu
--0x 0000 --0u 0000
---- -xxx ---- -uuu
0000 000x 0000 000u
---- ---0 ---- ---0
--00 0000 --uu uuuu
0000 0000 0000 0000
-000 0000 -000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
--00 0000 --00 0000
0000 -00x 0000 -00x
0000 0000 0000 0000
0000 0000 0000 0000
--00 0000 --00 0000
xxxx xxxx uuuu uuuu
Value on
all other
RESETS
(2)
2000 Microchip Technology Inc. Advance Information DS30325A-page 15
PIC16F7X
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR,
BOR
Value on:
Bank 1
80h
81h
82h
83h
84h
(4)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register)
OPTION_
REG
(4)
PCL Program Counter’s (PC) Least Significant Byte
(4)
STATUS IRP RP1 RP0 TO PD ZDCC
(4)
FSR Indirect data memory address pointer
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
0000 0000 0000 0000
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register
87h TRISC PORTC Data Direction Register
(5)
88h
89h
8Ah
8Bh
8Ch PIE1
TRISD PORTD Data Direction Register
(5)
TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter
(4)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
(3)
PSPIE
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1111
0000 -111 0000 -111
---0 0000 ---0 0000
0000 000x 0000 000u
0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
8Eh PCON — — — — — — POR BOR
8Fh — Unimplemented
90h — Unimplemented
91h — Unimplemented
---- --qq ---- --uu
— —
— —
— —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD
Synchronous Serial Port (I
2
C mode) Address Register
94h SSPSTAT SMP CKE D/A PSR/WUA BF
95h — Unimplemented
0000 0000 0000 0000
0000 0000 0000 0000
— —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D
99h SPBRG Baud Rate Generator Register
9Ah — Unimplemented
9Bh — Unimplemented
9Ch — Unimplemented
0000 -010 0000 -010
0000 0000 0000 0000
— —
— —
— —
9Dh — Unimplemented — —
9Eh — Unimplemented
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0
— —
---- -000 ---- -000
Legend: x = unknown, u = unchanged, q = value depe nds on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimple mented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are transferred to the upper byte of the program counter.
2: Other (non power-up) RESETS include external RESET through MCLR
and Watchdog Timer Reset.
3: Bits PSPI E an d PSPIF are reser v e d on the 28-pin dev i ce s ; al w ays maintain th es e bi ts cle a r.
4: These registers can be addressed from any ban k.
5: PORTD, PORTE, TRISD, and TRISE are not physically implemented on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
Value on
all other
RESETS
(2)
DS30325A-page 16 Advance Information 2000 Microchip Technology Inc.
PIC16F7X
TABLE 2-1: SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR,
BOR
Value on:
Bank 2
(4)
100h
INDF Addressing this location uses contents of FSR to address data memory (not a physical register)
101h TMR0 Timer0 Module’s Register
(4)
102h
103h
104h
PCL Program Counter's (PC) Least Significant Byte
(4)
STATUS IRP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu
(4)
FSR Indirect Data Memory Address Pointer
105h — Unimplemented
106h PORTB PORTB Data Latch when written: PORTB pins when read
107h — Unimplemented
108h — Unimplemented
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
xxxx xxxx uuuu uuuu
— —
xxxx xxxx uuuu uuuu
— —
— —
109h — Unimplemented — —
10Ah
10Bh
(1,4)
PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter
(4)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
---0 0000 ---0 0000
0000 000x 0000 000u
10Ch PMDATA Data Register Low Byte xxxx xxxx uuuu uuuu
10Dh PMADR Address Register Low Byte
10Eh PMDATH — — Data Register High Byte
10Fh PMADRH — — — Address Register High Byte
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
Bank 3
(4)
180h
181h
182h
183h
184h
INDF Addressing this location uses contents of FSR to address data memory (not a physical register)
OPTION_
REG
(4)
PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
(4)
STATUS IRP RP1 RP0 TO PD Z DC C
(4)
FSR Indirect Data Memory Address Pointer xxxx xxxx uuuu uuuu
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
185h — Unimplemented
186h TRISB PORTB Data Direction Register
187h — Unimplemented — —
188h — Unimplemented
189h — Unimplemented
(1,4)
18Ah
18Bh
PCLATH — — —
(4)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
18Ch PMCON1
—
(6)
— — — — — — RD
Write Buffer for the upper 5 bits of the Program Counter
18Dh — Unimplemented — —
18Eh — Reserved maintain clear 0000 0000 0000 0000
18Fh — Reserved maintain clear
Legend: x = unknown, u = unchanged, q = value depe nds on condition, - = unimplemented read as '0', r = reserved.
Shaded locations are unimple mented, read as ‘0’.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose
contents are tran sf erred to the upper byte of the pr ogram counter.
2: Other (non power-up) RESETS include external RESET through MCLR
and Watchdog Timer Reset.
3: Bits PSPI E an d PSPIF are reser v e d on the 28-pin dev i ce s ; al w ays maintain th es e bi ts cle a r.
4: These registers can be addressed from any ban k.
5: PORTD, PORTE, TRISD, and TRISE are not physically implement ed on the 28-pin devices, read as ‘0’.
6: This bit always reads as a ‘1’.
0000 0000 0000 0000
1111 1111 1111 1111
0001 1xxx 000q quuu
— —
1111 1111 1111 1111
— —
— —
---0 0000 ---0 0000
0000 000x 0000 000u
1--- ---0 1--- ---0
0000 0000 0000 0000
Value on
all other
RESETS
(2)
2000 Microchip Technology Inc. Advance Information DS30325A-page 17
PIC16F7X
2.2.2.1 STATUS Register The STATUS register contains the arithmetic status of
the ALU, the RESET statu s and the b ank sele ct bit s for
data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC, or C bits, then the wri te to thes e three bi ts is
disabled. These bit s are set or cleared ac cording to the
device logic. Furthermore, the TO
writable, therefore, the result of an instruction with the
STATUS r egister as dest ination may be di fferent than
intended.
and PD bits are not
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This le aves the STATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C, or DC bits from the STATUS register.
For other in s tru ct i o ns no t aff ec t in g an y s tat us b its, s ee
the "Instruction Set Summary."
Note 1: The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
REGISTER 2-1: STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO
bit 7 bit 0
bit 7 IRP: Register Bank Select bit (used for indirec t addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5 RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4 TO
bit 3 PD: Pow er-down bit
bit 2 Z: Zero bit
bit 1 DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
bit 0 C: Carry/borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
(for borrow
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
the polarity is reversed)
PD ZDCC
Note: For borrow
complement of the second operand. For rotate (RRF, RLF) instructions, this bit is
loaded with either the high or low order bit of the source register.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS30325A-page 18 Advance Information 2000 Microchip Technology Inc.
, the polarity is reversed. A subtraction is executed by adding the two’s
2.2.2.2 OPTION_REG Register The OPTION_REG register is a readable and writable
register , which cont ains various contr ol bits to conf igure
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
the TMR0 prescaler/WDT postscaler (single assignable register k nown als o as th e presca ler), t he Externa l
INT Interrupt, TMR0 and the w eak pull-up s on POR TB.
REGISTER 2-2: OPTION_REG REGISTER (ADDRESS 81h, 181h)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0
bit 7 bit 0
PIC16F7X
bit 7 RBPU
: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6 INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5 T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock ( CLKOUT)
bit 4 T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3 PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0 PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc. Advance Information DS30325A-page 19
PIC16F7X
2.2.2.3 INTCON R egister The INTCON register is a readable and writable regis-
ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.
Note: Interrupt flag bits are set whe n an interrupt
condition occurs, re gardless of the sta t e of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
REGISTER 2-3: INTCON REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
bit 7 bit 0
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all inter rupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4 INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3 RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 regi ster did not overflow
bit 1 INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0 RBIF: RB Port Change Interrupt Flag bit
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch
condition and allow flag bit RBIF to be cleared.
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS30325A-page 20 Advance Information 2000 Microchip Technology Inc.
2.2.2.4 PIE1 Register
PIC16F7X
The PIE1 register cont ains the ind ividual enab le bits for
the periph eral interrupts.
Note: Bit PEIE (INTCON<6>) must be set to
REGISTER 2-4: PIE1 REGISTER (ADDRESS 8Ch)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
PSPIE
bit 7 bit 0
bit 7 PSPIE
bit 6 ADIE: A/D Converter Interrupt Enable bit
bit 5 RCIE: USART Receive Interrupt Enable bit
bit 4 TXIE: USART Transmit Interrupt Enable bit
bit 3 SSPIE: Synchronous Serial Port Interrupt Enable bit
bit 2 CCP1IE: CCP1 Interrupt Enable bit
bit 1 TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit
(1)
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
1 = Enables the TMR1 overflow interrupt
0 = Disables t he TMR1 overflow interrupt
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
: Parallel Slave Port Read/Write Interrupt Enable bit
enable any peripheral interrupt.
Note 1: PSPIE is reserved on 28-pin devices; always maintain this bit clear.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc. Advance Information DS30325A-page 21
PIC16F7X
2.2.2.5 PIR1 Regi ster Note: Interrupt flag bits are set when an interrupt
The PIR1 register contains the individual flag bits for
the periph eral interrupts.
REGISTER 2-5: PIR1 REGISTER (ADDRESS 0Ch)
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
(1)
PSPIF
bit 7 bit 0
bit 7 PSPIF
bit 6 ADIF: A/D Converter Interrupt Flag bit
bit 5 RCIF: USART Receive Interrupt Flag bit
bit 4 TXIF: USART Transmit Interrupt Flag bit
bit 3 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag
bit 2 CCP1IF: CCP1 Interrupt Flag bit
bit 1 TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
bit 0 TMR1IF: TMR1 Overflow Interrupt Flag bit
(1)
1 = A read or a write operat ion has taken place (must be clea red in software)
0 = No read or write has oc cur r ed
1 = An A/D conversion completed
0 = The A/D conversion is not complete
1 = The USART receive buffer is full
0 = The USART receive buffer is empty
1 = The USART transmit buffer is empty
0 = The USART transmit buffer is full
1 = The SSP interrupt condition has occ urre d, and mu st be cle are d in so ftware befor e
returning from the Interrupt Service Routine. The conditions that will set this bit are:
SPI
A transmission/recept i on has taken place.
2
I
C Slave
A transmission/recept i on has taken place.
2
C Master
I
A transmission/recept i on has taken place.
The initiated START condition was completed by the SSP module.
The initiated STOP condition was completed by the SSP module.
The initiated Restart condition was completed by the SSP module.
The initiated Acknowledge condition was completed by the SSP module.
A START condition occurred while the SSP module was idle (Multi-master system).
A STOP condition occurred while the SSP module was idle (Multi-master system).
0 = No SSP interrup t condition has occurred.
Capture Mode
1 = A TMR1 register ca pt ur e occurred (must be clear ed i n software)
0 = No TMR1 register capt ur e occurred
Compare Mode
1 = A TMR1 register co m pare m at ch occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
1 = TMR2 to PR2 match oc cur re d ( must be cleared in software)
0 = No TMR2 to PR2 match occurred
1 = TMR1 register over flow ed (must be cleared in so ftwa re )
0 = TMR1 register did no t ov er f low
Note 1: PSPIF is reserved on 28-pin dev i ces ; a lwa ys maintain this bit clear.
ADIF RCIF T XIF SSPIF CCP1IF TMR2IF TMR1IF
: Parallel Slave Port Read/Write Interrupt Flag bit
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should en sure the approp riate interrup t
bits are cle ar pri or to en ab li ng an i nte rru pt.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cl ear ed x = Bit is unknown
DS30325A-page 22 Advance Information 2000 Microchip Technology Inc.
2.2.2.6 PIE2 Register The PIE2 register cont ains the ind ividual enab le bits for
the CCP2 peripheral interrupt.
REGISTER 2-6: PIE2 REGISTER (ADDRESS 8Dh)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CCP2IE
bit 7 bit 0
bit 7-1 Unimplemented: Read as ’0’
bit 0 CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
PIC16F7X
2000 Microchip Technology Inc. Advance Information DS30325A-page 23
PIC16F7X
2.2.2.7 PIR2 Regi ster
The PIR2 register contains the flag bits for the CCP2
interrupt.
.
Note: Interrupt flag bits are set whe n an interrupt
REGISTER 2-7: PIR2 REGISTER (ADDRESS 0Dh)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CCP2IF
bit 7 bit 0
bit 7-1 Unimplemented: Read as '0'
bit 0 CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused
condition occurs, re gardless of the sta t e of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
DS30325A-page 24 Advance Information 2000 Microchip Technology Inc.
PIC16F7X
2.2.2.8 PCON Register The Power Control (PCON) register contains flag bits
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset (BOR), a Watchdog Reset
(WDT) and an external MCLR
Reset.
Note: BOR is unknown on POR. It mus t be set by
REGISTER 2-8: PCON REGISTER (ADDRESS 8Eh)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-1
— — — — — — POR BOR
bit 7 bit 0
bit 7-2 Unimplemented: Read as '0'
bit 1 POR
bit 0 BOR: Brown-out Reset Status bit
: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
the user and checked on subsequent
RESETS to see if BOR is clear, indicating
a brown-out has occurre d. The BOR st atus
bit is a don’t care and is not predictable if
the brown-out circuit is disabled (by clearing the BODEN bit in the configuration
word).
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown
2000 Microchip Technology Inc. Advance Information DS30325A-page 25
PIC16F7X
2.3 PCL and PCLATH
The program counter (PC) is 13-bits wid e. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLA TH reg is ter. On any RESET, the up per bi t s of the
PC will be cleared. Fig ure2-5 shows the two situations
for the loading of the PC. The up per ex ample in th e figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower exam pl e i n th e fi gure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).
FIGURE 2-5: LOADING OF PC IN
DIFFERENT SITUATIONS
PCH PCL
12 8 7 0
PC
PCLATH<4:0>
5
PCLATH
PCH PCL
12 11 10 0
PC
2
87
PCLATH<4:3>
PCLATH
11
2.3.1 COMPUTED GOTO
A computed GOTO is accomplish ed by adding an of fs et
to the progr am counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercise d i f the t able loca tio n cros ses a PCL
memory boundary (each 256 byte block). Refer to the
application note, “Implementing a Table Read"
(AN556).
2.3.2 STACK
The PIC16F7X fami ly has an 8 -level de ep x 13-bi t wide
hardware s tack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writabl e. The PC i s PUSHed onto th e stac k
when a CALL instruction is executed, or an interrupt
causes a branch. The st ac k is POPed in the ev en t of a
RETURN,RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
The stack opera tes as a circular buf fer . This means that
after the st ack h as be en PUSHed ei ght ti mes, th e nin th
push overwrites the v alue tha t was stored fro m the first
push. The tenth pus h ov erwri t es the se co nd p us h (an d
so on).
8
Instruction with
PCL as
Destination
ALU
GOTO,CALL
Opcode <10:0>
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions or th e vectoring to an interrupt
address.
2.4 Program Memory Paging
PIC16F7X devices are cap able of add ressi ng a conti nuous 8K word block of program memory. The CALL and
GOTO instructions provide only 11 bits of address to
allow branching within any 2K program memory page.
When doing a CALL or GOTO instruction , the upper 2
bits of the address are provided by PCLATH<4:3>.
When doing a CALL or GOTO instruct ion, the user must
ensure that t he page select bits are progr ammed so
that the desired prog ram memory pa ge is addre ssed. If
a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is popped off the stack.
Therefore, manipulation of the PCLATH<4:3> bits are
not required for the return instruction s (which POPs the
address from the stack).
Note: The contents of the PCLATH are
unchanged after a RETURN or RETFIE
instruction is executed. The user must
setup the PCLATH for any subsequent
CALLS or GOTOS.
Example 2-1 shows the calling of a subroutine in
page 1 of the program memory . This e xample assu mes
that PCLATH is saved and restored by the Interrupt
Service Routine
(if interrupts are used).
EXAMPLE 2-1: CALL OF A SUBROUTINE IN
PAGE 1 FROM PAGE 0
ORG 0x500
BCF PCLATH,4
BSF PCLATH,3 ;Select page 1 (800h-FFFh)
CALL SUB1_P1 ;Call subroutine in
: ;page 1 (800h-FFFh)
:
ORG 0x900 ;page 1 (800h-FFFh)
SUB1_P1
: ;called subroutine
: ;page 1 (800h-FFFh)
:
RETURN ;return to Call subroutine
;in page 0 (000h-7FFh)
DS30325A-page 26 Advance Information 2000 Microchip Technology Inc.
PIC16F7X
2.5 Indirect Addressing, INDF and FSR Registers
The INDF register is not a physi cal register. Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruc tion using the INDF register actual ly
accesses the register pointed to by the File Sele ct Register, FSR. Reading the INDF register itself indirectly
(FSR = ’0’) will read 00h. Writing to the INDF register
indirectly result s in a no-operation (altho ugh status bits
may be affected ). An ef fective 9- bit add ress is obt ained
by concatenating the 8 -bit FSR regi ster and the IRP b it
(STATUS<7>), as sh own in Figure 2-6.
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
FIGURE 2-6: DIRECT/INDIRECT ADDRESSING
RP1:RP0 6
from opcode
0
EXAMPLE 2-2: INDIRECT ADDRESS ING
movlw 0x20 ;initialize pointer
NEXT clrf INDF ;clear INDF register
CONTINUE
movwf FSR ;to RAM
incf FSR,F ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;no clear next
: ;yes continue
Indirect AddressingDirect Addressing
IRP FSR register
7
0
bank select location select
00 01 10 11
00h
Data
(1)
Memory
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
Note 1: For register file map detail see Figure 2-3.
80h
FFh
100h
17Fh
180h
1FFh
bank select
location select
2000 Microchip Technology Inc. Advance Information DS30325A-page 27
PIC16F7X
NOTES:
DS30325A-page 28 Advance Information 2000 Microchip Technology Inc.
PIC16F7X
3.0 I/O PORTS
Some pins for th ese I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional inform atio n o n I/O ports ma y b e f oun d i n the
PICmicro™ Mid-Range Reference Manual,
(DS33023).
3.1 PORTA and the TRISA Register
PORTA is a 6-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (=1) will make t he co rrespon ding POR TA pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISA bit (=0) will
make the correspondin g POR TA pin an output (i.e., put
the contents of the output latch on the selected pin).
Reading the PORTA register reads the status of the
pins, whereas writing to i t will wri te to th e po rt latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, the value is modified and then written to the port
data latch.
Pin RA4 is multiplexed with the Ti mer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain o utput.
All other PORTA pins have TTL input levels and full
CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs
and analog V
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
Note: On a Power-on Reset, these pins are con-
The TRISA register controls the direction of the RA
pins, even when they are be ing us ed as ana lo g inputs.
The user must ensure the bits in the TRISA regi ster are
maintained set, when using them as analog inputs.
EXAMPLE 3-1: INITIALIZING PORTA
BCF STATUS, RP0 ;
BCF STATUS, RP1 ; Bank0
CLRF PORTA ; Initialize PORTA by
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0x06 ; Configure all pins
MOVWF ADCON1 ; as digital inputs
MOVLW 0xCF ; Value used to
MOVWF TRISA ; Set RA<3:0> as inputs
REF input. The operation of each pin is
figured as analog inputs and read as '0'.
; clearing output
; data latches
; initialize data
; direction
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as ’0’.
FIGURE 3-1: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
Data
Bus
WR
Port
Data Latch
WR
TRIS
TRIS Latch
RD PORT
To A/D Converter
Note 1: I/O pins have protection diodes to VDD and VSS.
CK
CK
QD
Q
QD
Q
RD TRIS
QD
Analog
Input
Mode
EN
VDD
P
N
V
I/O pin
SS
TTL
Input
Buffer
FIGURE 3-2: BLOCK DIAGRAM OF RA4/
T0CKI PIN
Data
Bus
WR
PORT
WR
TRIS
RD PORT
TMR0 clock input
Note 1: I/O pin has protection diodes to VSS only.
QD
Q
CK
Data Latch
QD
Q
CK
TRIS Latch
RD TRIS
N
SS
V
Schmitt
Trigger
Input
Buffer
QD
EN
EN
I/O pin
(1)
(1)
2000 Microchip Technology Inc. Advance Information DS30325A-page 29
PIC16F7X
TABLE 3-1: PORTA FUNCTIONS
Name Bit# Buffer Function
RA0/AN0 bit0 TTL Input/output or analog input.
RA1/AN1 bit1 TTL Input/output or analog input.
RA2/AN2 bit2 TTL Input/output or analog input.
RA3/AN3/V
RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type.
RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input.
Legend: TTL = TTL input, ST = Schmitt Trigge r input
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
REF bit3 TTL Input/output or analog input or VREF.
Value on:
POR,
BOR
Value on all
other
RESETS
05h PORTA
85h TRISA — — PORTA Data Direction Register
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
Note: When using the SSP module in SPI Slave mode and SS enabled, the A/D converter must be set to one of
the following modes where PCFG2:PCFG0 = 100, 101, 11x.
— — RA5 RA4 RA3 RA2 RA1 RA0
--0x 0000 --0u 0000
--11 1111 --11 1111
---- -000 ---- -000
DS30325A-page 30 Advance Information 2000 Microchip Technology Inc.
Loading...