Microchip Technology Inc PIC16CR54C-04-P, PIC16CR54C-04-SO, PIC16CR54C-04-SS, PIC16CR54C-04I-P, PIC16CR54C-04I-SO Datasheet

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1998 Microchip Technology Inc.

Preliminary

DS40191A-page 1

PIC16CR54C

Devices Included in this Data Sheet:

• PIC16CR54C

High-Performance RISC CPU:

• Only 33 single word instructions to learn

• All instructions are single cycle (200 ns) except for program branches which are two-cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• 12-bit wide instructions

• 8-bit wide data path

• Seven or eight special function hardware registers

• Two-level deep hardware stack

• Direct, indirect and relative addressing modes for data and instructions

Peripheral Features:

• 8-bit real time clock/counter (TMR0) with 8-bit programmable prescaler

• Power-On Reset (POR)

• Device Reset Timer (DRT)

• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options:

- RC: Low-cost RC oscillator

- XT: Standard crystal/resonator

- HS: High-speed crystal/resonator

- LP: Power saving, low-frequency crystal

CMOS Tec hnology:

• Low-power, high-speed CMOS ROM technology

• Fully static design

• Wide-operating voltage and temperature range:

- ROM Commercial/Industrial 3.0V to 5.5V

• Low-power consumption

- < 2 mA typical @ 5V, 4 MHz

- 15 µA typical @ 3V, 32 kHz

- < 0.6 µA typical standby current

(with WDT disabled) @ 3V, 0°C to 70°C

Device Pins I/O ROM RAM

PIC16CR54C 18 12 512 25

Pin Diagrams

PDIP and SOIC

PIC16CR54C

RA1 RA0 OSC1/CLKIN OSC2/CLKOUT V

VDD RB7 RB6 RB5 RB4

RA2 RA3

T0CKI

MCLR

VPP VSS

VSS RB0 RB1 RB2 RB3

•1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

SSOP

PIC16CR54C

RA2 RA3

T0CKI

MCLR

VPP

VSS RB0 RB1 RB2

RB3

•1 2 3 4 5 6 7 8 9

18 17 16 15 14 13 12

RA1 RA0 OSC1/CLKIN OSC2/CLKOUT V

RB7 RB6 RB5 RB4

ROM-Based 8-Bit CMOS Microcontroller Series

PIC16CR54C

DS40191A-page 2

Preliminary

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1998 Microchip Technology Inc.

Device Differences

Note 1:

If you change from this device to another device, please verify oscillator characteristics in your application.

Note 2:

In PIC16LV58A, MCLR

Filter = Yes

Device

Voltage

Range

Oscillator

Selection

(Program)

Oscillator

Process

Technology

(Microns)

ROM

Equivalent

MCLR

Filter

PIC16C52 3.0-6.25 User See Note 1 0.9 — No PIC16C54 2.5-6.25 Factory See Note 1 1.2 PIC16CR54A No PIC16C54A 2.0-6.25 User See Note 1 0.9 — No PIC16C54B 3.0-5.5 User See Note 1 0.7 PIC16CR54B

PIC16CR54C

Yes

PIC16C55 2.5-6.25 Factory See Note 1 1.7 — No PIC16C55A 3.0-5.5 User See Note 1 0.7 — Yes PIC16C56 2.5-6.25 Factory See Note 1 1.7 — No PIC16C56A 3.0-5.5 User See Note 1 0.7 PIC16CR56A Yes PIC16C57 2.5-6.25 Factory See Note 1 1.2 — No PIC16C57C 3.0-5.5 User See Note 1 0.7 PIC16CR57C Yes PIC16CR57C 2.5-5.5 Factory See Note 1 0.7 NA Yes PIC16C58A 2.0-6.25 User See Note 1 0.9 PIC16CR58A

(2)

PIC16C58B 3.0-5.5 User See Note 1 0.7 PIC16CR58B Yes PIC16CR54A 2.5-6.25 Factory See Note 1 1.2 NA Yes PIC16CR54B 2.5-5.5 Factory See Note 1 0.7 NA Yes PIC16CR54C 3.0-5.5 Factory See Note 1 0.7 NA Yes PIC16CR56A 2.5-5.5 Factory See Note 1 0.7 NA Yes PIC16CR57B 2.5-6.25 Factory See Note 1 0.9 NA Yes PIC16CR58A 2.5-6.25 Factory See Note 1 0.9 NA Yes PIC16CR58B 2.5-5.5 Factory See Note 1 0.7 NA Yes

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1998 Microchip Technology Inc.

Preliminary

DS40191A-page 3

PIC16CR54C

Table of Contents

1.0 General Description.............................................................................................................................................5

2.0 PIC16C5X Device Varieties.................................................................................................................................7

3.0 Architectural Overview.........................................................................................................................................9

4.0 Memory Organization........................................................................................................................................13

5.0 I/O Ports ............................................................................................................................................................ 19

6.0 Timer0 Module and TMR0 Register .................................................................................................................. 21

7.0 Special Features of the CPU.............................................................................................................................25

8.0 Instruction Set Summary...................................................................................................................................37

9.0 Development Support........................................................................................................................................49

10.0 Electrical Characteristics - PIC16CR54C..........................................................................................................53

11.0 DC and AC Characteristics - PIC16CR54C.......................................................................................................63

12.0 Packaging Information.......................................................................................................................................73

Appendix A: Compatibility.............................................................................................................................................77

Index ............................................................................................................................................................................79

On-Line Support............................................................................................................................................................81

Reader Response.........................................................................................................................................................82

PIC16CR54C Product Identification System.................................................................................................................83

PIC16CR54C

DS40191A-page 4

Preliminary

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1998 Microchip Technology Inc.

NOTES:

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1998 Microchip Technology Inc.

Preliminary

DS40191A-page 5

PIC16CR54C

1.0 GENERAL DESCRIPTION

The PIC16C5X from Microchip Technology is a family of low-cost, high performance, 8-bit, fully static, EPROM/ ROM-based CMOS microcontrollers. It employs a RISC architecture with only 33 single word/single cycle instructions. All instructions are single cycle (200 ns) except for program branches which take two cycles. The PIC16C5X delivers performance an order of magnitude higher than its competitors in the same price category. The 12-bit wide instructions are highly symmetrical resulting in 2:1 code compression over other 8-bit microcontrollers in its class. The easy to use and easy to remember instruction set reduces development time signiﬁcantly.

The PIC16C5X products are equipped with special f eatures that reduce system cost and power requirements. The Power-On Reset (POR) and Device Reset Timer (DRT) eliminate the need for external reset circuitry. There are four oscillator conﬁgurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator. Power saving SLEEP mode, Watchdog Timer and code protection features improve system cost, power and reliability.

The UV erasable CERDIP packaged versions are ideal for code development, while the cost-effective One Time Programmable (OTP) versions are suitable for production in any volume. The customer can take full advantage of Microchip’s price leadership in OTP microcontrollers while beneﬁting from the OTP’s ﬂexibility.

The PIC16C5X products are supported by a full-featured macro assembler , a softw are simulator , an in-circuit emulator, a ‘C’ compiler, fuzzy logic support tools, a low-cost development programmer, and a full featured programmer. All the tools are supported on IBM



PC and compatible machines.

1.1 Applications

The PIC16C5X series ﬁts perf ectly in applications ranging from high-speed automotive and appliance motor control to low-power remote transmitters/receivers, pointing devices and telecom processors. The EPROM technology makes customizing application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages, for through hole or surface mounting, make this microcontroller series perfect for applications with space limitations. Low-cost, low-power, high performance, ease of use and I/O ﬂexibility make the PIC16C5X series very versatile even in areas where no microcontroller use has been considered before (e.g., timer functions, replacement of “glue” logic in larger systems, coprocessor applications).

PIC16CR54C

DS40191A-page 6

Preliminary

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1998 Microchip Technology Inc.

TABLE 1-1: PIC16C5X FAMILY OF DEVICES

PIC16C52

PIC16C54s PIC16CR54s PIC16C55s PIC16C56s

Clock

Maximum Frequency of Operation (MHz)

4 20 20 20 20

Memory

EPROM Program Memory (x12 words)

384 512 — 512 1K

ROM Program Memory (x12 words)

— — 512 — —

RAM Data Memory (bytes) 25 25 25 24 25

Peripherals

Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0

Features

I/O Pins 12 12 12 20 12 Number of Instructions 33 33 33 33 33 Packages 18-pin DIP,

SOIC

18-pin DIP, SOIC; 20-pin SSOP

28-pin DIP, SOIC; 28-pin SSOP

18-pin DIP, SOIC; 20-pin SSOP

All PICmicro™ Family de vices ha v e Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectab le code protect and high I/O current capability.

PIC16CR56s

PIC16C57s PIC16CR57s PIC16C58s PIC16CR58s

Clock

Maximum Frequency of Operation (MHz)

20 20 20 20 20

Memory

EPROM Program Memory (x12 words)

— 2K — 2K —

ROM Program Memory (x12 words)

1K — 2K — 2K

RAM Data Memory (bytes) 25 72 72 73 73

Peripherals

Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0

Features

I/O Pins 12 20 20 12 12 Number of Instructions 33 33 33 33 33 Packages 18-pin DIP,

SOIC; 20-pin SSOP

28-pin DIP, SOIC; 28-pin SSOP

18-pin DIP, SOIC; 20-pin SSOP

All PICmicro™ Family de vices ha v e Power-on Reset, selectable Watchdog Timer (except PIC16C52), selectab le code protect and high I/O current capability.

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1998 Microchip Technology Inc.

Preliminary

DS40191A-page 7

PIC16CR54C

2.0 PIC16C5X DEVICE VARIETIES

A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in this section. When placing orders, please use the PIC16CR54C Product Identiﬁcation System at the back of this data sheet to specify the correct part number.

For the PIC16C5X family of devices, there are four device types, as indicated in the device number:

1.C, as in PIC16C54. These devices have EPROM program memory and operate over the standard voltage range.

, as in PIC16LC54A. These devices have EPROM program memory and operate over an extended voltage range.

3.LV, as in PIC16LV54A. These devices have EPROM program memory and operate over a

2.0V to 3.8V range.

, as in PIC16CR54A. These devices have ROM program memory and operate over the standard voltage range.

LCR

, as in PIC16LCR54B. These devices have ROM program memory and operate over an extended voltage range.

2.1 U

V Erasable Devices (EPROM)

The UV erasable versions, offered in CERDIP packages, are optimal for prototype development and pilot programs

UV erasable devices can be programmed for any of the four oscillator conﬁgurations. Microchip's PICSTART and PRO MATE programmers both support programming of the PIC16CR54C. Third party programmers also are available; refer to the Third Party Guide for a list of sources.

2.2 One-Time-Pr

ogrammable (OTP)

Devices

The availability of OTP devices is especially useful for customers expecting frequent code changes and updates.

The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the conﬁguration bits must be programmed.

2.3 Quic

k-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and conﬁguration bit options already programmed by the factory. Certain code and prototype veriﬁcation procedures apply before production shipments are available. Please contact your Microchip Technology sales ofﬁce for more details.

2.4 Serializ

ed Quick-Turnaround-Production (SQTP ) Devices

Microchip offers the unique programming service where a few user-deﬁned locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random or sequential. The devices are identical to the OTP devices but with all EPROM locations and conﬁguration bit options already programmed by the factory.

Serial programming allows each device to have a unique number which can serve as an entry code, password or ID number.

2.5 Read Onl

y Memory (ROM) Devices

Microchip offers masked ROM versions of several of the highest volume parts, giving the customer a low cost option for high volume, mature products.

PIC16CR54C

DS40191A-page 8

Preliminary

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NOTES:

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1998 Microchip Technology Inc.

Preliminary

DS40191A-page 9

PIC16CR54C

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16CR54C can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CR54C uses a Harvard architecture in which program and data are accessed on separate buses. This improves bandwidth over traditional von Neumann architecture where program and data are fetched on the same bus. Separating program and data memory further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 12-bits wide making it possible to have all single word instructions. A 12-bit wide program memory access bus fetches a 12-bit instruction in a single cycle. A two-stage pipeline overlaps fetch and execution of instructions. Consequently, all instructions (33) execute in a single cycle (200ns @ 20MHz) except for program branches.

The PIC16CR54C address 512 x 12 of program memory. All program memory is internal.

The PIC16CR54C can directly or indirectly address its register ﬁles and data memory. All special function registers including the program counter are mapped in the data memory. The PIC16CR54C has a highly orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16CR54C simple yet efﬁcient. In addition, the learning curve is reduced signiﬁcantly.

The PIC16CR54C device contains an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between data in the working register and any register ﬁle.

The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the W (working) register. The other operand is either a ﬁle register or an immediate constant. In single operand instructions, the operand is either the W register or a ﬁle register.

The W register is an 8-bit working register used for ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borr

ow and digit borrow out bit,

respectively, in subtraction. See the

SUBWF

and

ADDWF

instructions for examples. A simpliﬁed block diagram is shown in Figure 3-1, with

the corresponding device pins described in Table 3-1.

PIC16CR54C

DS40191A-page 10

Preliminary

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1998 Microchip Technology Inc.

FIGURE 3-1: PIC16CR54C SERIES BLOCK DIAGRAM

WDT TIME

OUT

STACK 1 STACK 2

ROM

512 X 12

INSTRUCTION

DECODER

WA TCHDOG

TIMER

CONFIGURA TION WORD

OSCILLA TOR/

TIMING &

CONTROL

GENERAL PURPOSE REGISTER

FILE

(SRAM)

25 Bytes

WDT/TMR0

PRESCALER

OPTION REG.

“OPTION”

“SLEEP”

“CODE

PROTECT”

“OSC

SELECT”

DIRECT ADDRESS

TMR0

FROM W

“TRIS 5”

“TRIS 6”

FSR

TRISA PORTA

TRISB PORTB

T0CKI

9-11

DATA BUS

ALU

STATUS

FROM W

CLKOUT

OSC1 OSC2 MCLR

LITERALS

“DISABLE”

RA3:RA0 RB7:RB0

DIRECT RAM

ADDRESS

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1998 Microchip Technology Inc.

Preliminary

DS40191A-page 11

PIC16CR54C

TABLE 3-1: PINOUT DESCRIPTION - PIC16CR54C

Name

DIP, SOIC

No.

SSOP

No.

I/O/P Type

Input

Levels

Description

RA0 RA1 RA2 RA3

17 18

1 2

19 20

1 2

I/O I/O I/O I/O

TTL TTL TTL TTL

Bi-directional I/O port

RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7

6 7 8

9 10 11 12 13

7 8

9 10 11 12 13 14

I/O I/O I/O I/O I/O I/O I/O I/O

TTL TTL TTL TTL TTL TTL TTL TTL

Bi-directional I/O port

T0CKI 3 3 I ST Clock input to Timer0. Must be tied to V

or V

DD,

if not in

use, to reduce current consumption.

MCLR/

4 4 I ST Master clear (reset) input/verify voltage input. This pin is an

active low reset to the device.

OSC1/CLKIN 16 18 I ST

(1)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT 15 17 O — Oscillator crystal output. Connects to crystal or resonator in

crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.

14 15,16 P — Positive supply for logic and I/O pins.

5 5,6 P — Ground reference for logic and I/O pins.

Legend: I = input, O = output, I/O = input/output,

P = power, — = Not Used, TTL = TTL input, ST = Schmitt Trigger input

Note 1:

Schmitt Trigger input only when in RC mode.

PIC16CR54C

DS40191A-page 12

Preliminary

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1998 Microchip Technology Inc.

3.1 Cloc

king Scheme/Instruction Cycle

The clock input (OSC1/CLKIN pin) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter is incremented every Q1, and the instruction is fetched from program memory and latched into instruction register in Q4. It is decoded and executed during the following Q1 through Q4. The clocks and instruction execution ﬂow is shown in Figure 3-2 and Example 3-1.

3.2 Instruction Flo

w/Pipelining

An Instruction Cycle consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.,

GOTO

) then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle, the fetched instruction is latched into the Instruction Register (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q2 Q3 Q4

OSC1

Q1 Q2 Q3

Q4 PC

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal phase clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

1. MOVLW 55H

Fetch 1 Execute 1

2. MOVWF PORTB

Fetch 2 Execute 2

3. CALL SUB_1

Fetch 3 Execute 3

4. BSF PORTA, BIT3

Fetch 4 Flush

Fetch SUB_1 Execute SUB_1



1998 Microchip Technology Inc.

Preliminary

DS40191A-page 13

PIC16CR54C

4.0 MEMORY ORGANIZATION

PIC16CR54C memory is organized into program memory and data memory. For devices with more than 512 bytes of program memory, a paging scheme is used. Program memory pages are accessed using one or two STATUS register bits. For devices with a data memory register ﬁle of more than 32 registers, a banking scheme is used. Data memory banks are accessed using the File Selection Register (FSR).

4.1 Pr

ogram Memory Organization

The PIC16CR54C has a 9-bit Program Counter (PC) capable of addressing a 512 x 12 program memory space (Figure 4-1). Accessing a location above the physically implemented address will cause a wraparound.

The reset vector for the PIC16CR54C is at 1FFh. A NOP at the reset vector location will cause a restart at location 000h.

FIGURE 4-1: PIC16CR54C PROGRAM

MEMORY MAP AND STACK

4.2 Data Memor

y Organization

Data memory is composed of registers, or bytes of RAM. Therefore, data memory for a device is speciﬁed by its register ﬁle. The register ﬁle is divided into two functional groups: special function registers and general purpose registers.

The special function registers include the TMR0 register, the Program Counter (PC), the Status Register, the I/O registers (ports), and the File Select Register (FSR). In addition, special purpose registers are used to control the I/O port conﬁguration and prescaler options.

The general purpose registers are used for data and control information under command of the instructions.

For the PIC16CR54C, the register ﬁle is composed of 7 special function registers and 25 general purpose registers (Figure 4-2).

PC<8:0>

Stack Level 1 Stack Level 2

User Memory

Space

CALL, RETLW

000h

1FFh

Reset Vector

0FFh 100h

On-chip Program Memory

4.2.1 GENERAL PURPOSE REGISTER FILE The register ﬁle is accessed either directly or indirectly

through the ﬁle select register FSR (Section 4.7).

FIGURE 4-2: PIC16CR54C REGISTER FILE

MAP

4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by

the CPU and peripheral functions to control the operation of the device (Table 4-1).

The special registers can be classiﬁed into two sets. The special function registers associated with the “core” functions are described in this section. Those related to the operation of the peripheral features are described in the section for each peripheral feature.

File Address

00h 01h 02h 03h 04h 05h 06h

1Fh

INDF

(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

General

Purpose

Registers

Note 1: Not a physical register. See Section 4.7

0Fh 10h

07h

PIC16CR54C

DS40191A-page 14

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1998 Microchip Technology Inc.

TABLE 4-1: SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-On

Reset

Value on

MCLR

and

WDT Reset

N/A TRIS I/O control registers (TRISA, TRISB)

1111 1111 1111 1111

N/A OPTION Contains control bits to conﬁgure Timer0 and Timer0/WDT prescaler

--11 1111 --11 1111

00h INDF Uses contents of FSR to address data memory (not a physical register)

xxxx xxxx uuuu uuuu

01h TMR0 8-bit real-time clock/counter

xxxx xxxx uuuu uuuu

02h

(1)

PCL Low order 8 bits of PC

1111 1111 1111 1111

03h STATUS

PA2 PA1 PA0 TO PD Z DC C

0001 1xxx 000q quuu

04h FSR Indirect data memory address pointer

1xxx xxxx 1uuu uuuu

05h PORTA — — — — RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu Legend: Shaded boxes = unimplemented or unused, – = unimplemented, read as '0' (if applicable)

x = unknown, u = unchanged, q = see the tables in Section 7.7 for possible values.

Note 1: The upper byte of the Program Counter is not directly accessible. See Section 4.5

for an explanation of how to access these bits.

 1998 Microchip Technology Inc. Preliminary DS40191A-page 15

PIC16CR54C

4.3 STATUS Register

This register contains the arithmetic status of the ALU, the RESET status, and the page preselect bits for program memories larger than 512 words.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Further more, the T

O and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF and MOVWF instructions be used to alter the STATUS register because these instructions do not affect the Z, DC or C bits from the STATUS register. For other instructions, which do affect STATUS bits, see Section 8.0, Instruction Set Summary.

FIGURE 4-3: STATUS REGISTER (ADDRESS:03h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

PA2 PA1 PA0 TO PD Z DC C R = Readable bit

W = Writable bit

- n = Value at POR reset

bit7 6 5 4 3 2 1 bit0

bit 7: PA2: This bit unused at this time.

Use of the PA2 bit as a general purpose read/write bit is not recommended, since this may affect upward

compatibility with future products. bit 6-5: Not Applicable bit 4: TO: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction

0 = A WDT time-out occurred bit 3: PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (for ADDWF and SUBWF instructions)

ADDWF

1 = A carry from the 4th low order bit of the result occurred

0 = A carry from the 4th low order bit of the result did not occur

SUBWF

1 = A borrow from the 4th low order bit of the result did not occur

0 = A borrow from the 4th low order bit of the result occurred bit 0: C: Carry/borrow bit (for ADDWF, SUBWF and RRF, RLF instructions)

ADDWF SUBWF RRF or RLF

1 = A carry occurred 1 = A borrow did not occur Load bit with LSb or MSb, respectively

0 = A carry did not occur 0 = A borrow occurred

PIC16CR54C

DS40191A-page 16 Preliminary  1998 Microchip Technology Inc.

4.4 OPTION Register

The OPTION register is a 6-bit wide, write-only register which contains various control bits to conﬁgure the Timer0/WDT prescaler and Timer0.

By executing the OPTION instruction, the contents of the W register will be transferred to the OPTION register. A RESET sets the OPTION<5:0> bits.

FIGURE 4-4: OPTION REGISTER

U-0 U-0 W-1 W-1 W-1 W-1 W-1 W-1

— — T0CS T0SE PSA PS2 PS1 PS0 W = Writable bit

U = Unimplemented bit

- n = Value at POR reset

bit7 6 5 4 3 2 1 bit0

bit 7-6: Unimplemented. bit 5: T0CS: Timer0 clock source select bit

1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: Timer0 source edge select bit

1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin

bit 3: PSA: Prescaler assignment bit

1 = Prescaler assigned to the WDT (not implemented on PIC16C52) 0 = Prescaler assigned to Timer0

bit 2-0: PS2:PS0: Prescaler rate select bits

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Bit Value Timer0 Rate WDT Rate (not implemented on PIC16C52)

 1998 Microchip Technology Inc. Preliminary DS40191A-page 17

PIC16CR54C

4.5 Program Counter

As a program instruction is executed, the Program Counter (PC) will contain the address of the next program instruction to be executed. The PC value is increased by one every instruction cycle, unless an instruction changes the PC.

For a GOTO instruction, bits 8:0 of the PC are provided by the GOTO instruction word. The PC Latch (PCL) is mapped to PC<7:0> (Figure 4-5 and Figure 4-6).

For a CALL instruction, or any instruction where the PCL is the destination, bits 7:0 of the PC again are provided by the instruction word. However, PC<8> does not come from the instruction word, but is always cleared (Figure 4-10 and Figure 4-11)/

Instructions where the PCL is the destination, or Modify PCL instructions, include MOVWF PC, ADDWF PC, and BSF PC, 5.

Note: Because PC<8> is cleared in the CALL

instruction, or any Modify PCL instruction, all subroutine calls or computed jumps are limited to the ﬁrst 256 locations of any program memory page (512 words long).

FIGURE 4-5: LOADING OF PC

BRANCH INSTRUCTIONS PIC16CR54C

4.5.1 EFFECTS OF RESET The Program Counter is set upon a RESET, which

means that the PC addresses the last location in the last page i.e., the reset vector.

The STATUS register page preselect bits are cleared upon a RESET, which means that page 0 is pre-selected.

Therefore, upon a RESET, a GOTO instruction at the reset vector location will automatically cause the program to jump to page 0.

4.6 Stack

PIC16CR54C device has a 9-bit, two-level hardware push/pop stack (Figure 4-1).

A CALL instruction will

push

the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one , into stac k le v el 1. If more than two sequential CALL’s are executed, only the most recent two return addresses are stored.

A RETLW instruction will

pop

the contents of stack level 1 into the program counter and then copy stack level 2 contents into level 1. If more than two sequential RETLW’s are executed, the stack will be filled with the address previously stored in level 2. Note that the W register will be loaded with the literal value speciﬁed in the instruction. This is particularly useful for the implementation of data look-up tables within the program memory.

8 7 0

PCL

8 7 0

PCL

Reset to '0'

Instruction Word

GOTO Instruction

CALL or Modify PCL Instruction

PIC16CR54C

DS40191A-page 18 Preliminary  1998 Microchip Technology Inc.

4.7 Indirect Data Addressing; INDF and FSR Registers

The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the FSR register (FSR is a

pointer

). This is indirect addressing.

EXAMPLE 4-1: INDIRECT ADDRESSING

• Register ﬁle 05 contains the value 10h

• Register ﬁle 06 contains the value 0Ah

• Load the value 05 into the FSR register

• A read of the INDF register will return the value

of 10h

• Increment the value of the FSR register by one

(FSR = 06)

• A read of the INDR register now will return the

value of 0Ah.

Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 10h-1Fh using indirect addressing is shown in Example 4-2.

EXAMPLE 4-2: HOW TO CLEAR RAM

USING INDIRECT ADDRESSING

movlw 0x10 ;initialize pointer movwf FSR ; to RAM

NEXT clrf INDF ;clear INDF register

incf FSR,F ;inc pointer btfsc FSR,4 ;all done? goto NEXT ;NO, clear next

CONTINUE

: ;YES, continue

The FSR is a 5-bit ( PIC16CR54C) wide register. It is used in conjunction with the INDF register to indirectly address the data memory area.

The FSR<4:0> bits are used to select data memory addresses 00h to 1Fh.

PIC16CR54C: Do not use banking. FSR<6:5> are unimplemented and read as '1's.

FIGURE 4-6: DIRECT/INDIRECT ADDRESSING

Note 1: For register map detail see Section 4.2.

bank

location select

bank select

Indirect AddressingDirect Addressing

Data Memory

(1)

0Fh 10h

Bank 0

(FSR)

00h

1Fh

(opcode) 04

(FSR)

 1998 Microchip Technology Inc. Preliminary DS40191A-page 19

PIC16CR54C

5.0 I/O PORTS

As with any other register, the I/O registers can be written and read under program control. Ho wever, read instructions (e.g., MOVF PORTB,W) always read the I/O pins independent of the pin’s input/output modes. On RESET, all I/O ports are deﬁned as input (inputs are at hi-impedance) since the I/O control registers (TRISA, TRISB, TRISC) are all set.

5.1 PORTA

PORTA is a 4-bit I/O register. Only the low order 4 bits are used (RA3:RA0). Bits 7-4 are unimplemented and read as '0's.

5.2 PORTB

PORTB is an 8-bit I/O register (PORTB<7:0>).

5.3 TRIS Registers

The output driver control registers are loaded with the contents of the W register by executing the TRIS f instruction. A '1' from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A '0' puts the contents of the output data latch on the selected pins, enabling the output buffer.

The TRIS registers are “write-only” and are set (output drivers disabled) upon RESET.

5.4 I/O Interfacing

The equivalent circuit for an I/O port pin is shown in Figure 5-1. All ports may be used for both input and output operation. For input operations these ports are non-latching. Any input must be present until read by an input instruction (e.g., MOVF PORTB, W). The

Note: A read of the ports reads the pins, not the

output data latches. That is, if an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low.

outputs are latched and remain unchanged until the output latch is rewritten. To use a port pin as output, the corresponding direction control bit (in TRISA, TRISB) must be cleared (= 0). For use as an input, the corresponding TRIS bit must be set. Any I/O pin can be programmed individually as input or output.

FIGURE 5-1: EQUIVALENT CIRCUIT

FOR A SINGLE I/O PIN

Note 1: I/O pins have protection diodes to VDD and VSS.

Data Bus

WR Port

TRIS ‘f’

Data

TRIS

RD Port

VSS

VDD

I/O pin

(1)

W Reg

Latch

Reset

TABLE 5-1: SUMMARY OF PORT REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

N/A TRIS I/O control registers (TRISA, TRISB) 1111 1111 1111 1111 05h PORTA — — — — RA3 RA2 RA1 RA0 ---- xxxx ---- uuuu 06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu Legend: Shaded boxes = unimplemented, read as ‘0’,

– = unimplemented, read as '0', x = unknown, u = unchanged

PIC16CR54C

DS40191A-page 20 Preliminary  1998 Microchip Technology Inc.

5.5 I/O Programming Considerations

5.5.1 BI-DIRECTIONAL I/O PORTS

Some instructions operate internally as read followed by write operations. The BCF and BSF instructions, for example, read the entire port into the CPU, execute the bit operation and re-write the result. Caution must be used when these instructions are applied to a port where one or more pins are used as input/outputs. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU, bit5 to be set and the PORTB value to be written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (say bit0) and it is deﬁned as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched into output mode later on, the content of the data latch may now be unknown.

Example 5-1 shows the effect of two sequential read-modify-write instructions (e.g., BCF, BSF , etc.) on an I/O port.

A pin actively outputting a high or a low should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”, “wired-and”). The resulting high output currents may damage the chip.

EXAMPLE 5-1: READ-MODIFY-WRITE

INSTRUCTIONS ON AN I/O PORT

;Initial PORT Settings ; PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- --------- BCF PORTB, 7 ;01pp pppp 11pp pppp BCF PORTB, 6 ;10pp pppp 11pp pppp MOVLW 03Fh ; TRIS PORTB ;10pp pppp 10pp pppp ; ;Note that the user may have expected the pin ;values to be 00pp pppp. The 2nd BCF caused ;RB7 to be latched as the pin value (High).

5.5.2 SUCCESSIVE OPERATIONS ON I/O PORTS

The actual write to an I/O port happens at the end of an instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-2). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should allow the pin voltage to stabilize (load dependent) before the next instruction, which causes that ﬁle to be read into the CPU, is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.

FIGURE 5-2: SUCCESSIVE I/O OPERATION

PC PC + 1 PC + 2

PC + 3

Q1 Q2

Instruction

fetched

RB7:RB0

MOVWF PORTB

NOP

Port pin sampled here

NOP

MOVF PORTB,W

Instruction

executed

MOVWF PORTB

(Write to

PORTB)

NOP

MOVF PORTB,W

This example shows a write to PORTB followed by a read from PORTB.

(Read

PORTB)

Port pin written here

 1998 Microchip Technology Inc. Preliminary DS40191A-page 21

PIC16CR54C

6.0 TIMER0 MODULE AND TMR0 REGISTER

The Timer0 module has the following features:

• 8-bit timer/counter register, TMR0

- Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

- Edge select for external clock

Figure 6-1 is a simpliﬁed block diagram of the Timer0 module, while Figure 6-2 shows the electrical structure of the Timer0 input.

Timer mode is selected by clearing the T0CS bit (OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If TMR0 register is written, the increment is inhibited for the following two cycles (Figure 6-3 and Figure 6-4). The user can work around this by writing an adjusted value to the TMR0 register.

Counter mode is selected by setting the T0CS bit (OPTION<5>). In this mode, Timer0 will increment either on every rising or falling edge of pin T0CKI. The incrementing edge is determined by the source edge select bit T0SE (OPTION<4>). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.1.

The prescaler may be used by either the Timer0 module or the Watchdog Timer, but not both. The prescaler assignment is controlled in software by the control bit PSA (OPTION<3>). Clearing the PSA bit will assign the prescaler to Timer0. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale v alues of 1:2, 1:4,..., 1:256 are selectable. Section 6.2 details the operation of the prescaler.

A summary of registers associated with the Timer0 module is found in Table 6-1.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

FIGURE 6-2: ELECTRICAL STRUCTURE OF T0CKI PIN

Note 1: Bits T0CS, T0SE, PSA, PS2, PS1 and PS0 are located in the OPTION register.

2: The prescaler is shared with the Watchdog Timer (Figure 6-6).

T0CKI

T0SE

(1)

T0CS

(1)

FOSC/4

Programmable

Prescaler

(2)

Sync with

Internal

Clocks

TMR0 reg

PSout

(2 cycle delay)

PSout

Data bus

PSA

(1)

PS2, PS1, PS0

(1)

Sync

VSS

RIN

Schmitt Trigger

Input Buffer

T0CKI

Note 1: ESD protection circuits

(1)

PIC16CR54C

DS40191A-page 22 Preliminary  1998 Microchip Technology Inc.

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

FIGURE 6-4: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

01h TMR0 Timer0 - 8-bit real-time clock/counter xxxx xxxx uuuu uuuu N/A OPTION

— — T0CS T0SE PSA PS2 PS1 PS0 --11 1111 --11 1111

Legend: Shaded cells: Unimplemented bits,

- = unimplemented, x = unknown, u = unchanged,

PC-1

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC (Program Counter)

Instruction Fetch

Timer0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

Read TMR0 reads NT0 + 2

Instruction Executed

PC-1

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC (Program Counter)

Instruction Fetch

Timer0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

T0+1

NT0

Instruction Execute

 1998 Microchip Technology Inc. Preliminary DS40191A-page 23

PIC16CR54C

6.1 Using Timer0 with an External Clock

When an external clock input is used for Timer0, it must meet certain requirements. The external clock requirement is due to internal phase clock (T

OSC)

synchronization. Also, there is a delay in the actual incrementing of Timer0 after synchronization.

6.1.1 EXTERNAL CLOCK SYNCHRONIZATION

When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2T

OSC (and a small RC delay of 20 ns)

and low for at least 2T

OSC (and a small RC delay of

20 ns). Refer to the electrical speciﬁcation of the desired device.

When a prescaler is used, the external clock input is divided by the asynchronous ripple counter-type prescaler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4T

OSC (and a small RC delay of

40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to parameters 40, 41 and 42 in the electrical speciﬁcation of the desired device.

6.1.2 TIMER0 INCREMENT DELAY Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing.

FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Increment Timer0 (Q4)

External Clock Input or

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

Timer0

T0 T0 + 1 T0 + 2

Small pulse misses sampling

External Clock/Prescaler Output After Sampling

(3)

Note 1:

2: 3:

Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc). Therefore, the error in measuring the interval between two edges on Timer0 input = ± 4Tosc max. External clock if no prescaler selected, Prescaler output otherwise. The arrows indicate the points in time where sampling occurs.

Prescaler Output (2)

(1)

PIC16CR54C

DS40191A-page 24 Preliminary  1998 Microchip Technology Inc.

6.2 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer (WDT) (WDT postscaler not implemented on PIC16C52), respectively (Section 6.1.2). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that the prescaler may be used by either the Timer0 module or the WDT, but not both. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the WDT, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF 1, MOVWF 1, BSF 1,x, etc.) will clear the prescaler. When assigned to WDT, a CLRWDT instruction will clear the prescaler along with the WDT. The prescaler is neither readable nor writable. On a RESET, the prescaler contains all '0's.

6.2.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control

(i.e., it can be changed “on the ﬂy” during program execution). To avoid an unintended device RESET, the

following instruction sequence (Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT.

EXAMPLE 6-1: CHANGING PRESCALER

(TIMER0→WDT)

1.CLRWDT ;Clear WDT

2.CLRF TMR0 ;Clear TMR0 & Prescaler

3.MOVLW '00xx1111’b ;These 3 lines (5, 6, 7)

4.OPTION ; are required only if ; desired

5.CLRWDT ;PS<2:0> are 000 or 001

6.MOVLW '00xx1xxx’b ;Set Postscaler to

7.OPTION ; desired WDT rate

To change prescaler from the WDT to the Timer0 module, use the sequence shown in Example 6-2. This sequence must be used even if the WDT is disabled. A CLRWDT instruction should be executed before switching the prescaler.

EXAMPLE 6-2: CHANGING PRESCALER

(WDT→TIMER0)

CLRWDT ;Clear WDT and

;prescaler

MOVLW 'xxxx0xxx' ;Select TMR0, new

;prescale value and ;clock source

OPTION

FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

T0CKI

T0SE

TCY ( = Fosc/4)

Sync

Cycles

TMR0 reg

8-bit Prescaler

8 - to - 1MUX

MUX

Watchdog

Timer

PSA

WDT

Time-Out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.

PSA

WDT Enable bit

Data Bus

PSA

T0CS

M U

U X

 1998 Microchip Technology Inc. Preliminary DS40191A-page 25

PIC16CR54C

7.0 SPECIAL FEATURES OF THE CPU

What sets a microcontroller apart from other processors are special circuits that deal with the needs of real-time applications. The PIC16C5X family of microcontrollers has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These features are:

• Oscillator selection

• Reset

• Power-On Reset (POR)

• Device Reset Timer (DRT)

• Watchdog Timer (WDT)

• SLEEP

• Code protection

The PIC16CR54C Family has a Watchdog Timer which can be shut off only through conﬁguration bit WDTE. It runs off of its own RC oscillator for added reliability. There is an 18 ms delay provided by the Device Reset Timer (DRT), intended to keep the chip in reset until the crystal oscillator is stable. With this timer on-chip, most applications need no external reset circuitry.

The SLEEP mode is designed to offer a very low current power-down mode. The user can wak e up from SLEEP through external reset or through a Watchdog Timer time-out. Several oscillator options are also made available to allow the par t to ﬁt the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of conﬁguration bits are used to select various options.

7.1 Conﬁguration Bits

Conﬁguration bits can be programmed to select various device conﬁgurations. Two bits are for the selection of the oscillator type and one bit is the Watchdog Timer enable bit. Nine bits are code protection bits (Figure 7-1 and Figure 7-2) for the PIC16CR54C devices.

ROM devices have the oscillator conﬁguration programmed at the factory and these parts are tested accordingly (see "Product Identiﬁcation System" diagrams in the back of this data sheet).

FIGURE 7-1: CONFIGURATION WORD FOR PIC16CR54C

CP CP CP CP CP CP CP CP CP WDTE FOSC1 FOSC0 Register: CONFIG

Address

(1)

: 0FFFh

bit11 10 9 8 7 6 5 4 3 2 1 bit0

bit 11-3: CP: Code protection bits

1 = Code protection off 0 = Code protection on

bit 2: WDTE: Watchdog timer enable bit

1 = WDT enabled 0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator selection bits

11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator

Note 1: Refer to the PIC16C5X Programming Speciﬁcation (Literature number DS30190) to determine how to

access the conﬁguration word.

PIC16CR54C

DS40191A-page 26 Preliminary  1998 Microchip Technology Inc.

7.2 Oscillator Conﬁgurations

7.2.1 OSCILLATOR TYPES

PIC16CR54Cs can be operated in four different oscillator modes. The user can program two conﬁguration bits (FOSC1:FOSC0) to select one of these four modes:

• LP: Low Power Crystal

• XT: Crystal/Resonator

• HS: High Speed Crystal/Resonator

• RC: Resistor/Capacitor

7.2.2 CRYSTAL OSCILLATOR / CERAMIC RESONATORS

In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 7-2). The PIC16CR54C oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers speciﬁcations. When in XT, LP or HS modes, the device can have an external clock source drive the OSC1/CLKIN pin (Figure 7-3).

FIGURE 7-2: CRYSTAL OPERATION

(OR CERAMIC RESONATOR) (HS, XT OR LP OSC CONFIGURATION)

Note 1: See Capacitor Selection tables for

recommended values of C1 and C2.

2: A series resistor (RS) may be required for

AT strip cut crystals.

3: RF varies with the crystal chosen (approx.

value = 10 MΩ).

(1)

XTAL

OSC2

OSC1

(3)

SLEEP

To internal

logic

(2)

PIC16CR54C

FIGURE 7-3: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP OSC CONFIGURATION)

TABLE 7-1: CAPACITOR SELECTION

FOR CERAMIC RESONATORS

- PIC16CR54C

TABLE 7-2: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR

- PIC16CR54C

Osc

Type

Resonator

Freq

Cap. RangeC1Cap. Range

XT 455 kHz

2.0 MHz

4.0 MHz

68-100 pF

15-33 pF 10-22 pF

68-100 pF

15-33 pF 10-22 pF

HS 8.0 MHz

16.0 MHz

10-22 pF

10 pF

10-22 pF

10 pF

These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components.

Osc

Type

Resonator

Freq

Cap.Range

Cap. Range

LP 32 kHz

(1)

15 pF 15 pF

XT 100 kHz

200 kHz 455 kHz

1 MHz 2 MHz 4 MHz

15-30 pF 15-30 pF 15-30 pF 15-30 pF

15 pF 15 pF

200-300 pF 100-200 pF

15-100 pF

15-30 pF

15 pF 15 pF

HS 4 MHz

8 MHz

20 MHz

15 pF 15 pF 15 pF

Note 1: For V

DD > 4.5V, C1 = C2 ≈ 30 pF is

recommended. These values are for design guidance only. Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive lev el speciﬁ cation. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.

Note: If you change from this device to

another device, please verify oscillator characteristics in your application.

Clock from ext. system

OSC1

OSC2

PIC16CR54C

Open

 1998 Microchip Technology Inc. Preliminary DS40191A-page 27

PIC16CR54C

7.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT

Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates. Two types of crystal oscillator circuits can be used: one with parallel resonance, or one with series resonance.

Figure 7-4 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 kΩ resistor provides the negative feedback for stability. The 10 kΩ potentiometers bias the 74AS04 in the linear region. This circuit could be used for external oscillator designs.

FIGURE 7-4: EXTERNAL PARALLEL

RESONANT CRYSTAL OSCILLATOR CIRCUIT (USING XT, HS OR LP OSCILLATOR MODE)

Figure 7-5 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180-degree phase shift in a series resonant oscillator circuit. The 330 Ω resistors provide the negative feedback to bias the inverters in their linear region.

Note: If you change from this device to

another device, please verify oscillator characteristics in your application.

20 pF

+5V

20 pF

10k

4.7k

10k

74AS04

XTAL

10k

74AS04

PIC16CR54C

CLKIN

To Other Devices

OSC2

100k

FIGURE 7-5: EXTERNAL SERIES

RESONANT CRYSTAL OSCILLATOR CIRCUIT (USING XT, HS OR LP OSCILLATOR MODE)

7.2.4 RC OSCILLATOR For timing insensitive applications, the RC device option

offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used.

Figure 7-6 shows how the R/C combination is connected to the PIC16CR54C. For Rext values below

2.2 kΩ, the oscillator operation may become unstable, or stop completely. For very high Rext values (e.g., 1 MΩ) the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend keeping Rext between 3 kΩ and 100 kΩ.

Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance.

Note: If you change from this device to

another device, please verify oscillator characteristics in your application.

330

74AS04

PIC16CR54C

CLKIN

To Other Devices

XTAL

330

74AS04

0.1 µF OSC2

100k

PIC16CR54C

DS40191A-page 28 Preliminary  1998 Microchip Technology Inc.

The Electrical Speciﬁcations sections show RC frequency variation from part to part due to normal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more).

Also, see the Electrical Speciﬁcations sections for variation of oscillator frequency due to V

DD for given

Rext/Cext values as well as frequency variation due to operating temperature for giv en R, C, and V

DD values.

The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic.

FIGURE 7-6: RC OSCILLATOR MODE

Note: If you change from this device to

another device, please verify oscillator characteristics in your application.

VDD

Rext

Cext V

OSC1

Internal clock

OSC2/CLKOUT

Fosc/4

PIC16CR54C

7.3 Reset

PIC16CR54C devices may be reset in one of the following ways:

• Power-On Reset (POR)

• M

CLR reset (normal operation)

• MCLR

wake-up reset (from SLEEP)

• WDT reset (normal operation)

• WDT wake-up reset (from SLEEP) Table 7-3 shows these reset conditions for the PCL

and STATUS registers. Some registers are not affected in any reset condition.

Their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a “reset state” on Power-On Reset (POR), MCLR

WDT reset. A MCLR

or WDT wake-up from SLEEP also results in a device reset, and not a continuation of operation before SLEEP.

The T

O and PD bits (STATUS <4:3>) are set or cleared depending on the different reset conditions (Section 7.7). These bits may be used to determine the nature of the reset.

Table 7-4 lists a full description of reset states of all registers. Figure 7-7 shows a simpliﬁed block diagram of the on-chip reset circuit.

PIC16CR54C

DS40191A-page 29 Preliminary  1998 Microchip Technology Inc.

TABLE 7-3: RESET CONDITIONS FOR SPECIAL REGISTERS

TABLE 7-4: RESET CONDITIONS FOR ALL REGISTERS

FIGURE 7-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

Condition

PCL

Addr: 02h

STATUS

Addr: 03h

Power-On Reset 1111 1111 0001 1xxx MCLR

reset (normal operation) 1111 1111 000u uuuu

(1)

MCLR wake-up (from SLEEP) 1111 1111 0001 0uuu WDT reset (normal operation) 1111 1111 0000 1uuu

(2)

WDT wake-up (from SLEEP) 1111 1111 0000 0uuu Legend: u = unchanged, x = unknown, - = unimplemented read as '0'.

Note 1: T

O and PD bits retain their last value until one of the other reset conditions occur.

2: The CLRWDT instruction will set the T

O and PD bits.

or WDT Reset

W N/A

xxxx xxxx uuuu uuuu

TRIS N/A

1111 1111 1111 1111

OPTION N/A

--11 1111 --11 1111

INDF 00h

xxxx xxxx uuuu uuuu

TMR0 01h

xxxx xxxx uuuu uuuu

PCL

(1)

02h

1111 1111 1111 1111

STATUS

(1)

03h

0001 1xxx 000q quuu

FSR 04h

111x xxxx 111u uuuu

PORTA 05h

---- xxxx ---- uuuu

PORTB 06h

xxxx xxxx uuuu uuuu

General Purpose Register Files 07-1Fh

xxxx xxxx uuuu uuuu

Legend: u = unchanged, x = unknown, - = unimplemented, read as '0',

q = see tables in Section 7.7 for possible values.

Note 1: See Table 7-3 for reset value for speciﬁc conditions.

8-bit Asynch

Ripple Counter

(Start-Up Timer)

S Q

VDD

MCLR/VPP pin

Power-Up

Detect

On-Chip RC OSC

POR (Power-On Reset)

WDT Time-out

RESET

CHIP RESET

WDT

PIC16CR54C

DS40191A-page 30 Preliminary  1998 Microchip Technology Inc.

7.4 Power-On Reset (POR)

The PIC16CR54C incorporates on-chip Power-On Reset (POR) circuitry which provides an internal chip reset for most power-up situations. To use this feature, the user merely ties the MCLR

/VPP pin to VDD. A simpliﬁed block diagram of the on-chip Power-On Reset circuit is shown in Figure 7-7.

The Power-On Reset circuit and the Device Reset Timer (Section 7.5) circuit are closely related. On power-up, the reset latch is set and the DRT is reset. The DRT timer begins counting once it detects MCLR to be high. After the time-out period, which is typically 18 ms, it will reset the reset latch and thus end the on-chip reset signal.

A power-up example where MCLR

is not tied to VDD is

shown in Figure 7-9. V

DD is allowed to rise and

stabilize before bringing MCLR

high. The chip will

actually come out of reset T

DRT msec after MCLR

goes high. In Figure 7-10, the on-chip Power-On Reset feature is

being used (MCLR

and VDD are tied together). The

DD is stable before the start-up timer times out and

there is no problem in getting a proper reset. However, Figure 7-11 depicts a problem situation where V

rises too slowly. The time between when the DRT senses a high on the MCLR

/VPP pin, and when the

MCLR

/VPP pin (and VDD) actually reach their full value , is too long. In this situation, when the start-up timer times out, V

DD has not reached the VDD (min) value

and the chip is, therefore, not guaranteed to function correctly. For such situations, we recommend that external RC circuits be used to achieve longer POR delay times (Figure 7-8).

For more information on PIC16CR54C POR, see

Power-Up Considerations

- AN522 in the Embedded

Control Handbook. The POR circuit does not produce an internal reset

when V

DD declines.

Note: When the device starts normal operation

(exits the reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be meet to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met.

FIGURE 7-8: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW VDD POWER-UP)

MCLR

PIC16CR54C

VDDVDD

• External Power-On Reset circuit is required only if V

DD power-up is too slow. The diode D

helps discharge the capacitor quickly when V

DD powers down.

• R < 40 kΩ is recommended to make sure that voltage drop across R does not violate the device electrical speciﬁcation.

• R1 = 100Ω to 1 kΩ will limit any current ﬂowing into MCLR

from external capacitor C

in the event of MCLR

pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).

PIC16CR54C

DS40191A-page 31 Preliminary  1998 Microchip Technology Inc.

FIGURE 7-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD)

FIGURE 7-10: TIME-OUT SEQUENCE ON POWER-UP (MCLR

TIED TO VDD): FAST VDD RISE TIME

FIGURE 7-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR

TIED TO VDD): SLOW VDD RISE TIME

VDD

MCLR

INTERNAL POR

DRT TIME-OUT

INTERNAL RESET

TDRT

VDD

MCLR

INTERNAL POR

DRT TIME-OUT

INTERNAL RESET

TDRT

VDD

MCLR

INTERNAL POR

DRT TIME-OUT

INTERNAL RESET

TDRT

When VDD rises slowly, the TDRT time-out expires long before VDD has reached its ﬁnal value. In this example, the chip will reset properly if, and only if, V1 ≥ V

DD min

PIC16CR54C

DS40191A-page 32 Preliminary  1998 Microchip Technology Inc.

7.5 Device Reset Timer (DRT)

The Device Reset Timer (DRT) provides a ﬁxed 18 ms nominal time-out on reset. The DRT operates on an internal RC oscillator. The processor is kept in RESET as long as the DRT is active. The DRT delay allows V

DD to rise above VDD min., and for the oscillator to

stabilize. Oscillator circuits based on crystals or ceramic

resonators require a certain time after power-up to establish a stable oscillation. The on-chip DRT keeps the device in a RESET condition for approximately 18 ms after the voltage on the MCLR

/VPP pin has

reached a logic high (V

IH) level. Thus, external RC

networks connected to the MCLR

input are not required in most cases, allowing for savings in cost-sensitive and/or space restricted applications.

The Device Reset time delay will v ary from chip to chip due to V

DD, temperature, and process variation. See

AC parameters for details. The DRT will also be triggered upon a W atchdog Timer

time-out. This is particularly impor tant for applications using the WDT to wake the PIC16CR54C from SLEEP mode automatically.

7.6 Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins have been stopped, for example, by execution of a SLEEP instruction. During normal operation or SLEEP, a WDT reset or wake-up reset generates a device RESET.

The T

O bit (STATUS<4>) will be cleared upon a

Watchdog Timer reset. The WDT can be permanently disabled by prog r amming

the conﬁguration bit WDTE as a '0' (Section 7.1). Refer to the PIC16C5X Programming Speciﬁcations (Literature Number DS30190) to determine how to access the conﬁguration word.

7.6.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms, (with

no prescaler). If a longer time-out period is desired, a prescaler with a division ratio of up to 1:128 can be assigned to the WDT (under software control) by writing to the OPTION register. Thus, time-out a period of a nominal 2.3 seconds can be realized. These periods vary with temperature, V

DD and part-to-part process

variations (see DC specs). Under worst case conditions (V

DD = Min., Temperature

= Max., max. WDT prescaler), it may take several seconds before a WDT time-out occurs.

7.6.2 WDT PROGRAMMING CONSIDERATIONS The CLRWDT instruction clears the WDT and the

postscaler, if assigned to the WDT, and prevents it from timing out and generating a device RESET.

The SLEEP instruction resets the WDT and the postscaler, if assigned to the WDT. This gives the maximum SLEEP time before a WDT wake-up reset.

PIC16CR54C

DS40191A-page 33 Preliminary  1998 Microchip Technology Inc.

FIGURE 7-12: WATCHDOG TIMER BLOCK DIAGRAM

TABLE 7-5: SUMMARY OF REGISTERS ASSOCIATED WITH THE WATCHDOG TIMER

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on

Power-On

Reset

Value on

MCLR and

WDT Reset

N/A OPTION — — T0CS T0SE PSA PS2 PS1 PS0 --11 1111 --11 1111 Legend: Shaded boxes = Not used by Watchdog Timer,

– = unimplemented, read as '0', u = unchanged

From TMR0 Clock Source

To TMR0

Postscaler

WDT Enable

EPROM Bit

PSA

WDT

Time-out

PS2:PS0

PSA

MUX

8 - to - 1 MUX

Postscaler

U X

Watchdog

Timer

Note: T0CS, T0SE, PSA, PS2:PS0

are bits in the OPTION register.

PIC16CR54C

DS40191A-page 34 Preliminary  1998 Microchip Technology Inc.

7.7 Time-Out Sequence and Power Down

Status Bits (TO/PD)

The TO and PD bits in the STATUS register can be tested to determine if a RESET condition has been caused by a power-up condition, a MCLR

or W atchdog

Timer (WDT) reset, or a MCLR

or WDT wake-up reset.

These STATUS bits are only affected by events listed in Table 7-7.

Table 7-3 lists the reset conditions for the special function registers, while Table 7-4 lists the reset conditions for all the registers.

TABLE 7-6: TO/PD STATUS AFTER

RESET

TO PD RESET was caused by

1 1

Power-up (POR)

u u

MCLR reset (normal operation)

(1)

1 0

MCLR wake-up reset (from SLEEP)

0 1

WDT reset (normal operation)

0 0

WDT wake-up reset (from SLEEP)

Legend: u = unchanged Note 1: The TO and PD bits maintain their status (u) until

a reset occurs. A low-pulse on the MCLR input does not change the TO and PD status bits.

TABLE 7-7: EVENTS AFFECTING TO/PD

STATUS BITS

Event TO PD Remarks

Power-up

1 1

WDT Time-out

0 u

No effect on PD

SLEEP instruction

1 0

CLRWDT instruction

1 1

Legend: u = unchanged A WDT time-out will occur regardless of the status of the TO bit. A SLEEP instruction will be executed, regardless of the status of the PD bit. Table 7-6 reﬂects the status of TO and PD after the corresponding event.

7.8 Reset on Brown-Out

A brown-out is a condition where device power (VDD) dips below its minimum value, b ut not to z ero , and then recovers. The device should be reset in the event of a brown-out.

To reset PIC16CR54C devices when a brown-out occurs, external brown-out protection circuits may be built, as shown in Figure 7-13 and Figure 7-14.

FIGURE 7-13: BROWN-OUT PROTECTION

CIRCUIT 1

FIGURE 7-14: BROWN-OUT PROTECTION

CIRCUIT 2

This circuit will activate reset when VDD goes below Vz +

0.7V (where Vz = Zener voltage).

33k

10k

40k

MCLR

PIC16CR54C

VDD

This brown-out circuit is less expensive, although less accurate. Transistor Q1 turns off when V

is below a certain level such that:

DD •

R1 + R2

= 0.7V

40k

VDD

MCLR

PIC16CR54C

VDD

 1998 Microchip Technology Inc. Preliminary DS40191A-page 35

PIC16CR54C

7.9 Power-Down Mode (SLEEP)

A device may be powered down (SLEEP) and later powered up (Wake-up from SLEEP).

7.9.1 SLEEP The Power-Down mode is entered by executing a

SLEEP instruction. If enabled, the Watchdog Timer will be cleared but

keeps running, the T

O bit (STATUS<4>) is set, the PD bit (STATUS<3>) is cleared and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, driving low, or hi-impedance).

It should be noted that a RESET generated by a WDT time-out does not drive the MCLR

/VPP pin low.

For lowest current consumption while powered down, the T0CKI input should be at V

DD or VSS and the

MCLR

/VPP pin must be at a logic high level

IH MCLR).

7.9.2 WAKE-UP FROM SLEEP The device can wake up from SLEEP through one of

the following events:

1. An external reset input on MCLR

/VPP pin.

2. A Watchdog Timer time-out reset (if WDT was

enabled).

Both of these events cause a de vice reset. The T

O and

bits can be used to determine the cause of device

reset. The T

O bit is cleared if a WDT time-out

occurred (and caused wake-up). The PD

bit, which is

set on power-up, is cleared when SLEEP is invoked. The WDT is cleared when the device wakes from

sleep, regardless of the wake-up source.

7.10 Program Veriﬁcation/Code Protection

If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for veriﬁcation purposes.

Note: Microchip does not recommend code pro-

tecting windowed devices.

PIC16CR54C

DS40191A-page 36 Preliminary  1998 Microchip Technology Inc.

NOTES:

 1998 Microchip Technology Inc. Preliminary DS40191A-page 37

PIC16CR54C

8.0 INSTRUCTION SET SUMMARY

Each PIC16CR54C instruction is a 12-bit word divided into an OPCODE, which speciﬁes the instruction type, and one or more operands which further specify the operation of the instruction. The PIC16CR54C instruction set summary in Table 8-2 groups the instructions into byte-oriented, bit-oriented, and literal and control operations. Table 8-1 shows the opcode ﬁeld descriptions.

For byte-oriented instructions, 'f' represents a ﬁle register designator and 'd' represents a destination designator. The ﬁle register designator is used to specify which one of the 32 ﬁle registers is to be used by the instruction.

The destination designator speciﬁes where the result of the operation is to be placed. If 'd' is '0', the result is placed in the W register. If 'd' is '1', the result is placed in the ﬁle register speciﬁed in the instruction.

For bit-oriented instructions, 'b' represents a bit ﬁeld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ﬁle in which the bit is located.

For literal and control operations, 'k' represents an 8 or 9-bit constant or literal value.

TABLE 8-1: OPCODE FIELD

DESCRIPTIONS

Field Description

f Register ﬁle address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit ﬁle register k Literal ﬁeld, constant data or label

Don't care location (= 0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools.

Destination select;

d = 0 (store result in W) d = 1 (store result in ﬁle register 'f')

Default is d = 1

label Label name

TOS Top of Stack

PC Program Counter

WDT Watchdog Timer Counter

Time-Out bit

PD Power-Down bit

dest

Destination, either the W register or the speciﬁed register ﬁle location

[ ]

Options

( )

Contents

→

Assigned to

< >

∈

In the set of

talics

User deﬁned term (font is courier)

All instructions are executed within one single instruction cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 µs. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 µs.

Figure 8-1 shows the three general formats that the instructions can have. All examples in the ﬁgure use the following format to represent a hexadecimal number:

0xhhh

where 'h' signiﬁes a hexadecimal digit.

FIGURE 8-1: GENERAL FORMAT FOR

INSTRUCTIONS

Byte-oriented ﬁle register operations

11 6 5 4 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f f = 5-bit ﬁle register address

Bit-oriented ﬁle register operations

11 8 7 5 4 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address f = 5-bit ﬁle register address

Literal and control operations (except GOTO)

11 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

Literal and control operations - GOTO instruction

11 9 8 0

OPCODE k (literal)

k = 9-bit immediate value

PIC16CR54C

DS40191A-page 38 Preliminary  1998 Microchip Technology Inc.

TABLE 8-2: INSTRUCTION SET SUMMARY

Mnemonic,

Operands Description Cycles

12-Bit Opcode

Status

Affected NotesMSb LSb

ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF

f,d f,d f – f, d f, d f, d f, d f, d f, d f, d f – f, d f, d f, d f, d f, d

Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate left f through Carry Rotate right f through Carry Subtract W from f Swap f Exclusive OR W with f

1 1 1 1 1 1

1(2)

1 1 1 1 1 1 1 1 1

0001 0001 0000 0000 0010 0000 0010 0010 0011 0001 0010 0000 0000 0011 0011 0000 0011 0001

11df 01df 011f 0100 01df 11df 11df 10df 11df 00df 00df 001f 0000 01df 00df 10df 10df 10df

ffff ffff ffff 0000 ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff

C,DC,Z

Z Z Z Z Z

None

Z None None

C C

C,DC,Z

None

1,2,4

2,4

2,4 2,4 2,4 2,4 2,4 2,4 1,4

2,4 2,4

1,2,4

2,4 2,4

BIT-ORIENTED FILE REGISTER OPERATIONS BCF

BSF BTFSC BTFSS

f, b f, b f, b f, b

Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set

1 1 (2) 1 (2)

0100 0101 0110 0111

bbbf bbbf bbbf bbbf

ffff ffff ffff ffff

None None None None

2,4 2,4

LITERAL AND CONTROL OPERATIONS ANDLW

CALL CLRWDT GOTO IORLW MOVLW OPTION RETLW SLEEP TRIS XORLW

k k k k k k k k – f k

AND literal with W Call subroutine Clear Watchdog Timer Unconditional branch Inclusive OR Literal with W Move Literal to W Load OPTION register Return, place Literal in W Go into standby mode Load TRIS register Exclusive OR Literal to W

1110 1001 0000 101k 1101 1100 0000 1000 0000 0000 1111

kkkk kkkk 0000 kkkk kkkk kkkk 0000 kkkk 0000 0000 kkkk

kkkk kkkk 0100 kkkk kkkk kkkk 0010 kkkk 0011 0fff kkkk

None

O, PD

None

Z None None None

O, PD

None

Note 1: The 9th bit of the program counter will be forced to a '0' by any instruction that writes to the PC except for GOTO .

(See individual device data sheets, Memory Section/Indirect Data Addressing, INDF and FSR Registers)

2: When an I/O register is modiﬁed as a function of itself (e.g. MOVF PORTB, 1), the value used will be that value

present on the pins themselves. For example, if the data latch is '1' f or a pin conﬁgured as input and is driv en low by an external device , the data will be written back with a '0'.

3: The instruction TRIS f, where f = 5 or 6 causes the contents of the W register to be written to the tristate

latches of PORTA or B respectively. A '1' forces the pin to a hi-impedance state and disables the output buffers.

4: If this instruction is executed on the TMR0 register (and, where applicab le , d = 1), the prescaler will be cleared

(if assigned to TMR0).

 1998 Microchip Technology Inc. Preliminary DS40191A-page 39

PIC16CR54C

ADDWF Add W and f

Syntax: [

label

] ADDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W) + (f) → (dest) Status Affected: C, DC, Z Encoding:

0001 11df ffff

Description:

Add the contents of the W register and

in the W register . If 'd' is '1' the result is

stored back in register 'f'

. Words: 1 Cycles: 1 Example:

ADDWF FSR, 0

Before Instruction

W = 0x17 FSR = 0xC2

After Instruction

W = 0xD9 FSR = 0xC2

ANDLW And literal with W

Syntax: [

label

] ANDLW k Operands: 0 ≤ k ≤ 255 Operation: (W).AND. (k) → (W) Status Affected: Z Encoding:

1110 kkkk kkkk

Description:

The contents of the W register are AND’ed with the eight-bit literal 'k'. The result is placed in the W register

. Words: 1 Cycles: 1 Example:

ANDLW 0x5F

Before Instruction

W = 0xA3

After Instruction

W = 0x03

ANDWF AND W with f

Syntax: [

label

] ANDWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W) .AND. (f) → (dest) Status Affected: Z Encoding:

0001 01df ffff

Description:

The contents of the W register are

AND’ed with register 'f'. If 'd' is 0 the

result is stored in the W register . If 'd' is

'1' the result is stored back in register 'f'

. Words: 1 Cycles: 1 Example:

ANDWF FSR, 1

Before Instruction

W = 0x17 FSR = 0xC2

After Instruction

W = 0x17 FSR = 0x02

BCF Bit Clear f

Syntax: [

label

] BCF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7 Operation: 0 → (f<b>) Status Affected: None Encoding:

0100 bbbf ffff

Description:

Bit 'b' in register 'f' is cleared.

Words: 1 Cycles: 1 Example:

BCF FLAG_REG, 7

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

PIC16CR54C

DS40191A-page 40 Preliminary  1998 Microchip Technology Inc.

BSF Bit Set f

Syntax: [

label

] BSF f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7 Operation: 1 → (f<b>) Status Affected: None Encoding:

0101 bbbf ffff

Description:

Bit 'b' in register 'f' is set.

Words: 1 Cycles: 1 Example:

BSF FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

BTFSC Bit Test f, Skip if Clear

Syntax: [

label

] BTFSC f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b ≤ 7 Operation: skip if (f<b>) = 0 Status Affected: None Encoding: 0110

bbbf ffff

Description:

If bit 'b' in register 'f' is 0 then the next

instruction is skipped.

If bit 'b' is 0 then the next instruction

fetched during the current instruction

execution is discarded, and an NOP is

executed instead, making this a 2 cycle

instruction.

Words: 1 Cycles: 1(2) Example:

HERE

FALSE

TRUE

BTFSC GOTO

•

FLAG,1 PROCESS_CODE

Before Instruction

PC = address (HERE)

After Instruction

if FLAG<1> = 0, PC = address (TRUE); if FLAG<1> = 1, PC = address(FALSE)

BTFSS Bit Test f, Skip if Set

Syntax: [

label

] BTFSS f,b

Operands: 0 ≤ f ≤ 31

0 ≤ b < 7 Operation: skip if (f<b>) = 1 Status Affected: None Encoding:

0111 bbbf ffff

Description:

If bit 'b' in register 'f' is '1' then the next

instruction is skipped.

If bit 'b' is '1', then the next instruction

fetched during the current instruction

execution, is discarded and an NOP is

executed instead, making this a 2 cycle

instruction.

Words: 1 Cycles: 1(2) Example:

HERE BTFSS FLAG,1

FALSE GOTO PROCESS_CODE

TRUE •

•

Before Instruction

PC = address (HERE)

After Instruction

If FLAG<1> = 0, PC = address (FALSE); if FLAG<1> = 1, PC = address (TRUE)

 1998 Microchip Technology Inc. Preliminary DS40191A-page 41

PIC16CR54C

CALL Subroutine Call

Syntax: [

label

] CALL k Operands: 0 ≤ k ≤ 255 Operation: (PC) + 1→ Top of Stack;

k → PC<7:0>; (STATUS<6:5>) → PC<10:9>;

0 → PC<8> Status Affected: None Encoding:

1001 kkkk kkkk

Description:

Subroutine call. First, return address

(PC+1) is pushed onto the stack. The

eight bit immediate address is loaded

into PC bits <7:0>. The upper bits

PC<10:9> are loaded from STA-

TUS<6:5>, PC<8> is cleared. CALL is

a two cycle instruction.

Words: 1 Cycles: 2 Example:

HERE CALL THERE

Before Instruction

PC = address (HERE)

After Instruction

PC = address (THERE) TOS= address (HERE + 1)

CLRF Clear f

Syntax: [

label

] CLRF f Operands: 0 ≤ f ≤ 31 Operation: 00h → (f);

1 → Z Status Affected: Z Encoding:

0000 011f ffff

Description:

The contents of register 'f' are cleared

and the Z bit is set.

Words: 1 Cycles: 1 Example:

CLRF FLAG_REG

Before Instruction

FLAG_REG = 0x5A

After Instruction

FLAG_REG = 0x00 Z = 1

CLRW Clear W

Syntax: [

label

] CLRW Operands: None Operation: 00h → (W);

1 → Z Status Affected: Z Encoding:

0000 0100 0000

Description:

The W register is cleared. Zero bit (Z)

is set.

Words: 1 Cycles: 1 Example:

CLRW

Before Instruction

W = 0x5A

After Instruction

W = 0x00 Z = 1

CLRWDT Clear Watchdog Timer

Syntax: [

label

] CLRWDT Operands: None Operation: 00h → WDT;

0 → WDT prescaler (if assigned); 1 → T

1 → PD Status Affected: TO, PD Encoding:

0000 0000 0100

Description:

The CLRWDT instruction resets the

WDT. It also resets the prescaler , if the

prescaler is assigned to the WDT and

not Timer0. Status bits TO and PD are

set.

Words: 1 Cycles: 1 Example:

CLRWDT

Before Instruction

WDT counter = ?

After Instruction

WDT counter = 0x00 WDT prescale = 0 TO = 1 PD = 1

PIC16CR54C

DS40191A-page 42 Preliminary  1998 Microchip Technology Inc.

COMF Complement f

Syntax: [

label

] COMF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f

) → (dest) Status Affected: Z Encoding:

0010 01df ffff

Description:

The contents of register 'f' are complemented. If 'd' is 0 the result is stored in the W register. If 'd' is 1 the result is stored back in register 'f'.

Words: 1 Cycles: 1 Example:

COMF REG1,0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13 W = 0xEC

DECF Decrement f

Syntax: [

label

] DECF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) – 1 → (dest) Status Affected: Z Encoding:

0000 11df ffff

Description:

Decrement register 'f'. If 'd' is 0 the

result is stored in the W register . If 'd' is

1 the result is stored back in register 'f'.

Words: 1 Cycles: 1 Example:

DECF CNT,

Before Instruction

CNT = 0x01 Z = 0

After Instruction

CNT = 0x00 Z = 1

DECFSZ Decrement f, Skip if 0

Syntax: [

label

] DECFSZ f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) – 1 → d; skip if result = 0 Status Affected: None Encoding:

0010 11df ffff

Description:

The contents of register 'f' are decre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

If the result is 0, the next instruction,

which is already fetched, is discarded

and an NOP is executed instead mak-

ing it a two cycle instruction.

Words: 1 Cycles: 1(2) Example:

HERE DECFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address (HERE)

After Instruction

CNT = CNT - 1; if CNT = 0, PC = address (CONTINUE); if CNT ≠ 0, PC = address (HERE+1)

GOTO Unconditional Branch

Syntax: [

label

] GOTO k Operands: 0 ≤ k ≤ 511 Operation: k → PC<8:0>;

STATUS<6:5> → PC<10:9> Status Affected: None Encoding:

101k kkkk kkkk

Description:

GOTO is an unconditional branch. The

9-bit immediate value is loaded into PC

bits <8:0>. The upper bits of PC are

loaded from STATUS<6:5>. GOTO is a

two cycle instruction.

Words: 1 Cycles: 2 Example:

GOTO THERE

After Instruction

PC = address (THERE)

 1998 Microchip Technology Inc. Preliminary DS40191A-page 43

PIC16CR54C

INCF Increment f

Syntax: [

label

] INCF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) + 1 → (dest) Status Affected: Z Encoding:

0010 10df ffff

Description:

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Example:

INCF CNT,

Before Instruction

CNT = 0xFF Z = 0

After Instruction

CNT = 0x00 Z = 1

INCFSZ Increment f, Skip if 0

Syntax: [

label

] INCFSZ f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: None Encoding:

0011 11df ffff

Description:

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

If the result is 0, then the next instruc-

tion, which is already fetched, is dis-

carded and an NOP is executed

instead making it a two cycle instruc-

tion.

Words: 1 Cycles: 1(2) Example:

HERE INCFSZ CNT, 1

GOTO LOOP

CONTINUE •

•

Before Instruction

PC = address (HERE)

After Instruction

CNT = CNT + 1; if CNT = 0, PC = address (CONTINUE); if CNT ≠ 0, PC = address (HERE +1)

IORLW Inclusive OR literal with W

Syntax: [

label

] IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. (k) → (W) Status Affected: Z Encoding:

1101 kkkk kkkk

Description:

The contents of the W register are OR’ed with the eight bit literal 'k'. The result is placed in the W register.

Words: 1 Cycles: 1 Example:

IORLW 0x35

Before Instruction

W = 0x9A

After Instruction

W = 0xBF Z = 0

IORWF Inclusive OR W with f

Syntax: [

label

] IORWF f,d Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W).OR. (f) → (dest) Status Affected: Z Encoding:

0001 00df ffff

Description:

Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Example:

IORWF RESULT, 0

Before Instruction

RESULT = 0x13 W = 0x91

After Instruction

RESULT = 0x13 W = 0x93 Z = 0

PIC16CR54C

DS40191A-page 44 Preliminary  1998 Microchip Technology Inc.

MOVF Move f

Syntax: [

label

] MOVF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Encoding:

0010 00df ffff

Description:

The contents of register 'f' is moved to

destination 'd'. If 'd' is 0, destination is

the W register. If 'd' is 1, the destination

is ﬁle register 'f'. 'd' is 1 is useful to test

a ﬁle register since status ﬂag Z is

affected.

Words: 1 Cycles: 1 Example:

MOVF FSR, 0

After Instruction

W = value in FSR register

MOVLW Move Literal to W

Syntax: [

label

] MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W) Status Affected: None Encoding:

1100 kkkk kkkk

Description:

The eight bit literal 'k' is loaded into the W register. The don’t cares will assemble as 0s.

Words: 1 Cycles: 1 Example:

MOVLW 0x5A

After Instruction

W = 0x5A

MOVWF Move W to f

Syntax: [

label

] MOVWF f Operands: 0 ≤ f ≤ 31 Operation: (W) → (f) Status Affected: None Encoding:

0000 001f ffff

Description:

Move data from the W register to register 'f'

. Words: 1 Cycles: 1 Example:

MOVWF TEMP_REG

Before Instruction

TEMP_REG = 0xFF W = 0x4F

After Instruction

TEMP_REG = 0x4F W = 0x4F

NOP No Operation

Syntax: [

label

] NOP Operands: None Operation: No operation Status Affected: None Encoding:

0000 0000 0000

Description: No operation. Words: 1 Cycles: 1 Example:

NOP

 1998 Microchip Technology Inc. Preliminary DS40191A-page 45

PIC16CR54C

OPTION Load OPTION Register

Syntax: [

label

] OPTION Operands: None Operation: (W) → OPTION Status Affected: None Encoding:

0000 0000 0010

Description:

The content of the W register is loaded into the OPTION register.

Words: 1 Cycles: 1 Example

OPTION

Before Instruction

W = 0x07

After Instruction

OPTION = 0x07

RETLW Return with Literal in W

Syntax: [

label

] RETLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W);

TOS → PC Status Affected: None Encoding:

1000 kkkk kkkk

Description:

The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two cycle

instruction.

Words: 1 Cycles: 2 Example:

TABLE

CALL TABLE ;W contains

;table offset

;value.

• ;W now has table

• ;value.

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

RLF Rotate Left f through Carry

Syntax: [

label

] RLF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: See description below Status Affected: C Encoding:

0011 01df ffff

Description:

The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0 the result is placed in the

W register. If 'd' is 1 the result is stored

back in register 'f'.

Words: 1 Cycles: 1 Example:

RLF REG1,0

Before Instruction

REG1 = 1110 0110 C = 0

After Instruction

REG1 = 1110 0110 W = 1100 1100 C = 1

RRF Rotate Right f through Carry

Syntax: [

label

] RRF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: See description below Status Affected: C Encoding:

0011 00df ffff

Description:

The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0 the result is placed in the

W register. If 'd' is 1 the result is placed

back in register 'f'.

Words: 1 Cycles: 1 Example:

RRF REG1,0

Before Instruction

REG1 = 1110 0110 C = 0

After Instruction

REG1 = 1110 0110 W = 0111 0011 C = 0

PIC16CR54C

DS40191A-page 46 Preliminary  1998 Microchip Technology Inc.

SLEEP Enter SLEEP Mode

Syntax:

[

label

]

SLEEP Operands: None Operation: 00h → WDT;

0 → WDT prescaler; 1 → T

0 → PD Status Affected: TO, PD Encoding:

0000 0000 0011

Description:

Time-out status bit (TO) is set. The

power down status bit (PD) is cleared.

The WDT and its prescaler are

cleared.

The processor is put into SLEEP mode

with the oscillator stopped. See sec-

tion on SLEEP for more details.

Words: 1 Cycles: 1 Example: SLEEP

SUBWF Subtract W from f

Syntax:

[

label

] SUBWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (f) – (W) → (dest) Status Affected: C, DC, Z Encoding:

0000 10df ffff

Description:

Subtract (2’s complement method) the

W register from register 'f'. If 'd' is 0 the

result is stored in the W register . If 'd' is

1 the result is stored back in register 'f'.

Words: 1 Cycles: 1 Example 1

SUBWF REG1, 1

Before Instruction

REG1 = 3 W = 2 C = ?

After Instruction

REG1 = 1 W = 2 C = 1 ; result is positive

Example 2:

Before Instruction

REG1 = 2 W = 2 C = ?

After Instruction

REG1 = 0 W = 2 C = 1 ; result is zero

Example 3:

Before Instruction

REG1 = 1 W = 2 C = ?

After Instruction

REG1 = FF W = 2 C = 0 ; result is negative

 1998 Microchip Technology Inc. Preliminary DS40191A-page 47

PIC16CR54C

SWAPF Swap Nibbles in f

Syntax: [

label

] SWAPF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>);

(f<7:4>) → (dest<3:0>) Status Affected: None Encoding:

0011 10df ffff

Description:

The upper and lower nibbles of register

'f' are exchanged. If 'd' is 0 the result is

placed in W register . If 'd' is 1 the result

is placed in register 'f'.

Words: 1 Cycles: 1 Example

SWAPF

REG1, 0

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5 W = 0X5A

TRIS Load TRIS Register

Syntax: [

label

] TRIS f Operands: f = 5, 6 or 7 Operation: (W) → TRIS register f Status Affected: None Encoding:

0000 0000 0fff

Description:

TRIS register 'f' (f = 5, 6, or 7) is loaded with the contents of the W register

Words: 1 Cycles: 1 Example

TRIS PORTA

Before Instruction

W = 0XA5

After Instruction

TRISA = 0XA5

XORLW Exclusive OR literal with W

Syntax:

[

label

] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Encoding:

1111 kkkk kkkk

Description:

The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register.

Words: 1 Cycles: 1 Example: XORLW 0xAF

Before Instruction

W = 0xB5

After Instruction

W = 0x1A

XORWF Exclusive OR W with f

Syntax: [

label

] XORWF f,d

Operands: 0 ≤ f ≤ 31

d ∈ [0,1] Operation: (W) .XOR. (f) → (dest) Status Affected: Z Encoding:

0001 10df ffff

Description:

Exclusive OR the contents of the W

result is stored in the W register . If 'd' is

1 the result is stored back in register 'f'.

Words: 1 Cycles: 1 Example XORWF

REG,1

Before Instruction

REG = 0xAF W = 0xB5

After Instruction

REG = 0x1A W = 0xB5

PIC16CR54C

DS40191A-page 48 Preliminary  1998 Microchip Technology Inc.

NOTES:

 1998 Microchip Technology Inc. Preliminary DS40191A-page 49

PIC16CR54C

9.0 DEVELOPMENT SUPPORT

9.1 Development Tools

The PICmicrο microcontrollers are supported with a full range of hardware and software development tools:

• PICMASTER



/PICMASTER CE Real-Time

In-Circuit Emulator

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator

• PRO MATE



II Universal Programmer

• PICSTART



Plus Entry-Level Prototype

Programmer

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

• MPLAB SIM Software Simulator

• MPLAB-C17 (C Compiler)

• Fuzzy Logic Development System (

fuzzy

TECH−MP)

9.2 PICMASTER: High Performance

Universal In-Circuit Emulator with MPLAB IDE

The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC14C000, PIC12CXXX, PIC16C5X, PIC16CXXX and PIC17CXX families. PICMASTER is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, “make” and download, and source debugging from a single environment.

Interchangeable target probes allow the system to be easily reconﬁgured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new Microchip microcontrollers.

The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows



3.x environment were chosen to best make these

features available to you, the end user. A CE compliant version of PICMASTER is availab le for

European Union (EU) countries.

9.3 ICEPIC: Low-Cost PICmicro™ In-Circuit Emulator

ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC12CXXX, PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers.

ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT



through Pentium based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation.

9.4 PRO MATE II: Universal Programmer

The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode. PRO MATE II is CE compliant.

The PRO MATE II has programmable V

DD and VPP

supplies which allows it to verify programmed memory at V

DD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set conﬁguration and code-protect bits in this mode.

9.5 PICSTART Plus Entry Level

Development System

The PICSTART programmer is an easy-to-use, low-cost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efﬁcient. PICSTART Plus is not recommended for production programming.

PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923, PIC16C924 and PIC17C756 may be supported with an adapter socket. PICSTART Plus is CE compliant.

9.6 PICDEM-1 Low-Cost PICmicro

Demonstration Board

The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test ﬁrmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the ﬁrmware to the emulator for testing.

PIC16CR54C

DS40191A-page 50 Preliminary  1998 Microchip Technology Inc.

Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.

9.7 PICDEM-2 Low-Cost PIC16CXX Demonstration Board

The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test ﬁrmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test ﬁrmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I

C bus and separate headers for connection to an LCD module and a keypad.

9.8 PICDEM-3 Low-Cost PIC16CXXX

Demonstration Board

The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test ﬁrmware. The PICMASTER emulator may also be used with the PICDEM-3 board to test ﬁrmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.

9.9 MPLAB™ Integrated Development Environment Software

The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains:

• A full featured editor

• Three operating modes

- editor

- emulator

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

MPLAB allows you to:

• Edit your source ﬁles (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PICmicro tools (automatically updates all project information)

• Debug using:

- source ﬁles

- absolute listing ﬁle

• Transfer data dynamically via DDE (soon to be

replaced by OLE)

• Run up to four emulators on the same PC

The ability to use MPLAB with Microchip’s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.

9.10 Assembler (MPASM)

The MPASM Universal Macro Assembler is a PC-hosted symbolic assembler. It supports all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, conditional assembly, and several source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers.

MPASM allows full symbolic debugging from PICMASTER, Microchip’s Universal Emulator System.

MPASM has the following features to assist in developing software for speciﬁc use applications.

• Provides translation of Assembler source code to

object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the ﬁles (Object, Listing, Symbol,

and special) required for symbolic debug with Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source

and listing formats.

 1998 Microchip Technology Inc. Preliminary DS40191A-page 51

PIC16CR54C

MPASM provides a rich directive language to support programming of the PICmicro. Directives are helpful in making the development of your assemble source code shorter and more maintainable.

9.11 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PICmicro series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/output radix can be set by the user and the execution can be performed in; single step, execute until break, or in a trace mode.

MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MPASM. The Software Simulator offers the low cost ﬂexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.

9.12 C Compiler (MPLAB-C17)

The MPLAB-C Code Development System is a complete ‘C’ compiler and integrated development environment for Microchip’s PIC17CXXX family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers.

For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display.

9.13 Fuzzy Logic Development System (

fuzzy

TECH-MP)

fuzzy

TECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version,

fuzzy

TECH-MP, Edition for implementing more complex systems.

Both versions include Microchip’s

fuzzy

LAB demonstration board for hands-on experience with fuzzy logic systems implementation.

9.14 MP-DriveWay – Application Code

Generator

MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can visually conﬁgure all the peripherals in a PICmicro device and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Microchip’s MPLAB-C C compiler. The code produced is highly modular and allows easy integration of your

own code. MP-DriveWay is intelligent enough to maintain your code through subsequent code generation.

9.15 SEEVAL Evaluation and Programming System

The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. The Total Endurance Disk is included to aid in trade-off analysis and reliability calculations. The total kit can signiﬁcantly reduce time-to-market and result in an optimized system.

9.16 KEELOQ Evaluation and Programming Tools

KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.

PIC16CR54C

DS40191A-page 52 Preliminary  1998 Microchip Technology Inc.

TABLE 9-1: DEVELOPMENT TOOLS FROM MICROCHIP

PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C75X

24CXX 25CXX 93CXX

HCS200 HCS300 HCS301

EMULATOR PRODUCTS

PICMASTER/ PICMASTER-CE In-Circuit Emulator

ü ü ü ü ü ü ü ü ü ü

ICEPIC Low-Cost In-Circuit Emulator

ü ü ü ü ü ü ü

SOFTWARE PRODUCTS

MPLAB Integrated Development Environment

ü ü ü ü ü ü ü ü ü ü

MPLAB C17 Compiler

ü ü

fuzzy

TECH-MP Explorer/Edition Fuzzy Logic Dev. Tool

ü ü ü ü ü ü ü ü ü

MP-DriveWay Applications Code Generator

ü ü ü ü ü ü ü

Total Endurance Software Model

PROGRAMMERS

PICSTARTPlus Low-Cost Universal Dev. Kit

ü ü ü ü ü ü ü ü ü ü

PRO MATE II Universal Programmer

ü ü ü ü ü ü ü ü ü ü ü ü

KEELOQ Programmer

DEMO BOARDS

SEEVAL Designers Kit

PICDEM-1

ü ü ü ü

PICDEM-2

ü ü

PICDEM-3

KEELOQ Evaluation Kit

 1998 Microchip Technology Inc. Preliminary DS40191A-page 53

PIC16CR54C

10.0 ELECTRICAL CHARACTERISTICS - PIC16CR54C

Absolute Maximum Ratings

†

Ambient temperature under bias............................................................................................................–55°C to +125°C

Storage temperature............................................................................................................................. –65°C to +150°C

Voltage on V

DD with respect to VSS ..................................................................................................................0 to +7.5V

Voltage on MCLR

with respect to VSS................................................................................................................0 to +14V

Voltage on all other pins with respect to V

SS ................................................................................. –0.6V to (VDD + 0.6V)

Total power dissipation

(1)

.....................................................................................................................................800 mW

Max. current out of V

SS pin....................................................................................................................................150 mA

Max. current into V

DD pin ......................................................................................................................................100 mA

Max. current into an input pin (T0CKI only)......................................................................................................................±500 µA

Input clamp current, I

IK (VI < 0 or VI > VDD)....................................................................................................................±20 mA

Output clamp current, I

OK (VO < 0 or VO > VDD)..............................................................................................................±20 mA

Max. output current sunk by any I/O pin..................................................................................................................15 mA

Max. output current sourced by any I/O pin ............................................................................................................15 mA

Max. output current sourced by a single I/O port A ................................................................................................45 mA

Max. output current sourced by a single I/O port B ................................................................................................45 mA

Max. output current sunk by a single I/O port A......................................................................................................45 mA

Max. output current sunk by a single I/O port B .....................................................................................................45 mA

Note 1: Power dissipation is calculated as follows: Pdis = V

DD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL)

†

NOTICE: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

PIC16CR54C

DS40191A-page 54 Preliminary  1998 Microchip Technology Inc.

10.1 DC Characteristics:PIC16CR54C-04, 20 (Commercial) PIC16CR54C-04I, 20I (Industrial)

DC Characteristics Power Supply Pins

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ T

A ≤ +70°C (commercial)

–40°C ≤ T

A ≤ +85°C (industrial)

Characteristic Sym Min Typ

(1)

Max Units Conditions

Supply Voltage

XT, RC and LP options HS option

3.0

4.5

5.5

5.5VV

RAM Data Retention Voltage

(2)

VDR 1.5* V Device in SLEEP mode

DD start voltage to ensure

Power-On Reset

VPOR VSS V See Section 7.4 for details on

Power-on Reset

DD rise rate to ensure

Power-On Reset

SVDD 0.05* V/ms See Section 7.4 for details on

Power-on Reset

Supply Current

(3)

XT and RC

(4)

options HS option LP option, Commercial LP option, Industrial

1.8

4.5 14 17

2.4 16 32 40

mA mA

µA µA

OSC = 4.0 MHz, VDD = 5.5V

OSC = 20 MHz, VDD = 5.5V

OSC = 32 kHz, VDD = 3.0V, WDT disabled

Power Down Current

(5)

Commercial Industrial

4.0

0.25

4.0

0.25

4.0 14

5.0

µA µA µA µA

DD = 3.0V, WDT enabled

DD = 3.0V, WDT disabled

DD = 3.0V, WDT enabled

DD = 3.0V, WDT disabled

* These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is f or design guidance

only and is not tested.

2: This is the limit to which V

DD can be lowered in SLEEP mode without losing RAM data.

3: The supply current is mainly a function of the operating voltage and frequency. Other factors such as bus

loading, oscillator type, bus rate, internal code execution pattern, and temperature also have an impact on the current consumption.

a) The test conditions for all I

DD measurements in active operation mode are:

OSC1 = external square wave, from rail-to-rail; all I/O pins tristated, pulled to V

ss, T0CKI = VDD, MCLR = VDD; WDT enabled/disabled as speciﬁed.

b) For standby current measurements, the conditions are the same, except that

the device is in SLEEP mode.

4: Does not include current through Rext. The current through the resistor can be estimated by the

formula: I

R = VDD/2Rext (mA) with Rext in kΩ.

5: The power down current in SLEEP mode does not depend on the oscillator type. Power down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

DD and VSS.

 1998 Microchip Technology Inc. Preliminary DS40191A-page 55

PIC16CR54C

10.2 DC Characteristics:PIC16CR54C-04, 20, PIC16CR54C-04I, 20I (Commercial, Industrial)

DC Characteristics

All Pins Except

Power Supply Pins

Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ T

A ≤ +70°C (commercial)

–40°C ≤ T

A ≤ +85°C (industrial)

Operating Voltage V

DD range is described in Section 10.1

Characteristic Sym Min Typ

(1)

Max Units Conditions

Input Low Voltage

I/O Ports I/O P

orts MCLR (Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1

VSS VSS VSS VSS VSS

0.8 VDD

0.15 VDD

0.3 VDD

V V V V V

Pin at hi-impedance 4.5V , VDD ≤ 5.5V Pin at hi-impedance 2.5V , VDD ≤ 4.5V

RC option only

(4)

XT, HS and LP options

Input High Voltage

I/O ports MCLR

(Schmitt Trigger) T0CKI (Schmitt Trigger) OSC1 (Schmitt Trigger) OSC1

0.25 VDD+0.8V

2.0

0.85 V

0.85 VDD

0.7 VDD

VDD VDD VDD VDD VDD VDD

V V V V V V

For all V

(5)

4.5V < VDD ≤ 5.5V

(5)

RC option only

(4)

XT, HS and LP options

Hysteresis of Schmitt Trigger inputs

HYS 0.15VDD* V

Input Leakage Current

(3)

I/O ports MCLR T0CKI

OSC1

-1.0

-5.0

-3.0

0.5

+1.0 +5.0

+3.0 +3.0

µA µA

µA µA µA

For V

DD ≤ 5.5V

SS ≤ VPIN ≤ VDD,

Pin at hi-impedance V

PIN = VSS +0.25V

(2)

VPIN = VDD

(2)

VSS ≤ VPIN ≤ VDD VSS ≤ VPIN ≤ VDD, XT, HS and LP options

Output Low Voltage

I/O ports OSC2/CLKOUT

0.6

VVIOL = 5.0 mA, VDD = 4.5V

OL = 1.6 mA, VDD = 4.5V,

RC option only

Output High Voltage

I/O ports

(3)

OSC2/CLKOUT

VDD-0.7 V

DD-0.7

VVI

OH = -3.0 mA, VDD = 4.5V

OH = -1.0 mA, VDD = 4.5V,

RC option only

* These parameters are characterized but not tested. Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is f or design guidance

only and is not tested.

2: The leakage current on the MCLR

/VPP pin is strongly dependent on the applied voltage lev el. The speciﬁed lev-

els represent normal operating conditions. Higher leakage current may be measured at different input voltage. 3: Negative current is deﬁned as coming out of the pin. 4: For the RC option, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PIC16CR54C

be driven with external clock in RC mode. 5: The user may use the better of the two speciﬁcations.

PIC16CR54C

DS40191A-page 56 Preliminary  1998 Microchip Technology Inc.

10.3 Timing Parameter Symbology and Load Conditions

The timing parameter symbols have been created following one of the following formats:

1. TppS2ppS

2. TppS

F Frequency T Time Lowercase subscripts (pp) and their meanings:

2 to mc MCLR ck CLKOUT osc oscillator cy cycle time os OSC1 drt device reset timer t0 T0CKI io I/O port wdt watchdog timer Uppercase letters and their meanings:

F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance

FIGURE 10-1: LOAD CONDITIONS - PIC16CR54C

VSS

CL = 50 pF for all pins except OSC2

15 pF for OSC2 in XT, HS or LP

options when external clock is used to drive OSC1

 1998 Microchip Technology Inc. Preliminary DS40191A-page 57

PIC16CR54C

10.4 Timing Diagrams and Speciﬁcations FIGURE 10-2: EXTERNAL CLOCK TIMING - PIC16CR54C

TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54C

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ T

A ≤ +70°C (commercial)

–40°C ≤ T

A ≤ +85°C (industrial)

Operating Voltage V

DD range is described in Section 10.1

Parameter

No. Sym Characteristic Min Typ

(1)

Max Units Conditions

FOSC External CLKIN Frequency

(2)

DC — 4.0 MHz XT osc mode DC — 4.0 MHz HS osc mode (04) DC — 20 MHz HS osc mode (20) DC — 200 kHz LP osc mode

Oscillator Frequency

(2)

DC — 4.0 MHz RC osc mode

0.455 — 4.0 MHz XT osc mode 4 — 4.0 MHz HS osc mode (04) 4 — 20 MHz HS osc mode (20) 5 — 200 kHz LP osc mode

1 TOSC External CLKIN Period

(2)

250 — — ns XT osc mode 250 — — ns HS osc mode (04)

50 — — ns HS osc mode (20)

5.0 — — µs LP osc mode

Oscillator Period

(2)

250 — — ns RC osc mode 250 — 2,200 ns XT osc mode 250 — 250 ns HS osc mode (04)

50 — 250 ns HS osc mode (20)

5.0 — 200 µs LP osc mode

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25

°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

2: All speciﬁed values are based on characterization data for that particular oscillator type under standard operating condi-

tions with the device ex ecuting code. Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices.

3: Instruction cycle period (T

CY) equals four times the input oscillator time base period.

OSC1

CLKOUT

Q1 Q2

Q3 Q4 Q1

1 3 3

4 4

PIC16CR54C

DS40191A-page 58 Preliminary  1998 Microchip Technology Inc.

2 TCY Instruction Cycle Time

(3)

— 4/FOSC — —

3 TosL, TosH Clock in (OSC1) Low or High Time 50* — — ns XT oscillator

20* — — ns HS oscillator

2.0* — — µs LP oscillator

4 TosR, TosF Clock in (OSC1) Rise or Fall Time — — 25* ns XT oscillator

— — 25* ns HS oscillator — — 50* ns LP oscillator

TABLE 10-1: EXTERNAL CLOCK TIMING REQUIREMENTS - PIC16CR54C (CONTINUED)

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ T

A ≤ +70°C (commercial)

–40°C ≤ T

A ≤ +85°C (industrial)

Operating Voltage V

DD range is described in Section 10.1

Parameter

No. Sym Characteristic Min Typ

(1)

Max Units Conditions

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25

°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

2: All speciﬁed values are based on characterization data for that particular oscillator type under standard operating condi-

3: Instruction cycle period (T

CY) equals four times the input oscillator time base period.

 1998 Microchip Technology Inc. Preliminary DS40191A-page 59

PIC16CR54C

FIGURE 10-3: CLKOUT AND I/O TIMING - PIC16CR54C

TABLE 10-2: CLKOUT AND I/O TIMING REQUIREMENTS - PIC16CR54C

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ T

A ≤ +70°C (commercial)

–40°C ≤ T

A ≤ +85°C (industrial)

Operating Voltage V

DD range is described in Section 10.1

Parameter

No. Sym Characteristic Min Typ

(1)

Max Units

10 TosH2ckL OSC1↑ to CLKOUT↓

(2)

— 15 30** ns

11 TosH2ckH OSC1↑ to CLKOUT↑

(2)

— 15 30** ns

12 TckR CLKOUT rise time

(2)

— 5.0 15** ns

13 TckF CLKOUT fall time

(2)

— 5.0 15** ns

14 TckL2ioV CLKOUT↓ to Port out valid

(2)

— — 40** ns

15 TioV2ckH Port in valid before CLKOUT↑

(2)

0.25 TCY+30* — — ns

16 TckH2ioI Port in hold after CLKOUT↑

(2)

0* — — ns

17 TosH2ioV OSC1↑ (Q1 cycle) to Port out valid

(3)

— — 100* ns

18 TosH2ioI OSC1↑ (Q2 cycle) to Port input invalid

(I/O in hold time)

TBD — — ns

19 TioV2osH Port input valid to OSC1↑

(I/O in setup time)

TBD — — ns

20 TioR Port output rise time

(3)

— 10 25** ns

21 TioF Port output fall time

(3)

— 10 25** ns

* These parameters are characterized but not tested. ** These parameters are design targets and are not tested. No characterization data available at this time.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25

°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

2: Measurements are taken in RC Mode where CLKOUT output is 4 x T

OSC.

3: See Figure 10-1 for loading conditions.

OSC1

CLKOUT

I/O Pin (input)

I/O Pin (output)

Q2 Q3

20, 21

Old Value

New Value

Note: All tests must be done with speciﬁed capacitive loads (see data sheet) 50 pF on I/O pins and CLKOUT.

PIC16CR54C

DS40191A-page 60 Preliminary  1998 Microchip Technology Inc.

FIGURE 10-4: RESET, WATCHDOG TIMER, AND

DEVICE RESET TIMER TIMING - PIC16CR54C

TABLE 10-3: RESET, WATCHDOG TIMER, AND DEVICE RESET TIMER - PIC16CR54C

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ T

A ≤ +70°C (commercial)

–40°C ≤ T

A ≤ +85°C (industrial)

Operating Voltage V

DD range is described in Section 10.1

Parameter

No. Sym Characteristic Min Typ

(1)

Max Units Conditions

TmcL MCLR Pulse Width (low) 1000* — — ns VDD = 5.0V

Twdt Watchdog Timer Time-out Period

(No Prescaler)

9.0* 18* 30* ms VDD = 5.0V (Commercial)

TDRT Device Reset Timer Period 9.0* 18* 30* ms VDD = 5.0V (Commercial)

TioZ I/O Hi-impedance from MCLR Low 100* 300* 1000* ns

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design

guidance only and are not tested.

VDD

MCLR

Internal

POR

DRT

Time-out

Internal

RESET

Watchdog

Timer

RESET

I/O pin

(Note 1)

Note 1: I/O pins must be taken out of hi-impedance mode by enabling the output drivers in software.

 1998 Microchip Technology Inc. Preliminary DS40191A-page 61

PIC16CR54C

FIGURE 10-5: TIMER0 CLOCK TIMINGS - PIC16CR54C

TABLE 10-4: TIMER0 CLOCK REQUIREMENTS - PIC16CR54C

AC Characteristics Standard Operating Conditions (unless otherwise speciﬁed)

Operating Temperature 0°C ≤ T

A ≤ +70°C (commercial)

–40°C ≤ T

A ≤ +85°C (industrial)

Operating Voltage V

DD range is described in Section 10.1

Parameter

No.

Sym Characteristic Min Typ

(1)

Max Units Conditions

40 Tt0H T0CKI High Pulse Width - No Prescaler 0.5 TCY + 20* — — ns

- With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pulse Width - No Prescaler 0.5 TCY + 20* — — ns

- With Prescaler 10* — — ns

42 Tt0P T0CKI Period 20 or TCY + 40*

— — ns Whichever is greater.

N = Prescale Value

(1, 2, 4,..., 256)

* These parameters are characterized but not tested.

Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

T0CKI

40 41

PIC16CR54C

DS40191A-page 62 Preliminary  1998 Microchip Technology Inc.

NOTES:

 1998 Microchip Technology Inc. Preliminary DS40191A-page 63

PIC16CR54C PIC16CR54C

11.0 DC AND AC CHARACTERISTICS - PIC16CR54C

The graphs and tables provided in this section are for design guidance and are not tested or guaranteed. In some graphs or tables the data presented are outside speciﬁed operating range (e.g., outside speciﬁed V

DD range). This is

for information only and devices will operate properly only within the speciﬁed range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of

time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and (mean – 3σ) respectively, where σ is standard deviation.

FIGURE 11-1: TYPICAL RC OSCILLATOR FREQUENCY vs. TEMPERATURE

TABLE 11-1: RC OSCILLATOR FREQUENCIES

Cext Rext

Average

Fosc @ 5 V, 25°C

20 pF 3.3 k 4.973 MHz ± 27%

5 k 3.82 MHz ± 21%

10 k 2.22 MHz ± 21%

100 k 262.15 kHz ± 31%

100 pF 3.3 k 1.63 MHz ± 13%

5 k 1.19 MHz ± 13%

10 k 684.64 kHz ± 18%

100 k 71.56 kHz ± 25%

300 pF 3.3 k 660 kHz ± 10%

5.0 k 484.1 kHz ± 14% 10 k 267.63 kHz ± 15%

160 k 29.44 kHz ± 19%

The frequencies are measured on DIP packages. The percentage variation indicated here is part-to-part variation due to normal process distribution. The variation

indicated is ±3 standard deviation from average value for V

DD = 5 V.

FOSC

FOSC (25°C)

1.10

1.08

1.06

1.04

1.02

1.00

0.98

0.96

0.94

0.92

0.90

0 10 20 25 30 40 50 60 70

T(°C)

Frequency normalized to +25°C

VDD = 5.5 V

VDD = 3.5 V

Rext ≥ 10 kΩ Cext = 100 pF

0.88

PIC16CR54C PIC16CR54C

DS40191A-page 64 Preliminary  1998 Microchip Technology Inc.

FIGURE 11-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 20 PF

FIGURE 11-3: TYPICAL RC OSCILLATOR FREQUENCY vs. V

DD, CEXT = 100 PF

0.00

1.00

2.00

3.00

4.00

5.00

6.00

2.5 3 3.5 4 4.5 5 5.5 6

VDD(Volts)

Fosc(MHz)

R=3.3K

R=5.0K

R=10K

R=100K

Cext=20pF, T=25C

0.00

0.20

0.40

0.60

0.80

1.00

1.20

1.40

1.60

1.80

2.5 3 3.5 4 4.5 5 5.5 6

VDD(Volts)

Fosc(MHz)

R=3.3K

R=5.0K

R=10K

R=100K

Cext=100pF, T=25C

 1998 Microchip Technology Inc. Preliminary DS40191A-page 65

PIC16CR54C PIC16CR54C

FIGURE 11-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD, CEXT = 300 PF

FIGURE 11-5: TYPICAL IPD vs. VDD, WATCHDOG DISABLED (25°C)

0.00

100.00

200.00

300.00

400.00

500.00

600.00

700.00

2.5 3 3.5 4 4.5 5 5.5 6

VDD(Volts)

Fosc(KHz)

R=3.3K

R=5.0K

R=10K

R=100K

Cext=300pF, T=25C

0.5

1.5

2.5

2.5 3 3.5 4 4.5 5 5.5 6

VDD(Volts)

Ipd(nA)

Ipd(µA)

PIC16CR54C PIC16CR54C

DS40191A-page 66 Preliminary  1998 Microchip Technology Inc.

FIGURE 11-6: TYPICAL IPD vs. VDD, WATCHDOG ENABLED (25°C)

FIGURE 11-7: TYPICAL I

PD vs. VDD, WATCHDOG ENABLED (–40°C, 85°C)

VDD (Volts)

IPD (uA)

2.5 3 3.5

4.5

5.5

5 6

VDD (Volts)

IPD (uA)

2.5 3 3.5

4.5

5.5

5 6

(-40°C)

(+85°C)

 1998 Microchip Technology Inc. Preliminary DS40191A-page 67

PIC16CR54C PIC16CR54C

FIGURE 11-8: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF I/O PINS vs. VDD

FIGURE 11-9: VIH, VIL OF MCLR, T0CKI AND OSC1 (IN RC MODE) vs. VDD

2.00

1.80

1.60

1.40

1.20

1.00

2.5 3.0 3.5 4.0 4.5 5.0 V

DD (Volts)

0.80

0.60

5.5 6.0

Typ (+25°C)

VTH (Volts)

3.5

3.0

2.5

2.0

1.5

1.0

2.5 3.0 3.5 4.0 4.5 5.0

DD (Volts)

0.5

0.0

5.5 6.0

VIH, VIL (Volts)

4.0

4.5

min (–40°C to +85°C)

max (–40°C to +85°C)

typ +25°C

min (–40°C to +85°C)

max (–40°C to +85°C)

typ +25°C

Note: These input pins have Schmitt Trigger input buffers.

PIC16CR54C PIC16CR54C

DS40191A-page 68 Preliminary  1998 Microchip Technology Inc.

FIGURE 11-10: VTH (INPUT THRESHOLD TRIP POINT VOLTAGE) OF OSC1 INPUT

(IN XT, HS, AND LP MODES) vs. VDD

FIGURE 11-11: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 20 PF, 25°C)

2.4

2.2

2.0

1.8

1.6

1.4

2.5 3.0 3.5 4.0 4.5 5.0 V

DD (Volts)

1.2

1.0

5.5 6.0

Typ (+25°C)

VTH (Volts)

2.6

2.8

3.0

3.2

3.4

100

1000

10000

100000 1000000 10000000

Freq(Hz)

Idd(uA)

2.5V

3.5V

4.5V

5.5V

 1998 Microchip Technology Inc. Preliminary DS40191A-page 69

PIC16CR54C PIC16CR54C

FIGURE 11-12: TYPICAL IDD vs. FREQUENCY (WDT DIS, RC MODE @ 100 PF, 25°C)

FIGURE 11-13: TYPICAL I

DD vs. FREQUENCY (WDT DIS, RC MODE @ 300 PF, 25°C)

100

1000

10000

10000 100000 1000000 10000000

Freq(Hz)

Idd(uA)

2.5V

3.5V

4.5V

5.5V

100

1000

10000

10000 100000 1000000

Freq(Hz)

Idd(uA)

2.5V

3.5V

4.5V

5.5V

PIC16CR54C PIC16CR54C

DS40191A-page 70 Preliminary  1998 Microchip Technology Inc.

FIGURE 11-14: WDT TIMER TIME-OUT

PERIOD vs. VDD

2 3 4 5 6 7

DD (Volts)

WDT period (ms)

Typ +125°C

Typ +85°C

Typ +25°C

Typ –40°C

 1998 Microchip Technology Inc. Preliminary DS40191A-page 71

PIC16CR54C PIC16CR54C

FIGURE 11-15: IOH vs. VOH, VDD = 3 V

FIGURE 11-16: IOH vs. VOH, VDD = 5 V

–5

–10

–15

–20

–25

0 0.5 1.0 1.5 2.0 2.5

OH (Volts)

IOH (mA)

Min +85°C

3.0

Typ +25°C

Max –40°C

–10

–20

–30

–40

1.5 2.0 2.5 3.0 3.5 4.0 V

OH (Volts)

IOH (mA)

Typ –40°C

4.5 5.0

Typ +85°C

Typ +125°C

Typ +25°C

FIGURE 11-17: IOL vs. VOL, VDD = 3 V

FIGURE 11-18: IOL vs. VOL, VDD = 5 V

0.0 0.5 1.0 1.5 2.0 2.5 V

OL (Volts)

IOL (mA)

Min +85°C

Max –40°C

Typ +25°C

3.0

0.0 0.5 1.0 1.5 2.0 2.5 V

OL (Volts)

IOL (mA)

Min +85°C

Max –40°C

Typ +25°C

3.0

PIC16CR54C PIC16CR54C

DS40191A-page 72 Preliminary  1998 Microchip Technology Inc.

NOTES:

 1998 Microchip Technology Inc. Preliminary DS40191A-page 73

PIC16CR54C

12.0 PACKAGING INFORMATION

12.1 Package Marking Information

MMMMMMMMMMMMXXX MMMMMMMMXXXXXXX

AABB CDE

18-Lead PDIP

PIC16CR54C04/P123

9813 HBA

Example

Legend: MM...M Microchip part number information

XX...X Customer speciﬁc information* AA Year code (last 2 digits of calendar year) BB Week code (week of January 1 is week ‘01’) C Facility code of the plant at which wafer is manufactured

O = Outside Vendor C = 5” Line S = 6” Line

H = 8” Line D Mask revision number E Assembly code of the plant or country of origin in which

part was assembled

* Standard ROM marking consists of Microchip part number, year code, week

code, facility code, mask rev#, and assembly code. For ROM marking beyond this, certain price adders apply. Please check with your Microchip Sales Ofﬁce.

Note: In the e v ent the full Microchip part number cannot be marked on one line,

it will be carried over to the next line thus limiting the number of available characters for customer speciﬁc information.

18-Lead SOIC

MMMMMMMMM

AABB CDE

XXXXXXXXX

20-Lead SSOP

XXXXXXXX

AABB CDE

MMMMMMMM

Example

PIC16CR54C-

9810 HDK

04I/S0218

Example

04I/218

9810 HBP

PIC16CR54C

DS40191A-page 74 Preliminary  1998 Microchip Technology Inc.

Package Type: K04-007 18-Lead Plastic Dual In-line (P) – 300 mil

* Controlling Parameter.

†

Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.”

‡

Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX PCB Row Spacing 0.300 7.62 Number of Pins n 18 18 Pitch p 0.100 2.54 Lower Lead Width B 0.013 0.018 0.023 0.33 0.46 0.58 Upper Lead Width B1

†

0.055 0.060 0.065 1.40 1.52 1.65 Shoulder Radius R 0.000 0.005 0.010 0.00 0.13 0.25 Lead Thickness c 0.005 0.010 0.015 0.13 0.25 0.38 Top to Seating Plane A 0.110 0.155 0.155 2.79 3.94 3.94 Top of Lead to Seating Plane A1 0.075 0.095 0.115 1.91 2.41 2.92 Base to Seating Plane A2 0.000 0.020 0.020 0.00 0.51 0.51 Tip to Seating Plane L 0.125 0.130 0.135 3.18 3.30 3.43 Package Length D

‡

0.890 0.895 0.900 22.61 22.73 22.86 Molded Package Width E

‡

0.245 0.255 0.265 6.22 6.48 6.73 Radius to Radius Width E1 0.230 0.250 0.270 5.84 6.35 6.86 Overall Row Spacing eB 0.310 0.349 0.387 7.87 8.85 9.83 Mold Draft Angle Top

5 10 15 5 10 15

Mold Draft Angle Bottom

5 10 15 5 10 15

2 1

 1998 Microchip Technology Inc. Preliminary DS40191A-page 75

PIC16CR54C

Package Type: K04-051 18-Lead Plastic Small Outline (SO) – Wide, 300 mil

0.014

0.009

0.010

0.011

0.005

0.010

0.394

0.292

0.450

0.004

0.048

0.093

MIN

nNumber of Pins

Mold Draft Angle Bottom

Mold Draft Angle Top

Lower Lead Width

Chamfer Distance

Outside Dimension

Molded Package Width

Molded Package Length

Overall Pack. Height

Lead Thickness

Radius Centerline

Foot Angle

Foot Length

Gull Wing Radius

Shoulder Radius

Standoff

Shoulder Height

†

‡

Dimension Limits Pitch

Units

1818

0.020

0.017

0.011

0.015

0.016

0.005

0.407

0.296

0.456

0.008

0.058

0.099

0.029

0.019

0.012

0.020

0.021

0.010

0.419

0.299

0.462

0.011

0.068

0.104

0.42

0.27

0.38

0.41

0.13

0.50

10.33

7.51

11.58

0.19

1.47

2.50

0.25

0.36

0.23

0.25

0.28

0.13

10.01

7.42

11.43

0.10

1.22

2.36

0.74

4 8

0.48

0.30

0.51

0.53

0.25

10.64

7.59

11.73

0.28

1.73

2.64

INCHES*

0.050

NOM MAX

1.27

MILLIMETERS

MIN NOM MAX

2 1

Controlling Parameter.

†

Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”

‡

Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

PIC16CR54C

DS40191A-page 76 Preliminary  1998 Microchip Technology Inc.

Package Type: K04-072 20-Lead Plastic Shrink Small Outine (SS) – 5.30 mm

MIN

pPitch

Mold Draft Angle Bottom

Mold Draft Angle Top

Lower Lead Width

Radius Centerline

Gull Wing Radius

Shoulder Radius

Outside Dimension

Molded Package Width

Molded Package Length

Shoulder Height

Overall Pack. Height

Lead Thickness

Foot Angle

Foot Length

Standoff

Number of Pins

†

R2 L

‡

Dimension Limits

Units

0.650.026

0 0

5 5 10

0.012

0.007

0.005

0.020

0.005

0.306

0.208

0.283

0.005

0.036

0.073

0.301

0.010

0.005

0.000

0.015

0.005

0.205

0.278

0.002

0.026

0.068

0.311

0.015

0.009

0.010

0.025

0.010

4 8

0.212

0.289

0.008

0.046

0.078

0 0 5

5 10

7.65

0.25

0.13

0.00

0.38

0.13

5.20

7.07

0.05

0.66

1.73

7.907.78

0.32

0.18

0.13

0.51

0.13

0.38

0.22

0.25

0.64

0.25

5.29

7.20

0.13

1.86

0.91

5.38

7.33

0.21

1.99

1.17

NOM

INCHES

MAX NOM

MILLIMETERS*

MIN MAX

Controlling Parameter.

†

Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003”

(0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.”

‡

Dimensions “D” and “E” do not include mold ﬂash or protrusions. Mold ﬂash or protrusions shall not

exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.”

 1998 Microchip Technology Inc. Preliminary DS40191A-page 77

PIC16CR54C

APPENDIX A: COMPATIBILITY

To convert code written for PIC16CXX to PIC16C5X, the user should take the following steps:

1. Check any CALL, GOTO or instructions that modify the PC to determine if any program memory page select operations (PA2, PA1, PA0 bits) need to be made.

2. Revisit any computed jump operations (write to PC or add to PC, etc.) to make sure page bits are set properly under the new scheme.

3. Eliminate any special function register page switching. Redeﬁne data variables to reallocate them.

4. Verify all writes to STATUS, OPTION, and FSR registers since these have changed.

5. Change reset vector to proper value for processor used.

6. Remove any use of the ADDLW and SUBLW instructions.

7. Rewrite any code segments that use interrupts.

PIC16CR54C

DS40191A-page 78 Preliminary  1998 Microchip Technology Inc.

NOTES:

 1998 Microchip Technology Inc. DS40191A-page 79

PIC16CR54C

INDEX A

Absolute Maximum Ratings ...............................................53

ALU ...................................................................................... 9

Applications .......................................................................... 5

Architectural Overview ......................................................... 9

Assembler

MPASM Assembler ............................................................50

Block Diagram

On-Chip Reset Circuit ........................................................ 29

PIC16CR54C Series Block Diagram .................................. 10

Timer0 ................................................................................21

TMR0/WDT Prescaler ........................................................24

Watchdog Timer ................................................................. 33

Brown-Out Protection Circuit ............................................. 34

Carry bit ............................................................................... 9

Clocking Scheme ............................................................... 12

Code Protection ...........................................................25, 35

Configuration Bits ............................................................... 25

Configuration Word ............................................................ 25

PIC16CR54C .....................................................................25

DC and AC Characteristics - PIC16CR54C ....................... 63

DC Characteristics ............................................................. 54

Development Support ........................................................49

Development Tools ............................................................ 49

Device Varieties ................................................................... 7

Digit Carry bit .......................................................................9

Electrical Characteristics

PIC16CR54C .....................................................................53

External Power-On Reset Circuit ....................................... 30

Family of Devices

PIC16C5X ............................................................................ 6

Features ...............................................................................1

FSR ....................................................................................29

FSR Register ..................................................................... 18

Fuzzy Logic Dev. System (

fuzzy

TECH-MP) ................... 51

I/O Interfacing .................................................................... 19

I/O Ports .............................................................................19

I/O Programming Considerations ....................................... 20

ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ...........49

INDF ................................................................................... 29

INDF Register ....................................................................18

Indirect Data Addressing .................................................... 18

Instruction Cycle ................................................................ 12

Instruction Flow/Pipelining .................................................12

Instruction Set Summary .................................................... 37

KeeLoq Evaluation and Programming Tools ...................51

Loading of PC ....................................................................17

MCLR ................................................................................ 29

Memory Map ...................................................................... 13

PIC16C54s/CR54s/C55s ................................................... 13

Memory Organization ........................................................ 13

Data Memory ..................................................................... 13

Program Memory ............................................................... 13

MP-DriveWay™ - Application Code Generator ................. 51

MPLAB C ........................................................................... 51

MPLAB Integrated Development Environment Software ... 50

One-Time-Programmable (OTP) Devices ............................7

OPTION Register .............................................................. 16

OSC selection .................................................................... 25

Oscillator Configurations ................................................... 26

Oscillator Types

HS ...................................................................................... 26

LP ...................................................................................... 26

RC ..................................................................................... 26

XT ...................................................................................... 26

Package Marking Information ............................................ 73

Packaging Information ....................................................... 73

PC ................................................................................ 17, 29

PIC16CR54C Product Identification System ..................... 83

PICDEM-1 Low-Cost PICmicro Demo Board .................... 49

PICDEM-2 Low-Cost PIC16CXX Demo Board .................. 50

PICDEM-3 Low-Cost PIC16CXXX Demo Board ............... 50

PICMASTER In-Circuit Emulator .................................... 49

PICSTART Plus Entry Level Development System ........ 49

Pin Configurations ................................................................1

Pinout Description - PIC16CR54C .................................... 11

POR

Device Reset Timer (DRT) .......................................... 25, 32

................................................................................ 28, 34

Power-On Reset (POR) ......................................... 25, 29, 30

TO ................................................................................ 28, 34

PORTA ........................................................................ 19, 29

PORTB ........................................................................ 19, 29

Power-Down Mode ............................................................ 35

Prescaler ........................................................................... 24

PRO MATE II Universal Programmer ............................. 49

Program Counter ............................................................... 17

Q cycles ............................................................................. 12

Quick-Turnaround-Production (QTP) Devices ......................7

RC Oscillator ..................................................................... 27

Read Only Memory (ROM) Devices .....................................7

Read-Modify-Write ............................................................. 20

Registers

Special Function ................................................................ 13

Reset ........................................................................... 25, 28

Reset on Brown-Out .......................................................... 34

SEEVAL Evaluation and Programming System ............. 51

Serialized Quick-Turnaround-Production (SQTP) Devices ..7

SLEEP ......................................................................... 25, 35

Software Simulator (MPLAB-SIM) ..................................... 51

Special Features of the CPU ............................................. 25

PIC16CR54C

DS40191A-page 80  1998 Microchip Technology Inc.

Special Function Registers ................................................13

Stack ..................................................................................17

STATUS .............................................................................29

STATUS Register ...........................................................9, 15

Timer0

Switching Prescaler Assignment ........................................ 24

Timer0 (TMR0) Module ......................................................21

TMR0 with External Clock .................................................. 23

Timing Diagrams and Specifications .................................. 57

Timing Parameter Symbology and Load Conditions ..........56

TRIS Registers ................................................................... 19

UV Erasable Devices ........................................................... 7

W ........................................................................................ 29

Wake-up from SLEEP ........................................................35

Watchdog Timer (WDT) ...............................................25, 32

Period ................................................................................. 32

Programming Considerations .............................................32

Zero bit .................................................................................9

 1998 Microchip Technology Inc. DS40191A-page 81

PIC16CR54C

Systems Information and Upgrade Hot Line

The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are:

1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world.

Trademarks: The Microchip name, logo , PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. PICmicro,

Flex

ROM, MPLAB and

fuzzy-

LAB are trademarks and SQTP is a service mark of Microchip in the U.S.A.

fuzzy

TECH is a registered trademark of Inform Software Corporation. IBM, IBM PC-AT are registered trademarks of International Business Machines Corp. Pentium is a trademark of Intel Corporation. Windows is a trademark and MS-DOS, Microsoft Windows are registered trademarks of Microsoft Corporation. CompuServe is a registered trademark of CompuServe Incorporated.

All other trademarks mentioned herein are the property of their respective companies.

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip World Wide Web (WWW) site.

The web site is used by Microchip as a means to make ﬁles and information easily available to customers. To view the site, the user must hav e access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.

Connecting to the Microchip Internet Web Site

The Microchip web site is available by using your favorite Internet browser to attach to:

www.microchip.com

The ﬁle transfer site is available by using an FTP service to connect to:

ftp://ftp.futureone.com/pub/microchip

The web site and ﬁle transfer site provide a v ariety of services. Users may download ﬁles for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip speciﬁc business information is also available, including listings of Microchip sales ofﬁces, distributors and factory representatives. Other data available for consideration is:

• Latest Microchip Press Releases

• Technical Support Section with Frequently Asked Questions

• Design Tips

• Device Errata

• Job Postings

• Microchip Consultant Program Member Listing

• Links to other useful web sites related to Microchip Products

• Conferences for products , Dev elopment Systems, technical information and more

• Listing of seminars and events

980106

PIC16CR54C

DS40191A-page 82  1998 Microchip Technology Inc.

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of y our Microchip product. If y ou wish to provide your comments on organization, clarity, subject matter , and wa ys in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578.

Please list the following information, and use this outline to provide us with your comments about this Data Sheet.

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you ﬁnd the organization of this data sheet easy to follow? If not, why?

4. What additions to the data sheet do you think would enhance the structure and subject?

5. What deletions from the data sheet could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

8. How would you improve our software, systems, and silicon products?

To:

Technical Publications Manager

RE: Reader Response

Total Pages Sent

From:

Name Company

Address City / State / ZIP / Country

Telephone: (_______) _________ - _________

Application (optional): Would you like a reply? Y N

Device:

Literature Number:

Questions:

FAX: (______) _________ - _________

DS40191A

PIC16CR54C

 1998 Microchip Technology Inc. Preliminary DS40191A-page 83

PIC16CR54C

PIC16CR54C PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales ofﬁce.

ART NO. -XX

X /XX XXX

PatternPackageTemperature

Range

Frequency

Range

Device

Device PIC16CR54C

(2)

, PIC16CR54CT

(3)

Frequency Range

04 20 C

= 4 MHz = 20 MHz

Temperature Range

(1)

= 0°C to +70°C (Commercial) = -40°C to +85°C (Industrial)

Package P

SO SS

= PDIP = SOIC (Gull Wing, 300 mil body) = SSOP (209 mil body)

Pattern 3-digit Pattern Code for ROM (blank otherwise)

Examples:

a) PIC16CR54C -04/P 301 = Commercial

temp., PDIP package, 4MHz, normal VDD limitis, pattern #301.

b) PIC16CR54C - 20I/P355 = ROM pro-

gram memory, Industrial temp., PDIP package, 20MHz, normal VDD limits.

Note 1: b = blank

2: CR = ROM Version, Standard VDD

range

3: T = in tape and reel - SOIC, SSOP

packages only.

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS40191A-page 84  1998 Microchip Technology Inc.

AMERICAS

Corporate Ofﬁce

Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277

Technical Support:

602 786-7627

Web:

http://www.microchip.com

Atlanta

Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307

Boston

Microchip Technology Inc. 5 Mount Royal Avenue Marlborough, MA 01752 Tel: 508-480-9990 Fax: 508-480-8575

Chicago

Microchip Technology Inc. 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075

Dallas

Microchip Technology Inc. 14651 Dallas Parkway, Suite 816 Dallas, TX 75240-8809 Tel: 972-991-7177 Fax: 972-991-8588

Dayton

Microchip Technology Inc. Two Prestige Place, Suite 150 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175

Los Angeles

Microchip Technology Inc. 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 714-263-1888 Fax: 714-263-1338

New York

Microchip Technology Inc. 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 516-273-5305 Fax: 516-273-5335

San Jose

Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955

Toronto

Microchip Technology Inc. 5925 Airport Road, Suite 200 Mississauga, Ontario L4V 1W1, Canada Tel: 905-405-6279 Fax: 905-405-6253

ASIA/PACIFIC

Hong Kong

Microchip Asia Paciﬁc RM 3801B, Tower Two Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2-401-1200 Fax: 852-2-401-3431

India

Microchip Technology Inc. India Liaison Ofﬁce No. 6, Legacy, Convent Road Bangalore 560 025, India Tel: 91-80-229-0061 Fax: 91-80-229-0062

Japan

Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa 222-0033 Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122

Korea

Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934

Shanghai

Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan’an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060

Singapore

Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore 188980 Tel: 65-334-8870 Fax: 65-334-8850

ASIA/PACIFIC (continued)

Taiwan, R.O.C

Microchip Technology Taiwan 10F-1C 207 Tung Hua North Road Taipei, Taiwan, ROC Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPE

United Kingdom

Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44-1189-21-5858 Fax: 44-1189-21-5835

France

Arizona Microchip Technology SARL Zone Industrielle de la Bonde 2 Rue du Buisson aux Fraises 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany

Arizona Microchip Technology GmbH Gustav-Heinemann-Ring 125 D-81739 Müchen, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

Italy

Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-39-6899939 Fax: 39-39-6899883

4/3/98

WORLDWIDE SALES AND SERVICE

Microchip received ISO 9001 Quality System certiﬁcation for its worldwide headquarters, design, and wafer fabrication facilities in January , 1997. Our ﬁeld-programmable PICmicro™ 8-bit MCUs, Serial EEPROMs, related specialty memory products and development systems conform to the stringent quality standards of the International Standard Organization (ISO).

Microchip Technology Inc PIC16CR54C-04-P, PIC16CR54C-04-SO, PIC16CR54C-04-SS, PIC16CR54C-04I-P, PIC16CR54C-04I-SO Datasheet

Specifications and Main Features

Frequently Asked Questions

User Manual