Microchip Technology Inc PIC16CE623-04-JW, PIC16CE623-04-P, PIC16CE623-04-SS, PIC16CE623-04E-JW, PIC16CE623-04E-P Datasheet
...
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 1
Devices included in this data sheet:
• PIC16CE623
• PIC16CE624
• PIC16CE625
High Performance RISC CPU:
• Only 35 instructions to learn
• All single-cycle instructions (200 ns), except for
program branches which are two-cycle
• Operating speed:
- DC - 20 MHz clock input
- DC - 200 ns instruction cycle
• Interrupt capability
• 16 special function hardware registers
• 8-level deep hardware stack
• Direct, Indirect and Relative addressing modes
Peripheral Features:
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Analog comparator module with:
- Two analog comparators
- Programmable on-chip voltage reference
(V
REF
) module
- Programmable input multiplexing from de vice
inputs and internal voltage reference
- Comparator outputs can be output signals
• Timer0: 8-bit timer/counter with 8-bit
programmable prescaler
Special Microcontroller Features:
• In-Circuit Serial Programming (ICSP™) (via two
pins)
• Power-on Reset (POR)
• Power-up Timer (PWRT) and Oscillator Start-up
Timer (OST)
• Brown-out Reset
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
Device Program
Memory
RAM
Data
Memory
EEPROM
Data
Memory
PIC16CE623 512x14 96x8 128x8
PIC16CE624 1Kx14 96x8 128x8
PIC16CE625 2Kx14 128x8 128x8
Pin Diagrams
Special Microcontroller Features (cont’d)
• 1,000,000 erase/write cycle EEPROM data memory
• EEPROM data retention > 40 years
• Programmable code protection
• Power saving SLEEP mode
• Selectable oscillator options
• Four user programmable ID locations
CMOS Tec hnology:
• Low-power, high-speed CMOS EPROM/EEPROM
technology
• Fully static design
• Wide operating voltage range
- 3.0V to 5.5V
• Commercial, industrial and extended temperature range
• Low power consumption
- < 2.0 mA @ 5.0V, 4.0 MHz
- 15 µA typical @ 3.0V, 32 kHz
- < 1.0 µA typical standby current @ 3.0V
RA1/AN1
RA0/AN0
OSC2/CLKOUT
V
DD
RB7
RB6
RB5
RB4
OSC1/CLKIN
RA2/AN2/V
REF
RA3/AN3
MCLR
VSS
RB0/INT
RB1
RB2
RB3
RA4/T0CKI
PIC16CE62X
RA1/AN1
RA0/AN0
OSC2/CLKOUT
V
DD
RB7
RB6
RB5
RB4
OSC1/CLKIN
RA2/AN2/V
REF
RA3/AN3
MCLR
VSS
VSS
RB0/INT
RB1
RB2
RA4/T0CKI
PIC16CE62X
RB3RB3
V
DD
PDIP, SOIC, Windowed CERDIP
SSOP
2
3
4
5
6
7
8
9
10
•1
2
3
4
5
6
7
8
9
•1
19
18
16
15
14
13
12
11
17
18
17
15
14
13
12
11
10
16
20
OTP 8-Bit CMOS MCU with EEPROM Data Memory
PIC16CE62X
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PIC16CE62X
DS40182A-page 2
Preliminary
1998 Microchip Technology Inc.
Table of Contents
1.0 General Description..................................................................................................................................................................... 3
2.0 PIC16CE62X Device Varieties.................................................................................................................................................... 5
3.0 Architectural Overview ................................................................................................................................................................ 7
4.0 Memory Organization................................................................................................................................................................ 11
5.0 I/O Ports .................................................................................................................................................................................... 23
6.0 EEPROM Peripheral Operation................................................................................................................................................. 29
7.0 Timer0 Module .......................................................................................................................................................................... 35
8.0 Comparator Module................................................................................................................................................................... 41
9.0 Voltage Reference Module........................................................................................................................................................47
10.0 Special Features of the CPU.....................................................................................................................................................49
11.0 Instruction Set Summary........................................................................................................................................................... 65
12.0 Development Support................................................................................................................................................................ 77
13.0 Electrical Specifications............................................................................................................................................................. 81
14.0 Packaging Information............................................................................................................................................................... 93
Appendix A: Code for Accessing EEPROM Data Memory ............................................................................................................. 99
Index ..................................................................................................................................................................................................101
PIC16CE62X Product Identification System...................................................................................................................................... 105
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. To this end, we recently converted to a new publishing software package which we believe will enhance our entire documentation process and
product. As in any conversion process, information may have accidently been altered or deleted. We have spent an
exceptional amount of time to ensure that these documents are correct. However, we realize that we may have
missed a few things. If you find any information that is missing or appears in error from the previous version of this
data sheet (PIC16CE62X Data Sheet, Literature Number DS40182A), please use the reader response form in the
back of this data sheet to inform us. We appreciate your assistance in making this a better document.
62X.bk Page 2 Tuesday, March 10, 1998 3:40 PM
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 3
PIC16CE62X
1.0 GENERAL DESCRIPTION
The PIC16CE62X are 18 and 20 Pin EPROM-based
members of the versatile PICmicro™ family of low-cost,
high-performance, CMOS, fully-static, 8-bit
microcontrollers with EEPROM data memory.
All PICmicro™ microcontrollers employ an advanced
RISC architecture. The PIC16CE62X have enhanced
core features, eight-le vel deep stack, and multiple internal and external interrupt sources. The separate
instruction and data buses of the Harvard architecture
allow a 14-bit wide instruction word with the separate
8-bit wide data. The two-stage instruction pipeline
allows all instructions to execute in a single-cycle,
except for program branches (which require two
cycles). A total of 35 instructions (reduced instruction
set) are available . Additionally , a large register set giv es
some of the architectural innovations used to achie ve a
very high performance.
PIC16CE62X microcontrollers typically achieve a 2:1
code compression and a 4:1 speed improvement over
other 8-bit microcontrollers in their class.
The PIC16CE623 and PIC16CE624 have 96 bytes of
RAM. The PIC16CE625 has 128 bytes of RAM. Each
microcontroller contains a 128x8 EEPROM memory
array for storing non-volatile information such as calibration data or security codes. This memor y has an
endurance of 1,000,000 erase/write cycles and a retention of 40 plus years.
Each device has 13 I/O pins and an 8-bit timer/counter
with an 8-bit programmable prescaler. In addition, the
PIC16CE62X adds two analog comparators with a
programmable on-chip voltage reference module. The
comparator module is ideally suited for applications
requiring a low-cost analog interface (e.g., battery
chargers, threshold detectors, white goods
controllers, etc).
PIC16CE62X devices have special features to reduce
external components, thus reducing system cost,
enhancing system reliability and reducing power consumption. There are f our oscillator options, of which the
single pin RC oscillator provides a low-cost solution,
the LP oscillator minimizes power consumption, XT is a
standard crystal, and the HS is for High Speed crystals.
The SLEEP (power-down) mode offers power savings.
The user can wake up the chip from SLEEP through
several external and internal interrupts and reset.
A highly reliable Watchdog Timer with its own on-chip
RC oscillator provides protection against software
lock- up.
A UV-erasable CERDIP-packaged version is ideal for
code development while the cost-effective One-Time
Programmable (OTP) version is suitable for production
in any volume.
Table 1-1 shows the features of the PIC16CE62X
mid-range microcontroller families.
A simplified block diagram of the PIC16CE62X is
shown in Figure 3-1.
The PIC16CE62X series fit perfectly in applications
ranging from multi-pocket battery chargers to
low-power remote sensors. The EPROM technology
makes customization of application programs (detection levels, pulse generation, timers, etc.) extremely
fast and convenient. The small footprint packages
make this microcontroller series perfect for all applications with space limitations. Low-cost, low-power,
high-performance, ease of use and I/O flexibility make
the PIC16CE62X very versatile.
1.1 De
velopment Support
The PIC16CE62X family is supported by a full-featured
macro assembler, a software simulator, an in-circuit
emulator, a low-cost development programmer and a
full-featured programmer. A “C” compiler and fuzzy
logic support tools are also available.
62X.bk Page 3 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
DS40182A-page 4
Preliminary
1998 Microchip Technology Inc.
TABLE 1-1: PIC16CE62X FAMILY OF DEVICES
PIC16CE623 PIC16CE624 PIC16CE625
Clock
Maximum Frequency
of Operation (MHz)
20 20 20
Memory
EPROM Program
Memory
(x14 words)
512 1K 2K
Data Memory (bytes) 96 96 128
Peripherals
EEPROM Data Memory (bytes) 128 128 128
Timer Module(s) TMR0 TMR0 TMR0
Comparators(s) 2 2 2
Internal Reference
Voltage
Yes Yes Yes
Features
Interrupt Sources 4 4 4
I/O Pins 13 13 13
Voltage Range (Volts) 3.0-5.5 3.0-5.5 3.0-5.5
Brown-out Reset Yes Yes Yes
Packages 18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
18-pin DIP,
SOIC;
20-pin SSOP
All PICmicro™ Family devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current
capability. All PIC16CE62X Family devices use serial programming with clock pin RB6 and data pin RB7.
62X.bk Page 4 Tuesday, March 10, 1998 3:40 PM
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 5
PIC16CE62X
2.0 PIC16CE62X DEVICE
VARIETIES
A variety of frequency ranges and packaging options are
available . Depending on application and production
requirements the proper device option can be selected
using the information in the PIC16CE62X Product
Identification System section at the end of this data
sheet. When placing orders, please use this page of the
data sheet to specify the correct part number.
2.1 UV Erasab
le Devices
The UV erasable version, offered in CERDIP package
is optimal for prototype development and pilot
programs. This version can be erased and
reprogrammed to any of the oscillator modes.
Microchip's PICSTART
and PRO MATE
programmers both support programming of the
PIC16CE62X.
2.2 One-Time-Pr
ogrammable (OTP)
Devices
The availability of OTP devices is especially useful for
customers who need the flexibility for frequent code
updates and small volume applications. In addition to
the program memory, the configuration bits must also
be programmed.
2.3 Quic
k-Turn-Programming (QTP)
Devices
Microchip offers a QTP Programming Service for
factory production orders. This service is made
available f or users who chose not to program a medium
to high quantity of units and whose code patterns have
stabilized. The devices are identical to the OTP devices
but with all EPROM locations and configuration options
already programmed by the factory. Certain code and
prototype verification procedures apply before
production shipments are available. Please contact
your Microchip Technology sales office for more details.
2.4 Serializ
ed Quick-Turn-Programming
(SQTP
SM
)
Devices
Microchip offers a unique programming service where
a few user-defined locations in each device are
programmed with different serial numbers. The serial
numbers may be random, pseudo-random or
sequential.
Serial programming allows each device to have a
unique number which can serve as an entry-code,
password or ID number.
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PIC16CE62X
DS40182A-page 6
Preliminary
1998 Microchip Technology Inc.
NOTES:
62X.bk Page 6 Tuesday, March 10, 1998 3:40 PM
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 7
PIC16CE62X
3.0 ARCHITECTURAL OVERVIEW
The high performance of the PIC16CE62X family can
be attributed to a number of architectural features
commonly found in RISC microprocessors. To begin
with, the PIC16CE62X uses a Harvard architecture, in
which, program and data are accessed from separate
memories using separate busses. This improves
bandwidth over traditional von Neumann architecture
where program and data are fetched from the same
memory. Separating program and data memory further
allows instructions to be sized differently than 8-bit
wide data word. Instruction opcodes are 14-bits wide
making it possible to have all single word instructions.
A 14-bit wide program memory access bus fetches a
14-bit instruction in a single cycle. A two-stage pipeline
overlaps fetch and execution of instructions.
Consequently, all instructions (35) execute in a single-cycle (200 ns @ 20 MHz) except for program
branches.
The PIC16CE623 addresses 512 x 14 on-chip program
memory. The PIC16CE624 addresses 1K x 14 program
memory. The PIC16CE625 addresses 2K x 14 program
memory. All program memory is internal.
The PIC16CE62X can directly or indirectly address its
register files or data memory. All special function
registers including the program counter are mapped in
the data memory. The PIC16CE62X have an orthogonal (symmetrical) instruction set that makes it possible
to carry out any operation on any register using any
addressing mode. This symmetr ical nature and lack of
‘special optimal situations’ make programming with the
PIC16CE62X simple yet efficient. In addition, the
learning curve is reduced significantly.
The PIC16CE62X devices contain an 8-bit ALU and
working register. The ALU is a general purpose
arithmetic unit. It performs arithmetic and Boolean
functions between data in the working register and any
register file.
The ALU is 8-bit wide and capable of addition,
subtraction, shift and logical operations. Unless
otherwise mentioned, arithmetic operations are two's
complement in nature. In two-operand instructions,
typically one operand is the working register
(W register). The other operand is a file register or an
immediate constant. In single operand instructions, the
operand is either the W register or a file register.
The W register is an 8-bit working register used for ALU
operations. It is not an addressable register.
Depending on the instruction executed, the ALU may
affect the values of the Carry (C), Digit Carry (DC), and
Zero (Z) bits in the STATUS register. The C and DC bits
operate as a Bo
rrow and Digit Borrow out bit,
respectively, bit in subtraction. See the
SUBLW
and
SUBWF
instructions for examples.
A simplified block diagram is shown in Figure 3-1, with
a description of the device pins in Table 3-1.
62X.bk Page 7 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
DS40182A-page 8
Preliminary
1998 Microchip Technology Inc.
FIGURE 3-1: BLOCK DIAGRAM
EPROM
Program
Memory
13
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr
7
RAM Addr
(1)
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR
VDD, VSS
Voltage
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
Device Program Memory
Data Memory
(RAM)
EEPROM DATA
MEMORY
PIC16CE623
PIC16CE624
PIC16CE625
512 X 14
1K X14
2K X 14
96 X 8
96 X 8
128 X 8
128 X 8
128 X 8
128 X 8
8
3
TMR0
I/O Ports
PORTB
Comparator
RA3/AN3
RA2/AN2/VREF
RA1/AN1
RA0/AN0
Reference
RA4/T0CKI
+
-
+
-
EEPROM
Data
Memory
128x8
VDD
SDA
EEINTF
SCL
62X.bk Page 8 Tuesday, March 10, 1998 3:40 PM
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 9
PIC16CE62X
TABLE 3-1: PIC16CE62X PINOUT DESCRIPTION
Name
DIP/
SOIC
Pin #
SSOP
Pin #
I/O/P
Type
Buffer
Type
Description
OSC1/CLKIN 16 18 I ST/CMOS Oscillator crystal input/external clock source input.
OSC2/CLKOUT 15 17 O — Oscillator crystal output. Connects to crystal or resonator
in crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR
/V
PP
4 4 I/P ST Master clear (reset) input/programming voltage input.
This pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0 17 19 I/O ST Analog comparator input
RA1/AN1 18 20 I/O ST Analog comparator input
RA2/AN2/V
REF
1 1 I/O ST Analog comparator input or V
REF
output
RA3/AN3 2 2 I/O ST Analog comparator input /output
RA4/T0CKI 3 3 I/O ST Can be selected to be the clock input to the Timer0
timer/counter or a comparator output. Output is open
drain type.
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
RB0/INT 6 7 I/O
TTL/ST
(1)
RB0/INT can also be selected as an external
interrupt pin.
RB1 7 8 I/O TTL
RB2 8 9 I/O TTL
RB3 9 10 I/O TTL
RB4 10 11 I/O TTL Interrupt on change pin.
RB5 11 12 I/O TTL Interrupt on change pin.
RB6 12 13 I/O TTL/ST
(2)
Interrupt on change pin. Serial programming clock.
RB7 13 14 I/O TTL/ST
(2)
Interrupt on change pin. Serial programming data.
V
SS
5 5,6 P — Ground reference for logic and I/O pins.
V
DD
14 15,16 P — Positive supply for logic and I/O pins.
Legend: O = output I/O = input/output P = power
— = Not used I = Input ST = Schmitt Trigger input
TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
62X.bk Page 9 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
DS40182A-page 10
Preliminary
1998 Microchip Technology Inc.
3.1 Cloc
king Scheme/Instruction Cycle
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
3.2 Instruction Flo
w/Pipelining
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (e.g.,
GOTO
)
then two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle , the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
Q1
Q2 Q3 Q4
Q1
Q2 Q3 Q4
Q1
Q2 Q3 Q4
OSC1
Q1
Q2
Q3
Q4
PC
OSC2/CLKOUT
(RC mode)
PC PC+1 PC+2
Fetch INST (PC)
Execute INST (PC-1) Fetch INST (PC+1)
Execute INST (PC) Fetch INST (PC+2)
Execute INST (PC+1)
Internal
phase
clock
All instructions are single cycle, except for any program branches. These take two cycles since the fetch
instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed.
1. MOVLW 55h
Fetch 1 Execute 1
2. MOVWF PORTB
Fetch 2 Execute 2
3. CALL SUB_1
Fetch 3 Execute 3
4. BSF PORTA, BIT3
Fetch 4 Flush
5. Instruction @
address SUB_1
Fetch SUB_1 Execute SUB_1
62X.bk Page 10 Tuesday, March 10, 1998 3:40 PM
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 11
PIC16CE62X
4.0 MEMORY ORGANIZATION
4.1 Pr
ogram Memory Organization
The PIC16CE62X has a 13-bit program counter capable of addressing an 8K x 14 program memory space.
Only the first 512 x 14 (0000h - 01FFh) for the
PIC16CE623, 1K x 14 (0000h - 03FFh) for the
PIC16CE624 and 2K x 14 (0000h - 07FFh) for the
PIC16CE625 are physically implemented. Accessing a
location above these boundaries will cause a
wrap-around within the first 512 x 14 space
(PIC16CE623) or 1K x 14 space (PIC16CE624) or 2K
x 14 space (PIC16CE625). The reset v ector is at 0000h
and the interrupt vector is at 0004h (Figure 4-1,
Figure 4-2, Figure 4-3).
FIGURE 4-1: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16CE623
PC<12:0>
13
000h
0004
0005
01FFh
0200h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
FIGURE 4-2: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16CE624
FIGURE 4-3: PROGRAM MEMORY MAP
AND STACK FOR THE
PIC16CE625
PC<12:0>
13
000h
0004
0005
03FFh
0400h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
PC<12:0>
13
000h
0004
0005
07FFh
0800h
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
Stack Level 2
62X.bk Page 11 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
DS40182A-page 12
Preliminary
1998 Microchip Technology Inc.
4.2 Data Memor
y Organization
The data memory (Figure 4-4 and Figure 4-5) is
partitioned into two Banks which contain the general
purpose registers and the special function registers.
Bank 0 is selected when the RP0 bit is cleared. Bank 1
is selected when the RP0 bit (STATUS <5>) is set. The
Special Function Registers are located in the first 32
locations of each Bank. Register locations 20-7Fh
(Bank0) on the PIC16CE623/624 and 20-7Fh (Bank0)
and A0-BFh (Bank1) on the PIC16CE625 are general
purpose registers implemented as static RAM. Some
special purpose registers are mapped in Bank 1. In all
three microcontrollers, address space F0h-FFh is
mapped to 70-7Fh.
4.2.1 GENERAL PURPOSE REGISTER FILE
The register file is organized as 96 x 8 in the
PIC16CE623/624 and 128 x 8 in the PIC16CE625.
Each is accessed either directly or indirectly through
the File Select Register FSR (Section 4.4).
62X.bk Page 12 Tuesday, March 10, 1998 3:40 PM
1998 Microchip Technology Inc.
Preliminary
DS40182A-page 13
PIC16CE62X
FIGURE 4-4: DATA MEMORY MAP FOR
THE PIC16CE623/624
INDF
(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
CMCON
INDF
(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
VRCON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h
A0h
General
Purpose
Register
7Fh
FFh
Bank 0 Bank 1
File
Address
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
File
Address
EEINTF
EFh
F0h
Accesses
70h-7Fh
FIGURE 4-5: DATA MEMORY MAP FOR
THE PIC16CE625
INDF
(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
CMCON
INDF
(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
PCLATH
INTCON
PIE1
PCON
VRCON
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h
A0h
General
Purpose
Register
7Fh
FFh
Bank 0 Bank 1
File
Address
BFh
C0h
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
File
Address
General
Purpose
Register
EEINTF
Accesses
70h-7Fh
F0h
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PIC16CE62X
DS40182A-page 14
Preliminary
1998 Microchip Technology Inc.
4.2.2 SPECIAL FUNCTION REGISTERS
The special function registers are registers used by the
CPU and Peripheral functions for controlling the
desired operation of the device (Table 4-1). These
registers are static RAM.
The special registers can be classified into two sets
(core and peripheral). The special function registers
associated with the “core” functions are described in
this section. Those related to the operation of the
peripheral features are described in the section of that
peripheral feature.
TABLE 4-1: SPECIAL REGISTERS FOR THE PIC16CE62X
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR/BOR
Reset
Value on all
other
resets
(1)
Bank 0
00h INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx xxxx xxxx
01h TMR0 Timer0 Module’s Register
xxxx xxxx uuuu uuuu
02h PCL Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
03h STATUS
IRP
(2)
RP1
(2)
RP0 T
O PD Z DC C
0001 1xxx 000q quuu
04h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA
— — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
07h Unimplemented — —
08h Unimplemented — —
09h Unimplemented — —
0Ah PCLATH — — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000
0Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
0Ch PIR1
— CMIF — — — — — — -0-- ---- -0-- ----
0Dh-1Eh Unimplemented — —
1Fh CMCON C2OUT C1OUT
— — CIS CM2 CM1 CM0 00-- 0000 00-- 0000
Bank 1
80h INDF
Addressing this location uses contents of FSR to address data memory (not a physical
register)
xxxx xxxx xxxx xxxx
81h OPTION RBPU
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS IRP RP1 RP0 T
O PD Z DC C 0001 1xxx 000q quuu
84h FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA
— — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
87h Unimplemented — —
88h Unimplemented — —
89h Unimplemented — —
8Ah PCLATH
— — — Write buffer for upper 5 bits of program counter ---0 0000 ---0 0000
8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000x
8Ch PIE1
— CMIE — — — — — — -0-- ---- -0-- ----
8Dh Unimplemented — —
8Eh PCON
— — — — — — POR BOR ---- --0x ---- --uq
8Fh-9Eh Unimplemented — —
90h EEINTF
— — — — — EESCL EESDA EEVDD uuuu u111 uuuu u111
9Fh VRCON VREN VROE VRR
— VR3 VR2 VR1 VR0 000- 0000 000- 0000
Legend: — = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition,
shaded = unimplemented
Note 1: Other (non power-up) resets include MCLR reset, Brown-out Reset and Watchdog Timer Reset during
normal operation.
Note 2: IRP & RPI bits are reserved, always maintain these bits clear.
62X.bk Page 14 Tuesday, March 10, 1998 3:40 PM
1998 Microchip Technology Inc. Preliminary DS40182A-page 15
PIC16CE62X
4.2.2.1 STATUS REGISTER
The STATUS register, shown in Figure 4-6, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, like any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the T
O and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This lea ves the status register as
000uu1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect any status bit. For other instructions, not affecting
any status bits, see the “Instruction Set Summary”.
Note 1: The IRP and RP1 bits (STATUS<7:6>)
are not used by the PIC16CE62X and
should be programmed as ’0'. Use of
these bits as general purpose R/W bits is
NOT recommended, since this may
affect upward compatibility with future
products.
Note 2: The C and DC bits operate as a Borro
w
and Digit Borrow out bit, respectively, in
subtraction. See the SUBLW and SUBWF
instructions for examples.
FIGURE 4-6: STATUS REGISTER (ADDRESS 03H OR 83H)
Reserved Reserved R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1
RP0 TO PD Z DC C R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
-x = Unknown at POR reset
bit7 bit0
bit 7: IRP: The IRP bit is reserved on the PIC16CE62X, always maintain this bit clear.
bit 6:5 RP1: RPO: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. The RP1 bit is reserved, always maintain this bit clear.
bit 4: T
O: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3: PD
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borro
w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0: C: Carry/borro
w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borro
w the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
62X.bk Page 15 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
DS40182A-page 16 Preliminary 1998 Microchip Technology Inc.
4.2.2.2 OPTION REGISTER
The OPTION register is a readable and writable
register which contains various control bits to configure
the TMR0/WDT prescaler, the external RB0/INT
interrupt, TMR0, and the weak pull-ups on PORTB.
Note: To achieve a 1:1 prescaler assignment for
TMR0, assign the prescaler to the WDT
(PSA = 1).
FIGURE 4-7: OPTION REGISTER (ADDRESS 81H)
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
W = Writable bit
- n = Value at POR reset
bit7 bit0
bit 7: RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
62X.bk Page 16 Tuesday, March 10, 1998 3:40 PM
1998 Microchip Technology Inc. Preliminary DS40182A-page 17
PIC16CE62X
4.2.2.3 INTCON REGISTER
The INTCON register is a readable and writable
register which contains the various enable and flag bits
for all interrupt sources except the comparator module.
See Section 4.2.2.4 and Section 4.2.2.5 for a
description of the comparator enable and flag bits.
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
FIGURE 4-8: INTCON REGISTER (ADDRESS 0BH OR 8BH)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
-x = Unknown at POR reset
bit7 bit0
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6: PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1: INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = When at least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
62X.bk Page 17 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
DS40182A-page 18 Preliminary 1998 Microchip Technology Inc.
4.2.2.4 PIE1 REGISTER
This register contains the individual enable bit for the
comparator interrupt.
FIGURE 4-9: PIE1 REGISTER (ADDRESS 8CH)
U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
— CMIE — — — — — — R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: Unimplemented: Read as '0'
bit 6: CMIE: Comparator Interrupt Enable bit
1 = Enables the Comparator interrupt
0 = Disables the Comparator interrupt
bit 5-0: Unimplemented: Read as '0'
4.2.2.5 PIR1 REGISTER
This register contains the individual flag bit for the com-
parator interrupt.
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User
software should ensure the appropriate
interrupt flag bits are clear prior to enabling
an interrupt.
FIGURE 4-10: PIR1 REGISTER (ADDRESS 0CH)
U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0
— CMIF — — — — — — R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: Unimplemented: Read as '0'
bit 6: CMIF: Comparator Interrupt Flag bit
1 = Comparator input has changed
0 = Comparator input has not changed
bit 5-0: Unimplemented: Read as '0'
62X.bk Page 18 Tuesday, March 10, 1998 3:40 PM
1998 Microchip Technology Inc. Preliminary DS40182A-page 19
PIC16CE62X
4.2.2.6 PCON REGISTER
The PCON register contains flag bits to differentiate
between a Power-on Reset, an external MCLR
reset,
WDT reset or a Brown-out Reset.
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if BOR
is
cleared, indicating a brown-out has
occurred. The BOR
status bit is a "don't
care" and is not necessarily predictable if
the brown-out circuit is disabled (by
programming BODEN bit in the
Configuration word).
FIGURE 4-11: PCON REGISTER (ADDRESS 8Eh)
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — POR BOR R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-2: Unimplemented: Read as '0'
bit 1: POR
: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0: BOR
: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
62X.bk Page 19 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
DS40182A-page 20 Preliminary 1998 Microchip Technology Inc.
4.3 PCL and PCLATH
The program counter (PC) is 13-bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The high byte (PC<12:8>) is not directly
readable or writable and comes from PCLATH. On any
reset, the PC is cleared. Figure 4-12 shows the two
situations for the loading of the PC. The upper example in
the figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lo wer example in the figure
shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).
FIGURE 4-12: LOADING OF PC IN
DIFFERENT SITUATIONS
4.3.1 COMPUTED GOTO
A computed GOTO is accomplished by adding an
offset to the program counter (ADDWF PCL). When doing
a table read using a computed GOTO method, care
should be exercised if the tab le location crosses a PCL
memory boundary (each 256 byte block). Refer to the
application note
“Implementing a Table Read"
(AN556).
PC
12 8 7 0
5
PCLA TH<4:0>
PCLA TH
Instr
uction with
ALU result
GOTO, CALL
Opcode <10:0>
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
8 7
2
PCLATH
PCH PCL
PCL as
Destination
4.3.2 STACK
The PIC16CE62X family has an 8 level deep x 13-bit
wide hardware stack (Figure 4-2 and Figure 4-3). The
stack space is not part of either program or data space
and the stack pointer is not readable or writable. The
PC is PUSHed onto the stack when a CALL instruction
is executed or an interrupt causes a branch. The stack
is POPed in the e vent of a RETURN, RETLW or a RETFIE
instruction execution. PCLATH is not affected by a
PUSH or POP operation.
The stack operates as a circular buff er . This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
Note 1: There are no STATUS bits to indicate
stack overflow or stack underflow
conditions.
Note 2: There are no instruction mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
62X.bk Page 20 Tuesday, March 10, 1998 3:40 PM
1998 Microchip Technology Inc. Preliminary DS40182A-page 21
PIC16CE62X
4.4 Indirect Addressing, INDF and FSR
Registers
The INDF register is not a physical register . Addressing
the INDF register will cause indirect addressing.
Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually
accesses data pointed to by the file select register
(FSR). Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a
no-operation (although status bits may be affected). An
effective 9-bit address is obtained by concatenating the
8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 4-13. However, IRP is not used in the
PIC16CE62X.
A simple program to clear RAM location 20h-2Fh using
indirect addressing is shown in Example 4-1.
EXAMPLE 4-1: INDIRECT ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR ;to RAM
N
EXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;no clear next
;yes continue
CONTINUE:
FIGURE 4-13: DIRECT/INDIRECT ADDRESSING PIC16CE62X
For memory map detail see Figure 4-4 and Figure 4-5.
Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.
Data
Memory
Indirect AddressingDirect Addressing
bank select location select
(1)
RP1 RP0 6
0
from opcode
IRP
(1)
FSR register
7
0
bank select
location select
00 01 10 11
00h
7Fh
00h
7Fh
Bank 0 Bank 1 Bank 2 Bank 3
not used
62X.bk Page 21 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
DS40182A-page 22 Preliminary 1998 Microchip Technology Inc.
NOTES:
62X.bk Page 22 Tuesday, March 10, 1998 3:40 PM
1998 Microchip Technology Inc. Preliminary DS40182A-page 23
PIC16CE62X
5.0 I/O PORTS
The PIC16CE62X parts have two ports, PORTA and
PORTB. Some pins for these I/O ports are multiplexed
with an alternate function for the peripheral features on
the device. In general, when a peripheral is enabled,
that pin may not be used as a general purpose I/O pin.
5.1 PORTA and TRISA Registers
PORTA is a 5-bit wide latch. RA4 is a Schmitt Trigger input
and an open drain output. P ort RA4 is multiplexed with the
T0CKI clock input. All other RA port pins have Schmitt
Trigger input levels and full CMOS output driv ers. All pins
have data direction bits (TRIS registers) which can configure these pins as input or output.
A '1' in the TRISA register puts the corresponding output
driver in a hi- impedance mode. A '0' in the TRISA register
puts the contents of the output latch on the selected pin(s).
Reading the PORTA register reads the status of the pins
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the port pins are first read, then this
value is modified and written to the port data latch.
The PORTA pins are multiplexed with comparator and
voltage reference functions. The operation of these
pins are selected by control bits in the CMCON
(comparator control register) register and the VRCON
(voltage reference control register) register. When
selected as a comparator input, these pins will read
as '0's.
FIGURE 5-1: BLOCK DIAGRAM OF
RA1:RA0 PINS
Note: I/O pins have protection diodes to VDD and VSS.
Data
bus
QD
Q
CK
P
N
WR
PortA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog
V
SS
VDD
I/O Pin
QD
Q
CK
Input Mode
DQ
EN
To Comparator
Schmitt Trigger
Input Buffer
TRISA controls the direction of the RA pins, even when
they are being used as comparator inputs. The user
must make sure to keep the pins configured as inputs
when using them as comparator inputs.
The RA2 pin will also function as the output for the
voltage reference. When in this mode, the V
REF pin is a
very high impedance output. The user must configure
TRISA<2> bit as an input and use high impedance
loads.
In one of the comparator modes defined by the
CMCON register, pins RA3 and RA4 become outputs
of the comparators. The TRISA<4:3> bits must be
cleared to enable outputs to use this function.
EXAMPLE 5-1: INITIALIZING PORTA
FIGURE 5-2: BLOCK DIAGRAM OF RA2 PIN
Note: On reset, the TRISA register is set to all
inputs. The digital inputs are disabled and
the comparator inputs are forced to ground
to reduce excess current consumption.
CLRF PORTA ;Initialize PORTA by setting
;output data latches
MOVLW 0X07 ;Turn comparators off and
MOVWF CMCON ;enable pins for I/O
;functions
BSF STATUS, RP0 ;Select Bank1
MOVLW 0x1F ;Value used to initialize
;data direction
MOVWF TRISA ;Set RA<4:0> as inputs
;TRISA<7:5> are always
;read as '0'.
Note: I/O pins have protection diodes to VDD and VSS.
Data
bus
QD
Q
CK
P
N
WR
PortA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog
VSS
VDD
RA2 Pin
QD
Q
CK
Input Mode
DQ
EN
To Comparator
Schmitt Trigger
Input Buffer
VROE
VREF
62X.bk Page 23 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
DS40182A-page 24 Preliminary 1998 Microchip Technology Inc.
FIGURE 5-3: BLOCK DIAGRAM OF RA3 PIN
FIGURE 5-4: BLOCK DIAGRAM OF RA4 PIN
Data
bus
QD
Q
CK
P
N
WR
PortA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
Analog
VSS
VDD
RA3 Pin
QD
Q
CK
DQ
EN
To Comparator
Schmitt Trigger
Input Buffer
Input Mode
Comparator Output
Comparator Mode = 110
Note: I/O pins have protection diodes to VDD and VSS
Data
bus
QD
Q
CK
N
WR
PortA
WR
TRISA
Data Latch
TRIS Latch
RD TRISA
RD PORTA
VSS
RA4 Pin
QD
Q
CK
DQ
EN
TMR0 Clock Input
Schmitt Trigger
Input Buffer
Comparator Output
Comparator Mode = 110
Note: RA4 has protection diodes to VSS only
62X.bk Page 24 Tuesday, March 10, 1998 3:40 PM
1998 Microchip Technology Inc. Preliminary DS40182A-page 25
PIC16CE62X
TABLE 5-1: PORTA FUNCTIONS
TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit #
Buffer
Type
Function
RA0/AN0 bit0 ST Input/output or comparator input
RA1/AN1 bit1 ST Input/output or comparator input
RA2/AN2/V
REF bit2 ST Input/output or comparator input or VREF output
RA3/AN3 bit3 ST Input/output or comparator input/output
RA4/T0CKI bit4 ST Input/output or external clock input for TMR0 or comparator output.
Output is open drain type.
Legend: ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR / BOR
Value on
All Other
Resets
05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000
85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111
1Fh CMCON C2OUT C1OUT — — CIS CM2 CM1 CM0 00-- 0000 00-- 0000
9Fh VRCON VREN VROE VRR — VR3 VR2 VR1 VR0 000- 0000 000- 0000
Legend: — = Unimplemented locations, read as ‘0’
Note: Note: Shaded bits are not used by PORTA.
62X.bk Page 25 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
DS40182A-page 26 Preliminary 1998 Microchip Technology Inc.
5.2 PORTB and TRISB Registers
PORTB is an 8-bit wide bi-directional port. The
corresponding data direction register is TRISB. A '1' in
the TRISB register puts the corresponding output driver
in a high impedance mode. A '0' in the TRISB register
puts the contents of the output latch on the selected
pin(s).
Reading PORTB register reads the status of the pins,
whereas writing to it will write to the port latch. All write
operations are read-modify-write operations. So a write
to a port implies that the por t pins are first read, then
this value is modified and written to the port data latch.
Each of the PORTB pins has a weak internal pull-up
(≈200 µA typical). A single control bit can turn on all the
pull-ups. This is done by clearing the RBPU
(OPTION<7>) bit. The weak pull-up is automatically
turned off when the port pin is configured as an output.
The pull-ups are disabled on Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt
on change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RBIF interrupt (flag
latched in INTCON<0>).
FIGURE 5-5: BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
From other
RBPU
(2)
P
V
DD
I/O
QD
CK
QD
CK
Q D
EN
Q D
EN
Data bus
WR PortB
WR TRISB
Set RBIF
TRIS Latch
RD TRISB
RD PortB
RB7:RB4 pins
weak
pull-up
RD Port
Latch
TTL
Input
Buffer
pin
(1)
Note 1: I/O pins have diode protection to VDD and VSS.
Note 2: TRISB = 1 enables weak pull-up if RBPU
= '0'
(OPTION<7>).
ST
Buffer
RB7:RB6 in serial programming mode
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the
interrupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
This interrupt on mismatch feature, together with
software configurable pull-ups on these four pins allow
easy interface to a key pad and make it possible for
wake-up on key-depression. (See AN552 in the
Microchip
Embedded Control Handbook
.)
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 5-6: BLOCK DIAGRAM OF
RB3:RB0 PINS
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RBIF interrupt flag may not get set.
Data Latch
RBPU
(2)
P
V
DD
QD
CK
QD
CK
Q D
EN
Data bus
WR PortB
WR TRISB
RD TRISB
RD PortB
weak
pull-up
RD Port
RB0/INT
I/O
pin
(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to V
DD and VSS.
Note 2: TRISB = 1 enables weak pull-up if RBPU
= '0'
(OPTION<7>).
ST
Buffer
62X.bk Page 26 Tuesday, March 10, 1998 3:40 PM
1998 Microchip Technology Inc. Preliminary DS40182A-page 27
PIC16CE62X
TABLE 5-3: PORTB FUNCTIONS
TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit # Buffer Type Function
RB0/INT bit0
TTL/ST
(1)
Input/output or external interrupt input. Internal software programmable
weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software
programmable weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software
programmable weak pull-up.
RB6 bit6
TTL/ST
(2)
Input/output pin (with interrupt on change). Internal software
programmable weak pull-up. Serial programming clock pin.
RB7 bit7
TTL/ST
(2)
Input/output pin (with interrupt on change). Internal software
programmable weak pull-up. Serial programming data pin.
Legend: ST = Schmitt Trigger, TTL = TTL input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR / BOR
Value on
All Other
Resets
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 1111 1111 1111 1111
81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Note: Shaded bits are not used by PORTB.
u = unchanged
x = unknown
62X.bk Page 27 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
DS40182A-page 28 Preliminary 1998 Microchip Technology Inc.
5.3 I/O Programming Considerations
5.3.1 BI-DIRECTIONAL I/O PORTS
Any instruction which writes, operates internally as a
read followed by a write operation. The BCF and BSF
instructions, for example, read the register into the
CPU, ex ecute the bit operation and write the result back
to the register. Caution must be used when these
instructions are applied to a port with both inputs and
outputs defined. For example, a BSF operation on bit5
of PORTB will cause all eight bits of PORTB to be read
into the CPU. Then the BSF operation takes place on
bit5 and PORTB is written to the output latches. If
another bit of PORTB is used as a bidirectional I/O pin
(e.g., bit0) and it is defined as an input at this time, the
input signal present on the pin itself would be read into
the CPU and re-written to the data latch of this
particular pin, overwriting the previous content. As long
as the pin stays in the input mode, no problem occurs.
However, if bit0 is switched into output mode later on,
the content of the data latch may now be unknown.
Reading the port register, reads the values of the port
pins. Writing to the port register writes the value to the
port latch. When using read modify write instructions
(ex. BCF, BSF , etc.) on a port, the value of the port pins
is read, the desired operation is done to this value, and
this value is then written to the port latch.
Example 5-2 shows the effect of two sequential
read-modify-write instructions (ex., BCF, BSF, etc.) on
an I/O port.
A pin actively outputting a Low or High should not be
driven from external devices at the same time in order
to change the level on this pin (“wired-or”, “wired-and”).
The resulting high output currents may damage
the chip.
EXAMPLE 5-2: READ-MODIFY-WRITE
INSTRUCTIONS ON AN
I/O PORT
5.3.2 SUCCESSIVE OPERATIONS ON I/O PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 5-7). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load
dependent) before the next instruction which causes
that file to be read into the CPU is executed. Otherwise ,
the previous state of that pin may be read into the CPU
rather than the new state. When in doubt, it is better to
separate these instructions with an NOP or another
instruction not accessing this I/O port.
;;Initial PORT settings: PORTB<7:4> Inputs
; PORTB<3:0> Outputs
;;PORTB<7:6> have external pull-up and are not
connected to other circuitry
;
; PORT latch PORT pins
; ---------- ----------
BCF PORTB, 7 ;01pp pppp 11pp pppp
BCF PORTB, 6 ;10pp pppp 11pp pppp
BSF STATUS,RP0 ;
BCF TRISB, 7 ;10pp pppp 11pp pppp
BCF TRISB, 6 ;10pp pppp 10pp pppp
;
; Note that the user may have expected the pin
; values to be 00pp pppp. The 2nd BCF caused
; RB7 to be latched as the pin value (High).
FIGURE 5-7: SUCCESSIVE I/O OPERATION
Note:
This example shows write to PORTB
followed by a read from PORTB.
Note that:
data setup time = (0.25 T
CY - TPD)
where TCY = instruction cycle and
TPD = propagation delay of Q1 cycle
to output valid.
Therefore, at higher clock frequencies,
a write followed by a read may be
problematic.
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
RB <7:0>
Port pin
sampled here
PC
PC + 1 PC + 2 PC + 3
NOPNOPMOVF PORTB, W
Read PORTB
MOVWF PORTB
Write to
PORTB
PC
Instruction
fetched
T
PD
Execute
MOVWF
PORTB
Execute
MOVF
PORTB, W
Execute
NOP
RB7:RB0
62X.bk Page 28 Tuesday, March 10, 1998 3:40 PM
1998 Microchip Technology Inc. Preliminary DS40182A-page 29
PIC16CE62X
6.0 EEPROM PERIPHERAL
OPERATION
The PIC16CE623/624/625 each have 128 bytes of
EEPROM data memory. The EEPROM data memory
supports a bi-directional 2-wire bus and data transmission protocol. These two-wires are serial data (SDA)
and serial clock (SCL), that are mapped to bit1 and bit2,
respectively , of the EEINTF register (SFR 90h). In
addition, the power to the EEPROM can be controlled
using bit0 (EEV
DD) of the EEINTF register. For most
applications, all that is required is calls to the following
functions:
; Byte_Write: Byte write routine
; Inputs: EEPROM Address EEADDR
; EEPROM Data EEDATA
; Outputs: Return 01 in W if OK, else
return 00 in W
;
; Read_Current: Read EEPROM at address
currently held by EE device.
; Inputs: NONE
; Outputs: EEPROM Data EEDATA
; Return 01 in W if OK, else
return 00 in W
;
; Read_Random: Read EEPROM byte at supplied
address
; Inputs: EEPROM Address EEADDR
; Outputs: EEPROM Data EEDATA
; Return 01 in W if OK,
else return 00 in W
The code for these functions is not yet determined, but
will be available on our web site (www.microchip.com)
when it is completed. The code will be accessed by
either including the source code FLASH62X.INC or by
linking FLASH62X.ASM.
6.0.1 SERIAL DATA
SDA is a bi-directional pin used to transfer addresses
and data into and data out of the memory.
For normal data transfer SD A is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP conditions.
6.0.2 SERIAL CLOCK
This SCL input is used to synchronize the data tr ansf er
from and to the memory.
6.0.3 EEINTF REGISTER
The EEINTF register (SFR 90h) controls the access to
the EEPROM. Figure 6.1 details the function of each
bit. User code must generate the clock and data signals.
FIGURE 6-1: EEINFT REGISTER (ADDRESS 90h)
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1
- - - - - EESCL EESDA EEVDD R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-3: Unimplemented: Read as '0'
bit 2: EESCL: Clock line to the EEPROM
1 = Clock high
0 = Clock low
bit 1: EESDA: Data line to EEPROM
1 = Data line is high (pin is tri-stated, line is pulled high by a pull-up resistor)
0 = Data line is low
bit 0: EEVDD: V
DD control bit for EEPROM
1 = V
DD is turned on EEPROM
0 = V
DD is turned off EEPROM (all pins are tri-stated and the EEPROM is powered down)
Note: EESDA, EESCL and EEV
DD will read ‘0’ if EEVDD is turned off
62X.bk Page 29 Tuesday, March 10, 1998 3:40 PM
PIC16CE62X
DS40182A-page 30 Preliminary 1998 Microchip Technology Inc.
6.1 BUS CHARACTERISTICS
In this section, the term “processor” ref ers to the portion
of the PIC16CE62X that interfaces to the EEPROM
through software manipulating the EEINTF register.
The following bus protocol is to be used with the
EEPROM data memory.
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted by the EEPROM as a START or STOP
condition.
Accordingly , the following bus conditions have been
defined (Figure 6-2).
6.1.1 BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
6.1.2 START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
6.1.3 STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
6.1.4 DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the processor and
is theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in,
first-out fashion.
6.1.5 ACKNOWLEDGE
The EEPROM will generate an acknowledge after the
reception of each byte. The processor must generate
an extra clock pulse which is associated with this
acknowledge bit.
When the EEPROM acknowledges, it pulls down the
SDA line during the acknowledge cloc k pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. The processor must signal an end of data to
the EEPROM by not generating an acknowledge bit on
the last byte that has been clocked out of the EEPR OM.
In this case, the EEPROM must leave the data line
HIGH to enable the processor to generate the STOP
condition (Figure 6-3).
Note: Acknowledge bits are not generated if an
internal programming cycle is in progress.
62X.bk Page 30 Tuesday, March 10, 1998 3:40 PM
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