Microchip Technology Inc PIC16C73B-04-SO, PIC16C73B-04-SP, PIC16C73B-04-SS, PIC16C73B-04I-SO, PIC16C73B-04I-SP Datasheet
...
1998 Microchip Technology Inc. DS30605A-page 1
M
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 4K x 14 words of Program Memory,
192 x 8 bytes of Data Memory (RAM)
• Interrupt capability (up to 12 internal/external
interrupt sources)
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS EPROM
technology
• Fully static design
• In-Circuit Serial Programming™ (ICSP)
• Wide operating voltage range: 2.5V to 5.5V
• High Sink/Source Current 25/25 mA
• Commercial, Industrial and Extended temperature
ranges
• Low-power consumption:
- < 2 mA @ 5V, 4 MHz
- 22.5 µA typical @ 3V, 32 kHz
- < 1 µA typical standby current
Pin Diagram
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Two Capture, Compare, PWM modules
• Capture is 16-bit, max. resolution is 12.5 ns,
Compare is 16-bit, max. resolution is 200 ns,
PWM maximum resolution is 10-bit
• 8-bit multi-channel Analog-to-Digital converter
• Synchronous Serial Port (SSP) with Enhanced
SPI
and I2C
• Universal Synchronous Asynchronous Receiver
Transmitter (USART/SCI)
• Parallel Slave Port (PSP) 8-bits wide, with
external RD
, WR and CS controls
• Brown-out detection circuitry for
Brown-out Reset (BOR)
Device Pins A/D PSP
PIC16C63A 28 NO NO
PIC16C73B 28 YES NO
PIC16C65B 40 NO YES
PIC16C74B 40 YES YES
PDIP , Windowed CERDIP
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
V
DD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/V
REF
RA4/T0CKI
RA5/SS
/AN4
RE0/RD
/AN5
RE1/WR
/AN6
RE2/CS
/AN7
V
DD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16C74B
PIC16C63A/65B/73B/74B
28/40-Pin 8-Bit CMOS Microcontrollers
PIC16C63A/65B/73B/74B
DS30605A-page 2
1998 Microchip Technology Inc.
Pin Diagrams
PIC16C73B
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
V
SS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDIP, SOIC, SSOP, Windowed CERDIP
PDIP , Windowed CERDIP
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
V
DD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP
RA0
RA1
RA2
RA3
RA4/T0CKI
RA5/SS
RE0/RD
RE1/WR
RE2/CS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RD0/PSP0
RD1/PSP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC16C65B
PIC16C63A
MCLR/VPP
RA0
RA1
RA2
RA3
RA4/T0CKI
RA5/SS
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDIP, SOIC, SSOP, Windowed CERDIP
RB3
RB2
RB1
RB0/INT
V
DD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RA4/T0CKI
RA5/SS
RE0/RD
RE1/WR
RE2/CS
VDD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
RA3
RA2
RA1
RA0
MCLR
/VPP
NC
RB7
RB6
RB5
RB4
NC
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
65432
1
4443424140
2827262524232221201918
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
V
SS
VDD
RE2/CS
RE1/WR
RE0/RD
RA5/SS
RA4/T0CKI
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
V
SS
VDD
RB0/INT
RB1
RB2
RB3
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
RA3
RA2
RA1
RA0
MCLR
/VPP
RB7
RB6
RB5
RB4
NC
NC
4443424140393837363534
2221201918171615141312
MQFP
PLCC
PIC16C65B
PIC16C65B
TQFP
RC1/T1OSI/CCP2
PIC16C63A/65B/73B/74B
1998 Microchip Technology Inc. DS30605A-page 3
Pin Diagrams (Cont.’d)
RB3
RB2
RB1
RB0/INT
V
DD
VSS
RD7/PSP7
RD6/PSP6
RD5/PSP5
RD4/PSP4
RC7/RX/DT
RA4/T0CKI
RA5/SS
/AN4
RE0/RD
/AN5
RE1/WR
/AN6
RE2/CS
/AN7
V
DD
VSS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
NC
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
MCLR
/VPP
NC
RB7
RB6
RB5
RB4
NC
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
NC
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
65432
1
4443424140
2827262524232221201918
NC
RC0/T1OSO/T1CKI
OSC2/CLKOUT
OSC1/CLKIN
V
SS
VDD
RE2/CS/AN7
RE1/WR
/AN6
RE0/RD
/AN5
RA5/SS
/AN4
RA4/T0CKI
RC7/RX/DT
RD4/PSP4
RD5/PSP5
RD6/PSP6
RD7/PSP7
V
SS
VDD
RB0/INT
RB1
RB2
RB3
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
RD1/PSP1
RD0/PSP0
RC3/SCK/SCL
RC2/CCP1
RC1/T1OSI/CCP2
NC
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
MCLR
/VPP
RB7
RB6
RB5
RB4
NC
NC
4443424140393837363534
2221201918171615141312
MQFP
PLCC
PIC16C74B
PIC16C74B
TQFP
RC1/T1OSI/CCP2
Key Features
PICmicro Mid-Range Reference Manual
(DS33023)
PIC16C63A PIC16C65B PIC16C73B PIC16C74B
Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz
Resets (and Delays) POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
POR, BOR
(PWRT, OST)
Program Memory (14-bit words) 4K 4K 4K 4K
Data Memory (bytes) 192 192 192 192
Interrupts 10 11 11 12
I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E
Timers 3333
Capture/Compare/PWM modules 2222
Serial Communications SSP, USART SSP, USART SSP, USART SSP, USART
Parallel Communications — PSP — PSP
8-bit Analog-to-Digital Module — — 5 input channels 8 input channels
Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions
PIC16C63A/65B/73B/74B
DS30605A-page 4
1998 Microchip Technology Inc.
Table of Contents
1.0 Device Overview.......................................................................................................................................................................... 5
2.0 Memory Organization................................................................................................................................................................. 11
3.0 I/O Ports.....................................................................................................................................................................................25
4.0 Timer0 Module........................................................................................................................................................................... 37
5.0 Timer1 Module........................................................................................................................................................................... 39
6.0 Timer2 Module........................................................................................................................................................................... 43
7.0 Capture/Compare/PWM (CCP) Module(s)................................................................................................................................. 45
8.0 Synchronous Serial Port (SSP) Module.....................................................................................................................................51
9.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) .................................................................................... 61
10.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 75
11.0 Special Features of the CPU...................................................................................................................................................... 81
12.0 Instruction Set Summary............................................................................................................................................................ 95
13.0 Development Support ................................................................................................................................................................ 97
14.0 Electrical Characteristics.......................................................................................................................................................... 101
15.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 123
16.0 Packaging Information ............................................................................................................................................................. 125
Appendix A: Revision History........................................................................................................................................................... 137
Appendix B: Device Differences.......................................................................................................................................................137
Appendix C: Conversion Considerations.......................................................................................................................................... 137
Appendix D: Migration from Baseline to Midrange Devices.............................................................................................................. 138
Appendix E: Bit/Register Cross-Reference List................................................................................................................................ 139
Index .................................................................................................................................................................................................. 141
On-Line Support................................................................................................................................................................................. 147
Reader Response.............................................................................................................................................................................. 148
PIC16C63A/65B/73B/74B Product Identification System .................................................................................................................. 149
To Our Valued Customers
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please check our worldwide web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number , found on the bottom outside corner
of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of document DS30000.
Errata
An errata sheet may exist f or current de vices, describing minor operational diff erences (from the data sheet) and recommended workarounds. As de vice/documentation issues become kno wn to us, we will pub lish an errata sheet. The
errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s worldwide web site at http://www.microchip.com
• Your local Microchip sales office (see last page)
• The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277
When contacting a sales office or the literature center, please specify which de vice, re vision of silicon and data sheet
(include literature number) you are using.
Corrections to this Data Sheet
We constantly strive to improv e the quality of all our products and documentation. W e hav e spent a great deal of time
to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any
information that is missing or appears in error, please:
• Fill out and mail in the reader response form in the back of this data sheet, or
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We appreciate your assistance in making this a better document.
PIC16C63A/65B/73B/74B
1998 Microchip Technology Inc. DS30605A-page 5
1.0 DEVICE OVERVIEW
This document contains device-specific information.
Additional information may be found in the PICmicro
Mid-Range Reference Manual (DS33023) which may
be obtained from your local Microchip Sales Representative or downloaded from the Microchip web site. The
Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
There are four devices (PIC16C63A, PIC16C65B,
PIC16C73B, PIC16C74B) covered by this data sheet.
These devices come in 28- and 40-pin packages. The
28-pin devices do not have a Parallel Slave Port implemented. The PIC16C6X devices do not have the A/D
module implemented.
The following two figures are device block diagrams
sorted by pin number; 28-pin for Figure 1-1 and 40-pin
for Figure 1-2. The 28-pin and 40-pin pinouts are listed
in Table 1-1 and Table 1-2 respectively.
FIGURE 1-1: PIC16C63A/PIC16C73B BLOCK DIAGRAM
EPROM
Program
Memory
13
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr
7
RAM Addr
(1)
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR
VDD, VSS
USART
PORTA
PORTB
PORTC
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
2: The A/D module is not available on the PIC16C63A.
CCP1 CCP2
Synchronous
A/D
(2)
Timer0 Timer1 Timer2
Serial Port
RA4/T0CKI
RA5/SS
/AN4
(2)
RA3/AN3/VREF
(2)
RA2/AN2
(2)
RA1/AN1
(2)
RA0/AN0
(2)
8
3
4K x 14
192 x 8
PIC16C63A/65B/73B/74B
DS30605A-page 6
1998 Microchip Technology Inc.
FIGURE 1-2: PIC16C65B/PIC16C74B BLOCK DIAGRAM
EPROM
Program
Memory
13
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
Direct Addr
7
RAM Addr
(1)
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR
VDD, VSS
PORTA
PORTB
PORTC
PORTD
PORTE
RA4/T0CKI
RA5/SS/AN4
(2)
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI/CCP2
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6/TX/CK
RC7/RX/DT
RD7/PSP7:RD0/PSP0
RE0/RD
/AN5
(2)
RE1/WR/AN6
(2)
RE2/CS/AN7
(2)
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
2: The A/D module is not available on the PIC16C65B.
USART
CCP1 CCP2
Synchronous
A/D
(2)
Timer0 Timer1 Timer2
Serial Port
RA3/AN3/VREF
(2)
RA2/AN2
(2)
RA1/AN1
(2)
RA0/AN0
(2)
Parallel Slave Port
8
3
4K x 14
192 x 8
PIC16C63A/65B/73B/74B
1998 Microchip Technology Inc. DS30605A-page 7
TABLE 1-1: PIC16C63A/PIC16C73B PINOUT DESCRIPTION
Pin Name
DIP
Pin#
SOIC
Pin#
I/O/P
Type
Buffer
Type
Description
OSC1/CLKIN 9 9 I
ST/CMOS
(3)
Oscillator crystal input/external clock source input.
OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, the OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and denotes
the instruction cycle rate.
MCLR
/V
PP
1 1 I/P ST Master clear (reset) input or programming voltage input. This
pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0
(4)
2 2 I/O TTL RA0 can also be analog input0
RA1/AN1
(4)
3 3 I/O TTL RA1 can also be analog input1
RA2/AN2
(4)
4 4 I/O TTL RA2 can also be analog input2
RA3/AN3/V
REF
(4)
5 5 I/O TTL RA3 can also be analog input3 or analog reference voltage
RA4/T0CKI 6 6 I/O ST RA4 can also be the clock input to the Timer0 module.
Output is open drain type.
RA5/SS
/AN4
(4)
7 7 I/O TTL RA5 can also be analog input4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 21 21 I/O TTL/ST
(1)
RB0 can also be the external interrupt pin.
RB1 22 22 I/O TTL
RB2 23 23 I/O TTL
RB3 24 24 I/O TTL
RB4 25 25 I/O TTL Interrupt on change pin.
RB5 26 26 I/O TTL Interrupt on change pin.
RB6 27 27 I/O TTL/ST
(2)
Interrupt on change pin. Serial programming clock.
RB7 28 28 I/O TTL/ST
(2)
Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1
clock input.
RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2
input/Compare2 output/PWM2 output.
RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output
for both SPI and I2C modes.
RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
V
SS
8, 19 8, 19 P — Ground reference for logic and I/O pins.
V
DD
20 20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
4: The A/D module is not available on the PIC16C63A.
PIC16C63A/65B/73B/74B
DS30605A-page 8
1998 Microchip Technology Inc.
TABLE 1-2: PIC16C65B/PIC16C74B PINOUT DESCRIPTION
Pin Name
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Description
OSC1/CLKIN 13 14 30 I ST/CMOS
(4)
Oscillator crystal input/external clock source input.
OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in
crystal oscillator mode. In RC mode, OSC2 pin outputs
CLKOUT which has 1/4 the frequency of OSC1, and
denotes the instruction cycle rate.
MCLR
/V
PP
1 2 18 I/P ST Master clear (reset) input or programming voltage input.
This pin is an active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0
(5)
2 3 19 I/O TTL RA0 can also be analog input0
RA1/AN1
(5)
3 4 20 I/O TTL RA1 can also be analog input1
RA2/AN2
(5)
4 5 21 I/O TTL RA2 can also be analog input2
RA3/AN3/V
REF
(5)
5 6 22 I/O TTL RA3 can also be analog input3 or analog reference
voltage
RA4/T0CKI 6 7 23 I/O ST RA4 can also be the clock input to the Timer0 timer/
counter. Output is open drain type.
RA5/SS
/AN4
(5)
7 8 24 I/O TTL RA5 can also be analog input4 or the slave select for
the synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be softw are
programmed for internal weak pull-up on all inputs.
RB0/INT 33 36 8 I/O TTL/ST
(1)
RB0 can also be the external interrupt pin.
RB1 34 37 9 I/O TTL
RB2 35 38 10 I/O TTL
RB3 36 39 11 I/O TTL
RB4 37 41 14 I/O TTL Interrupt on change pin.
RB5 38 42 15 I/O TTL Interrupt on change pin.
RB6 39 43 16 I/O TTL/ST
(2)
Interrupt on change pin. Serial programming clock.
RB7 40 44 17 I/O TTL/ST
(2)
Interrupt on change pin. Serial programming data.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
5: The A/D module is not available on the PIC16C65B.
PIC16C63A/65B/73B/74B
1998 Microchip Technology Inc. DS30605A-page 9
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a
Timer1 clock input.
RC1/T1OSI/CCP2
16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or
Capture2 input/Compare2 output/PWM2 output.
RC2/CCP1
17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/
PWM1 output.
RC3/SCK/SCL
18 20 37 I/O ST RC3 can also be the synchronous serial clock input/
output for both SPI and I2C modes.
RC4/SDI/SDA
23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I2C mode).
RC5/SDO
24 26 43 I/O ST RC5 can also be the SPI Data Out
(SPI mode).
RC6/TX/CK
25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or
Synchronous Clock.
RC7/RX/DT
26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or
Synchronous Data.
PORTD is a bi-directional I/O port or parallel slave port
when interfacing to a microprocessor bus.
RD0/PSP0 19 21 38 I/O ST/TTL
(3)
RD1/PSP1 20 22 39 I/O ST/TTL
(3)
RD2/PSP2 21 23 40 I/O ST/TTL
(3)
RD3/PSP3 22 24 41 I/O ST/TTL
(3)
RD4/PSP4 27 30 2 I/O ST/TTL
(3)
RD5/PSP5 28 31 3 I/O ST/TTL
(3)
RD6/PSP6 29 32 4 I/O ST/TTL
(3)
RD7/PSP7 30 33 5 I/O ST/TTL
(3)
PORTE is a bi-directional I/O port.
RE0/RD
/AN5
(5)
8 9 25 I/O ST/TTL
(3)
RE0 can also be read control for the parallel slave port,
or analog input5.
RE1/WR
/AN6
(5)
9 10 26 I/O ST/TTL
(3)
RE1 can also be write control for the parallel slave port,
or analog input6.
RE2/CS
/AN7
(5)
10 11 27 I/O ST/TTL
(3)
RE2 can also be select control for the parallel slave
port, or analog input7.
V
SS
12,31 13,34 6,29 P — Ground reference for logic and I/O pins.
V
DD
11,32 12,35 7,28 P — Positive supply for logic and I/O pins.
NC — 1,17,28,4012,13,
33,34
— These pins are not internally connected. These pins should
be left unconnected.
TABLE 1-2: PIC16C65B/PIC16C74B PINOUT DESCRIPTION (Cont.’d)
Pin Name
DIP
Pin#
PLCC
Pin#
QFP
Pin#
I/O/P
Type
Buffer
Type
Description
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel
Slave Port mode (for interfacing to a microprocessor bus).
4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise.
5: The A/D module is not available on the PIC16C65B.
PIC16C63A/65B/73B/74B
DS30605A-page 10
1998 Microchip Technology Inc.
NOTES:
PIC16C63A/65B/73B/74B
1998 Microchip Technology Inc. DS30605A-page 11
2.0 MEMORY ORGANIZATION
There are two memory blocks in each of these PICmicro
microcontrollers. Each block (Program Memory and
Data Memory) has its own bus so that concurrent
access can occur.
Additional information on device memory may be found
in the PICmicro Mid-Range Reference Manual
(DS33023).
2.1 Pr
ogram Memory Organization
The PIC16C63A/65B/73B/74B microcontrollers have a
13-bit program counter capable of addressing an 8K x
14 program memory space. Each device has 4K x 14
words of program memory. Accessing a location above
the physically implemented address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK
2.2 Data Memor
y Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2 (not implemented)
= 11 → Bank3 (not implemented)
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Abo ve the Special Function Registers are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some “high use” special function
registers from one bank may be mirrored in another
bank for code reduction and quicker access.
2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly , or indi-
rectly through the File Select Register FSR
(Section 2.5).
PC<12:0>
13
0000h
0004h
0005h
07FFh
0800h
0FFFh
1000h
1FFFh
Stack Level 1
Stack Level 8
Reset V ector
Interrupt Vector
On-chip Program
On-chip Program
Memory (Page 1)
Memory (Page 0)
CALL, RETURN
RETFIE, RETLW
User Memory
Space
RP1
(1)
RP0 (STATUS<6:5>)
Note 1: Maintain this bit clear to ensure upward compati-
bility with future products.
PIC16C63A/65B/73B/74B
DS30605A-page 12 1998 Microchip Technology Inc.
FIGURE 2-2: REGISTER FILE MAP
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
give in Table 2-1.
The special function registers can be classified into two
sets; core (CPU) and peripheral. Those registers associated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.
INDF
(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PORTD
(2)
PORTE
(2)
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
CCPR2L
CCPR2H
CCP2CON
ADRES
(3)
ADCON0
(3)
INDF
(1)
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
(2)
TRISE
(2)
PCLATH
INTCON
PIE1
PIE2
PCON
PR2
SSPADD
SSPSTAT
TXSTA
SPBRG
ADCON1
(3)
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h A0h
General
Purpose
Register
General
Purpose
Register
7Fh
FFh
Bank 0 Bank 1
File
Address
File
Address
Unimplemented data memory locations, read
as ’0’.
Note 1: Not a physical register.
2: These registers are not implemented on the
PIC16C63A/73B, read as '0'.
3: These registers are not implemented on the
PIC16C63A/65B, read as '0'.
PIC16C63A/65B/73B/74B
1998 Microchip Technology Inc. DS30605A-page 13
TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOR
Value on all
other resets
(5)
Bank 0
00h INDF
(1)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
02h PCL
(1)
Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
03h STATUS
(1)
IRP
(6)
RP1
(6)
RP0 TO PD ZDCCrr01 1xxx rr0q quuu
04h FSR
(1)
Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA
(7)
— — PORTA Data Latch when written: PORTA pins when read --0x 0000 --0u 0000
06h PORTB
(8)
PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu
07h PORTC
(8)
PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuuu
08h PORTD
(3,8)
PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuuu
09h PORTE
(3,8)
— — — — — RE2 RE1 RE0 ---- -xxx ---- -uuu
0Ah PCLATH
(1,2)
— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh INTCON
(1)
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1 PSPIF
(3)
ADIF
(4)
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000
0Dh PIR2 — — — – — — — CCP2IF ---- ---0 ---- ---0
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x
19h TXREG USART Transmit Data Register 0000 0000 0000 0000
1Ah RCREG USART Receive Data Register 0000 0000 0000 0000
1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuuu
1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuuu
1Dh CCP2CON
— — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000
1Eh ADRES
(4)
A/D Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0
(4)
ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0',
Shaded locations are unimplemented, read as '0'.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: PORTD and PORTE are not implemented on the PIC16C63A/73B, maintain as ’0’.
4: A/D not implemented on the PIC16C63A/65B, maintain as ’0’.
5: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
6: The IRP and RP1 bits are reserved. Always maintain these bits clear.
7: On any device reset, these pins are configured as inputs.
8: This is the value that will be in the port output latch.
PIC16C63A/65B/73B/74B
DS30605A-page 14 1998 Microchip Technology Inc.
Bank 1
80h INDF
(1)
Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h PCL
(1)
Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000
83h STATUS
(1)
IRP
(6)
RP1
(6)
RP0 TO PD ZDCCrr01 1xxx rr0q quuu
84h FSR
(1)
Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
88h TRISD
(3)
PORTD Data Direction Register 1111 1111 1111 1111
89h TRISE
(3)
IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111
8Ah PCLATH
(1,2)
— — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh INTCON
(1)
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 PSPIE
(3)
ADIE
(4)
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000
8Dh PIE2 — — — — — — — CCP2IE ---- ---0 ---- ---0
8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT SMP CKE D/A P S R/W UA BF 0000 0000 0000 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010
99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ADCON1
(4)
— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0',
Shaded locations are unimplemented, read as '0'.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents
are transferred to the upper byte of the program counter.
3: PORTD and PORTE are not implemented on the PIC16C63A/73B, maintain as ’0’.
4: A/D not implemented on the PIC16C63A/65B, maintain as ’0’.
5: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset.
6: The IRP and RP1 bits are reserved. Always maintain these bits clear.
7: On any device reset, these pins are configured as inputs.
8: This is the value that will be in the port output latch.
TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOR
Value on all
other resets
(5)
PIC16C63A/65B/73B/74B
1998 Microchip Technology Inc. DS30605A-page 15
2.2.2.1 STATUS REGISTER
The STATUS register, shown in Figure 2-3, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the T
O and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the ST ATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STA TUS register . For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
FIGURE 2-3: STATUS REGISTER (ADDRESS 03h, 83h)
Note 1: These devices do not use bits IRP and
RP1 (STATUS<7:6>). Maintain these bits
clear to ensure upward compatibility with
future products.
Note 2: The C and DC bits operate as a borro
w
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh) - not implemented, maintain clear
0 = Bank 0, 1 (00h - FFh) - not implemented, maintain clear
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh) - not implemented, maintain clear
10 = Bank 2 (100h - 17Fh) - not implemented, maintain clear
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4: T
O: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3: PD
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borro
w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0: C: Carry/borro
w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borro
w the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
PIC16C63A/65B/73B/74B
DS30605A-page 16 1998 Microchip Technology Inc.
2.2.2.2 OPTION_REG REGISTER
The OPTION_REG register is a readable and writable
register which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External
INT Interrupt, TMR0, and the weak pull-ups on PORTB .
FIGURE 2-4: OPTION_REG REGISTER (ADDRESS 81h)
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer .
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
PIC16C63A/65B/73B/74B
1998 Microchip Technology Inc. DS30605A-page 17
2.2.2.3 INTCON REGISTER
The INTCON Register is a readable and writable regis-
ter which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and Exter nal
RB0/INT pin interrupts.
FIGURE 2-5: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6: PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: IINTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1: INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
PIC16C63A/65B/73B/74B
DS30605A-page 18 1998 Microchip Technology Inc.
2.2.2.4 PIE1 REGISTER
This register contains the individual enable bits for the
peripheral interrupts.
FIGURE 2-6: PIE1 REGISTER (ADDRESS 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIE
(1)
ADIE
(2)
RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: PSPIE
(1)
: Parallel Slave Port Read/Write Interrupt Enable bit
1 = Enables the PSP read/write interrupt
0 = Disables the PSP read/write interrupt
bit 6: ADIE
(2)
: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5: RCIE: USART Receive Interrupt Enable bit
1 = Enables the USART receive interrupt
0 = Disables the USART receive interrupt
bit 4: TXIE: USART Transmit Interrupt Enable bit
1 = Enables the USART transmit interrupt
0 = Disables the USART transmit interrupt
bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2: CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Note 1: PIC16C63A/73B devices do not have a Parallel Slave Port implemented. This bit location is reserved on these
devices. Always maintain this bit clear.
2: PIC16C63A/65B devices do not have an A/D module . This bit location is reserved on these devices. Alw ays maintain
this bit clear.
PIC16C63A/65B/73B/74B
1998 Microchip Technology Inc. DS30605A-page 19
2.2.2.5 PIR1 REGISTER
This register contains the individual flag bits for the
peripheral interrupts.
FIGURE 2-7: PIR1 REGISTER (ADDRESS 0Ch)
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
PSPIF
(1)
ADIF
(2)
RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: PSPIF
(1)
: Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
bit 6: ADIF
(2)
: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5: RCIF: USART Receive Interrupt Flag bit
1 = The USART receive buffer is full (cleared by reading RCREG)
0 = The USART receive buffer is empty
bit 4: TXIF: USART Transmit Interrupt Flag bit
1 = The USART transmit buffer is empty (cleared by writing to TXREG)
0 = The USART transmit buffer is full
bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2: CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Note 1: PIC16C63A/73B devices do not have a Parallel Slave Port implemented. This bit location is reserved on these
devices. Always maintain this bit clear.
2: PIC16C63A/65B devices do not have an A/D module . This bit location is reserved on these devices. Alw ays maintain
this bit clear.
PIC16C63A/65B/73B/74B
DS30605A-page 20 1998 Microchip Technology Inc.
2.2.2.6 PIE2 REGISTER
This register contains the individual enable bit for the
CCP2 peripheral interrupt.
FIGURE 2-8: PIE2 REGISTER (ADDRESS 8Dh)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CCP2IE R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-1: Unimplemented: Read as '0'
bit 0: CCP2IE: CCP2 Interrupt Enable bit
1 = Enables the CCP2 interrupt
0 = Disables the CCP2 interrupt
PIC16C63A/65B/73B/74B
1998 Microchip Technology Inc. DS30605A-page 21
2.2.2.7 PIR2 REGISTER
This register contains the CCP2 interrupt flag bit.
.
FIGURE 2-9: PIR2 REGISTER (ADDRESS 0Dh)
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — CCP2IF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-1: Unimplemented: Read as '0'
bit 0: CCP2IF: CCP2 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused
PIC16C63A/65B/73B/74B
DS30605A-page 22 1998 Microchip Technology Inc.
2.2.2.8 PCON REGISTER
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR
Reset or WDT Reset.
Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset
condition from a Power-on Reset condition.
FIGURE 2-10: PCON REGISTER (ADDRESS 8Eh)
Note: If the BODEN configuration bit is set, BOR
is ’1’ on Power-on Reset. If the BODEN
configuration bit is clear, BOR
is unknown
on Power-on Reset.
The BOR
status bit is a "don't care" and is
not necessarily predictable if the brown-out
circuit is disabled (the BODEN configuration bit is clear). BOR
must then be set by
the user and checked on subsequent
resets to see if it
is clear, indicating a
brown-out has occurred.
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q
— — — — — — POR BOR R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-2: Unimplemented: Read as '0'
bit 1: POR
: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0: BOR
: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
PIC16C63A/65B/73B/74B
1998 Microchip Technology Inc. DS30605A-page 23
2.3 PCL and PCLATH
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits and is not directly readable or writable. All updates
to the PCH register go through the PCLATH register.
2.3.1 STACK
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address from this branch in program execution.
Mid-Range devices have an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.
After the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
2.4 Program Memory Paging
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction
the upper bit of the address is provided by
PCLATH<3>. When doing a CALL or GOTO instruction,
the user must ensure that the page select bit is programmed so that the desired program memory page is
addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto
the stack. Therefore, manipulation of the PCLATH<3>
bit is not required for the return instructions (which
POPs the address from the stack).
PIC16C63A/65B/73B/74B
DS30605A-page 24 1998 Microchip Technology Inc.
2.5 Indirect Addressing, INDF and FSR
Registers
The INDF register is not a physical register. Addressing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer
). This is indirect addressing.
EXAMPLE 2-1: INDIRECT ADDRESSING
• Register file 05 contains the value 10h
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register
• A read of the INDF register will return the value of
10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDR register now will return the
value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR ; to RAM
NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;NO, clear next
CONTINUE
: ;YES, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-11. However, IRP is not used in the
PIC16C63A/65B/73B/74B.
FIGURE 2-11: DIRECT/INDIRECT ADDRESSING
Note 1: For register file map detail see Figure 2-2.
2: Maintain RP1 and IRP as clear for upward compatibility with future products.
3: Not implemented.
Data
Memory(1)
Indirect AddressingDirect Addressing
bank select location select
RP1:RP0 6
0
from opcode
IRP FSR register
7
0
bank select
location select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
not used
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
(2)
(2)
(3) (3)
PIC16C63A/65B/73B/74B
1998 Microchip Technology Inc. DS30605A-page 25
3.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a per ipheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PICmicro Mid-Range Reference Manual, (DS33023).
3.1 PORTA and the TRISA Register
PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output, i.e., put
the contents of the output latch on the selected pin.
Reading the PORTA register reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read. This v alue is modified and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
On PIC16C73B/74B devices, other PORTA pins are
multiplexed with analog inputs and analog V
REF input.
The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1).
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 3-1: INITIALIZING PORTA
BCF STATUS, RP0 ;
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as '0'.
FIGURE 3-1: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
FIGURE 3-2: BLOCK DIAGRAM OF
RA4/T0CKI PIN
Note: On a Power-on Reset, these pins are con-
figured as inputs and read as '0'.
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
Data
bus
QD
Q
CK
QD
Q
CK
QD
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
V
SS
VDD
I/O pin
(1)
Note 1: I/O pins have protection diodes to VDD and
VSS.
Analog
input
mode
TTL
input
buffer
To A/D Converter (73B/74B only)
(73B/74B
only)
Data
bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
T rigger
input
buffer
N
V
SS
I/O pin
(1)
TMR0 clock input
Note 1: I/O pin has protection diodes to V
SS only.
QD
Q
CK
QD
Q
CK
EN
QD
EN
PIC16C63A/65B/73B/74B
DS30605A-page 26 1998 Microchip Technology Inc.
TABLE 3-1: PORTA FUNCTIONS
TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit# Buffer Function
RA0/AN0 bit0 TTL
Input/output or analog input
(1)
RA1/AN1 bit1 TTL
Input/output or analog input
(1)
RA2/AN2 bit2 TTL
Input/output or analog input
(1)
RA3/AN3/VREF bit3 TTL
Input/output or analog input
(1)
or VREF
(1)
RA4/T0CKI bit4 ST Input/output or external clock input for Timer0
Output is open drain type
RA5/SS
/AN4 bit5 TTL
Input/output or slave select input for synchronous serial port or analog input
(1)
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: On PIC16C73B/74B devices only.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOR
Value on all
other resets
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
9Fh ADCON1
(1)
— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used b y POR TA.
Note 1: On PIC16C73B/74B devices only.
PIC16C63A/65B/73B/74B
1998 Microchip Technology Inc. DS30605A-page 27
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output, i.e., put
the contents of the output latch on the selected pin.
EXAMPLE 3-1: INITIALIZING PORTB
BCF STATUS, RP0 ;
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU
(OPTION_REG<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are disabled on a Power-on Reset.
FIGURE 3-3: BLOCK DIAGRAM OF
RB3:RB0 PINS
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin configured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the interrupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 3-4: BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
RBPU
(2)
P
V
DD
QD
CK
QD
CK
QD
EN
Data bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
RB0/INT
I/O
pin
(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to V
DD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU
bit (OPTION_REG<7>).
Schmitt T rigger
Buffer
TRIS Latch
Data Latch
From other
RBPU
(2)
P
V
DD
I/O
QD
CK
QD
CK
QD
EN
QD
EN
Data bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pins
weak
pull-up
RD Port
Latch
TTL
Input
Buffer
pin
(1)
Note 1: I/O pins have diode protection to VDD and VSS.
ST
Buffer
RB7:RB6 in serial programming mode
Q3
Q1
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU
bit (OPTION_REG<7>).
PIC16C63A/65B/73B/74B
DS30605A-page 28 1998 Microchip Technology Inc.
TABLE 3-3: PORTB FUNCTIONS
TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit# Buffer Function
RB0/INT bit0 TTL/ST
(1)
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB6 bit6 TTL/ST
(2)
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming clock.
RB7 bit7 TTL/ST
(2)
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOR
Value on all
other resets
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h OPTION_
REG
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
PIC16C63A/65B/73B/74B
1998 Microchip Technology Inc. DS30605A-page 29
3.3 PORTC and the TRISC Register
PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (=1) will make the corresponding PORTC pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output, i.e., put
the contents of the output latch on the selected pin.
PORTC is multiplex ed with se v eral peripheral functions
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
EXAMPLE 3-1: INITIALIZING PORTC
BCF STATUS, RP0 ; Select Bank 0
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
FIGURE 3-5: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
PORT/PERIPHERAL Select
(2)
Data bus
WR
PORT
WR
TRIS
RD
Data Latch
TRIS Latch
RD TRIS
Schmitt
T rigger
QD
Q
CK
QD
EN
Peripheral Data Out
0
1
QD
Q
CK
P
N
V
DD
VSS
PORT
Peripheral
OE
(3)
Peripheral input
I/O
pin
(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
PIC16C63A/65B/73B/74B
DS30605A-page 30 1998 Microchip Technology Inc.
TABLE 3-5: PORTC FUNCTIONS
TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit# Buffer Type Function
RC0/T1OSO/T1CKI
bit0
ST Input/output port pin or Timer1 oscillator output/Timer1 clock input
RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1
output
RC3/SCK/SCL bit3 ST
RC3 can also be the synchronous serial clock for both SPI and I
2
C
modes.
RC4/SDI/SDA bit4 ST
RC4 can also be the SPI Data In (SPI mode) or data I/O (I
2
C mode).
RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output
RC6 bit6 ST Input/output port pin
RC7 bit7 ST Input/output port pin
Legend: ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOR
Value on all
other resets
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged.
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