Microchip Technology Inc PIC16C72-04-SP, PIC16C72-04E-SO, PIC16C72-04E-SP, PIC16C72-04I-JW, PIC16C72-04I-SO Datasheet
...
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 1
M
Devices included:
Microcontroller Core Features:
• High-performance RISC CPU
• Only 35 single word instructions to learn
• All single cycle instructions except for program
branches which are two cycle
• Operating speed: DC - 20 MHz clock input
DC - 200 ns instruction cycle
• 2K x 14 words of Program Memory,
128 x 8 bytes of Data Memory (RAM)
• Interrupt capability
• Eight level deep hardware stack
• Direct, indirect, and relative addressing modes
• Power-on Reset (POR)
• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)
• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation
• Programmable code-protection
• Power saving SLEEP mode
• Selectable oscillator options
• Low-power, high-speed CMOS technology
• Fully static design
• Wide operating voltage range:
- 2.5V to 6.0V (PIC16C72)
- 2.5V to 5.5V (PIC16CR72)
• High Sink/Source Current 25/25 mA
• Commercial, Industrial and Extended temperature
ranges
• Low-power consumption:
- < 2 mA @ 5V, 4 MHz
- 15 µA typical @ 3V, 32 kHz
- < 1
µ A typical standby current
Pin Diagrams
Peripheral Features:
• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via external
crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
• Capture, Compare, PWM (CCP) module
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
• 8-bit 5-channel analog-to-digital converter
• Synchronous Serial Port (SSP) with
SPI
and I
2
C
• Brown-out detection circuitry for
Brown-out Reset (BOR)
• PIC16C72
• PIC16CR72
PIC16C72
MCLR/VPP
RA0/AN0
RA1/AN1
RA2/AN2
RA3/AN3/VREF
RA4/T0CKI
RA5/SS/AN4
V
SS
OSC1/CLKIN
OSC2/CLKOUT
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0/INT
VDD
VSS
RC7
RC6
RC5/SDO
RC4/SDI/SDA
• 1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SDIP, SOIC, SSOP,
PIC16CR72
Windowed Side Brazed Ceramic
PIC16C72 SERIES
8-Bit CMOS Microcontrollers with A/D Converter
PIC16C72 Series
DS39016A-page 2
Preliminary
1998 Microchip Technology Inc.
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 3
2.0 Memory Organization................................................................................................................................................................... 5
3.0 I/O Ports..................................................................................................................................................................................... 19
4.0 Timer0 Module ........................................................................................................................................................................... 25
5.0 Timer1 Module ........................................................................................................................................................................... 27
6.0 Timer2 Module ........................................................................................................................................................................... 31
7.0 Capture/Compare/PWM (CCP) Module..................................................................................................................................... 33
8.0 Synchronous Serial Port (SSP) Module..................................................................................................................................... 39
9.0 Analog-to-Digital Converter (A/D) Module..................................................................................................................................53
10.0 Special Features of the CPU...................................................................................................................................................... 59
11.0 Instruction Set Summary............................................................................................................................................................ 73
12.0 Development Support................................................................................................................................................................. 75
13.0 Electrical Characteristics - PIC16C72 Series............................................................................................................................. 77
14.0 DC and AC Characteristics Graphs and Tables - PIC16C72..................................................................................................... 97
15.0 DC and AC Characteristics Graphs and Tables - PIC16CR72 ................................................................................................ 107
16.0 Packaging Information.............................................................................................................................................................. 109
Appendix A: What’s New in this Data Sheet .................................................................................................................................. 115
Appendix B: What’s Changed in this Data Sheet........................................................................................................................... 115
Appendix C: Device Differences..................................................................................................................................................... 115
Index .................................................................................................................................................................................................. 117
On-Line Support................................................................................................................................................................................. 121
Reader Response.............................................................................................................................................................................. 122
PIC16C72 Series Product Identification System................................................................................................................................ 125
Sales and Support.............................................................................................................................................................................. 125
To Our Valued Customers
We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional
amount of time to ensure that these documents are correct. However, we realize that we may have missed a few
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Key Reference Manual Features PIC16C72 PIC16CR72
Operating Frequency DC - 20MHz DC - 20MHz
Resets POR, PWRT, OST, BOR POR, PWRT, OST, BOR
Program Memory - (14-bit words) 2K (EPROM) 2K (ROM)
Data Memory - RAM (8-bit bytes) 128 128
Interrupts 8 8
I/O Ports PortA, PortB, PortC PortA, PortB, PortC
Timers Timer0, Timer1, Timer2 Timer0, Timer1, Timer2
Capture/Compare/PWM Modules 1 1
Serial Communications Basic SSP SSP
8-Bit A/D Converter 5 channels 5 channels
Instruction Set (No. of Instructions) 35 35
PIC16C72 Series
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 3
1.0 DEVICE OVERVIEW
This document contains device-specific information for
the operation of the PIC16C72 device. Additional information may be found in the PICmicro™ Mid-Range
MCU Reference Manual (DS33023) which may be
downloaded from the Microchip website. The Reference Manual should be considered a complementary
document to this data sheet, and is highly recommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
The PIC16C72 belongs to the Mid-Range family of the
PICmicro devices. A block diagram of the device is
shown in Figure 1-1.
The program memory contains 2K words which translate to 2048 instructions, since each 14-bit program
memory word is the same width as each device instruction. The data memory (RAM) contains 128 bytes.
There are also 22 I/O pins that are user-configurable on
a pin-to-pin basis. Some pins are multiplex ed with other
device functions. These functions include:
• External interrupt
• Change on PORTB interrupt
• Timer0 clock input
• Timer1 clock/oscillator
• Capture/Compare/PWM
• A/D converter
• SPI/I
2
C
Table 1-1 details the pinout of the device with descriptions and details for each pin.
FIGURE 1-1: PIC16C72/CR72 BLOCK DIAGRAM
EPROM/
Program
Memory
2K x 14
13
Data Bus
8
14
Program
Bus
Instruction reg
Program Counter
8 Level Stack
(13-bit)
RAM
File
Registers
128 x 8
Direct Addr
7
RAM Addr
(1)
9
Addr MUX
Indirect
Addr
FSR reg
STATUS reg
MUX
ALU
W reg
Power-up
Timer
Oscillator
Start-up Timer
Power-on
Reset
Watchdog
Timer
Instruction
Decode &
Control
Timing
Generation
OSC1/CLKIN
OSC2/CLKOUT
MCLR
VDD, VSS
Timer0
A/D
Synchronous
Serial Port
PORTA
PORTB
PORTC
RB0/INT
RB7:RB1
RC0/T1OSO/T1CKI
RC1/T1OSI
RC2/CCP1
RC3/SCK/SCL
RC4/SDI/SDA
RC5/SDO
RC6
RC7
8
8
Brown-out
Reset
Note 1: Higher order bits are from the STATUS register.
CCP1
Timer1 Timer2
RA4/T0CKI
RA5/SS
/AN4
RA3/AN3/VREF
RA2/AN2
RA1/AN1
RA0/AN0
8
3
ROM
PIC16C72 Series
DS39016A-page 4
Preliminary
1998 Microchip Technology Inc.
TABLE 1-1 PIC16C72/CR72 PINOUT DESCRIPTION
Pin Name Pin#
I/O/P
Type
Buffer
Type
Description
OSC1/CLKIN 9 I
ST/CMOS
(3)
Oscillator crystal input/external clock source input.
OSC2/CLKOUT 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal
oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which
has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.
MCLR
/V
PP
1 I/P ST Master clear (reset) input or programming voltage input. This pin is an
active low reset to the device.
PORTA is a bi-directional I/O port.
RA0/AN0 2 I/O TTL RA0 can also be analog input0.
RA1/AN1 3 I/O TTL RA1 can also be analog input1.
RA2/AN2 4 I/O TTL RA2 can also be analog input2.
RA3/AN3/V
REF
5 I/O TTL RA3 can also be analog input3 or analog reference voltage
RA4/T0CKI 6 I/O ST RA4 can also be the clock input to the Timer0 module. Output is
open drain type.
RA5/SS/AN4
7 I/O TTL RA5 can also be analog input4 or the slave select for the
synchronous serial port.
PORTB is a bi-directional I/O port. PORTB can be software
programmed for internal weak pull-up on all inputs.
RB0/INT 21 I/O TTL/ST
(1)
RB0 can also be the external interrupt pin.
RB1 22 I/O TTL
RB2 23 I/O TTL
RB3 24 I/O TTL
RB4 25 I/O TTL Interrupt on change pin.
RB5 26 I/O TTL Interrupt on change pin.
RB6 27 I/O TTL/ST
(2)
Interrupt on change pin. Serial programming clock.
RB7 28 I/O TTL/ST
(2)
Interrupt on change pin. Serial programming data.
PORTC is a bi-directional I/O port.
RC0/T1OSO/T1CKI 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock
input.
RC1/T1OSI 12 I/O ST RC1 can also be the Timer1 oscillator input.
RC2/CCP1 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/PWM1
output.
RC3/SCK/SCL 14 I/O ST RC3 can also be the synchronous serial clock input/output f or both
SPI and I
2
C modes.
RC4/SDI/SDA 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or
data I/O (I
2
C mode).
RC5/SDO 16 I/O ST RC5 can also be the SPI Data Out (SPI mode).
RC6 17 I/O ST
RC7 18 I/O ST
V
SS
8, 19 P — Ground reference for logic and I/O pins.
V
DD
20 P — Positive supply for logic and I/O pins.
Legend: I = input O = output I/O = input/output P = power
— = Not used TTL = TTL input ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2:
This buffer is a Schmitt Trigger input when used in serial programming mode.
3:
This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise
.
PIC16C72 Series
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 5
2.0 MEMORY ORGANIZATION
There are two memory blocks in PIC16C72 Series
devices. These are the program memory and the data
memory. Each block has its own bus, so that access to
both blocks can occur during the same oscillator cycle.
The data memory can further be broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
Additional information on device memory may be found
in the PICmicro™ Mid-Range Reference Manual,
DS33023.
2.1 Pr
ogram Memory Organization
PIC16C72 Series devices have a 13-bit program
counter capable of addressing a 2K x 14 program
memory space. The address range for this program
memory is 0000h - 07FFh. Accessing a location above
the physically implemented address will cause a wraparound.
The reset vector is at 0000h and the interrupt vector is
at 0004h.
FIGURE 2-1: PROGRAM MEMORY MAP
AND STACK
PC<12:0>
13
0000h
0004h
0005h
07FFh
1FFFh
Stack Level 1
Stack Level 8
Reset Vector
Interrupt Vector
On-chip Program
Memory
CALL, RETURN
RETFIE, RETLW
0800h
User Memory
Space
PIC16C72 Series
DS39016A-page 6
Preliminary
1998 Microchip Technology Inc.
2.2 Data Memory Organization
The data memory is partitioned into multiple banks
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.
= 00 → Bank0
= 01 → Bank1
= 10 → Bank2 (not implemented)
= 11 → Bank3 (not implemented)
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Abo ve the Special Function Registers are General Purpose Registers, implemented as
static RAM.
All implemented banks contain special function registers. Some “high use” special function registers from
one bank may be mirrored in another bank for code
reduction and quicker access (ex; the STATUS register
is in Bank 0 and Bank 1).
2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be accessed either directly or indi-
rectly through the File Select Register FSR
(Section 2.5).
FIGURE 2-2: REGISTER FILE MAP
RP1* RP0 (STATUS<6:5>)
*
Maintain this bit clear to ensure upward compatibility with future products.
INDF
(1)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRES
ADCON0
INDF
(1)
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
ADCON1
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
20h
A0h
General
Purpose
Register
General
Purpose
Register
7Fh
FFh
Bank 0 Bank 1
File
Address
BFh
C0h
Unimplemented data memory locations, read as '0'.
Note 1: Not a physical register.
File
Address
PIC16C72 Series
1998 Microchip Technology Inc.
Preliminary
DS39016A-page 7
2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
The special function registers can be classified into two
sets (core and peripheral). Those registers associated
with the “core” functions are described in this section,
and those related to the operation of the peripheral features are described in the section of that peripheral feature.
T ABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on all
other resets
(3)
Bank 0
00h
(1)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
01h TMR0 Timer0 module’s register
xxxx xxxx uuuu uuuu
02h
(1)
PCL Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
03h
(1)
STATUS
IRP
(4)
RP1
(4)
RP0 T
O PD Z DC C 0001 1xxx 000q quuu
04h
(1)
FSR Indirect data memory address pointer
xxxx xxxx uuuu uuuu
05h PORTA
— — PORTA Data Latch when written: PORTA pins when read
--0x 0000 --0u 0000
06h PORTB PORTB Data Latch when written: PORTB pins when read
xxxx xxxx uuuu uuuu
07h PORTC PORTC Data Latch when written: PORTC pins when read
xxxx xxxx uuuu uuuu
08h
— Unimplemented — —
09h — Unimplemented — —
0Ah
(1,2)
PCLATH
— — — Write Buffer for the upper 5 bits of the Program Counter
---0 0000 ---0 0000
0Bh
(1)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1
— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
0Dh
— Unimplemented — —
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register
0000 0000 0000 0000
12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register (LSB)
xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register (MSB)
xxxx xxxx uuuu uuuu
17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
18h-1Dh
— Unimplemented — —
1Eh ADRES A/D Result Register
xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR
and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear.
5: SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.
PIC16C72 Series
DS39016A-page 8
Preliminary
1998 Microchip Technology Inc.
Bank 1
80h
(1)
INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000
81h OPTION_REG RBPU
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
82h
(1)
PCL Program Counter's (PC) Least Significant Byte
0000 0000 0000 0000
83h
(1)
STATUS
IRP
(4)
RP1
(4)
RP0 T
O PD Z DC C
0001 1xxx 000q quuu
84h
(1)
FSR Indirect data memory address pointer
xxxx xxxx uuuu uuuu
85h TRISA
— — PORTA Data Direction Register
--11 1111 --11 1111
86h TRISB PORTB Data Direction Register
1111 1111 1111 1111
87h TRISC PORTC Data Direction Register
1111 1111 1111 1111
88h
— Unimplemented — —
89h — Unimplemented — —
8Ah
(1,2)
PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000
8Bh
(1)
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1 — ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
8Dh — Unimplemented — —
8Eh PCON — — — — — — POR BOR ---- --qq ---- --uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h — Unimplemented — —
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000
94h SSPSTAT SMP
(5)
CKE
(5)
D/A P S R/W UA BF 0000 0000 0000 0000
95h — Unimplemented — —
96h — Unimplemented — —
97h — Unimplemented — —
98h — Unimplemented — —
99h — Unimplemented — —
9Ah — Unimplemented — —
9Bh — Unimplemented — —
9Ch — Unimplemented — —
9Dh — Unimplemented — —
9Eh — Unimplemented — —
9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on all
other resets
(3)
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1: These registers can be addressed from either bank.
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
tents are transferred to the upper byte of the program counter.
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C72/CR72. Always maintain these bits clear.
5: SSPSTAT<7:6> are not implemented on the PIC16C72, read as '0'.
PIC16C72 Series
1998 Microchip Technology Inc. Preliminary DS39016A-page 9
2.2.2.1 STATUS REGISTER
The STATUS register, shown in Figure 2-3, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the T
O and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
For example, CLRF STATUS will clear the upper-three
bits and set the Z bit. This leaves the ST ATUS register
as 000u u1uu (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register because these instructions do not
affect the Z, C or DC bits from the STA TUS register . For
other instructions, not affecting any status bits, see the
"Instruction Set Summary."
FIGURE 2-3: STATUS REGISTER (ADDRESS 03h, 83h)
Note 1: These devices do not use bits IRP and
RP1 (STATUS<7:6>). Maintain these bits
clear to ensure upward compatibility with
future products.
Note 2: The C and DC bits operate as a borro
w
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x
IRP RP1 RP0 TO PD Z DC C R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes. For devices with only Bank0 and Bank1, the IRP bit is reserved. Always maintain
this bit clear.
bit 4: T
O: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3: PD
: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2: Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1: DC: Digit carry/borro
w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0: C: Carry/borro
w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)
1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred
Note: For borro
w the polarity is reversed. A subtraction is executed by adding the two’s complement of the
second operand. For rotate (RRF , RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.
PIC16C72 Series
DS39016A-page 10 Preliminary 1998 Microchip Technology Inc.
2.2.2.2 OPTION_REG REGISTER
The OPTION_REG register is a readable and writable
register which contains various control bits to configure
the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External
INT Interrupt, TMR0, and the weak pull-ups on POR TB.
FIGURE 2-4: OPTION_REG REGISTER (ADDRESS 81h)
Note: To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6: INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5: T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKOUT)
bit 4: T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3: PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0: PS2:PS0: Prescaler Rate Select bits
000
001
010
011
100
101
110
111
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
Bit Value TMR0 Rate WDT Rate
PIC16C72 Series
1998 Microchip Technology Inc. Preliminary DS39016A-page 11
2.2.2.3 INTCON REGISTER
The INTCON Register is a readable and writable regis-
ter which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and Exter nal
RB0/INT pin interrupts.
FIGURE 2-5: INTCON REGISTER (ADDRESS 0Bh, 8Bh)
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x
GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6: PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5: T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4: INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3: RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2: T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1: INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0: RBIF: RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
PIC16C72 Series
DS39016A-page 12 Preliminary 1998 Microchip Technology Inc.
2.2.2.4 PIE1 REGISTER
This register contains the individual enable bits for the
peripheral interrupts.
FIGURE 2-6: PIE1 REGISTER (ADDRESS 8Ch)
Note: Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIE — — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: Unimplemented: Read as '0'
bit 6: ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
bit 5-4: Unimplemented: Read as '0'
bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2: CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
PIC16C72 Series
1998 Microchip Technology Inc. Preliminary DS39016A-page 13
2.2.2.5 PIR1 REGISTER
This register contains the individual flag bits for the
Peripheral interrupts.
FIGURE 2-7: PIR1 REGISTER (ADDRESS 0Ch)
Note: Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— ADIF — — SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7: Unimplemented: Read as '0'
bit 6: ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
bit 5-4: Unimplemented: Read as '0'
bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
bit 2: CCP1IF: CCP1 Interrupt Flag bit
Capture Mode
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare Mode
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM Mode
Unused in this mode
bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
PIC16C72 Series
DS39016A-page 14 Preliminary 1998 Microchip Technology Inc.
2.2.2.6 PCON REGISTER
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR) to an external MCLR
Reset or WDT Reset.
Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset
condition from a Power-on Reset condition.
FIGURE 2-8: PCON REGISTER (ADDRESS 8Eh)
Note: BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent resets to see if BOR
is
clear, indicating a brown-out has occurred.
The BOR
status bit is a don't care and is
not necessarily predictable if the brown-out
circuit is disabled (by clearing the BODEN
bit in the Configuration word).
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q
— — — — — — POR BOR R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-2: Unimplemented: Read as '0'
bit 1: POR
: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0: BOR
: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
PIC16C72 Series
1998 Microchip Technology Inc. Preliminary DS39016A-page 15
2.3 PCL and PCLATH
The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits and is not directly readable or writable. All updates
to the PCH register go through the PCLATH register.
Figure 2-9 shows the four situations for the loading of
the PC. Example 1 shows how the PC is loaded on a
write to PCL (PCLATH<4:0> → PCH). Example 2
shows how the PC is loaded during a GOTO instruction
(PCLATH<4:3> → PCH). Example 3 shows how the PC
is loaded during a CALL instruction (PCLATH<4:3> →
PCH), with the PC loaded (PUSHed) onto the Top of
Stack. Finally, example 4 shows how the PC is loaded
during one of the return instructions where the PC is
loaded (POPed) from the Top of Stack.
FIGURE 2-9: LOADING OF PC IN DIFFERENT SITUATIONS
PC
12 8 7 0
5
PCLATH<4:0>
PCLATH
ALU result
Opcode <10:0>
8
PC
12 11 10 0
11
PCLATH<4:3>
PCH PCL
8 7
2
PCLATH
PCH PCL
Situation 1 - Instruction with PCL as destination
Situation 2 - GOTO Instruction
STACK (13-bits x 8)
Top of STACK
STACK (13-bits x 8)
Top of STACK
Opcode <10:0>
PC
12 11 10 0
11
PCLATH<4:3>
8 7
2
PCLATH
PCH PCL
Situation 3 - CALL Instruction
STACK (13-bits x 8)
Top of STACK
Opcode <10:0>
PC
12 11 10 0
11
8 7
PCLATH
PCH PCL
Situation 4 - RETURN, RETFIE, or RETLW Instruction
STACK (13-bits x 8)
Top of STACK
13
13
Note: PCLATH is not updated with the contents of PCH.
PIC16C72 Series
DS39016A-page 16 Preliminary 1998 Microchip Technology Inc.
2.3.1 STACK
The stack allows a combination of up to 8 program calls
and interrupts to occur. The stack contains the return
address from this branch in program execution.
Midrange devices have an 8 level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.
After the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on). An example of the overwriting of the stack is
shown in Figure 2-10.
FIGURE 2-10: STACK MODIFICATION
2.4 Program Memory Paging
The CALL and GOTO instructions provide 11 bits of
address to allow branching within any 2K program
memory page. When doing a CALL or GOTO instruction
the upper 2 bits of the address are provided by
PCLATH<4:3>. When doing a CALL or GOTO instruction,
the user must ensure that the page select bits are programmed so that the desired program memory page is
addressed. If a return from a CALL instruction (or interrupt) is executed, the entire 13-bit PC is pushed onto
the stack. Therefore, manipulation of the
PCLATH<4:3> bits are not required for the return
instructions (which POPs the address from the stack).
Push1 Push9
Push2 Push10
Push3
Push4
Push5
Push6
Push7
Push8
Top of STACK
STACK
Note: PIC16C72 Series devices ignore paging
bit PCLATH<4>. The use of PCLATH<4>
as a general purpose read/write bit is not
recommended since this may affect
upward compatibility with future products.
PIC16C72 Series
1998 Microchip Technology Inc. Preliminary DS39016A-page 17
2.5 Indirect Addressing, INDF and FSR
Registers
The INDF register is not a physical register. Addressing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a
pointer
). This is indirect addressing.
EXAMPLE 2-1: INDIRECT ADDRESSING
• Register file 05 contains the value 10h
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register
• A read of the INDF register will return the value of
10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDR register now will return the
value of 0Ah.
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2: HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
movlw 0x20 ;initialize pointer
movwf FSR ; to RAM
NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;NO, clear next
CONTINUE
: ;YES, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-11. However, IRP is not used in the
PIC16C72 Series.
FIGURE 2-11: DIRECT/INDIRECT ADDRESSING
Note 1: For register file map detail see Figure 2-2.
2: Maintain RP1 and IRP as clear for upward compatibility with future products.
3: Not implemented.
Data
Memory(1)
Indirect AddressingDirect Addressing
bank select location select
RP1:RP0 6
0
from opcode
IRP FSR register
7
0
bank select
location select
00 01 10 11
Bank 0 Bank 1 Bank 2 Bank 3
not used
FFh
80h
7Fh
00h
17Fh
100h
1FFh
180h
(2)
(2)
(3) (3)
PIC16C72 Series
DS39016A-page 18 Preliminary 1998 Microchip Technology Inc.
NOTES:
PIC16C72 Series
1998 Microchip Technology Inc. Preliminary DS39016A-page 19
3.0 I/O PORTS
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Additional information on I/O ports may be found in the
PICmicro™ Mid-Range MCU Reference Manual,
DS33023.
3.1 PORTA and the TRISA Register
PORTA is a 6-bit wide bi-directional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (=1) will make the corresponding PORTA pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISA bit (=0) will
make the corresponding PORTA pin an output, i.e., put
the contents of the output latch on the selected pin.
Reading the PORTA register reads the status of the
pins whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open drain output.
All other RA port pins have TTL input levels and full
CMOS output drivers.
Other PORTA pins are multiplexed with analog inputs
and analog V
REF input. The operation of each pin is
selected by clearing/setting the control bits in the
ADCON1 register (A/D Control Register1).
The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bits in the TRISA register are
maintained set when using them as analog inputs.
EXAMPLE 3-1: INITIALIZING PORTA
BCF STATUS, RP0 ;
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<5:4> as outputs
; TRISA<7:6> are always
; read as '0'.
FIGURE 3-1: BLOCK DIAGRAM OF
RA3:RA0 AND RA5 PINS
FIGURE 3-2: BLOCK DIAGRAM OF RA4/
T0CKI PIN
Note: On a Power-on Reset, these pins are con-
figured as analog inputs and read as '0'.
Data
bus
QD
Q
CK
QD
Q
CK
Q D
EN
P
N
WR
Port
WR
TRIS
Data Latch
TRIS Latch
RD TRIS
RD PORT
V
SS
VDD
I/O pin
(1)
Note 1: I/O pins have protection diodes to VDD and
VSS.
Analog
input
mode
TTL
input
buffer
To A/D Converter
Data
bus
WR
PORT
WR
TRIS
RD PORT
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
input
buffer
N
V
SS
I/O pin
(1)
TMR0 clock input
Note 1: I/O pin has protection diodes to V
SS only.
QD
Q
CK
QD
Q
CK
EN
Q D
EN
PIC16C72 Series
DS39016A-page 20 Preliminary 1998 Microchip Technology Inc.
TABLE 3-1 PORTA FUNCTIONS
TABLE 3-2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name Bit# Buffer Function
RA0/AN0 bit0 TTL Input/output or analog input
RA1/AN1 bit1 TTL Input/output or analog input
RA2/AN2 bit2 TTL Input/output or analog input
RA3/AN3/V
REF bit3 TTL Input/output or analog input or VREF
RA4/T0CKI bit4 ST Input/output or external clock input for Timer0
Output is open drain type
RA5/SS
/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input
Legend: TTL = TTL input, ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on all
other resets
05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 --0x 0000 --0u 0000
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
9Fh ADCON1
— — — — — PCFG2 PCFG1 PCFG0 ---- -000 ---- -000
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.
PIC16C72 Series
1998 Microchip Technology Inc. Preliminary DS39016A-page 21
3.2 PORTB and the TRISB Register
PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (=1) will make the corresponding PORTB pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISB bit (=0) will
make the corresponding PORTB pin an output, i.e., put
the contents of the output latch on the selected pin.
EXAMPLE 3-1: INITIALIZING PORTB
BCF STATUS, RP0 ;
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU
(OPTION<7>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disab led on a
Power-on Reset.
FIGURE 3-3: BLOCK DIAGRAM OF
RB3:RB0 PINS
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. an y RB7:RB4 pin configured as an output is excluded from the interrupt on
change comparison). The input pins (of RB7:RB4) are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the interrupt in the following manner:
a) Any read or write of PORTB. This will end the
mismatch condition.
b) Clear flag bit RBIF.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition, and
allow flag bit RBIF to be cleared.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
FIGURE 3-4: BLOCK DIAGRAM OF
RB7:RB4 PINS
Data Latch
RBPU
(2)
P
V
DD
QD
CK
QD
CK
Q D
EN
Data bus
WR Port
WR TRIS
RD TRIS
RD Port
weak
pull-up
RD Port
RB0/INT
I/O
pin
(1)
TTL
Input
Buffer
Note 1: I/O pins have diode protection to V
DD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU
bit (OPTION<7>).
Schmitt Trigger
Buffer
TRIS Latch
Data Latch
From other
RBPU
(2)
P
V
DD
I/O
QD
CK
QD
CK
Q D
EN
Q D
EN
Data bus
WR Port
WR TRIS
Set RBIF
TRIS Latch
RD TRIS
RD Port
RB7:RB4 pins
weak
pull-up
RD Port
Latch
TTL
Input
Buffer
pin
(1)
Note 1: I/O pins have diode protection to VDD and VSS.
ST
Buffer
RB7:RB6 in serial programming mode
Q3
Q1
2: To enable weak pull-ups, set the appropriate TRIS bit(s)
and clear the RBPU
bit (OPTION<7>).
PIC16C72 Series
DS39016A-page 22 Preliminary 1998 Microchip Technology Inc.
TABLE 3-3 PORTB FUNCTIONS
TABLE 3-4 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Name Bit# Buffer Function
RB0/INT bit0 TTL/ST
(1)
Input/output pin or external interrupt input. Internal software
programmable weak pull-up.
RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up.
RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up.
RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up.
RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable
weak pull-up.
RB6 bit6 TTL/ST
(2)
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming clock.
RB7 bit7 TTL/ST
(2)
Input/output pin (with interrupt on change). Internal software programmable
weak pull-up. Serial programming data.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in serial programming mode.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on all
other resets
06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu
86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
81h, 181h OPTION RBPU
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
PIC16C72 Series
1998 Microchip Technology Inc. Preliminary DS39016A-page 23
3.3 PORTC and the TRISC Register
PORTC is an 8-bit wide bi-directional port. The corresponding data direction register is TRISC. Setting a
TRISC bit (=1) will make the corresponding PORTC pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output, i.e., put
the contents of the output latch on the selected pin.
PORTC is multiplex ed with se v eral peripheral functions
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
EXAMPLE 3-1: INITIALIZING PORTC
BCF STATUS, RP0 ; Select Bank 0
CLRF PORTC ; Initialize PORTC by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0xCF ; Value used to
; initialize data
; direction
MOVWF TRISC ; Set RC<3:0> as inputs
; RC<5:4> as outputs
; RC<7:6> as inputs
FIGURE 3-5: PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE)
PORT/PERIPHERAL Select
(2)
Data bus
WR
PORT
WR
TRIS
RD
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
QD
Q
CK
Q D
EN
Peripheral Data Out
0
1
QD
Q
CK
P
N
V
DD
VSS
PORT
Peripheral
OE
(3)
Peripheral input
I/O
pin
(1)
Note 1: I/O pins have diode protection to VDD and VSS.
2: Port/Peripheral select signal selects between port
data and peripheral output.
3: Peripheral OE (output enable) is only activated if
peripheral select is active.
PIC16C72 Series
DS39016A-page 24 Preliminary 1998 Microchip Technology Inc.
TABLE 3-5 PORTC FUNCTIONS
TABLE 3-6 SUMMARY OF REGISTERS ASSOCIATED WITH PORTC
Name Bit# Buffer Type Function
RC0/T1OSO/T1CKI
bit0
ST Input/output port pin or Timer1 oscillator output/Timer1 clock input
RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input
RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1
output
RC3/SCK/SCL bit3 ST
RC3 can also be the synchronous serial clock for both SPI and I
2
C
modes.
RC4/SDI/SDA bit4 ST
RC4 can also be the SPI Data In (SPI mode) or data I/O (I
2
C mode).
RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output
RC6 bit6 ST Input/output port pin
RC7 bit7 ST Input/output port pin
Legend: ST = Schmitt Trigger input
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on all
other resets
07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu
87h TRISC PORTC Data Direction Register 1111 1111 1111 1111
Legend: x = unknown, u = unchanged.
PIC16C72 Series
1998 Microchip Technology Inc. Preliminary DS39016A-page 25
4.0 TIMER0 MODULE
The Timer0 module timer/counter has the following f eatures:
• 8-bit timer/counter
• Readable and writable
• Internal or external clock select
• Edge select for external clock
• 8-bit software programmable prescaler
• Interrupt on overflow from FFh to 00h
Figure 4-1 is a simplified block diagram of the Timer0
module.
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Reference Manual,
DS33023.
4.1 Timer0 Operation
Timer0 can operate as a timer or as a counter.
Timer mode is selected by clearing bit T0CS
(OPTION_REG<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is wr itten, the increment is
inhibited for the following two instruction cycles. The
user can work around this by writing an adjusted value
to the TMR0 register.
Counter mode is selected by setting bit T0CS
(OPTION_REG<5>). In counter mode, Timer0 will
increment either on every rising or falling edge of pin
RA4/T0CKI. The incrementing edge is determined by
the Timer0 Source Edge Select bit T0SE
(OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are
discussed in below.
When an external clock input is used for Timer0, it must
meet certain requirements. The requirements ensure
the external clock can be synchronized with the internal
phase clock (T
OSC). Also, there is a delay in the actual
incrementing of Timer0 after synchronization.
Additional information on external clock requirements
is available in the PICmicro™ Mid-Range MCU Reference Manual, DS33023.
4.2 Prescaler
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer, respectively (Figure 4-2). For simplicity, this
counter is being referred to as “prescaler” throughout
this data sheet. Note that there is only one prescaler
available which is m utually e xclusiv ely shared between
the Timer0 module and the Watchdog Timer. Thus, a
prescaler assignment for the Timer0 module means
that there is no prescaler for the Watchdog Timer, and
vice-versa.
The prescaler is not readable or writable.
The PSA and PS2:PS0 bits (OPTION_REG<3:0>)
determine the prescaler assignment and prescale ratio.
Clearing bit PSA will assign the prescaler to the Timer0
module. When the prescaler is assigned to the Timer0
module, prescale values of 1:2, 1:4, ..., 1:256 are
selectable.
Setting bit PSA will assign the prescaler to the Watchdog Timer (WDT). When the prescaler is assigned to
the WDT, prescale values of 1:1, 1:2, ..., 1:128 are
selectable.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,
BSF 1,x....etc.) will clear the prescaler. When assigned
to WDT , a CLRWDT instruction will clear the prescaler
along with the WDT.
FIGURE 4-1: TIMER0 BLOCK DIAGRAM
Note: Writing to TMR0 when the prescaler is
assigned to Timer0 will clear the prescaler
count, but will not change the prescaler
assignment.
Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>).
2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram).
RA4/T0CKI
T0SE
0
1
1
0
pin
T0CS
FOSC/4
Programmable
Prescaler
Sync with
Internal
clocks
TMR0
PSout
(2 cycle delay)
PSout
Data bus
8
PSA
PS2, PS1, PS0
Set interrupt
flag bit T0IF
on overflow
3
PIC16C72 Series
DS39016A-page 26 Preliminary 1998 Microchip Technology Inc.
4.2.1 SWITCHING PRESCALER ASSIGNMENT
The prescaler assignment is fully under software con-
trol, i.e., it can be changed “on the fly” during program
execution.
4.3 Timer0 Interrupt
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit
T0IF (INTCON<2>). The interr upt can be masked by
clearing bit T0IE (INTCON<5>). Bit T0IF must be
cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0
interrupt cannot awaken the processor from SLEEP
since the timer is shut off during SLEEP.
FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TABLE 4-1 REGISTERS ASSOCIATED WITH TIMER0
Note: To avoid an unintended device RESET, a
specific instruction sequence (shown in the
PICmicro™ Mid-Range MCU Reference
Manual, DS3023) must be executed when
changing the prescaler assignment from
Timer0 to the WDT. This sequence must be
followed even if the WDT is disabled.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on all
other resets
01h,101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu
0Bh,8Bh,
10Bh,18Bh
INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
81h,181h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111
85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.
RA4/T0CKI
T0SE
pin
M
U
X
CLKOUT (=Fosc/4)
SYNC
2
Cycles
TMR0 reg
8-bit Prescaler
8 - to - 1MUX
M
U
X
M U X
Watchdog
Timer
PSA
0
1
0
1
WDT
Time-out
PS2:PS0
8
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).
PSA
WDT Enable bit
M
U
X
0
1
0
1
Data Bus
Set flag bit T0IF
on Overflow
8
PSA
T0CS
PIC16C72 Series
1998 Microchip Technology Inc. Preliminary DS39016A-page 27
5.0 TIMER1 MODULE
The Timer1 module timer/counter has the following f eatures:
• 16-bit timer/counter
(Two 8-bit registers; TMR1H and TMR1L)
• Readable and writable (Both registers)
• Internal or external clock select
• Interrupt on overflow from FFFFh to 0000h
• Reset from CCP module trigger
Timer1 has a control register, shown in Figure 5-1.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Figure 5-2 is a simplified block diagram of the Timer1
module.
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Reference Manual,
DS33023.
5.1 Timer1 Operation
Timer1 can operate in one of these modes:
• As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
In timer mode, Timer1 increments every instruction
cycle. In counter mode, it increments on every rising
edge of the external clock input.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins
become inputs. That is, the TRISC<1:0> value is
ignored.
Timer1 also has an internal “reset input”. This reset can
be generated by the CCP module (Section 7.0).
FIGURE 5-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
R = Readable bit
W = Writable bit
U = Unimplemented bit,
read as ‘0’
- n = Value at POR reset
bit7 bit0
bit 7-6: Unimplemented: Read as '0'
bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut off
Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain
bit 2: T1SYNC
: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1: TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge)
0 = Internal clock (F
OSC/4)
bit 0: TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
PIC16C72 Series
DS39016A-page 28 Preliminary 1998 Microchip Technology Inc.
FIGURE 5-2: TIMER1 BLOCK DIAGRAM
TMR1H
TMR1L
T1OSC
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
SLEEP input
T1OSCEN
Enable
Oscillator
(1)
FOSC/4
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
0
1
Synchronized
clock input
2
RC0/T1OSO/T1CKI
RC1/T1OSI
Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
Set flag bit
TMR1IF on
Overflow
TMR1
PIC16C72 Series
1998 Microchip Technology Inc. Preliminary DS39016A-page 29
5.2 Timer1 Oscillator
A crystal oscillator circuit is built in between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will
continue to run during SLEEP. It is primarily intended
for a 32 kHz crystal. Table 5-1 shows the capacitor
selection for the Timer1 oscillator.
The Timer1 oscillator is identical to the LP oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
TABLE 5-1 CAPACITOR SELECTION
FOR THE TIMER1
OSCILLATOR
5.3 Timer1 Interrupt
The TMR1 Register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
TMR1 Interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR1IF (PIR1<0>).
This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
5.4 Resetting Timer1 using a CCP Trigger
Output
If the CCP module is configured in compare mode to
generate a “special event trigger" (CCP1M3:CCP1M0
= 1011), this signal will reset Timer1 and start an A/D
conversion (if the A/D module is enabled).
Timer1 must be configured for either timer or synchronized counter mode to take advantage of this f eature. If
Timer1 is running in asynchronous counter mode, this
reset operation may not work.
In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence.
In this mode of operation, the CCPR1H:CCPR1L registers pair effectively becomes the period register for
Timer1.
TABLE 5-2 REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Osc Type Freq C1 C2
LP 32 kHz 33 pF 33 pF
100 kHz 15 pF 15 pF
200 kHz 15 pF 15 pF
These values are for design guidance only.
Crystals Tested:
32.768 kHz Epson C-001R32.768K-A ± 20 PPM
100 kHz Epson C-2 100.00 KC-P ± 20 PPM
200 kHz STD XTL 200.000 kHz ± 20 PPM
Note 1: Higher capacitance increases the stability
of oscillator but also increases the start-up
time.
2: Since each resonator/crystal has its own
characteristics, the user should consult the
resonator/crystal manufacturer for appropriate values of external components.
Note: The special event triggers from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on:
POR,
BOR
Value on
all other
resets
0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF
0000 000x 0000 000u
0Ch PIR1
(1)
ADIF
(1) (1)
SSPIF CCP1IF TMR2IF TMR1IF
0000 0000 0000 0000
8Ch PIE1
(1)
ADIE
(1) (1)
SSPIE CCP1IE TMR2IE TMR1IE
0000 0000 0000 0000
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register
xxxx xxxx uuuu uuuu
10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
--00 0000 --uu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module.
Note 1: These bits are unimplemented, read as '0'.
PIC16C72 Series
DS39016A-page 30 Preliminary 1998 Microchip Technology Inc.
NOTES:
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