Microchip Technology Inc PIC16C717-I-SO, PIC16C717-I-SS, PIC16C717-JW, PIC16C717-P, PIC16C717-SO Datasheet



1999 Microchip Technology Inc.

Advanced Information DS41120A-page 1

Microcontroller Core Features:

• High-performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program
branches which are two cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• Interrupt capability (up to 10 internal/external
interrupt sources)

• Eight level deep hardware stack

• Direct, indirect and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) and
Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC
oscillator for reliable operation

• Selectable oscillator options:

- INTRC - Internal RC, dual speed (4MHz and

37KHz) dynamically switchab le for power sa v­ings

- ER - External resistor, dual speed (user

selectable frequency and 37KHz) dynami­cally switchable for power savings

- EC - External clock

- HS - High speed crystal/resonator

- XT - Crystal/resonator

- LP - Low power crystal

• Low-power, high-speed CMOS EPROM
technology

• In-Circuit Serial Programming™ (ISCP)

• Wide operating voltage range: 2.5V to 5.5V

• 15 I/O pins with individual control for:

- Direction (15 pins)

- Digital/Analog input (6 pins)

- PORTB interrupt on change (8 pins)

- PORTB weak pull-up (8 pins)

- High voltage open drain (1 pin)

• Commercial and Industrial temperature ranges

• Low-power consumption:

- < 2 mA @ 5V, 4 MHz

- 22.5 µA typical @ 3V, 32 kHz

-< 1 µA typical standby current

Pin Diagram

Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• Timer1: 16-bit timer/counter with prescaler,
can be incremented during sleep via ex ternal
crystal/clock

• Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler

• Enhanced Capture, Compare, PWM (ECCP)
module

- Capture is 16 bit, max. resolution is 12.5 ns

- Compare is 16 bit, max. resolution is 200 ns

- PWM max. resolution is 10 bit

- Enhanced PWM:

- Single, Half-Bridge and Full-Bridge output
modes

- Digitally prog rammable deadba nd del ay

• Analog-to-Digital converter:

- PIC16C770/771 12-bit resolution

- PIC16C717 10-bit resolution

• On-chip absolute bandgap voltage reference
generator

• Programmable Brown-out Reset (PBOR)
circuitry

• Programmable Low-Voltage Detection (PLVD)
circuitry

• Master Synchronous Serial Port (MSSP) with two
modes of operation:

- 3-wire SPI™ (supports all 4 SPI modes)

-I

2

C™ compatible including master mode

support

• Program Memory Read (PMR) capability for look­up table, character string storage and checksum
calculation purposes

Device

Memory

Pins

A/D

Resolution

A/D

Channels

Program

x14

Data

x8

PIC16C717 2K 256 18, 20 10 bits 6
PIC16C770 2K 256 20 12 bits 6
PIC16C771 4K 256 20 12 bits 6

RB3/CCP1/P1A
RB2/SCK/SCL
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD

RB7/T1OSI/P1D
RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B
RB4/SDI/SDA

RA0/AN0

RA1/AN1/LVDIN

RA4/T0CKI

RA5/MCLR/VPP

VSS

RA2/AN2/VREF-/VRL

RA3/AN3/VREF+/VRH

RB0/AN4/INT

RB1/AN5/SS

1
2
3
4
5
6
7
8
9

20
19
18
17
16
15
14
13
12

AVDD

AVSS

10

11

PIC16C770/771

20-Pin PDIP, SOIC, SSOP

PIC16C717/770/771

18/20-Pin, 8-Bit CMOS Microcontrollers with 10/12-Bit A/D

PIC16C717/770/771

DS41120A-page 2 Advanced Information 

1999 Microchip Technology Inc.

Pin Diagrams

18-Pin PDIP, SOIC

RB3/CCP1/P1A
RB2/SCK/SCL
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD
RB7/T1OSI/P1D

RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B
RB4/SDI/SDA

RA0/AN0

RA1/AN1/LVDIN

RA4/T0CKI

RA5/MCLR/VPP

VSS

RA2/AN2/VREF-/VRL

RA3/AN3/VREF+/VRH

RB0/AN4/INT

RB1/AN5/SS

1
2
3
4
5
6
7
8
9

18
17
16
15
14
13
12
11
10

PIC16C717

RB3/CCP1/P1A
RB2/SCK/SCL
RA7/OSC1/CLKIN
RA6/OSC2/CLKOUT
VDD

(2)

RB7/T1OSI/P1D
RB6/T1OSO/T1CKI/P1C
RB5/SDO/P1B

RB4/SDI/SDA

RA0/AN0

RA1/AN1/LVDIN

RA4/T0CKI

RA5/MCLR/VPP

VSS

(1)

RA2/AN2/VREF-/VRL

RA3/AN3/VREF+/VRH

RB0/AN4/INT

RB1/AN5/SS

1
2
3
4
5
6
7
8
9

20
19
18
17
16
15
14
13
12

PIC16C717

VDD

(2)

VSS

(1)

10

11

20-Pin SSOP

Note 1: VSS pins 5 and 6 must be tied together.

2: V

DD pins 15 and 16 must be tied together.

Key Features

PICmicroTM Mid-Range Reference Manual

(DS33023)

PIC16C717 PIC16C770 PIC16C771

Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz
Resets (and Delays)

POR, BOR, MCLR,
WDT (PWRT, OST)

POR, BOR, MCLR,
WDT (PWRT, OST)

POR, BOR, MCLR,

WDT (PWRT, OST)
Program Memory (14-bit words) 2K 2K 4K
Data Memor y (bytes) 256 256 256
Interrupts 10 10 10
I/O Ports Ports A,B Ports A,B Ports A,B
Timers 333
Enhanced Capture/Compare/PWM (ECCP)

modules

111

Serial Communications MSSP MSSP MSSP
12-bit Analog-to-Dig i tal Module  6 input channels 6 input channels
10-bit Analog-to-Digital Module 6 input channels 
Instruction Set 35 Instructions 35 Instructions 35 Instructions

PIC16C717/770/771



1999 Microchip Technology Inc.

Advanced Information DS41120A-page 3

Table of Contents

1.0 Device Overv iew............................................................. .................................. ..... ...... ..... ...... ..............................5

2.0 Memory Organization..........................................................................................................................................11

3.0 I/O Ports..............................................................................................................................................................27

4.0 Program Memory Read (PMR)...........................................................................................................................43

5.0 Timer0 Module....................................................................................................................................................47

6.0 Timer1 Module....................................................................................................................................................49

7.0 Timer2 Module....................................................................................................................................................53

8.0 Enhanced Capture/Compare/PWM(ECCP) Modules .........................................................................................55

9.0 Master Synchronous Serial Port (MSSP) Module...............................................................................................67

10.0 Voltage Reference Module and Low-voltage Detect.........................................................................................109

11.0 Analog-to-Digital Converter (A/D) Module ........................................................................................................113

12.0 Special Features of the CPU............................................................................................................................125

13.0 Instruction Set Summary...................................................................................................................................141

14.0 Development Support.......................................................................................................................................149

15.0 Electrical Characteristics..................... .................................. ..... ...... ..... ...... ...... ................................. ...... ..... ....155

16.0 DC and AC Characteristics Graphs and Tables...............................................................................................177

17.0 Packaging Information......................................................................................................................................179

Revision History ........................................................................................................................................................189

Device Differences ............................................................. ...... ...... ..... ...... ..... .................................. ...... ..... ...... .........189

Index .......................................................................................................................................................................... 191

On-Line Support..........................................................................................................................................................197

Reader Response.......................................................................................................................................................198

PIC16C717/770/771 Product Identification System....................................................................................................199

To Our Valued Customers

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We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure
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We appreciate your assistance in making this a better document.

PIC16C717/770/771

DS41120A-page 4 Advanced Information 

1999 Microchip Technology Inc.

NOTES:

PIC16C717/770/771



1999 Microchip Technology Inc.

Advanced Information DS41120A-page 5

1.0 DEVICE OVERVIEW

This document contains device-specific information.
Additional information may be found in the PICmicro

TM

Mid-Range Reference Manual, (DS33023), which may
be obtained from your local Microchip Sales Represen­tative or downloaded from the Microchip website. The
Reference Manual should be considered a comple­mentary document to this data she et, and is high ly rec­ommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.

There are three devices (PIC16C717, PIC16C770 and
PIC16C771) covered by this datasheet. The
PIC16C717 device comes in 18/20-pin packages and
the PIC16C770/771 devices come in 20-pin packages.

The following two fig u res a r e device blo ck di agr am s o f
the PIC16C717 and the PIC16C770/771.

FIGURE 1-1: PIC16C717 BLOCK DIAGRAM

EPROM
Program

Memory

2K x 14

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

256 x 8

Direct Addr

7

Addr

(1)

9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Tim er

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKIN
OSC2/CLKOUT

V

DD, VSS

PORTA

PORTB

RA4/T0CKI

RB0/AN4/INT

RB4/SDI/SDA

8

8

Brown-out

Reset

Note 1: Higher order bits are from the STATUS register.

Enhanced CCP

Master

Timer0 Timer1 Timer2

Synchronous

RA3/AN3/VREF+/VRH

RA2/AN2/VREF-/VRL

RA1/AN1/LVDIN

RA0/AN0

8

3

Timing

Generation

10-bit

ADC

RB1/AN5/SS
RB2/SCK/SCL
RB3/CCP1/P1A

RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN

RB5/SDO/P1B
RB6/T1OSO/T1CKI/P1C
RB7/T1OSI/P1O

Internal
4MHz, 37KHz
and ER mode

(ECCP1)

Serial Port (MSSP)

Bandgap
Reference

Low-voltage

Detect

RAM

Program Memory

Read (PMR)

PIC16C717/770/771

DS41120A-page 6 Advanced Information 

1999 Microchip Technology Inc.

FIGURE 1-2: PIC16C7 70/7 71 BLOCK DIAGRAM

EPROM
Program

Memory

(2)

13

Data Bus

8

14

Program

Bus

Instruction reg

Program Counter

8 Lev el Stack

(13-bit)

RAM

File

Registers

256 x 8

Direct Addr

7

Addr

(1)

9

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

OSC1/CLKIN
OSC2/CLKOUT

V

DD, VSS

PORTA

PORTB

RA4/T0CKI

RB0/AN4/INT

RB4/SDI/SDA

8

8

Brown-out

Reset

Note 1: Higher order bits are from the STATUS register.

2: Program memory for PIC16C770 is 2K x 14. Program memory for PIC16C771 is 4K x 14.

Enhanced CCP

Master

Timer0 Timer1 Timer2

Synchronous

RA3/AN3/VREF+/VRH

RA2/AN2/VREF-/VRL

RA1/AN1/LVDIN

RA0/AN0

8

3

Timing

Generation

12-bit

ADC

RB1/AN5/SS
RB2/SCK/SCL
RB3/CCP1/P1A

RA5/MCLR/VPP
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN

RB5/SDO/P1B
RB6/T1OSO/T1CKI/P1C
RB7/T1OSI/P1O

Internal

4MHz, 37KHz
and ER mode

(ECCP1)

Serial Port (MSSP)

Bandgap

Reference

Low-voltage

Detect

RAM

Program Memory

Read (PMR)

AVDD
AVSS

PIC16C717/770/771



1999 Microchip Technology Inc.

Advanced Information DS41120A-page 7

TABLE 1-1: PIC16C770/771 PINOUT DESCRIPTION

Name Function

Input

Type

Output

Type

Description

RA0/AN0

RA0 ST CMOS Bi-directional I/O
AN0 AN A/D input

RA1/AN1/LVDIN

RA1 ST CMOS Bi-directional I/O
AN1 AN A/D input

LV DI N AN LVD input reference

RA2/AN2/V

REF-/VRL

RA2 ST CMOS Bi-directional I/O
AN2 AN A/D input

V

REF- AN Negative analog reference input

VRL AN Internal voltage reference low output

RA3/AN3/V

REF+/VRH

RA3 ST CMOS Bi-directional I/O
AN3 AN A/D input

V

REF+ AN Positive analog reference input

VRH AN Internal voltage reference high output

RA4/T0CKI

RA4 ST OD Bi-directional I/O

T0CKI ST TMR0 clock input

RA5/MCLR

/VPP

RA5 ST Input por t

MCLR

ST Master clear

V

PP Power Programming voltage

RA6/OSC2/CLKOUT

RA6 ST CMOS Bi-directional I/O

OSC2 XTAL Crystal/resonator

CLKOUT CMOS F

OSC/4 output

RA7/OSC1/CLKIN

RA7 ST CMOS Bi-directional I/O
OSC1 XTA L Crystal/resonator
CLKIN ST External clock input/ER resistor connection

RB0/AN4/INT

RB0 TTL CMOS Bi-directional I/O

(1)

AN4 AN A/D input

INT ST Interrupt input

RB1/AN5/SS

RB1 TTL CMOS Bi-directional I/O

(1)

AN5 AN A/D input

SS

ST SSP slave select input

RB2/SCK/SCL

RB2 TTL CMOS Bi-directional input

(1)

SCK ST CMOS Serial clock I/O for SPI

SCL ST OD Serial clock I/O for I

2

C

RB3/CCP1/P1A

RB3 TTL CMOS Bi-directional input

(1)

CCP1 ST CMOS Capture 1 input/Compare 1 output

P1A CMOS PWM P1A output

RB4/SDI/SDA

RB4 TTL CMOS Bi-directional input

(1)

SDI ST Serial data in for SPI

SDA ST OD Serial data I/O for I

2

C

RB5/SDO/P1B

RB5 ST CMOS Bi-directional I/O

(1)

SDO CMOS Serial data out for SPI

P1B CMOS PWM P1B output

Note 1: Bit programmable pull-ups.

PIC16C717/770/771

DS41120A-page 8 Advanced Information 

1999 Microchip Technology Inc.

RB6/T1OSO/T1CKI/P1C

RB6 TTL CMOS Bi-directional I/O

(1)

T1OSO XTAL Crystal/Resonator

T1CKI ST TMR1 clock input

P1C CMOS PWM P1C output

RB7/T1OSI/P1D

RB7 TTL CMOS Bi-directional I/O

(1)

T1OSI XTAL TMR1 crystal/resonator

P1D CMOS PWM P1D output

V

SS VSS Power Ground reference for logic and I/O pins

V

DD VDD Power Positive supply for logic and I/O pins

AV

SS AVSS Power Ground reference for analog

AV

DD AVDD Power Positive supply for analog

TABLE 1-1: PIC16C770/771 PINOUT DESCRIPTION (CONTINUED)

Name Function

Input

Type

Output

Type

Description

Note 1: Bit programmable pull-ups.

PIC16C717/770/771



1999 Microchip Technology Inc.

Advanced Information DS41120A-page 9

TABLE 1-2: PIC16C717 PINOUT DESCRIPTION

Name Function

Input

Type

Output

Type

Description

RA0/AN0

RA0 ST CMOS Bi-directional I/O
AN0 AN A/D input

RA1/AN1/LVDIN

RA1 ST CMOS Bi-directional I/O
AN1 AN A/D input reference

LVDIN AN LVD input reference

RA2/AN2/V

REF-/VRL

RA2 ST CMOS Bi-directional I/O
AN2 AN A/D input

V

REF- AN Negative analog reference input

VRL AN Internal voltage reference low output

RA3/AN3/V

REF+/VRH

RA3 ST CMOS Bi-directional I/O
AN3 AN A/D input

V

REF+ AN Positive analog reference high output

VRH AN Internal voltage reference high output

RA4/T0CKI

RA4 ST OD Bi-directional I/O

T0CKI ST TMR0 clock input

RA5/MCLR

/VPP

RA5 ST Input port

MCLR

ST Master Clear

V

PP Power Programming Voltage

RA6/OSC2/CLKOUT

RA6 ST CMOS Bi-directional I/O

OSC2 XTAL Crystal/Resonator

CLKOUT CMOS F

OSC/4 output

RA7/OSC1/CLKIN

RA7 ST CMOS Bi-directional I/O

OSC1 XTAL Crystal/Resonator

CLKIN ST External clock input/ER resistor connection

RB0/AN4/INT

RB0 TTL CMOS Bi-directional I/O

(1)

AN4 AN A/D input

INT ST Interrupt input

RB1/AN5/SS

RB1 TTL CMOS Bi-directional I/O

(1)

AN5 AN A/D input

SS

ST SSP slave select input

RB2/SCK/SCL

RB2 TTL CMOS Bi-directional input

(1)

SCK ST CMOS Ser ial clock I/O for SPI
SCL ST OD Serial clock I/O for I

2

C

RB3/CCP1/P1A

RB3 TTL CMOS Bi-directional input

(1)

CCP1 ST CMOS Capture 1 input/Compare 1 output

P1A CMOS PWM P1A output

RB4/SDI/SDA

RB4 TTL CMOS Bi-directional input

(1)

SDI ST Serial data in for SPI

SDA ST OD Serial data I/O for I

2

C

RB5/SDO/P1B

RB5 ST CMOS Bi-directional I/O

(1)

SDO CMOS Serial data out for SPI
P1B CMOS PWM P1B output

Note 1: Bit programmable pull-ups.

PIC16C717/770/771

DS41120A-page 10 Advanced Information 

1999 Microchip Technology Inc.

RB6/T1OSO/T1CKI/P1C

RB6 TTL CMOS Bi-directional I/O

(1)

T1OSO XTAL TMR1 Crystal/Resonator

T1CKI ST TMR1 Clock input

P1C CMOS PWM P1C output

RB7/T1OSI/P1D

RB7 TTL CMOS Bi-directional I/O

(1)

T1OSI XTAL TMR1 Crystal/Resonator

P1D CMOS PWM P1D output

V

SS VSS Power Ground

V

DD VDD Power Positiv e Supply

TABLE 1-2: PIC16C717 PINOUT DESCRIPTION (CONTINUED)

Name Function

Input

Type

Output

Type

Description

Note 1: Bit programmable pull-ups.

PIC16C717/770/771



1999 Microchip Technology Inc.

Advanced Information DS41120A-page 11

2.0 MEMORY ORGANIZATION

There are two memory blocks in each of these
PICmicro

®

microcontrollers. Each block (Pro­gram Memory and Data Memory) has its own bu s,
so that concurrent access can occur.

Additional inf ormation on de vice m emory may be f ound
in the PICmicro Mid-Range Reference Manual,
(DS33023).

2.1 Program Memory Organization

The PIC16C717/770/771 devices have a 13-bit pro­gram counter capable of addressing an 8K x 14 pro­gram memory space. The PIC16C717 and the
PIC16C770 have 2K x 14 words of program memory.
The PIC16C771 has 4K x 14 words of program mem­ory. Accessing a location above the physically imple­mented address will cause a wraparound.

The reset vector is at 0000h and the interrupt vector is
at 0004h.

FIGURE 2-1: PROGRAM MEMORY MAP

AND STACK OF THE
PIC16C717 AND PIC16C770

FIGURE 2-2: PROGRAM MEMORY MAP

AND STACK OF THE
PIC16C771

2.2 Data Memory Organization

The data memory is partitioned into multiple banks,
which contain the General Purpose Registers and the
Special Function Registers. Bits RP1 and RP0 are the
bank select bits.

= 00 → Bank0
= 01 → Bank1
= 10 → Bank2
= 11 → Bank3

Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers . Abo v e the Spec ial Fun ction Re gis­ters are General Purpose Registers, implemented as
static RAM. All implemented banks contain special
function registers. Some frequently used special func­tion registers from one bank are mirrored in another
bank for code reduction and quicker access.

2.2.1 GENERAL PURPOSE REGISTER FILE
The register file can be a ccessed ei ther direc tly, or indi-

rectly, through the File Select Register FSR.

PC<12:0>

13

0000h

0004h
0005h

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip

CALL, RETURN
RETFIE, RETLW

Stack Level 2

Program

Memory

Page 0

07FFh

3FFFh

RP1 RP0 (STATUS<6:5>)

PC<12:0>

13

0000h

0004h
0005h

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip

CALL, RETURN
RETFIE, RETLW

Stack Level 2

Program

Memory

Page 0

Page 1

07FFh
0800h

0FFFh
1000h

3FFFh

PIC16C717/770/771

DS41120A-page 12 Advanced Information 

1999 Microchip Technology Inc.

FIGURE 2-3: REGISTER FILE MAP

Indirect addr.

(*)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH
INTCON

PIR1

TMR1L
TMR1H
T1CON

TMR2

T2CON

SSPBUF
SSPCON

CCPR1L

CCPR1H

CCP1CON

OPTION_REG

PCL

STATUS

FSR
TRISA
TRISB

PCLATH
INTCON

PIE1

PCON

PR2

SSPADD

SSPSTAT

00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh

80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh

20h

A0h

7Fh

FFh

Bank 0 Bank 1

Unimplemented data memory locations, read as ’0’.

* Not a physical register.

Indirect addr.

(*)

ADRESL

PIR2

PIE2

ADRESH
ADCON0

ADCON1

General
Purpose
Register

General
Purpose
Register

EFh
F0h

accesses

70h-7Fh

96 Bytes

80 Bytes

LVDCON

100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
120h

17Fh

Bank 2

6Fh
70h

File

Address

PCL

STATUS

FSR

PCLATH
INTCON

180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
191h
192h
193h
194h
195h
196h
197h
198h
199h
19Ah
19Bh
19Ch
19Dh
19Eh
19Fh

1A0h

1FFh

Bank 3

Indirect addr.

(*)

OPTION_REG

1EFh
1F0h

accesses
70h - 7Fh

TRISB

PCL

STATUS

FSR

PCLATH

INTCON

Indirect addr.

(*)

TMR0

General
Purpose
Register

accesses
70h - 7Fh

PORTB

80 Bytes

File

Address

File

Address

File

Address

REFCON

SSPCON2

WPUB

IOCB

ANSEL

P1DEL

PMDATL

PMADRL

PMDATH

PMADRH

PMCON1

PIC16C717/770/771



1999 Microchip Technology Inc.

Advanced Information DS41120A-page 13

2.2.2 SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.

The special fu nction re gisters can be classifi ed into two
sets; core (CPU) and periphe ral. Those registers asso­ciated with the core functions are described in detail in
this section. Those related to the operation of the
peripheral features are described in detail in that
peripheral feature section.

TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other resets

(2)

Bank 0

00h

(3)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

02h

(3)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

03h

(3)

ST ATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

04h

(3)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
05h PORTA RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx 0000 uuuu 0000
06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xx00 uuuu uu00
07h — Unimplemented — —
08h — Unimplemented — —
09h — Unimplemented — —
0Ah

(1,3)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
0Bh

(3)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
0Ch PIR1

—ADIF— — SSPIF CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000

0Dh PIR2 LVDIF

— — —BCLIF— — — 0--- 0--- 0--- 0---
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu
10h T1CON

— — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
11h TMR2 Timer2 module’s register 0000 0000 0000 0000
12h T2CON

— TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuuu
16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuuu
17h CCP1CON PWM1M1 PWM1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 0000 0000 0000 0000
18h — Unimplemented — —
19h — Unimplemented — —
1Ah — Unimplemented — —
1Bh — Unimplemented — —
1Ch — Unimplemented — —
1Dh — Unimplemented — —
1Eh ADRESH A/D High Byte Result Register xxxx xxxx uuuu uuuu
1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE

CHS3 ADON 0000 0000 0000 0000

Legend:x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.

2: Other (non power-up) resets include external reset through MCLR

and Watchdog Timer Reset.

3: These registers can be addressed from any bank.

PIC16C717/770/771

DS41120A-page 14 Advanced Information 

1999 Microchip Technology Inc.

Bank 1

80h

(3)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

81h OPTION_REG RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

82h

(3)

PCL Program Counter’s (PC) Least Significant Byte 0000 0000 0000 0000

83h

(3)

ST ATUS IRP RP1 RP0 TO PD ZDCC0001 1xxx 000q quuu

84h

(3)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
85h TRISA PORTA Data Direction Register 1111 1111 1111 1111
86h TRISB PORTB Data Direction Register 1111 1111 1111 1111
87h — Unimplemented — —

88h — Unimplemented — —
89h — Unimplemented — —
8Ah

(1,3)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000
8Bh

(3)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
8Ch PIE1

—ADIE — — SSPIE CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000

8Dh PIE2 LVDIE

— — —BCLIE— — — 0--- 0--- 0--- 0---

8Eh PCON

— — — —OSCF—PORBOR ---- 1-qq ---- 1-uu
8Fh — Unimplemented — —
90h — Unimplemented — —
91h SSPCON2 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN 0000 0000 0000 0000
92h PR2 Timer2 Period Register 1111 1111 1111 1111
93h SSPADD Synchronous Serial Port (I

2

C mode) Address Register 0000 0000 0000 0000

94h SSPSTAT SMP CKE D/A

PSR/WUA BF 0000 0000 0000 0000
95h WPUB PORTB Weak Pull-up Control 1111 1111 1111 1111
96h IOCB PORTB Interrupt on Change Control 1111 0000 1111 0000

97h P1DEL PWM 1 Delay value 0000 0000 0000 0000

98h — Unimplemented — —
99h — Unimplemented — —
9Ah — Unimplemented — —
9Bh REFCON VRHEN VRLEN VRHOEN VRLOEN

— — — — 0000 ---- 0000 ----

9Ch LVDCON

— — BGST LVDEN LVV3 LVV2 LVV1 LVV0 --00 0101 --00 0101

9Dh ANSEL

Analog Channel Select

1111 1111 1111 1111

9Eh ADRESL A/D Low Byte Result Register xxxx xxxx uuuu uuuu
9Fh ADCON1 ADFM VCFG2 VCFG1 VCFG0

0000 0000 0000 0000

TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other resets

(2)

Legend:x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.

2: Other (non power-up) resets include external reset through MCLR

and Watchdog Timer Reset.

3: These registers can be addressed from any bank.

PIC16C717/770/771



1999 Microchip Technology Inc.

Advanced Information DS41120A-page 15

Bank 2

100h

(3)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

101h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu

102h

(3)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

103h

(3)

STATUS I RP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu

104h

(3)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

105h — Unimplemented — —
106h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xx00 uuuu uu00
107h — Unimplemented — —
108h — Unimplemented — —
109h — Unimplemented — —

10Ah

(1,3)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

10Bh

(3)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

10Ch PMDATL Program memory read data low xxxx xxxx uuuu uuuu
10Dh PMADRL Program memory read address low xxxx xxxx uuuu uuuu
10Eh PMDATH

— — Program memory read data high - -xx xxxx --uu uuuu

10Fh PMADRH

— — — — Program memory read address high ---- xxxx ---- uuuu

110h­11Fh

— Unimplemented — —

Bank 3

180h

(3)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

181h OPTION_REG RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

182h

(3)

PCL Program Counter's (PC) Least Significant Byte 0000 0000 0000 0000

183h

(3)

STATUS I RP RP1 RP0 TO PD Z DC C 0001 1xxx 000q quuu

184h

(3)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu
185h — Unimplemented — —
186h TRISB PORTB Data Direction Register 1111 1111 1111 1111
187h — Unimplemented — —
188h — Unimplemented — —
189h — Unimplemented — —
18Ah

(1,3)

PCLATH — — —

Write Buffer for the upper 5 bits of the Program Counter

---0 0000 ---0 0000

18Bh

(3)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u
18Ch PMCON1 Reserved

— — — — — — RD 1--- ---0 1--- ---0

18Dh­18Fh

— Unimplemented — —

TABLE 2-1: PIC16C717/770/771 SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other resets

(2)

Legend:x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.

Shaded locations are unimplemented, read as ‘0’.

Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-

tents are transferred to the upper byte of the program counter.

2: Other (non power-up) resets include external reset through MCLR

and Watchdog Timer Reset.

3: These registers can be addressed from any bank.

PIC16C717/770/771

DS41120A-page 16 Advanced Information 

1999 Microchip Technology Inc.

2.2.2.1 STATUS REGISTER
The STATUS register, shown in Register 2-1, contains

the arithmetic status of th e ALU , the RE SET status an d
the bank select bits for data memory.

The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. The se bi ts ar e set or c leared a ccordi ng to the
device logic. Fur th erm ore, the TO

and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS re gister as desti nation may be different th an
intended.

For example, CLRF STATUS will clear th e up p er -t h ree
bits and set the Z bi t. T his l ea v es the STATUS register
as 000u u1uu (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter t he
STATUS register, because these instructions do not
affect the Z, C or DC b its from the STA TU S regist er . F or
other instructions not affecting any status bits, see the
"Instruction Set Summary."

REGISTER 2-1: STATUS REGISTER (STATUS: 03h, 83h, 103h, 183h)

Note 2: The C and DC bits oper ate as a borro w and

digit borrow

bit, respectively , in subtraction.
See the SUBLW and SUBWF instructions for
examples.

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO

PD Z DC C R = Readable bit

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)

bit 6-5: RP<1:0>: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes

bit 4: TO

: Time-out bit

1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred

bit 3: PD

: Power-down bit

1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borrow

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the p ol arity is reversed)

1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borrow

bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)

1 = A carry-out from the most significant bit of the result occurred
0 = No carry-out from the most significant bit of the result occurred

Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the sec-

ond operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of
the source register.

PIC16C717/770/771



1999 Microchip Technology Inc.

Advanced Information DS41120A-page 17

2.2.2.2 OPTION_REG REGISTER
The OPTION_REG register is a readable and writable

register , which contai ns various c ontrol bits to c onfigure
the TMR0 prescaler/WDT postscaler (single assign­able regist er kno wn also as the prescale r), the Ext ernal
INT Interrupt, TMR0 and the w eak pul l-ups on PO R TB .

REGISTER 2-2: OPTION REGISTER (OPTION_REG: 81h, 181h)

Note: To achieve a 1:1 prescaler assignme nt for

the TMR0 register, assign the prescaler to
the Watchdog Timer.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: RBPU: PORTB Pull-up Enable bit

(1)

1 = PORTB weak pull-ups are disabled
0 = PORTB weak pull-ups are enabled by the WPUB register

bit 6: INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin

bit 5: T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin
0 = Interna l instruction cycle clock (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3: PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS<2:0 >: Prescaler Rate Select bits

Note 1: Individual weak pull-up on RB pins can be enabled/disabled from the weak pull-up PORTB Register

(WPUB).

000
001
010
011
100
101
110
111

1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256

1 : 1
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128

Bit Value TMR0 Rate WDT Rate

PIC16C717/770/771

DS41120A-page 18 Advanced Information 

1999 Microchip Technology Inc.

2.2.2.3 INTCON REGISTER
The INTCON Regi ster i s a rea dab le a nd w ritabl e regi s-

ter, which contains various enable and flag bits for the
TMR0 register overflow, RB Port change and External
RB0/INT pin interrupts.

REGISTER 2-3: INTERRUPT CONTROL REGISTER (INTCON: 0Bh, 8Bh, 10Bh, 18Bh)

Note: Interrupt flag bits get set when an interrupt

condition occurs , regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft­ware should ensure the appropriate inter­rupt flag bits are clear prior to enabling an
interrupt.

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: GIE: Global Interrupt Enable bit

1 = Enables all un-masked interrupts
0 = Disables all interrupts

bit 6: PEIE: Peripheral Interrupt Enable bit

1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts

bit 5: T0IE: TMR0 Overflow Interrupt Enable bit

1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt

bit 4: INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt

bit 3: RBIE : RB Port Change Interrupt Enable bit

(1)

1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt

bit 2: T0IF: TMR0 Overflow Interrupt Flag bit

1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow

bit 1: INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur

bit 0: RBIF: RB Port Change Interrupt Flag bit

(1)

1 = At least one of the RB<7:0> pins changed state (must be cleared in software)
0 = None of the RB<7:0> pins have changed state

Note 1: Individual RB pin interrupt on change can be enabled/disabled from the Interrupt on Change PORTB register (IOCB).

PIC16C717/770/771



1999 Microchip Technology Inc.

Advanced Information DS41120A-page 19

2.2.2.4 PIE1 R EGISTER
This register contains the individual enable bits for the

peripheral interrupts.

REGISTER 2-4: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (PIE1: 8Ch)

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

—ADIE— — SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as ’0’
bit 6: ADIE : A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt
0 = Disables the A/D interrupt

bit 5-4: Unimplemented: Read as ’0’
bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit

1 = Enables the SSP interrupt
0 = Disables the SSP interrupt

bit 2: CCP1IE: CCP1 Interrupt Enable bit

1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt

bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit

1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt

bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit

1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt

PIC16C717/770/771

DS41120A-page 20 Advanced Information 

1999 Microchip Technology Inc.

2.2.2.5 PIR1 REGISTER
This register contains the individual flag bits for the

peripheral interrupts.

REGISTER 2-5: PERIPHERAL INTERRUPT REGISTER 1 (PIR1: 0Ch)

Note: Interrupt flag bits get set when an interrupt

condition occurs , regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft­ware should ensure the appropriate inter­rupt flag bits are clear prior to enabling an
interrupt.

U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0

—

ADIF

— —

SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as ‘0’.
bit 6: ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed
0 = The A/D conversion is not complet e

bit 5-4: Unimplemented: Read as ‘0’.
bit 3: SSPIF: Synchronous Serial Port (SSP) Interrupt Flag

1 = The SSP interrupt condition has occ urred, an d must be clea red in s oftw are bef o re returning from the

interrupt service routine. The conditions that will set this bit are:
SPI

A transmission/reception has taken place.

I

2

C Slave / Master

A transmission/reception has taken place.

I2C Master

The initiated start condition was completed by the SSP module.
The initiated stop condition was completed by the SSP module.
The initiated restart condition was completed by the SSP module.
The initiated acknowledge condition was completed by the SSP module.
A start condition occurred while the SSP module was idle (Multimaster system).
A stop condition occurred while the SSP module was idle (Multimaster system).

0 = No SSP interrupt condition has occurred.

bit 2: CCP1IF: CCP1 Interrupt Flag bit

Capture Mode

1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred

C

ompare Mode

1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred

P

WM Mode

Unused in this mode

bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit

1 = TMR2 to PR2 match occurred (must be cleared in sof tware)
0 = No TMR2 to PR2 match occurred

bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit

1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow

PIC16C717/770/771

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1999 Microchip Technology Inc.

Advanced Information DS41120A-page 21

2.2.2.6 PIE2 R EGISTER
This register contains the individual enable bits for the

SSP bus collision and low voltage detect interrupts.

REGISTER 2-6: PERIPHERAL INTERRUPT REGISTER 2 (PIE2: 8Dh)

R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0
LVDIE

— — —BCLIE — — — R = Readable bit

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: LVDIE: Low-voltage Detect Interrupt Enable bit

1 = LVD Interrupt is enabled
0 = LVD Interrupt is disabled

bit 6-4: Unimplemented: Read as ’0’
bit 3: BCLI E: Bus Collision Interrupt Enable bit

1 = Bus Collision interrupt is enabled
0 = Bus Collision interrupt is disabled

bit 2-0: Unimplemented: Read as ’0’

PIC16C717/770/771

DS41120A-page 22 Advanced Information 

1999 Microchip Technology Inc.

2.2.2.7 PIR2 REGISTER
This register contains the SSP Bus Collision and low-

voltage detect interrupt flag bits.

.

REGISTER 2-7: PERIPHERAL INTERRUPT REGISTER 2 (PIR2: 0Dh)

Note: Interrupt flag bits get set when an interrupt

condition occurs , regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User soft­ware should ensure the appropriate inter­rupt flag bits are clear prior to enabling an
interrupt.

R/W-0 U-0 U-0 U-0 R/W-0 U-0 U-0 U-0
LVDIF

— — —BCLIF — — — R = Readable bit

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: LVDIF: Low-voltage Detect Interrupt Flag bit

1 = The supply voltage has fallen below the specified LVD voltage (must be cleared in software)
0 = The supply voltage is greater than the specified LVD voltage

bit 6-4: Unimplemented: Read as ’0’
bit 3: BCLI F: Bus Collision Interrupt Flag bit

1 = A bus collision has occurred while the SSP module configured in I

2

C Master was transmitting
(must be cleared in software)
0 = No bus collision occurred

bit 2-0: Unimplemented: Read as ’0’

PIC16C717/770/771



1999 Microchip Technology Inc.

Advanced Information DS41120A-page 23

2.2.2.8 PCON REGISTER
The Power Control (PCON) register contains a flag bit

to allow differentiation between a Power-on Reset
(POR) to an external MCLR Reset or WDT Reset.
Those devices with brown-out detection circuitry con­tain an additional bit to differentiate a Brown-out Reset
condition from a Power-on Reset condition.

The PCON register also contains the frequency select
bit of the INTRC or ER osci llator.

REGISTER 2-8: POWER CONTROL REGISTER (PCON: 8Eh)

Note: BOR is unknown on Power-on Reset. It

must then be set by the user and checked
on subsequent resets to see if BOR is
clear , i ndi ca ting a brown-out has occ urre d.
The BOR status bit is a don’t care and is
not necessarily predictab le if the brow n-out
circuit is disabled (by clearing the BODEN
bit in the Configuration word).

U-0 U-0 U-0 U-0 R/W-1 U-0 R/W-q R/W-q

— — — — OSCF —PORBOR R = Readable bit

W = Writable bit
U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-4,2:Unimplemented: Read as ’0’
bit 3: OSCF: Oscillator speed

INTRC Mode

1 = 4 MHz nominal
0 = 37 KHz nominal

ER Mode

1 = Oscillator frequency depends on the external resistor value on the OSC1 pin.
0 = 37 KHz nominal

All other modes
x = Ignored

bit 1: POR

: Power-on Reset Status bit

1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0: BO

R: Brown-out Reset Status bit

1 = No Brown-out Reset occurr ed
0 = A Brown-out Reset occur red (must be set in software after a Brown-out Reset occurs)

PIC16C717/770/771

DS41120A-page 24 Advanced Information 

1999 Microchip Technology Inc.

2.3 PCL and PCLATH

The program counter (PC) specifies the address of the
instruction to fetch for execution. The PC is 13 bits
wide. The low byte is called the PCL register. This reg­ister is readable and writable. The high byte is called
the PCH register. This register contains the PC<12:8>
bits and is not directly readable or w ritable. All update s
to the PCH register occur through the PCLATH register .

2.3.1 PROGRAM MEMORY PAGING
PIC16C717/770/771 devices are capable of address-

ing a continuous 8K word block of program memory.
The CALL and GOTO instructions prov ide only 11 bits of
address to allow branching within any 2K program
memory page. When d oing a CALL or GOTO instruction,
the upper 2 bits of the address are provided by
PCLATH<4:3>. Wh en doing a CALL or GOTO instruc­tion, the user must ensure that the page select bits are
programmed so that the desired program memory
page is addressed. A return instruction pops a PC
address off the stack onto the PC register. Therefore,
manipulation of the PCLA TH<4:3> bits are not required
for the return instructions (which POPs the address
from the st ack).

2.4 Stack

The stack allo ws a co mbination o f up to 8 pro gram ca lls
and interrupts to occur. The stack contains the return
address from this branch in program execution.

Mid-range devices have an 8-level deep x 13-bit wide
hardware stack. The stack space is not part of either
program or data space and the stack pointer is not
readable or writab le. The PC is PUSHed onto the stac k
when a CALL instruction is executed or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not modified when the stack is PUSHed or
POPed.

After the stack has been PUSHed eight times, the ninth
push overw rites th e value that was stored from the first
push. The tenth push overwrites the sec ond pus h (an d
so on).

PIC16C717/770/771

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1999 Microchip Technology Inc.

Advanced Information DS41120A-page 25

The INDF register is no t a physical r egis ter. Address­ing INDF actually addresses the register whose
address is contained in the FSR register (FSR is a

pointer

). This is indirect ad dressi ng .

Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no-operation (although STATUS bits may be affected).

A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-1.

EXAMPLE 2-1: HOW TO CLEAR RAM

USING INDIRECT
ADDRESSING

movlw 0x20 ;initialize pointer
movwf FSR ; to RAM
NEXT clrf INDF ;clear INDF register
incf FSR ;inc pointer
btfss FSR,4 ;all done?
goto NEXT ;NO, clear next
CONTINUE
: ;YES, continue

An effective 9-bit addres s is o btai ne d by concatenatin g
the 8-bit FSR register an d the IRP bit (S TATUS<7>), as
shown in Figure 2-4.

FIGURE 2-4: DIRECT/INDIRECT ADDRESSING

Note 1: For register file map detail see Figure 2-3.

Data
Memory

(1)

Indirect AddressingDirect Addressing

bank select location select

RP1:RP0 6

0

from opcode

IRP FSR register

7

0

bank select

location select

00 01 10 11

Bank 0 Ban k 1 Bank 2 Bank 3

FFh

80h

7Fh

00h

17Fh

100h

1FFh

180h

PIC16C717/770/771

DS41120A-page 26 Advanced Information 

1999 Microchip Technology Inc.

NOTES:

PIC16C717/770/771



1999 Microchip Technology Inc.

Advanced Information DS41120A-page 27

3.0 I/O PORTS

Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.

Additional information on I/O ports ma y b e found in the

PICmicro™ Mid-Range Reference Manual,
(DS33023).

3.1 I/O Port Analog/Digital Mode

The PIC16C717/770/771 have two I/O ports: PORTA
and PORTB . Some of thes e port pins are mix ed-si gnal
(can be digital or analog). When an analog signal is

present on a pin, the pin must be co nfigured as an ana­log input to prev ent un neces sary current dr a w from the
power supply. The Analog Select Register (ANSEL)
allows the user to individually select the digital/analog
mode on these pins. When the analog mode is active,
the port pin will always read 0.

REGISTER 3-1: ANALOG SELECT REGISTER (ANSEL: 9Dh)

3.2 PORTA and the TRISA Register

PORTA is a 8-bit wide bi-directional port. The corre­sponding data direction register is TRISA. Setting a
TRISA bit (=1) will m ak e the corresponding PO RTA pin
an input, i.e., put the corresponding output driver in a
hi-impedance mode. Clearing a TRISA bit (=0) will
make the corresp ond ing PORTA pin an output, i.e ., put
the contents of the output latch on the selected pin.

Reading the PORTA register reads the status of the
pins, whereas writin g to it w i ll write t o th e p ort latch. All
write operations are read-modify-write operations.
Therefore , a write to a port implies that the port pins are
read, this val ue is m odifie d, and then written to th e port
data latch.

Pins RA<3:0> are multiplexed with analog functions,
such as analog inputs to the A/D converter, analog
VREF inputs, and the on-board band gap ref erence out­puts. When the analog peripherals are using any of

these pins as analog input/output, the ANSEL register
must have the proper value to individually select the
analog mode of the corresponding pins.

Pin RA4 is multiplexed with the Timer0 module clock
input to become the RA4/T0CKI pin. The RA4/T0CKI
pin is a Schmitt Trigger input and an open d r a in ou tpu t.

Pin RA5 is multiplexed with the device reset (MCLR

)

and programming input (V

PP) functions. The RA5/

MCLR

/VPP input only pin has a Schmitt Trigger input
buffer . All other RA port pins hav e Schmitt Trigger input
buffers and full CMOS output buffers.

Pins RA6 and RA7 are multiplexed with the oscillator
input and output functions.

The TRISA register controls the direction of the RA
pins, even when they are being used as analog inputs.
The user must ensure the bi ts in the TRISA register are
maintained set when using them as analog inputs.

Note 1: On a P o wer-on Reset , the ANSEL reg ister

configures these mixed-signal pins as
analog mode.

2: If a pin is configured as analog mode, the

pin will always read '0', even if the digital
output is active.

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1

ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 R = Readable bit

W = Writable bit
U = Unimplemented bit, read as

‘0’

-n = Value at POR reset

bit7 bit0

bit 7-6: Reserved: Do not use
bit 5-0: ANS<5:0>: Analog Select between analog or digital function on pins AN<5:0>, respectively.

0 = Digital I/O. Pin is assigned to port or special function.
1 = Analog Input. Pin is assigned as analog input.

Note: Setting a pin to an analog input disables digital inputs and any pull-up that may be present. The corre-

sponding TRIS bit should be set to input mode when using pins as analog inputs.

Note: Upon reset, the ANSEL register configures

the RA<3:0> pins as analog inputs. All
RA<3:0> pins will read as ’0’.

PIC16C717/770/771

DS41120A-page 28 Advanced Information 

1999 Microchip Technology Inc.

EXAMPLE 3-1: INITIALIZING PORTA

BCF STATUS, RP0 ; Select Bank 0
CLRF PORTA ; Initialize PORTA by
; clearing output
; data latches
BSF STATUS, RP0 ; Select Bank 1
MOVLW 0Fh ; Value used to
; initialize data
; direction
MOVWF TRISA ; Set RA<3:0> as inputs
; RA<7:4> as outputs. RA<7:6>availability depends on oscillator selection.
MOVLW 03 ; Set RA<1:0> as analog inputs, RA<7:2> are digital I/O
MOVWF ANSEL
BCF STATUS, RP0 ; Return to Bank 0

FIGURE 3-1: BLOCK DIAGRAM OF RA0/AN0, RA1/AN1/LVDIN

Data
Bus

QD

Q

CK

QD

Q

CK

QD

EN

P

N

WR
PORT

WR
TRIS

Data Latch

TRIS Mode

V

SS

VDD

Schmitt
Trigger

To A/D Converter input or LVD Module input

RD
TRIS

QD

Q

CK

Analog Select

WR
ANSEL

RD

PORT

VDD

VSS

PIC16C717/770/771

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1999 Microchip Technology Inc.

Advanced Information DS41120A-page 29

FIGURE 3-2: BLOCK DIAGRAM OF RA2/AN2/VREF-/VRL AND RA3/AN3/VREF+/VRH

To A/D Converter input

VRH, VRL outputs

(From Vref-LVD-BO R Module)

and Vref+, Vref- inputs

Sense input for
VRH, VRL amplifier

VRH, VRL output enable

Data
Bus

QD

Q

CK

QD

Q

CK

P

N

WR
PORT

WR
TRIS

Data Latch

TRIS Mode

V

SS

VDD

Schmitt
Trigger

RD
TRIS

QD

Q

CK

Analog Select

WR
ANSEL

RD

PORT

VDD

VSS

QD

EN

PIC16C717/770/771

DS41120A-page 30 Advanced Information 

1999 Microchip Technology Inc.

FIGURE 3-3: BLOCK DIAGRAM OF RA4/T0CKI

Data
Bus

QD

Q

CK

QD

Q

CK

QD

EN

N

WR
Port

WR
TRIS

Data Latch

RD

V

SS

Schmitt Trigger
Input Buffer

TMR0 clock input

RD
TRIS

TRIS Latch

PORT

VSS