Microchip Technology Inc PIC16C71-04-P, PIC16C71-04I-P, PIC16C71-04I-SO, PIC16C710-20-SO, PIC16C710-20I-P Datasheet

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1997 Microchip Technology Inc. DS30272A-page 1

PIC16C71X

8-Bit CMOS Microcontrollers with A/D Converter

Devices included in this data sheet:

• PIC16C710

• PIC16C71

• PIC16C711

• PIC16C715

PIC16C71X Microcontroller Core Features:

• High-performance RISC CPU

• Only 35 single word instructions to learn

• All single cycle instructions except for program branches which are two cycle

• Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

• Up to 2K x 14 words of Program Memory, up to 128 x 8 bytes of Data Memory (RAM)

• Interrupt capability

• Eight level deep hardware stack

• Direct, indirect, and relative addressing modes

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)

• Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation

• Programmable code-protection

• Power saving SLEEP mode

• Selectable oscillator options

• Low-power, high-speed CMOS EPROM technology

• Fully static design

• Wide operating voltage range: 2.5V to 6.0V

• High Sink/Source Current 25/25 mA

• Commercial, Industrial and Extended temperature ranges

• Program Memory Parity Error Checking Circuitry with Parity Error Reset (PER) (PIC16C715)

• Low-power consumption:

- < 2 mA @ 5V, 4 MHz

- 15 µ A typical @ 3V, 32 kHz

- < 1 µ A typical standby current

PIC16C71X Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler

• 8-bit multichannel analog-to-digital converter

• Brown-out detection circuitry for Brown-out Reset (BOR)

• 13 I/O Pins with Individual Direction Control

Pin Diagrams

PIC16C7X Features 710 71 711 715

Program Memory (EPROM) x 14

512 1K 1K 2K

Data Memory (Bytes) x 8 36 36 68 128 I/O Pins 13 13 13 13 Timer Modules 1 1 1 1 A/D Channels 4 4 4 4 In-Circuit Serial Programming Yes Yes Yes Yes Brown-out Reset Yes — Yes Yes Interrupt Sources 4 4 4 4

RA2/AN2

RA3/AN3/V

REF

RA4/T0CKI

MCLR/VPP

VSS VSS

RB0/INT

RB1 RB2 RB3

RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT

RB7 RB6 RB5 RB4

• 1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

VDD

SSOP

RA2/AN2

RA3/AN3/V

REF

RA4/T0CKI

MCLR/VPP

VSS

RB0/INT

RB1 RB2 RB3

RA1/AN1 RA0/AN0 OSC1/CLKIN OSC2/CLKOUT V

RB7 RB6 RB5 RB4

• 1 2 3 4 5 6 7 8 9

18 17 16 15 14 13 12 11 10

PIC16C710

PDIP, SOIC, Windowed CERDIP

PIC16C71

PIC16C711

PIC16C715

PIC16C710

PIC16C711

PIC16C715

PIC16C71X

DS30272A-page 2

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1997 Microchip Technology Inc.

Table of Contents

1.0 General Description.................................................................................................................................................................... 3

2.0 PIC16C71X Device Varieties......................................................................................................................................................5

3.0 Architectural Overview................................................................................................................................................................7

4.0 Memory Organization ............................................................................................................................................................... 11

5.0 I/O Ports.................................................................................................................................................................................... 25

6.0 Timer0 Module..........................................................................................................................................................................31

7.0 Analog-to-Digital Converter (A/D) Module ................................................................................................................................ 37

8.0 Special Features of the CPU .................................................................................................................................................... 47

9.0 Instruction Set Summary .......................................................................................................................................................... 69

10.0 Development Support............................................................................................................................................................... 85

11.0 Electrical Characteristics for PIC16C710 and PIC16C711....................................................................................................... 89

12.0 DC and AC Characteristics Graphs and Tables for PIC16C710 and PIC16C711..................................................................101

13.0 Electrical Characteristics for PIC16C715................................................................................................................................ 111

14.0 DC and AC Characteristics Graphs and Tables for PIC16C715 ............................................................................................ 125

15.0 Electrical Characteristics for PIC16C71.................................................................................................................................. 135

16.0 DC and AC Characteristics Graphs and Tables for PIC16C71 .............................................................................................. 147

17.0 Packaging Information............................................................................................................................................................ 155

Appendix A: ...................................................................................................................................................................................... 161

Appendix B: Compatibility................................................................................................................................................................. 161

Appendix C: What’s New.................................................................................................................................................................. 162

Appendix D: What’s Changed .......................................................................................................................................................... 162

Index .................................................................................................................................................................................................. 163

PIC16C71X Product Identification System......................................................................................................................................... 173

To Our Valued Customers

We constantly strive to improve the quality of all our products and documentation. We have spent an exceptional amount of time to ensure that these documents are correct. However, we realize that we may have missed a few things. If you ﬁnd any information that is missing or appears in error, please use the reader response form in the back of this data sheet to inform us. We appreciate your assistance in making this a better document.

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1997 Microchip Technology Inc. DS30272A-page 3

PIC16C71X

1.0 GENERAL DESCRIPTION

The PIC16C71X is a family of

low-cost, high-performance, CMOS, fully-static, 8-bit microcontrollers with integrated analog-to-digital (A/D) converters, in the PIC16CXX mid-range family.

All PIC16/17 microcontrollers employ an advanced RISC architecture. The PIC16CXX microcontroller family has enhanced core features, eight-level deep stack, and multiple internal and external interrupt sources. The separate instruction and data buses of the Harvard architecture allow a 14-bit wide instruction word with the separate 8-bit wide data. The two stage instruction pipeline allows all instructions to execute in a single cycle, except for program branches which require two cycles. A total of 35 instructions (reduced instruction set) are available . Additionally , a large register set giv es some of the architectural innovations used to achie ve a very high performance.

PIC16CXX microcontrollers typically achieve a 2:1 code compression and a 4:1 speed improvement over other 8-bit microcontrollers in their class.

The PIC16C710/71 devices have 36 b ytes of RAM, the

PIC16C711 has 68 bytes of RAM and the PIC16C715

has 128 bytes of RAM. Each device has 13 I/O

pins. In addition a timer/counter is available. Also a 4-channel high-speed 8-bit A/D is provided. The 8-bit resolution is ideally suited for applications requiring low-cost analog interface, e.g. thermostat control, pressure sensing, etc.

The PIC16C71X family has special features to reduce external components, thus reducing cost, enhancing system reliability and reducing power consumption. There are four oscillator options, of which the single pin RC oscillator provides a low-cost solution, the LP oscillator minimizes power consumption, XT is a standard crystal, and the HS is for High Speed crystals. The SLEEP (power-down) feature provides a power saving mode. The user can wake up the chip from SLEEP through several external and internal interrupts and resets.

A highly reliable Watchdog Timer with its own on-chip RC oscillator provides protection against software lockup.

A UV erasable CERDIP packaged version is ideal for code development while the cost-effective One-TimeProgrammable (OTP) version is suitable for production in any volume.

The PIC16C71X family ﬁts perfectly in applications ranging from security and remote sensors to appliance control and automotive. The EPROM technology makes customization of application programs (transmitter codes, motor speeds, receiver frequencies, etc.) extremely fast and convenient. The small footprint packages make this microcontroller series perfect for all applications with space limitations. Low cost, low power, high perf ormance, ease of use and I/O ﬂe xibility make the PIC16C71X very versatile even in areas where no microcontroller use has been considered before (e.g. timer functions , serial communication, capture and compare, PWM functions and coprocessor applications).

1.1 F

amily and Upward Compatibility

Users familiar with the PIC16C5X microcontroller family will realize that this is an enhanced version of the PIC16C5X architecture. Please refer to Appendix A for a detailed list of enhancements. Code written for the PIC16C5X can be easily ported to the PIC16CXX family of devices (Appendix B).

1.2 De

velopment Support

PIC16C71X devices are supported by the complete line of Microchip Development tools.

Please refer to Section 10.0 for more details about Microchip’s development tools.

PIC16C71X

DS30272A-page 4

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1997 Microchip Technology Inc.

TABLE 1-1: PIC16C71X FAMILY OF DEVICES

PIC16C710

PIC16C71 PIC16C711 PIC16C715 PIC16C72 PIC16CR72

(1)

Clock

Maximum Frequency of Operation (MHz)

20 20 20 20 20 20

Memory

EPROM Program Memory (x14 words)

512 1K 1K 2K 2K —

ROM Program Memory (14K words)

— — — — — 2K

Data Memory (bytes) 36 36 68 128 128 128

Peripherals

Timer Module(s) TMR0 TMR0 TMR0 TMR0 TMR0,

TMR1, TMR2

TMR0, TMR1, TMR2

Capture/Compare/PWM Module(s)

— — — — 1 1

Serial Port(s) (SPI/I

C, USART)

— — — — SPI/I

C SPI/I

Parallel Slave Port — — — — — — A/D Converter (8-bit) Channels 4 4 4 4 5 5

Features

Interrupt Sources 4 4 4 4 8 8 I/O Pins 13 13 13 13 22 22 Voltage Range (Volts) 2.5-6.0 3.0-6.0 2.5-6.0 2.5-5.5 2.5-6.0 3.0-5.5 In-Circuit Serial Programming Yes Yes Yes Yes Yes Yes Brown-out Reset Yes — Yes Yes Yes Yes Packages 18-pin DIP,

SOIC; 20-pin SSOP

18-pin DIP, SOIC

18-pin DIP, SOIC; 20-pin SSOP

28-pin SDIP, SOIC, SSOP

PIC16C73A

PIC16C74A PIC16C76 PIC16C77

Clock

Maximum Frequency of Operation (MHz)

20 20 20 20

Memory

EPROM Program Memory (x14 words)

4K 4K 8K 8K

Data Memory (bytes) 192 192 376 376

Peripherals

Timer Module(s) TMR0,

TMR1, TMR2

TMR0, TMR1, TMR2

Capture/Compare/PWM Module(s)

2 2 2 2

Serial Port(s) (SPI/I

C, USART)

SPI/I

C, USART SPI/I

C, USART

Parallel Slave Port — Yes — Yes A/D Converter (8-bit) Channels 5 8 5 8

Features

Interrupt Sources 11 12 11 12 I/O Pins 22 33 22 33 Voltage Range (Volts) 2.5-6.0 2.5-6.0 2.5-6.0 2.5-6.0 In-Circuit Serial Programming Yes Yes Yes Yes Brown-out Reset Yes Yes Yes Yes Packages 28-pin SDIP,

SOIC

40-pin DIP; 44-pin PLCC, MQFP, TQFP

28-pin SDIP, SOIC

40-pin DIP; 44-pin PLCC, MQFP, TQFP

All PIC16/17 Family devices ha v e Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability . All PIC16C7XX Family devices use serial programming with clock pin RB6 and data pin RB7. Note 1: Please contact your local Microchip sales ofﬁce for availability of these devices.

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1997 Microchip Technology Inc. DS30272A-page 5

PIC16C71X

2.0 PIC16C71X DEVICE VARIETIES

A variety of frequency ranges and packaging options are available . Depending on application and production requirements, the proper device option can be selected using the information in the PIC16C71X Product Identiﬁcation System section at the end of this data sheet. When placing orders, please use that page of the data sheet to specify the correct part number.

For the PIC16C71X family, there are two device “types” as indicated in the device number:

1. C , as in PIC16 C 71. These devices have

EPROM type memory and operate over the standard voltage range.

2. LC , as in PIC16 LC 71. These devices have

EPROM type memory and operate over an extended voltage range.

2.1 UV Erasab

le Devices

The UV erasable version, offered in CERDIP package is optimal for prototype development and pilot programs. This version can be erased and reprogrammed to any of the oscillator modes.

Microchip's PICSTART



Plus and PRO MATE



II programmers both support programming of the PIC16C71X.

2.2 One-Time-Pr

ogrammable (OTP)

Devices

The availability of OTP devices is especially useful for customers who need the ﬂexibility for frequent code updates and small volume applications.

The OTP devices, packaged in plastic packages, permit the user to program them once. In addition to the program memory, the conﬁguration bits must also be programmed.

2.3 Quic

k-Turnaround-Production (QTP)

Devices

Microchip offers a QTP Programming Service for factory production orders. This service is made available for users who choose not to program a medium to high quantity of units and whose code patterns have stabilized. The devices are identical to the OTP devices but with all EPROM locations and conﬁguration options already programmed by the factory. Certain code and prototype veriﬁcation procedures apply before production shipments are available. Please contact your local Microchip Technology sales ofﬁce for more details.

2.4 Serializ

ed Quick-Turnaround

Production (SQTP

)

Devices

Microchip offers a unique programming service where a few user-deﬁned locations in each device are programmed with different serial numbers. The serial numbers may be random, pseudo-random, or sequential.

Serial programming allows each device to have a unique number which can serve as an entry-code, password, or ID number.

PIC16C71X

DS30272A-page 6

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1997 Microchip Technology Inc.

NOTES:

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1997 Microchip Technology Inc. DS30272A-page 7

PIC16C71X

3.0 ARCHITECTURAL OVERVIEW

The high performance of the PIC16CXX family can be attributed to a number of architectural features commonly found in RISC microprocessors. To begin with, the PIC16CXX uses a Harvard architecture, in which, program and data are accessed from separate memories using separate buses. This improves bandwidth over traditional von Neumann architecture in which program and data are fetched from the same memory using the same bus. Separating program and data buses further allows instructions to be sized differently than the 8-bit wide data word. Instruction opcodes are 14-bits wide making it possible to have all single word instructions. A 14-bit wide program memory access bus fetches a 14-bit instruction in a single cycle. A twostage pipeline overlaps fetch and execution of instructions (Example 3-1). Consequently, all instructions (35) execute in a single cycle (200 ns @ 20 MHz) e xcept f or program branches.

The table below lists program memory (EPROM) and data memory (RAM) for each PIC16C71X device.

The PIC16CXX can directly or indirectly address its register ﬁles or data memory. All special function registers, including the program counter, are mapped in the data memory. The PIC16CXX has an orthogonal (symmetrical) instruction set that makes it possible to carry out any operation on any register using any addressing mode. This symmetrical nature and lack of ‘special optimal situations’ make programming with the PIC16CXX simple yet efﬁcient. In addition, the learning curve is reduced signiﬁcantly.

Device

Program

Memory

Data Memory

PIC16C710 512 x 14 36 x 8 PIC16C71 1K x 14 36 x 8 PIC16C711 1K x 14 68 x 8 PIC16C715 2K x 14 128 x 8

PIC16CXX devices contain an 8-bit ALU and working register. The ALU is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the working register and any register ﬁle.

The ALU is 8-bits wide and capable of addition, subtraction, shift and logical operations. Unless otherwise mentioned, arithmetic operations are two's complement in nature. In two-operand instructions, typically one operand is the working register (W register). The other operand is a ﬁle register or an immediate constant. In single operand instructions, the operand is either the W register or a ﬁle register.

The W register is an 8-bit working register used f or ALU operations. It is not an addressable register.

Depending on the instruction executed, the ALU may affect the values of the Carry (C), Digit Carry (DC), and Zero (Z) bits in the STATUS register. The C and DC bits operate as a borro

w bit and a digit borrow out bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

PIC16C71X

DS30272A-page 8

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1997 Microchip Technology Inc.

FIGURE 3-1: PIC16C71X BLOCK DIAGRAM

EPROM

Program

Memory

Data Bus

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

RAM

File

Registers

Direct Addr

RAM Addr

(1)

Addr MUX

Indirect

Addr

FSR reg

STATUS reg

MUX

ALU

W reg

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN OSC2/CLKOUT

MCLR

VDD, VSS

Timer0

A/D

PORTA

PORTB

RB0/INT

RB7:RB1

Brown-out

Reset

(2)

Note 1: Higher order bits are from the STATUS register.

2: Brown-out Reset is not available on the PIC16C71.

Device Program Memory Data Memory (RAM)

PIC16C710 PIC16C71 PIC16C711 PIC16C715

512 x 14

1K x 14 1K x 14 2K x 14

36 x 8 36 x 8 68 x 8

128 x 8

RA4/T0CKI

RA3/AN3/VREF

RA2/AN2

RA1/AN1

RA0/AN0

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1997 Microchip Technology Inc. DS30272A-page 9

PIC16C71X

TABLE 3-1: PIC16C710/71/711/715 PINOUT DESCRIPTION

Pin Name

DIP

Pin#

SSOP

Pin#

(4)

SOIC

Pin#

I/O/P Type

Buffer

Type

Description

OSC1/CLKIN 16 18 16 I

ST/CMOS

(3)

Oscillator crystal input/external clock source input.

OSC2/CLKOUT 15 17 15 O — Oscillator crystal output. Connects to crystal or resonator in crystal

oscillator mode. In RC mode , OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate.

MCLR/V

4 4 4 I/P ST Master clear (reset) input or programming voltage input. This pin is

an active low reset to the device.

PORTA is a bi-directional I/O port. RA0/AN0 17 19 17 I/O TTL RA0 can also be analog input0 RA1/AN1 18 20 18 I/O TTL RA1 can also be analog input1 RA2/AN2 1 1 1 I/O TTL RA2 can also be analog input2 RA3/AN3/V

REF

2 2 2 I/O TTL RA3 can also be analog input3 or analog reference voltage

RA4/T0CKI 3 3 3 I/O ST RA4 can also be the cloc k input to the Timer0 module . Output is

open drain type.

PORTB is a bi-directional I/O port. PORTB can be software pro-

grammed for internal weak pull-up on all inputs. RB0/INT 6 7 6 I/O TTL/ST

(1)

RB0 can also be the external interrupt pin. RB1 7 8 7 I/O TTL RB2 8 9 8 I/O TTL RB3 9 10 9 I/O TTL RB4 10 11 10 I/O TTL Interrupt on change pin. RB5 11 12 11 I/O TTL Interrupt on change pin. RB6 12 13 12 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming clock. RB7 13 14 13 I/O TTL/ST

(2)

Interrupt on change pin. Serial programming data. V

5 4, 6 5 P — Ground reference for logic and I/O pins.

14 15, 16 14 P — Positive supply for logic and I/O pins.

Legend: I = input O = output I/O = input/output P = power

— = Not used TTL = TTL input ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when conﬁgured in RC oscillator mode and a CMOS input otherwise. 4: The PIC16C71 is not available in SSOP package.

PIC16C71X

DS30272A-page 10

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1997 Microchip Technology Inc.

3.1 Cloc

king Scheme/Instruction Cycle

The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution ﬂow is shown in Figure 3-2.

3.2 Instruction Flo

w/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instr uction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g. GOTO ) then two cycles are required to complete the instruction (Example 3-1).

A fetch cycle begins with the program counter (PC) incrementing in Q1.

In the execution cycle, the f etched instruction is latched into the “Instruction Register” (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).

FIGURE 3-2: CLOCK/INSTRUCTION CYCLE

EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW

Q2 Q3 Q4

OSC1

Q1 Q2 Q3

Q4 PC

OSC2/CLKOUT

(RC mode)

PC PC+1 PC+2

Fetch INST (PC)

Execute INST (PC-1) Fetch INST (PC+1)

Execute INST (PC) Fetch INST (PC+2)

Execute INST (PC+1)

Internal phase clock

All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “ﬂushed” from the pipeline while the new instruction is being fetched and then executed.

Tcy0 Tcy1 Tcy2 Tcy3 Tcy4 Tcy5

1. MOVLW 55h

Fetch 1 Execute 1

2. MOVWF PORTB

Fetch 2 Execute 2

3. CALL SUB_1

Fetch 3 Execute 3

4. BSF PORTA, BIT3 (Forced NOP)

Fetch 4 Flush

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

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1997 Microchip Technology Inc. DS30272A-page 11

PIC16C71X

4.0 MEMORY ORGANIZATION

4.1 Pr

ogram Memory Organization

The PIC16C71X family has a 13-bit program counter capable of addressing an 8K x 14 program memory space. The amount of program memory available to each device is listed below:

For those devices with less than 8K program memory, accessing a location above the physically implemented address will cause a wraparound.

The reset vector is at 0000h and the interrupt vector is at 0004h.

FIGURE 4-1: PIC16C710 PROGRAM

MEMORY MAP AND STACK

Device

Program

Memory

Address Range

PIC16C710 512 x 14 0000h-01FFh PIC16C71 1K x 14 0000h-03FFh PIC16C711 1K x 14 0000h-03FFh PIC16C715 2K x 14 0000h-07FFh

PC<12:0>

0000h

0004h 0005h

01FFh 0200h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN RETFIE, RETLW

User Memory

Space

FIGURE 4-2: PIC16C71/711 PROGRAM

MEMORY MAP AND STACK

FIGURE 4-3: PIC16C715 PROGRAM

MEMORY MAP AND STACK

PC<12:0>

0000h

0004h 0005h

03FFh 0400h

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN RETFIE, RETLW

User Memory

Space

PC<12:0>

0000h

0004h 0005h

07FFh

1FFFh

Stack Level 1

Stack Level 8

Reset Vector

Interrupt Vector

On-chip Program

Memory

CALL, RETURN RETFIE, RETLW

0800h

PIC16C71X

DS30272A-page 12  1997 Microchip Technology Inc.

4.2 Data Memory Organization

The data memory is partitioned into two Banks which contain the General Purpose Registers and the Special Function Registers. Bit RP0 is the bank select bit.

RP0 (STATUS<5>) = 1 → Bank 1 RP0 (STATUS<5>) = 0 → Bank 0 Each Bank extends up to 7Fh (128 bytes). The lower

locations of each Bank are reserved for the Special Function Registers. Abo ve the Special Function Registers are General Purpose Registers implemented as static RAM. Both Bank 0 and Bank 1 contain special function registers. Some "high use" special function registers from Bank 0 are mirrored in Bank 1 for code reduction and quicker access.

4.2.1 GENERAL PURPOSE REGISTER FILE The register ﬁle can be accessed either directly , or indi-

rectly through the File Select Register FSR (Section 4.5).

FIGURE 4-4: PIC16C710/71 REGISTER FILE

MAP

INDF

(1)

TMR0

PCL

ST A TUS

FSR PORT A PORTB

PCLA TH INTCON

ADRES

ADCON0

INDF

(1)

OPTION

PCL

ST A TUS

FSR TRISA TRISB

PCLA TH INTCON

ADCON1

00h 01h 02h 03h 04h 05h 06h 07h 08h

09h 0Ah 0Bh 0Ch

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch

General Purpose Register

7Fh

FFh

Bank 0 Bank 1

File

Address

ADRES

2Fh 30h

AFh B0h

File

Address

General Purpose Register

Mapped

in Bank 0

(3)

PCON

(2)

Unimplemented data memory locations, read

as '0'.

Note 1: Not a physical register.

2: The PCON register is not implemented on the

PIC16C71.

3: These locations are unimplemented in Bank 1.

Any access to these locations will access the corresponding Bank 0 register.

 1997 Microchip Technology Inc. DS30272A-page 13

PIC16C71X

FIGURE 4-5: PIC16C711 REGISTER FILE

MAP

INDF

(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH INTCON

ADRES

ADCON0

INDF

(1)

OPTION

PCL

STATUS

FSR TRISA TRISB

PCLATH INTCON

ADCON1

00h 01h 02h 03h 04h 05h 06h 07h 08h

09h 0Ah 0Bh 0Ch

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch

General Purpose Register

7Fh

FFh

Bank 0 Bank 1

File

Address

ADRES

4Fh 50h

CFh D0h

File

Address

General Purpose Register

Mapped

in Bank 0

(2)

PCON

Unimplemented data memory locations, read

as '0'.

Note 1: Not a physical register.

2: These locations are unimplemented in Bank 1.

Any access to these locations will access the corresponding Bank 0 register.

FIGURE 4-6: PIC16C715 REGISTER FILE

MAP

INDF

(1)

TMR0

PCL

STATUS

FSR

PORTA

PORTB

PCLATH INTCON

PIR1

ADRES

ADCON0

INDF

(1)

OPTION

PCL

STATUS

FSR TRISA TRISB

PCLATH INTCON

PIE1

PCON

ADCON1

00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah

0Bh 0Ch 0Dh 0Eh

0Fh

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h 1Ah 1Bh 1Ch 1Dh 1Eh

1Fh

80h 81h 82h 83h 84h 85h 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh 8Eh 8Fh 90h 91h 92h 93h 94h 95h 96h 97h 98h 99h 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh

20h

A0h

General Purpose Register

7Fh

FFh

Bank 0 Bank 1

File

Address

BFh C0h

File

Address

Unimplemented data memory locations, read

as '0'.

Note 1: Not a physical register.

PIC16C71X

DS30272A-page 14  1997 Microchip Technology Inc.

4.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by

the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM.

The special function registers can be classiﬁed into two sets (core and peripheral). Those registers associated with the “core” functions are described in this section, and those related to the operation of the peripheral features are described in the section of that peripheral feature.

TABLE 4-1: PIC16C710/71/711 SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on all

other resets

(1)

Bank 0

00h

(3)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h

(3)

PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 03h

(3)

STATUS

IRP

(5)

RP1

(5)

RP0 TO PD Z DC C 0001 1xxx 000q quuu

04h

(3)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA

— — — PORTA Data Latch when written: PORTA pins when read ---x 0000 ---u 0000 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h — Unimplemented — — 08h ADCON0 ADCS1 ADCS0 (6) CHS1 CHS0 GO/DONE ADIF ADON 00-0 0000 00-0 0000

09h

(3)

ADRES A/D Result Register

xxxx xxxx uuuu uuuu

0Ah

(2,3)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

0Bh

(3)

INTCON GIE ADIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

Bank 1

80h

(3)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000

81h OPTION RBPU

INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

82h

(3)

PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000

83h

(3)

STATUS

IRP

(5)

RP1

(5)

RP0 TO PD Z DC C 0001 1xxx 000q quuu

84h

(3)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu

85h TRISA

— — — PORTA Data Direction Register ---1 1111 ---1 1111 86h TRISB PORTB Data Direction Control Register 1111 1111 1111 1111 87h

(4)

PCON — — — — — — POR BOR ---- --qq ---- --uu

88h ADCON1 — — — — — — PCFG1 PCFG0 ---- --00 ---- --00 89h

(3)

ADRES A/D Result Register

xxxx xxxx uuuu uuuu

8Ah

(2,3)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000

8Bh

(3)

INTCON GIE ADIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter. 3: These registers can be addressed from either bank. 4: The PCON register is not physically implemented in the PIC16C71, read as ’0’. 5: The IRP and RP1 bits are reserved on the PIC16C710/71/711, always maintain these bits clear. 6: Bit5 of ADCON0 is a General Purpose R/W bit for the PIC16C710/711 only. For the PIC16C71, this bit is unimplemented,

read as '0'.

 1997 Microchip Technology Inc. DS30272A-page 15

PIC16C71X

TABLE 4-2: PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR, PER

Value on all

other resets

(3)

Bank 0

00h

(1)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 02h

(1)

PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 03h

(1)

STATUS IRP

(4)

RP1

(4)

RP0 TO PD Z DC C 0001 1xxx 000q quuu

04h

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 05h PORTA — — — PORTA Data Latch when written: PORTA pins when read ---x 0000 ---u 0000 06h PORTB PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuuu 07h — Unimplemented — — 08h — Unimplemented — — 09h — Unimplemented — — 0Ah

(1,2)

PCLATH — — — Write Buffer for the upper 5 bits of the Program Counter ---0 0000 ---0 0000 0Bh

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 — ADIF — — — — — — -0-- ---- -0-- ---- 0Dh — Unimplemented — — 0Eh — Unimplemented — — 0Fh — Unimplemented — — 10h — Unimplemented — — 11h — Unimplemented — — 12h — Unimplemented — — 13h — Unimplemented — — 14h — Unimplemented — — 15h — Unimplemented — — 16h — Unimplemented — — 17h — Unimplemented — — 18h — Unimplemented — — 19h — Unimplemented — — 1Ah — Unimplemented — — 1Bh — Unimplemented — — 1Ch — Unimplemented — — 1Dh — Unimplemented — — 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00-0

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

contents are transferred to the upper byte of the program counter. 3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C715, always maintain these bits clear.

PIC16C71X

DS30272A-page 16  1997 Microchip Technology Inc.

Bank 1

80h

(1)

INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 0000 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 82h

(1)

PCL Program Counter's (PC) Least Signiﬁcant Byte 0000 0000 0000 0000 83h

(1)

STATUS IRP

(4)

RP1

(4)

RP0 TO PD Z DC C 0001 1xxx 000q quuu

84h

(1)

FSR Indirect data memory address pointer xxxx xxxx uuuu uuuu 85h TRISA — — PORTA Data Direction Register --11 1111 --11 1111 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 87h — Unimplemented — — 88h — Unimplemented — — 89h — Unimplemented — — 8Ah

(1,2)

PCLATH — — — Write Buffer for the upper 5 bits of the PC ---0 0000 ---0 0000 8Bh

(1)

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 8Ch PIE1 — ADIE — — — — — — -0-- ---- -0-- ---- 8Dh — Unimplemented — — 8Eh PCON MPEEN — — — — PER POR BOR u--- -1qq u--- -1uu 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h — Unimplemented — — 93h — Unimplemented — — 94h — Unimplemented — — 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h — Unimplemented — — 99h — Unimplemented — — 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ADCON1 — — — — — — PCFG1 PCFG0 ---- --00 ---- --00

TABLE 4-2: PIC16C715 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR, PER

Value on all

other resets

(3)

Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.

Shaded locations are unimplemented, read as ‘0’.

Note 1: These registers can be addressed from either bank.

2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose

 1997 Microchip Technology Inc. DS30272A-page 17

PIC16C71X

4.2.2.1 STATUS REGISTER

The STATUS register, shown in Figure 4-7, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory.

The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic. Furthermore, the T

O and PD bits are not writable. Therefore, the result of an instruction with the STATUS register as destination may be different than intended.

For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the ST ATUS register as 000u u1uu (where u = unchanged).

Applicable Devices 710 71 711 715

It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C or DC bits from the STA TUS register . For other instructions, not affecting any status bits, see the "Instruction Set Summary."

Note 1: For those devices that do not use bits IRP

and RP1 (STATUS<7:6>), maintain these bits clear to ensure upward compatibility with future products.

Note 2: The C and DC bits operate as a borro

w and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF instructions for examples.

FIGURE 4-7: STATUS REGISTER (ADDRESS 03h, 83h)

R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x

IRP RP1 RP0 TO PD Z DC C R = Readable bit

W = Writable bit U = Unimplemented bit, read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: IRP: Register Bank Select bit (used for indirect addressing)

1 = Bank 2, 3 (100h - 1FFh) 0 = Bank 0, 1 (00h - FFh)

bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing)

11 = Bank 3 (180h - 1FFh) 10 = Bank 2 (100h - 17Fh) 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh)

Each bank is 128 bytes

bit 4: T

O: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred

bit 3: PD

: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction

bit 2: Z: Zero bit

1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero

bit 1: DC: Digit carry/borro

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result

bit 0: C: Carry/borro

w bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most signiﬁcant bit of the result occurred 0 = No carry-out from the most signiﬁcant bit of the result occurred Note: For borro

w the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register.

PIC16C71X

DS30272A-page 18  1997 Microchip Technology Inc.

4.2.2.2 OPTION REGISTER

The OPTION register is a readable and writable register which contains various control bits to conﬁgure the TMR0/WDT prescaler, the External INT Interrupt, TMR0, and the weak pull-ups on PORTB.

Applicable Devices 710 71 711 715

Note: To achieve a 1:1 prescaler assignment for

the TMR0 register, assign the prescaler to the Watchdog Timer by setting bit PSA (OPTION<3>).

FIGURE 4-8: OPTION REGISTER (ADDRESS 81h, 181h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: RBPU: PORTB Pull-up Enable bit

1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values

bit 6: INTEDG: Interrupt Edge Select bit

1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin

bit 5: T0CS: TMR0 Clock Source Select bit

1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT)

bit 4: T0SE: TMR0 Source Edge Select bit

1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin

bit 3: PSA: Prescaler Assignment bit

1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module

bit 2-0: PS2:PS0: Prescaler Rate Select bits

000 001 010 011 100 101 110 111

1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256

1 : 1 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128

Bit Value TMR0 Rate WDT Rate

 1997 Microchip Technology Inc. DS30272A-page 19

PIC16C71X

4.2.2.3 INTCON REGISTER

The INTCON Register is a readable and writable register which contains various enable and ﬂag bits for the TMR0 register overﬂow, RB Port change and Exter nal RB0/INT pin interrupts.

Applicable Devices 710 71 711 715

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).

FIGURE 4-9: INTCON REGISTER (ADDRESS 0Bh, 8Bh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x

GIE ADIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: GIE:

(1)

Global Interrupt Enable bit

1 = Enables all un-masked interrupts 0 = Disables all interrupts

bit 6: ADIE: A/D Converter Interrupt Enable bit

1 = Enables A/D interrupt 0 = Disables A/D interrupt

bit 5: T0IE: TMR0 Overﬂow Interrupt Enable bit

1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt

bit 4: INTE: RB0/INT External Interrupt Enable bit

1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt

bit 3: RBIE: RB Port Change Interrupt Enable bit

1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt

bit 2: T0IF: TMR0 Overﬂow Interrupt Flag bit

1 = TMR0 register has overﬂowed (must be cleared in software) 0 = TMR0 register did not overﬂow

bit 1: INTF: RB0/INT External Interrupt Flag bit

1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur

bit 0: RBIF: RB Port Change Interrupt Flag bit

1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state

Note 1: For the PIC16C71, if an interrupt occurs while the GIE bit is being cleared, the GIE bit may be uninten-

tionally re-enabled by the RETFIE instruction in the user’ s Interrupt Service Routine. Ref er to Section 8.5 for a detailed description.

Interrupt ﬂag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ﬂag bits are clear prior to enabling an interrupt.

PIC16C71X

DS30272A-page 20  1997 Microchip Technology Inc.

4.2.2.4 PIE1 REGISTER

This register contains the individual enable bits for the Peripheral interrupts.

Applicable Devices 710 71 711 715

Note: Bit PEIE (INTCON<6>) must be set to

enable any peripheral interrupt.

FIGURE 4-10: PIE1 REGISTER (ADDRESS 8Ch)

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

— ADIE — — — — — — R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as '0' bit 6: ADIE: A/D Converter Interrupt Enable bit

1 = Enables the A/D interrupt 0 = Disables the A/D interrupt

bit 5-0: Unimplemented: Read as '0'

 1997 Microchip Technology Inc. DS30272A-page 21

PIC16C71X

4.2.2.5 PIR1 REGISTER

This register contains the individual ﬂag bits for the Peripheral interrupts.

Applicable Devices 710 71 711 715

Note: Interrupt ﬂag bits get set when an interrupt

condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt ﬂag bits are clear prior to enabling an interrupt.

FIGURE 4-11: PIR1 REGISTER (ADDRESS 0Ch)

U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0

— ADIF — — — — — — R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: Unimplemented: Read as '0' bit 6: ADIF: A/D Converter Interrupt Flag bit

1 = An A/D conversion completed 0 = The A/D conversion is not complete

bit 5-0: Unimplemented: Read as '0'

PIC16C71X

DS30272A-page 22  1997 Microchip Technology Inc.

4.2.2.6 PCON REGISTER

The Power Control (PCON) register contains a ﬂag bit to allow differentiation between a Power-on Reset (POR) to an external MCLR

Reset or WDT Reset. Those devices with brown-out detection circuitry contain an additional bit to differentiate a Brown-out Reset (BOR) condition from a Power-on Reset condition. For the PIC16C715 the PCON register also contains status bits MPEEN and PER. MPEEN reﬂects the v alue of the MPEEN bit in the conﬁguration word. PER indicates a parity error reset has occurred.

Applicable Devices 710 71 711 715

Note: BOR is unknown on Power-on Reset. It

must then be set by the user and checked on subsequent resets to see if BOR

is clear, indicating a brown-out has occurred. The BOR

status bit is a don't care and is not necessarily predictable if the brown-out circuit is disabled (by clearing the BODEN bit in the Conﬁguration word).

FIGURE 4-12: PCON REGISTER (ADDRESS 8Eh), PIC16C710/711

FIGURE 4-13: PCON REGISTER (ADDRESS 8Eh), PIC16C715

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q

— — — — — — POR BOR R = Readable bit

W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-2: Unimplemented: Read as '0' bit 1: POR

: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0: BOR

: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

R-U U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-q

MPEEN — — — — PER POR BOR

(1)

R = Readable bit W = Writable bit U = Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7: MPEEN: Memory Parity Error Circuitry Status bit

Reﬂects the value of conﬁguration word bit, MPEEN

bit 6-3: Unimplemented: Read as '0' bit 2: PER

: Memory Parity Error Reset Status bit 1 = No Error occurred 0 = Program Memory Fetch Parity Error occurred (must be set in software after a Parity Error Reset)

bit 1: POR

: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)

bit 0: BOR

: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)

 1997 Microchip Technology Inc. DS30272A-page 23

PIC16C71X

4.3 PCL and PCLATH

The program counter (PC) is 13-bits wide. The lo w byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any reset, the upper bits of the PC will be cleared. Figure 4-14 shows the two situations for the loading of the PC. The upper example in the ﬁgure shows how the PC is loaded on a write to PCL (PCLA TH<4:0> → PCH). The low er example in the ﬁgure shows how the PC is loaded during a CALL or GOTO instruction (PCLATH<4:3> → PCH).

FIGURE 4-14: LOADING OF PC IN

DIFFERENT SITUATIONS

4.3.1 COMPUTED GOTO A computed GOTO is accomplished by adding an off-

set to the program counter (ADDWF PCL). When doing a table read using a computed GOTO method, care should be exercised if the tab le location crosses a PCL memory boundary (each 256 byte block). Refer to the application note

“Implementing a Table Read"

(AN556).

12 8 7 0

PCLA TH<4:0>

PCLA TH

Instr

uction with

ALU

GOTO, CALL

Opcode <10:0>

12 11 10 0

PCLATH<4:3>

PCH PCL

8 7

PCLATH

PCH PCL

PCL as Destination

4.3.2 STACK The PIC16CXX family has an 8 lev el deep x 13-bit wide

hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not affected by a PUSH or POP operation.

The stack operates as a circular buff er . This means that after the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the ﬁrst push. The tenth push overwrites the second push (and so on).

4.4 Program Memory Paging

The PIC16C71X devices ignore both paging bits (PCLATH<4:3>, which are used to access program memory when more than one page is available. The use of PCLATH<4:3> as general purpose read/write bits for the PIC16C71X is not recommended since this may affect upward compatibility with future products.

Note 1: There are no status bits to indicate stack

overﬂow or stack underﬂow conditions.

Note 2: There are no instructions/mnemonics

called PUSH or POP. These are actions that occur from the execution of the CALL, RETURN, RETLW, and RETFIE instructions, or the vectoring to an interrupt address.

PIC16C71X

DS30272A-page 24  1997 Microchip Technology Inc.

Example 4-1 shows the calling of a subroutine in page 1 of the program memory. This e xample assumes that PCLA TH is sa ved and restored by the interrupt service routine (if interrupts are used).

EXAMPLE 4-1: CALL OF A SUBROUTINE IN

PAGE 1 FROM PAGE 0

ORG 0x500 BSF PCLATH,3 ;Select page 1 (800h-FFFh) BCF PCLATH,4 ;Only on >4K devices CALL SUB1_P1 ;Call subroutine in : ;page 1 (800h-FFFh) : : ORG 0x900 SUB1_P1: ;called subroutine : ;page 1 (800h-FFFh) : RETURN ;return to Call subroutine ;in page 0 (000h-7FFh)

4.5 Indirect Addressing, INDF and FSR Registers

The INDF register is not a physical register . Addressing the INDF register will cause indirect addressing.

Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = '0') will read 00h. Writing to the INDF register indirectly results in a no-operation (although status bits may be affected). An effective 9-bit address is obtained by concatenating the 8-bit FSR register and the IRP bit (STATUS<7>), as shown in Figure 4-15. However, IRP is not used in the PIC16C71X devices.

A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 4-2.

EXAMPLE 4-2: INDIRECT ADDRESSING

movlw 0x20 ;initialize pointer movwf FSR ;to RAM NEXT clrf INDF ;clear INDF register incf FSR,F ;inc pointer btfss FSR,4 ;all done? goto NEXT ;no clear next CONTINUE : ;yes continue

FIGURE 4-15: DIRECT/INDIRECT ADDRESSING

For register ﬁle map detail see Figure 4-4.

Note 1: The RP1 and IRP bits are reserved, always maintain these bits clear.

Data Memory

Indirect AddressingDirect Addressing

bank select location select

RP1:RP0 6

from opcode

IRP

(1)

FSR register

bank select

location select

00 01 10 11

Bank 0 Bank 1 Bank 2 Bank 3

FFh

80h

7Fh

00h

17Fh

100h

1FFh

180h

Not

Used

 1997 Microchip Technology Inc. DS30272A-page 25

PIC16C71X

5.0 I/O PORTS

Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin.

5.1 PORTA and TRISA Registers

PORTA is a 5-bit latch. The RA4/T0CKI pin is a Schmitt Trigger input and an

open drain output. All other RA port pins have TTL input levels and full CMOS output drivers . All pins have data direction bits (TRIS registers) which can conﬁgure these pins as output or input.

Setting a TRISA register bit puts the corresponding output driver in a hi-impedance mode. Clearing a bit in the TRISA register puts the contents of the output latch on the selected pin(s).

Reading the PORTA register reads the status of the pins whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore a write to a port implies that the port pins are read, this value is modiﬁed, and then written to the port data latch.

Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin.

Other PORTA pins are multiplexed with analog inputs and analog V

REF input. The operation of each pin is

selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1).

The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs.

EXAMPLE 5-1: INITIALIZING PORTA

BCF STATUS, RP0 ; CLRF PORTA ; Initialize PORTA by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<4> as outputs ; TRISA<7:5> are always ; read as '0'.

Applicable Devices 710 71 711 715

Note: On a Power-on Reset, these pins are con-

ﬁgured as analog inputs and read as '0'.

FIGURE 5-1: BLOCK DIAGRAM OF

RA3:RA0 PINS

FIGURE 5-2: BLOCK DIAGRAM OF RA4/

T0CKI PIN

Data bus

Q D

WR Port

WR TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

VDD

I/O pin

(1)

Note 1: I/O pins have protection diodes to VDD and

VSS.

Analog input mode

TTL input buffer

To A/D Converter

Data bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

RD TRIS

Schmitt Trigger input buffer

I/O pin

(1)

TMR0 clock input

Note 1: I/O pin has protection diodes to VSS only.

Q D

PIC16C71X

DS30272A-page 26  1997 Microchip Technology Inc.

TABLE 5-1: PORTA FUNCTIONS

TABLE 5-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA

Name Bit# Buffer Function

RA0/AN0 bit0 TTL Input/output or analog input RA1/AN1 bit1 TTL Input/output or analog input RA2/AN2 bit2 TTL Input/output or analog input RA3/AN3/V

REF bit3 TTL Input/output or analog input/VREF

RA4/T0CKI bit4 ST Input/output or external clock input for Timer0

Output is open drain type

Legend: TTL = TTL input, ST = Schmitt Trigger input

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on all

other resets

05h PORTA — — — RA4 RA3 RA2 RA1 RA0 ---x 0000 ---u 0000 85h TRISA — — — PORTA Data Direction Register ---1 1111 ---1 1111 9Fh ADCON1 — — — — — — PCFG1 PCFG0 ---- --00 ---- --00

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA.

 1997 Microchip Technology Inc. DS30272A-page 27

PIC16C71X

5.2 PORTB and TRISB Registers

PORTB is an 8-bit wide bi-directional port. The corresponding data direction register is TRISB. Setting a bit in the TRISB register puts the corresponding output driver in a hi-impedance input mode. Clearing a bit in the TRISB register puts the contents of the output latch on the selected pin(s).

EXAMPLE 5-2: INITIALIZING PORTB

BCF STATUS, RP0 ; CLRF PORTB ; Initialize PORTB by ; clearing output ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISB ; Set RB<3:0> as inputs ; RB<5:4> as outputs ; RB<7:6> as inputs

Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU

(OPTION<7>). The weak pull-up is automatically turned off when the port pin is conﬁgured as an output. The pull-ups are disabled on a Power-on Reset.

FIGURE 5-3: BLOCK DIAGRAM OF

RB3:RB0 PINS

Data Latch

RBPU

(2)

Q D

Data bus

WR Port

WR TRIS

RD TRIS

RD Port

weak pull-up

RD Port

RB0/INT

I/O pin

(1)

TTL Input Buffer

Note 1: I/O pins have diode protection to V

DD and VSS.

2: TRISB = ’1’ enables weak pull-up if

RBPU

= ’0’ (OPTION<7>).

Schmitt Trigger Buffer

TRIS Latch

Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins conﬁgured as inputs can cause this interrupt to occur (i.e. an y RB7:RB4 pin conﬁgured as an output is excluded from the interrupt on change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB7:RB4 are OR’ed together to generate the RB Port Change Interrupt with ﬂag bit RBIF (INTCON<0>).

This interrupt can wake the device from SLEEP. The user, in the interrupt service routine, can clear the interrupt in the following manner:

a) Any read or write of PORTB. This will end the

mismatch condition.

b) Clear ﬂag bit RBIF. A mismatch condition will continue to set ﬂag bit RBIF.

Reading PORTB will end the mismatch condition, and allow ﬂag bit RBIF to be cleared.

This interrupt on mismatch feature, together with software conﬁgurable pull-ups on these four pins allow easy interface to a keypad and make it possible for wake-up on key-depression. Refer to the Embedded Control Handbook,

"Implementing Wake-Up on Key

Stroke"

(AN552).

The interrupt on change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt on change feature.

Note: For the PIC16C71

if a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then interrupt ﬂag bit RBIF may not get set.

PIC16C71X

DS30272A-page 28  1997 Microchip Technology Inc.

FIGURE 5-4: BLOCK DIAGRAM OF

RB7:RB4 PINS (PIC16C71)

Data Latch

From other

RBPU

(2)

I/O

Q D

Data bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weak pull-up

RD Port

Latch

TTL Input Buffer

(1)

Buffer

RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to VDD and VSS.

2: TRISB = ’1’ enables weak pull-up if

RBPU

= ’0’ (OPTION<7>).

FIGURE 5-5: BLOCK DIAGRAM OF

RB7:RB4 PINS (PIC16C710/711/715)

Data Latch

From other

RBPU

(2)

I/O

Q D

Data bus

WR Port

WR TRIS

Set RBIF

TRIS Latch

RD TRIS

RD Port

RB7:RB4 pins

weak pull-up

RD Port

Latch

TTL Input Buffer

(1)

Buffer

RB7:RB6 in serial programming mode

Note 1: I/O pins have diode protection to V

DD and VSS.

2: TRISB = ’1’ enables weak pull-up if

RBPU

= ’0’ (OPTION<7>).

TABLE 5-3: PORTB FUNCTIONS

Name Bit# Buffer Function

RB0/INT bit0 TTL/ST

(1)

Input/output pin or external interrupt input. Internal software

programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. RB6 bit6 TTL/ST

(2)

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial programming clock. RB7 bit7 TTL/ST

(2)

Input/output pin (with interrupt on change). Internal software programmable

weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input

Note 1: This buffer is a Schmitt Trigger input when conﬁgured as the external interrupt.

2: This buffer is a Schmitt Trigger input when used in serial programming mode.

 1997 Microchip Technology Inc. DS30272A-page 29

PIC16C71X

TABLE 5-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all

other resets

06h, 106h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h, 186h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h, 181h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.

PIC16C71X

DS30272A-page 30  1997 Microchip Technology Inc.

5.3 I/O Programming Considerations

5.3.1 BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a

read followed by a write operation. The BCF and BSF instructions, for example, read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs deﬁned. For example, a BSF operation on bit5 of PORTB will cause all eight bits of PORTB to be read into the CPU. Then the BSF operation takes place on bit5 and PORTB is written to the output latches. If another bit of PORTB is used as a bi-directional I/O pin (e.g., bit0) and it is deﬁned as an input at this time, the input signal present on the pin itself would be read into the CPU and rewritten to the data latch of this particular pin, overwriting the previous content. As long as the pin stays in the input mode, no problem occurs. However, if bit0 is switched to an output, the content of the data latch may now be unknown.

Reading the port register, reads the values of the port pins. Writing to the port register writes the value to the port latch. When using read-modify-write instructions (ex. BCF, BSF , etc.) on a port, the value of the port pins is read, the desired operation is done to this value, and this value is then written to the port latch.

Example 5-3 shows the effect of two sequential readmodify-write instructions on an I/O port.

EXAMPLE 5-3: READ-MODIFY-WRITE

INSTRUCTIONS ON AN I/O PORT

;Initial PORT settings: PORTB<7:4> Inputs ; PORTB<3:0> Outputs ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; PORT latch PORT pins ; ---------- -------- BCF PORTB, 7 ; 01pp pppp 11pp pppp BCF PORTB, 6 ; 10pp pppp 11pp pppp BSF STATUS, RP0 ; BCF TRISB, 7 ; 10pp pppp 11pp pppp BCF TRISB, 6 ; 10pp pppp 10pp pppp ; ;Note that the user may have expected the ;pin values to be 00pp ppp. The 2nd BCF ;caused RB7 to be latched as the pin value ;(high).

A pin actively outputting a Low or High should not be driven from external devices at the same time in order to change the level on this pin (“wired-or”, “wired-and”). The resulting high output currents may damage the chip.

5.3.2 SUCCESSIVE OPERATIONS ON I/O PORTS The actual write to an I/O port happens at the end of an

instruction cycle, whereas for reading, the data must be valid at the beginning of the instruction cycle (Figure 5-6). Therefore, care must be exercised if a write followed by a read operation is carried out on the same I/O port. The sequence of instructions should be such to allow the pin voltage to stabilize (load dependent) before the next instruction which causes that ﬁle to be read into the CPU is executed. Otherwise, the previous state of that pin may be read into the CPU rather than the new state. When in doubt, it is better to separate these instructions with a NOP or another instruction not accessing this I/O port.

FIGURE 5-6: SUCCESSIVE I/O OPERATION

PC PC + 1 PC + 2

PC + 3

Q1 Q2

Instruction

fetched

RB7:RB0

MOVWF PORTB

write to PORTB

NOP

Port pin sampled here

NOP

MOVF PORTB,W

Instruction

executed

MOVWF PORTB

write to PORTB

NOP

MOVF PORTB,W

TPD

Note: This example shows a write to PORTB

followed by a read from PORTB. Note that: data setup time = (0.25TCY - TPD) where TCY = instruction cycle

TPD = propagation delay

Therefore, at higher clock frequencies, a write followed by a read may be problematic.

 1997 Microchip Technology Inc. DS30272A-page 31

PIC16C71X

6.0 TIMER0 MODULE

The Timer0 module timer/counter has the following f eatures:

• 8-bit timer/counter

• Readable and writable

• 8-bit software programmable prescaler

• Internal or external clock select

• Interrupt on overﬂow from FFh to 00h

• Edge select for external clock Figure 6-1 is a simpliﬁed block diagram of the Timer0

module. Timer mode is selected by clearing bit T0CS

(OPTION<5>). In timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles (Figure 6-2 and Figure 6-3). The user can work around this by writing an adjusted value to the TMR0 register.

Counter mode is selected by setting bit T0CS (OPTION<5>). In counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION<4>). Clear ing

Applicable Devices 710 71 711 715

bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 6.2.

The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The prescaler assignment is controlled in software by control bit PSA (OPTION<3>). Clearing bit PSA will assign the prescaler to the Timer0 module. The prescaler is not readable or writable. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. Section 6.3 details the operation of the prescaler.

6.1 Timer0 Interrupt

The TMR0 interrupt is generated when the TMR0 register overﬂows from FFh to 00h. This overﬂow sets bit T0IF (INTCON<2>). The interr upt can be masked by clearing bit T0IE (INTCON<5>). Bit T0IF must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP since the timer is shut off during SLEEP. See Figure 6-4 for Timer0 interrupt timing.

FIGURE 6-1: TIMER0 BLOCK DIAGRAM

FIGURE 6-2: TIMER0 TIMING: INTERNAL CLOCK/NO PRESCALE

Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION<5:0>).

2: The prescaler is shared with Watchdog Timer (refer to Figure 6-6 for detailed block diagram).

RA4/T0CKI

T0SE

T0CS

FOSC/4

Programmable

Prescaler

Sync with

Internal

clocks

TMR0

PSout

(2 cycle delay)

PSout

Data bus

PSA

PS2, PS1, PS0

Set interrupt

ﬂag bit T0IF on overﬂow

PC-1

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC (Program Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0+1 T0+2 NT0 NT0 NT0 NT0+1 NT0+2

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

Read TMR0 reads NT0 + 2

Instruction Executed

PIC16C71X

DS30272A-page 32  1997 Microchip Technology Inc.

FIGURE 6-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1:2

FIGURE 6-4: TIMER0 INTERRUPT TIMING

PC+

PC-1

Q1 Q2 Q3 Q4

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

PC (Program Counter)

Instruction

Fetch

TMR0

PC PC+1 PC+2 PC+3 PC+4 PC+5 PC+6

T0 NT0+1

MOVWF TMR0

MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W MOVF TMR0,W

Write TMR0 executed

Read TMR0 reads NT0

Read TMR0 reads NT0 + 1

T0+1

NT0

Instruction Execute

Q2Q1 Q3 Q4Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT(3)

Timer0

T0IF bit (INTCON<2>)

FEh

GIE bit (INTCON<7>)

INSTR

UCTION

Instruction fetched

PC +1 PC +1 0004h 0005h

Instruction executed

Inst (PC)

Inst (PC-1)

Inst (PC+1)

Inst (PC)

Inst (0004h) Inst (0005h)

Inst (0004h)Dummy cycle Dummy cycle

FFh 00h 01h 02h

Note 1: Interrupt ﬂag bit T0IF is sampled here (every Q1).

2: Interrupt latency = 4Tcy where Tcy = instruction cycle time. 3: CLKOUT is available only in RC oscillator mode.

FLO

 1997 Microchip Technology Inc. DS30272A-page 33

PIC16C71X

6.2 Using Timer0 with an External Clock

When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (T

OSC). Also, there is a delay in the actual

incrementing of Timer0 after synchronization.

6.2.1 EXTERNAL CLOCK SYNCHRONIZATION When no prescaler is used, the external clock input is

the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks (Figure 6-5). Therefore, it is necessary for T0CKI to be high for at least 2Tosc (and a small RC delay of 20 ns) and low for at least 2Tosc (and a small RC delay of 20 ns). Refer to the electrical speciﬁcation of the desired device.

When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type pres-

caler so that the prescaler output is symmetrical. For the external clock to meet the sampling requirement, the ripple-counter must be taken into account. Therefore, it is necessary for T0CKI to have a period of at least 4Tosc (and a small RC delay of 40 ns) divided by the prescaler value. The only requirement on T0CKI high and low time is that they do not violate the minimum pulse width requirement of 10 ns. Refer to par ameters 40, 41 and 42 in the electrical speciﬁcation of the desired device.

6.2.2 TMR0 INCREMENT DELAY Since the prescaler output is synchronized with the

internal clocks, there is a small delay from the time the external clock edge occurs to the time the Timer0 module is actually incremented. Figure 6-5 shows the delay from the external clock edge to the timer incrementing.

FIGURE 6-5: TIMER0 TIMING WITH EXTERNAL CLOCK

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

External Clock Input or Prescaler output

(2)

External Clock/Prescaler Output after sampling

Increment Timer0 (Q4)

Timer0

T0 T0 + 1 T0 + 2

Small pulse misses sampling

Note 1: Delay from clock input change to Timer0 increment is 3Tosc to 7Tosc. (Duration of Q = Tosc).

Therefore, the error in measuring the interval between two edges on Timer0 input = ±4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs.

(3)

(1)

PIC16C71X

DS30272A-page 34  1997 Microchip Technology Inc.

6.3 Prescaler

An 8-bit counter is available as a prescaler for the Timer0 module, or as a postscaler for the Watchdog Timer, respectively (Figure 6-6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. Note that there is only one prescaler available which is m utually e xclusiv ely shared between the Timer0 module and the Watchdog Timer. Thus, a prescaler assignment for the Timer0 module means that there is no prescaler for the Watchdog Timer, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF 1, MOVWF 1,

BSF 1,x....etc.) will clear the prescaler. When

assigned to WDT, a CLRWDT instruction will clear the prescaler along with the Watchdog Timer. The prescaler is not readable or writable.

Note: Writing to TMR0 when the prescaler is

assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment.

FIGURE 6-6: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

RA4/T0CKI

T0SE

M U

CLKOUT (=Fosc/4)

SYNC

Cycles

TMR0 reg

8-bit Prescaler

8 - to - 1MUX

U X

M U X

Watchdog

Timer

PSA

WDT

Time-out

PS2:PS0

Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).

PSA

WDT Enable bit

U X

Data Bus

Set ﬂag bit T0IF

on Overﬂow

PSA

T0CS

 1997 Microchip Technology Inc. DS30272A-page 35

PIC16C71X

6.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con-

trol, i.e., it can be changed “on the ﬂy” during program execution.

Note: To a void an unintended de vice RESET, the

following instruction sequence (shown in Example 6-1) must be executed when changing the prescaler assignment from Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.

EXAMPLE 6-1: CHANGING PRESCALER (TIMER0→WDT)

BCF STATUS, RP0 ;Bank 0 CLRF TMR0 ;Clear TMR0 & Prescaler BSF STATUS, RP0 ;Bank 1 CLRWDT ;Clears WDT MOVLW b'xxxx1xxx' ;Selects new prescale value MOVWF OPTION_REG ;and assigns the prescaler to the WDT BCF STATUS, RP0 ;Bank 0

To change prescaler from the WDT to the Timer0 module use the sequence shown in Example 6-2.

EXAMPLE 6-2: CHANGING PRESCALER (WDT→TIMER0)

CLRWDT ;Clear WDT and prescaler BSF STATUS, RP0 ;Bank 1 MOVLW b'xxxx0xxx' ;Select TMR0, new prescale value and MOVWF OPTION_REG ;clock source BCF STATUS, RP0 ;Bank 0

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER0

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR, BOR

Value on all

other resets

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 0Bh,8Bh, INTCON GIE ADIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 81h OPTION RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA — — — PORTA Data Direction Register ---1 1111 ---1 1111

Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0.

PIC16C71X

DS30272A-page 36  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. DS30272A-page 37

PIC16C71X

FIGURE 7-1: ADCON0 REGISTER (ADDRESS 08h), PIC16C710/71/711

R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

ADCS1 ADCS0

—

(1)

CHS1 CHS0 GO/DONE ADIF ADON R =Readable bit

W =Writable bit U =Unimplemented

bit, read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits

00 = F

OSC/2

01 = F

OSC/8

10 = F

OSC/32

11 = F

RC (clock derived from an RC oscillation)

bit 5: Unimplemented: Read as '0'. bit 4-3: CHS1:CHS0: Analog Channel Select bits

00 = channel 0, (RA0/AN0) 01 = channel 1, (RA1/AN1) 10 = channel 2, (RA2/AN2) 11 = channel 3, (RA3/AN3)

bit 2: GO/DONE

: A/D Conversion Status bit

If ADON = 1

: 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete)

bit 1: ADIF: A/D Conversion Complete Interrupt Flag bit

1 = conversion is complete (must be cleared in software) 0 = conversion is not complete

bit 0: ADON: A/D On bit

1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current

Note 1: Bit5 of ADCON0 is a General Pur pose R/W bit for the PIC16C710/711 only. For the PIC16C71, this bit is

unimplemented, read as '0'.

7.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE

The analog-to-digital (A/D) converter module has four analog inputs.

The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Application Note AN546 for use of A/D Converter). The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog reference voltage is software selectable to either the device’ s positiv e supply v oltage (V

DD)

or the voltage level on the RA3/AN3/V

REF pin.

Applicable Devices 710 71 711 715

The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. T o operate in sleep, the A/D conversion clock must be derived from the A/D’s internal RC oscillator.

The A/D module has three registers. These registers are:

• A/D Result Register (ADRES)

• A/D Control Register 0 (ADCON0)

• A/D Control Register 1 (ADCON1)

The ADCON0 register, shown in Figure 7-1 and Figure 7-2, controls the operation of the A/D module. The ADCON1 register, shown in Figure 7-3 conﬁgures the functions of the port pins. The port pins can be conﬁgured as analog inputs (RA3 can also be a voltage reference) or as digital I/O.

PIC16C71X

DS30272A-page 38  1997 Microchip Technology Inc.

FIGURE 7-2: ADCON0 REGISTER (ADDRESS 1Fh), PIC16C715

FIGURE 7-3: ADCON1 REGISTER, PIC16C710/71/711 (ADDRESS 88h),

PIC16C715 (ADDRESS 9Fh)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0

ADCS1 ADCS0

— CHS1 CHS0 GO/DONE — ADON R =Readable bit

W =Writable bit U =Unimplemented bit,

read as ‘0’

- n = Value at POR reset

bit7 bit0

bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits

00 = F

OSC/2

01 = F

OSC/8

10 = F

OSC/32

11 = F

RC (clock derived from an RC oscillation)

bit 5: Unused bit 6-3: CHS1:CHS0: Analog Channel Select bits

000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 0, (RA0/AN0) 101 = channel 1, (RA1/AN1) 110 = channel 2, (RA2/AN2) 111 = channel 3, (RA3/AN3)

bit 2: GO/DONE

: A/D Conversion Status bit

If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conver-

sion is complete) bit 1: Unimplemented: Read as '0' bit 0: ADON: A/D On bit

1 = A/D converter module is operating

0 = A/D converter module is shutoff and consumes no operating current

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0

— — — — — — PCFG1 PCFG0 R =Readable bit

W =Writable bit U =Unimplemented

bit, read as ‘0’

- n =Value at POR reset

bit7 bit0

bit 7-2: Unimplemented: Read as '0' bit 1-0: PCFG1:PCFG0: A/D Port Conﬁguration Control bits

A = Analog input D = Di

ital I/O

PCFG1:PCFG0 RA1 & RA0 RA2 RA3 V

REF

00 A A A VDD 01 A A VREF RA3 10 A D D V

11 D D D VDD

 1997 Microchip Technology Inc. DS30272A-page 39

PIC16C71X

The ADRES register contains the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt ﬂag bit ADIF is set. The block diagram of the A/D module is shown in Figure 7-4.

After the A/D module has been conﬁgured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 7.1. After this acquisition time has elapsed the A/D conversion can be started. The following steps should be followed for doing an A/D conversion:

1. Conﬁgure the A/D module:

• Conﬁgure analog pins / voltage reference / and digital I/O (ADCON1)

• Select A/D input channel (ADCON0)

• Select A/D conversion clock (ADCON0)

• Turn on A/D module (ADCON0)

2. Conﬁgure A/D interrupt (if desired):

• Clear ADIF bit

• Set ADIE bit

• Set GIE bit

3. Wait the required acquisition time.

4. Start conversion:

• Set GO/DONE

bit (ADCON0)

5. Wait for A/D conversion to complete, by either:

• Polling for the GO/DONE

bit to be cleared

• Waiting for the A/D interrupt

6. Read A/D Result register (ADRES), clear bit ADIF if required.

7. For next conversion, go to step 1 or step 2 as required. The A/D conversion time per bit is deﬁned as T

AD. A minimum wait of 2TAD is

required before next acquisition starts.

FIGURE 7-4: A/D BLOCK DIAGRAM

(Input voltage)

VIN

VREF

(Reference

voltage)

PCFG1:PCFG0

CHS1:CHS0

00 or 10 or 11

RA3/AN3/V

REF

RA0/AN0

RA2/AN2

RA1/AN1

A/D

Converter

PIC16C71X

DS30272A-page 40  1997 Microchip Technology Inc.

7.1 A/D Acquisition Requirements

For the A/D converter to meet its speciﬁed accuracy, the charge holding capacitor (C

HOLD) must be allowed

to fully charge to the input channel voltage level. The analog input model is shown in Figure 7-5. The source impedance (R

S) and the internal sampling switch (RSS)

impedance directly affect the time required to charge the capacitor C

HOLD. The sampling switch (RSS)

impedance varies over the device voltage (V

DD),

Figure 7-5. The source impedance affects the offset voltage at the analog input (due to pin leakage current).

The maximum recommended impedance for analog sources is 10 kΩ . After the analog input channel is

selected (changed) this acquisition must be done before the conversion can be started.

To calculate the minimum acquisition time, Equation 71 may be used. This equation calculates the acquisition time to within 1/2 LSb error is used (512 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its speciﬁed accuracy.

EQUATION 7-1: A/D MINIMUM CHARGING

TIME

VHOLD = (VREF - (VREF/512)) • (1 - e

(-TCAP/CHOLD(RIC + RSS + RS))

) Given: VHOLD = (VREF/512), for 1/2 LSb resolution The above equation reduces to: TCAP = -(51.2 pF)(1 kΩ + RSS + RS) ln(1/511)

Example 7-1 shows the calculation of the minimum required acquisition time T

ACQ. This calculation is

based on the following system assumptions. C

HOLD = 51.2 pF

Rs = 10 k

Ω

1/2 LSb error V

DD = 5V → Rss = 7 kΩ

Temp (application system max.) = 50°C V

HOLD = 0 @ t = 0

EXAMPLE 7-1: CALCULATING THE

MINIMUM REQUIRED AQUISITION TIME

TACQ = Ampliﬁer Settling Time +

Holding Capacitor Charging Time + Temperature Coefﬁcient

ACQ = 5 µs + TCAP + [(Temp - 25°C)(0.05 µs/°C)]

CAP = -CHOLD (RIC + RSS + RS) ln(1/511)

-51.2 pF (1 kΩ + 7 kΩ + 10 kΩ) ln(0.0020)

-51.2 pF (18 kΩ) ln(0.0020)

-0.921 µs (-6.2364)

5.747 µs

ACQ = 5 µs + 5.747 µs + [(50°C - 25°C)(0.05 µs/°C)]

10.747 µs + 1.25 µs

11.997 µs

Note 1: The reference voltage (VREF) has no

effect on the equation, since it cancels itself out.

Note 2: The charge holding capacitor (C

HOLD) is

not discharged after each conversion.

Note 3: The maximum recommended impedance

for analog sources is 10 kΩ. This is required to meet the pin leakage speciﬁcation.

Note 4: After a conversion has completed, a

2.0T

AD delay must complete before acqui-

sition can begin again. During this time the holding capacitor is not connected to the selected A/D input channel.

FIGURE 7-5: ANALOG INPUT MODEL

CPIN

ANx

5 pF

VT = 0.6V

T = 0.6V

I leakage

IC ≤ 1k

Sampling Switch

CHOLD = DAC capacitance

Sampling Switch

5V 4V 3V 2V

5 6 7 8 9 10 11

( kΩ )

VDD

= 51.2 pF

± 500 nA

Legend CPIN

VT I leakage

RIC SS C

HOLD

= input capacitance = threshold voltage

= leakage current at the pin due to

= interconnect resistance = sampling switch = sample/hold capacitance (from DAC)

various junctions

 1997 Microchip Technology Inc. DS30272A-page 41

PIC16C71X

7.2 Selecting the A/D Conversion Clock

The A/D conversion time per bit is deﬁned as TAD. The A/D conversion requires 9.5T

AD per 8-bit conversion.

The source of the A/D conversion clock is software selectable. The four possible options for T

AD are:

• 2T

OSC

• 8TOSC

• 32TOSC

• Internal RC oscillator

For correct A/D conversions, the A/D conversion clock (T

AD) must be selected to ensure a minimum TAD time

of:

2.0 µs for the PIC16C71

1.6 µs for all other PIC16C71X devices Table 7-1 and Table 7-2 and show the resultant T

times derived from the device operating frequencies and the A/D clock source selected.

7.3 Configuring Analog Port Pins

The ADCON1 and TRISA registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (V

OH or VOL) will be converted.

The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits.

Note 1: When reading the port register, all pins

conﬁgured as analog input channels will read as cleared (a low level). Pins conﬁgured as digital inputs, will convert an analog input. Analog levels on a digitally conﬁgured input will not affect the conversion accuracy.

Note 2: Analog levels on any pin that is deﬁned as

a digital input (including the AN7:AN0 pins), may cause the input buffer to consume current that is out of the devices speciﬁcation.

TABLE 7-1: TAD vs. DEVICE OPERATING FREQUENCIES, PIC16C71

TABLE 7-2: TAD vs. DEVICE OPERATING FREQUENCIES, PIC16C710/711, PIC16C715

AD Clock Source (TAD) Device Frequency

Operation ADCS1:ADCS0 20 MHz 16 MHz 4 MHz 1 MHz 333.33 kHz

OSC 00

100 ns

(2)

125 ns

(2)

500 ns

(2)

2.0 µs 6 µs

8TOSC 01

400 ns

(2)

500 ns

(2)

2.0 µs 8.0 µs

24 µs

(3)

32TOSC 10

1.6 µs

(2)

2.0 µs 8.0 µs

32.0 µs

(3)

96 µs

(3)

(5)

2 - 6 µs

(1,4)

2 - 6 µs

(1,4)

2 - 6 µs

(1,4)

2 - 6 µs

(1)

2 - 6 µs

(1)

Legend: Shaded cells are outside of recommended range. Note 1: The RC source has a typical T

AD time of 4 µs.

2: These values violate the minimum required T

AD time.

3: For faster conversion times, the selection of another clock source is recommended. 4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for

sleep operation only.

5: For extended voltage devices (LC), please refer to Electrical Speciﬁcations section.

AD Clock Source (T

AD) Device Frequency

Operation ADCS1:ADCS0 20 MHz 5 MHz 1.25 MHz 333.33 kHz

OSC 00

100 ns

(2)

400 ns

(2)

1.6 µs 6 µs

8TOSC 01

400 ns

(2)

1.6 µs 6.4 µs

24 µs

(3)

32TOSC 10 1.6 µs 6.4 µs

25.6 µs

(3)

96 µs

(3)

(5)

2 - 6 µs

(1,4)

2 - 6 µs

(1,4)

2 - 6 µs

(1,4)

2 - 6 µs

(1)

Legend: Shaded cells are outside of recommended range. Note 1: The RC source has a typical T

AD time of 4 µs.

2: These values violate the minimum required T

AD time.

3: For faster conversion times, the selection of another clock source is recommended. 4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for

sleep operation only.

5: For extended voltage devices (LC), please refer to Electrical Speciﬁcations section.

PIC16C71X

DS30272A-page 42  1997 Microchip Technology Inc.

7.4 A/D Conversions

Example 7-2 shows how to perform an A/D conv ersion. The RA pins are conﬁgured as analog inputs. The analog reference (V

REF) is the device VDD. The A/D inter-

rupt is enabled, and the A/D conversion clock is F

RC.

The conversion is performed on the RA0 pin (channel

0).

Clearing the GO/DONE

bit during a conversion will abort the current conversion. The ADRES register will NOT be updated with the partially completed A/D conversion sample. That is, the ADRES register will continue to contain the value of the last completed conversion (or the last value written to the ADRES register). After the A/D conversion is aborted, a 2T

AD wait

is required before the next acquisition is started. After this 2T

AD wait, an acquisition is automatically star ted

on the selected channel.

Note: The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

EXAMPLE 7-2: A/D CON VER SION

BSF STATUS, RP0 ; Select Bank 1 CLRF ADCON1 ; Configure A/D inputs BCF STATUS, RP0 ; Select Bank 0 MOVLW 0xC1 ; RC Clock, A/D is on, Channel 0 is selected MOVWF ADCON0 ; BSF INTCON, ADIE ; Enable A/D Interrupt BSF INTCON, GIE ; Enable all interrupts ; ; Ensure that the required sampling time for the selected input channel has elapsed. ; Then the conversion may be started. ; BSF ADCON0, GO ; Start A/D Conversion : ; The ADIF bit will be set and the GO/DONE bit : ; is cleared upon completion of the A/D Conversion.

 1997 Microchip Technology Inc. DS30272A-page 43

PIC16C71X

7.4.1 FASTER CONVERSION - LOWER RESOLUTION TRADE-OFF

Not all applications require a result with 8-bits of resolution, but may instead require a f aster conversion time . The A/D module allows users to make the trade-off of conversion speed to resolution. Regardless of the resolution required, the acquisition time is the same. To speed up the conversion, the clock source of the A/D module may be switched so that the T

AD time violates

the minimum speciﬁed time (see the applicable electrical speciﬁcation). Once the T

AD time violates the mini-

mum speciﬁed time, all the following A/D result bits are not valid (see A/D Conversion Timing in the Electrical Speciﬁcations section.) The clock sources may only be switched between the three oscillator versions (cannot be switched from/to RC). The equation to determine the time before the oscillator can be switched is as follows:

Conversion time = 2T

AD + N • TAD + (8 - N)(2TOSC)

Where: N = number of bits of resolution required.

Since the T

AD is based from the device oscillator, the

user must use some method (a timer, software loop, etc.) to determine when the A/D oscillator may be changed. Example 7-3 shows a comparison of time required for a conversion with 4-bits of resolution, versus the 8-bit resolution conversion. The example is for devices operating at 20 MHz and 16 MHz (The A/D clock is programmed for 32T

OSC), and assumes that

immediately after 6T

AD, the A/D clock is programmed

for 2T

OSC.

The 2T

OSC violates the minimum TAD time since the

last 4-bits will not be converted to correct values.

EXAMPLE 7-3: 4-BIT vs. 8-BIT CONVERSION TIMES

Freq. (MHz)

(1)

Resolution

4-bit 8-bit

TAD 20 1.6 µs 1.6 µs

16 2.0 µs 2.0 µs

OSC 20 50 ns 50 ns

16 62.5 ns 62.5 ns

AD + N • TAD + (8 - N)(2TOSC) 20 10 µs 16 µs

16 12.5 µs 20 µs

Note 1: The PIC16C71 has a minimum T

AD time of 2.0 µs.

All other PIC16C71X devices have a minimum T

AD time of 1.6 µs.

PIC16C71X

DS30272A-page 44  1997 Microchip Technology Inc.

7.5 A/D Operation During Sleep

The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion. When the conversion is completed the GO/DONE

bit will be cleared, and the result loaded into the ADRES register. If the A/D interrupt is enabled, the device will wake-up from SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will remain set.

When the A/D clock source is another clock option (not RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off, though the ADON bit will remain set.

Turning off the A/D places the A/D module in its lowest current consumption state.

7.6 A/D Accuracy/Error

The absolute accuracy speciﬁed for the A/D converter includes the sum of all contributions for quantization error, integral error , diff erential error , full scale error, offset error, and monotonicity. It is deﬁned as the maximum deviation from an actual transition versus an ideal transition for any code. The absolute error of the A/D converter is speciﬁed at < ±1 LSb for V

DD = VREF (over

the device’s speciﬁed operating range). However, the accuracy of the A/D converter will degrade as V

diverges from VREF. For a given range of analog inputs, the output digital

code will be the same. This is due to the quantization of the analog input to a digital code. Quantization error is typically ± 1/2 LSb and is inherent in the analog to digital conversion process. The only way to reduce quantization error is to increase the resolution of the A/D converter.

Offset error measures the ﬁrst actual transition of a code versus the ﬁrst ideal transition of a code. Offset error shifts the entire transfer function. Offset error can be calibrated out of a system or introduced into a system through the interaction of the total leakage current and source impedance at the analog input.

Gain error measures the maximum deviation of the last actual transition and the last ideal transition adjusted for offset error . This error appears as a change in slope of the transfer function. The difference in gain error to

Note: For the A/D module to operate in SLEEP,

the A/D clock source must be set to RC (ADCS1:ADCS0 = 11). To perform an A/D conversion in SLEEP, ensure the SLEEP instruction immediately follows the instruction that sets the GO/DONE

bit.

full scale error is that full scale does not take offset error into account. Gain error can be calibrated out in software.

Linearity error refers to the uniformity of the code changes. Linearity errors cannot be calibrated out of the system. Integral non-linearity error measures the actual code transition versus the ideal code transition adjusted by the gain error for each code.

Differential non-linearity measures the maximum actual code width versus the ideal code width. This measure is unadjusted.

In systems where the device frequency is low, use of the A/D RC clock is preferred. At moderate to high frequencies, T

AD should be derived from the device oscil-

lator. T

AD must not violate the minimum and should be

≤ 8 µs for preferred operation. This is because T

AD,

when derived from T

OSC, is kept away from on-chip

phase clock transitions. This reduces , to a large e xtent, the effects of digital switching noise. This is not possible with the RC derived clock. The loss of accuracy due to digital switching noise can be signiﬁcant if many I/O pins are active.

In systems where the device will enter SLEEP mode after the start of the A/D conversion, the RC clock source selection is required. In this mode, the digital noise from the modules in SLEEP are stopped. This method gives high accuracy.

7.7 Effects of a RESET

A device reset forces all registers to their reset state. This forces the A/D module to be turned off, and any conversion is aborted.

The value that is in the ADRES register is not modiﬁed for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset.

7.8 Connection Considerations

If the input voltage exceeds the rail v alues (VSS or VDD) by greater than 0.2V, then the accuracy of the conversion is out of speciﬁcation.

An external RC ﬁlter is sometimes added for anti-aliasing of the input signal. The R component should be selected to ensure that the total source impedance is kept under the 10 kΩ recommended speciﬁcation. Any external components connected (via hi-impedance) to an analog input pin (capacitor, zener diode , etc.) should have very little leakage current at the pin.

Note: Care must be taken when using the RA0

pin in A/D conversions due to its proximity to the OSC1 pin.

 1997 Microchip Technology Inc. DS30272A-page 45

PIC16C71X

7.9 Transfer Function

The ideal transfer function of the A/D conv erter is as follows: the ﬁrst transition occurs when the analog input voltage (V

AIN) is Analog VREF/256 (Figure 7-6).

7.10 References

A very good reference for understanding A/D converters is the "Analog-Digital Conversion Handbook" third edition, published by Prentice Hall (ISBN 0-13-032848-0).

FIGURE 7-6: A/D TRANSFER FUNCTION

Digital code output

FFh FEh

04h 03h 02h 01h 00h

0.5 LSb

1 LSb

2 LSb

3 LSb

4 LSb

255 LSb

256 LSb

(full scale)

Analog input voltage

FIGURE 7-7: FLOWCHART OF A/D OPERATION

Acquire

ADON = 0

ADON = 0?

GO = 0?

A/D Clock

GO = 0

ADIF = 0

Abort Conversion

SLEEP

Power-down A/D

Wait 2 T

Wake-up

Yes

Finish Conversion

GO = 0

ADIF = 1

Device in

Yes

Finish Conversion

GO = 0

ADIF = 1

Wait 2 TAD

Stay in Sleep

Selected Channel

= RC?

SLEEP

Yes

Instruction?

Start of A/D

Conversion Delayed

1 Instruction Cycle

From Sleep?

Power-down A/D

Yes

Wait 2 TAD

Finish Conversion

GO = 0

ADIF = 1

SLEEP?

PIC16C71X

DS30272A-page 46  1997 Microchip Technology Inc.

TABLE 7-3: REGISTERS/BITS ASSOCIATED WITH A/D, PIC16C710/71/711

TABLE 7-4: REGISTERS/BITS ASSOCIATED WITH A/D, PIC16C715

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on

all other

Resets

0Bh,8Bh

INTCON GIE ADIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

89h

ADRES A/D Result Register xxxx xxxx uuuu uuuu

08h

ADCON0 ADCS1 ADCS0 — CHS1 CHS0 GO/DONE ADIF ADON 00-0 0000 00-0 0000

88h

ADCON1 — — — — — — PCFG1 PCFG0 ---- --00 ---- --00

05h PORTA — — — RA4 RA3 RA2 RA1 RA0

---x 0000 ---u 0000

85h TRISA — — — PORTA Data Direction Register

---1 1111 ---1 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Value on:

POR,

BOR

Value on all other

Resets

0Bh/8Bh

INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u

0Ch

PIR1 — ADIF — — — — — — -0-- ---- -0-- ----

8Ch

PIE1 — ADIE — — — — — — -0-- ---- -0-- ----

1Eh

ADRES A/D Result Register xxxx xxxx uuuu uuuu

1Fh

ADCON0ADCS1ADCS0CHS2 CHS1 CHS0 GO/

DONE

— ADON 0000 00-0 0000 00-0

9Fh

ADCON1 — — — — — — PCFG1 PCFG0 ---- --00 ---- --00

05h PORTA — —

—

RA4 RA3 RA2 RA1 RA0

---x 0000 ---u 0000

85h TRISA — —

—

TRISA4 TRISA3TRISA2 TRISA1 TRISA0

---1 1111 ---1 1111

Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion.

 1997 Microchip Technology Inc. DS30272A-page 47

PIC16C71X

8.0 SPECIAL FEATURES OF THE CPU

What sets a microcontroller apart from other processors are special circuits to deal with the needs of realtime applications. The PIC16CXX family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving oper ating modes and offer code protection. These are:

• Oscillator selection

• Reset

- Power-on Reset (POR)

- Power-up Timer (PWRT)

- Oscillator Start-up Timer (OST)

- Brown-out Reset (BOR) (PIC16C710/711/715)

- Parity Error Reset (PER) (PIC16C715)

• Interrupts

• Watchdog Timer (WDT)

• SLEEP

• Code protection

• ID locations

• In-circuit serial programming The PIC16CXX has a Watchdog Timer which can be

shut off only through conﬁguration bits. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in reset until the crystal oscillator is stable. The other is the Pow er-up Timer (PWRT), which provides a

Applicable Devices 710 71 711 715

ﬁxed delay of 72 ms (nominal) on power-up only, designed to keep the part in reset while the power supply stabilizes. With these two timers on-chip, most applications need no external reset circuitry.

SLEEP mode is designed to offer a very low current power-down mode. The user can wake-up from SLEEP through external reset, Watchdog Timer Wake-up, or through an interrupt. Several oscillator options are also made available to allow the part to ﬁt the application. The RC oscillator option saves system cost while the LP crystal option saves power. A set of conﬁguration bits are used to select various options.

8.1 Conﬁguration Bits

The conﬁguration bits can be programmed (read as '0') or left unprogrammed (read as '1') to select various device conﬁgurations. These bits are mapped in program memory location 2007h.

The user will note that address 2007h is beyond the user program memory space. In fact, it belongs to the special test/conﬁguration memory space (2000h 3FFFh), which can be accessed only during programming.

FIGURE 8-1: CONFIGURATION WORD FOR PIC16C71

— — — — — — — — — CP0 PWRTE WDTE FOSC1 FOSC0

bit13 bit0

bit 13-5: Unimplemented: Read as '1' bit 4: CP0: Code protection bit

1 = Code protection off 0 = All memory is code protected, but 00h - 3Fh is writable

bit 3: PWRTE: Power-up Timer Enable bit

1 = Power-up Timer enabled 0 = Power-up Timer disabled

bit 2: WDTE: Watchdog Timer Enable bit

1 = WDT enabled 0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator

PIC16C71X

DS30272A-page 48  1997 Microchip Technology Inc.

FIGURE 8-2: CONFIGURATION WORD, PIC16C710/711

FIGURE 8-3: CONFIGURATION WORD, PIC16C715

CP0 CP0 CP0 CP0 CP0 CP0 CP0 BODEN CP0 CP0 PWRTE WDTE FOSC1 FOSC0

bit13 bit0

bit 13-7 CP0: Code protection bits

(2)

5-4: 1 = Code protection off

0 = All memory is code protected, but 00h - 3Fh is writable

bit 6: BODEN: Brown-out Reset Enable bit

(1)

1 = BOR enabled 0 = BOR disabled

bit 3: PWRTE: Power-up Timer Enable bit

(1)

1 = PWRT disabled 0 = PWRT enabled

bit 2: WDTE: Watchdog Timer Enable bit

1 = WDT enabled 0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator

Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.

Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.

2: All of the CP0 bits have to be given the same value to enable the code protection scheme listed.

CP1 CP0 CP1 CP0 CP1 CP0 MPEEN BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0

bit13 bit0

bit 13-8 CP1:CP0: Code Protection bits

(2)

5-4: 11 = Code protection off

10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected

bit 7: MPEEN: Memory Parity Error Enable

1 = Memory Parity Checking is enabled 0 = Memory Parity Checking is disabled

bit 6: BODEN: Brown-out Reset Enable bit

(1)

1 = BOR enabled 0 = BOR disabled

bit 3: PWRTE: Power-up Timer Enable bit

(1)

1 = PWRT disabled 0 = PWRT enabled

bit 2: WDTE: Watchdog Timer Enable bit

1 = WDT enabled 0 = WDT disabled

bit 1-0: FOSC1:FOSC0: Oscillator Selection bits

11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator

Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE.

Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled.

2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed.

 1997 Microchip Technology Inc. DS30272A-page 49

PIC16C71X

8.2 Oscillator Conﬁgurations

8.2.1 OSCILLATOR TYPES The PIC16CXX can be operated in four different oscil-

lator modes. The user can program two conﬁguration bits (FOSC1 and FOSC0) to select one of these four modes:

• LP Low Power Crystal

• XT Crystal/Resonator

• HS High Speed Crystal/Resonator

• RC Resistor/Capacitor

8.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS

In XT, LP or HS modes a cr ystal or ceramic resonator is connected to the OSC1/CLKIN and OSC2/CLKOUT pins to establish oscillation (Figure 8-4). The PIC16CXX Oscillator design requires the use of a parallel cut crystal. Use of a series cut crystal may give a frequency out of the crystal manufacturers speciﬁcations. When in XT, LP or HS modes, the device can have an external clock source to drive the OSC1/ CLKIN pin (Figure 8-5).

FIGURE 8-4: CRYSTAL/CERAMIC

RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION)

FIGURE 8-5: EXTERNAL CLOCK INPUT

OPERATION (HS, XT OR LP OSC CONFIGURATION)

XTAL

OSC2

Note1

OSC1

SLEEP

PIC16CXXX

See Table 8-1 and Table 8-1 for recommended values of C1 and C2.

Note 1: A series resistor may be required for AT strip

cut crystals.

2: The buffer is on the OSC2 pin.

(2)

To internal logic

OSC1

OSC2

Open

Clock from ext. system

PIC16CXXX

TABLE 8-1: CERAMIC RESONATORS,

PIC16C71

TABLE 8-2: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR, PIC16C71

Ranges Tested:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

47 - 100 pF 15 - 68 pF 15 - 68 pF

HS 8.0 MHz

16.0 MHz

15 - 68 pF 10 - 47 pF

These values are for design guidance only. See notes at bottom of page.

Resonators Used:

455 kHz Panasonic EFO-A455K04B ± 0.3%

2.0 MHz Murata Erie CSA2.00MG ± 0.5%

4.0 MHz Murata Erie CSA4.00MG ± 0.5%

8.0 MHz Murata Erie CSA8.00MT ± 0.5%

16.0 MHz Murata Erie CSA16.00MX ± 0.5%

All resonators used did not have built-in capacitors.

Mode Freq OSC1 OSC2

LP 32 kHz

200 kHz

33 - 68 pF 15 - 47 pF

XT 100 kHz

500 kHz

1 MHz 2 MHz 4 MHz

47 - 100 pF

20 - 68 pF 15 - 68 pF 15 - 47 pF 15 - 33 pF

47 - 100 pF

20 - 68 pF 15 - 68 pF 15 - 47 pF 15 - 33 pF

HS 8 MHz

20 MHz

15 - 47 pF 15 - 47 pF

These values are for design guidance only. See notes at bottom of page.

PIC16C71X

DS30272A-page 50  1997 Microchip Technology Inc.

TABLE 8-3: CERAMIC RESONATORS,

PIC16C710/711/715

Ranges Tested:

Mode Freq OSC1 OSC2

XT 455 kHz

2.0 MHz

4.0 MHz

68 - 100 pF 15 - 68 pF 15 - 68 pF

HS 8.0 MHz

16.0 MHz

10 - 68 pF 10 - 22 pF

These values are for design guidance only. See notes at bottom of page.

Resonators Used:

455 kHz Panasonic EFO-A455K04B ± 0.3%

2.0 MHz Murata Erie CSA2.00MG ± 0.5%

4.0 MHz Murata Erie CSA4.00MG ± 0.5%

8.0 MHz Murata Erie CSA8.00MT ± 0.5%

16.0 MHz Murata Erie CSA16.00MX ± 0.5%

All resonators used did not have built-in capacitors.

TABLE 8-4: CAPACITOR SELECTION

FOR CRYSTAL OSCILLATOR, PIC16C710/711/715

Osc Type

Crystal

Freq

Cap. Range C1Cap. Range

LP 32 kHz 33 pF 33 pF

200 kHz 15 pF 15 pF

XT 200 kHz 47-68 pF 47-68 pF

1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF

HS 4 MHz 15 pF 15 pF

8 MHz 15-33 pF 15-33 pF

20 MHz 15-33 pF 15-33 pF

These values are for design guidance only. See notes at bottom of page.

Crystals Used

32 kHz Epson C-001R32.768K-A ± 20 PPM

200 kHz STD XTL 200.000KHz ± 20 PPM

1 MHz ECS ECS-10-13-1 ± 50 PPM 4 MHz ECS ECS-40-20-1 ± 50 PPM 8 MHz EPSON CA-301 8.000M-C ± 30 PPM

20 MHz EPSON CA-301 20.000M-C ± 30 PPM

Note 1: Recommended values of C1 and C2 are identical to the ranges tested table.

2: Higher capacitance increases the stability of oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal man-

ufacturer for appropriate values of external components.

4: Rs may be required in HS mode as well as XT mode to avoid overdriving crystals with low drive level speci-

ﬁcation.

 1997 Microchip Technology Inc. DS30272A-page 51

PIC16C71X

8.2.3 EXTERNAL CRYSTAL OSCILLATOR CIRCUIT

Either a prepackaged oscillator can be used or a simple oscillator circuit with TTL gates can be built. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator will provide good performance with TTL gates . Two types of crystal oscillator circuits can be used; one with series resonance, or one with parallel resonance.

Figure 8-6 shows implementation of a parallel resonant oscillator circuit. The circuit is designed to use the fundamental frequency of the crystal. The 74AS04 inverter performs the 180-degree phase shift that a parallel oscillator requires. The 4.7 kΩ resistor provides the negative feedback for stability. The 10 kΩ potentiometer biases the 74AS04 in the linear region. This could be used for external oscillator designs.

FIGURE 8-6: EXTERNAL PARALLEL

RESONANT CRYSTAL OSCILLATOR CIRCUIT

Figure 8-7 shows a series resonant oscillator circuit. This circuit is also designed to use the fundamental frequency of the crystal. The inverter performs a 180degree phase shift in a series resonant oscillator circuit. The 330 kΩ resistors provide the negative feedback to bias the inverters in their linear region.

FIGURE 8-7: EXTERNAL SERIES

RESONANT CRYSTAL OSCILLATOR CIRCUIT

20 pF

+5V

20 pF

10k

4.7k

10k

74AS04

XTAL

10k

74AS04

CLKIN

To Other Devices

PIC16CXXX

330 kΩ

74AS04

74AS04 PIC16CXXX

CLKIN

To Other Devices

XTAL

330 kΩ

74AS04

0.1 µF

8.2.4 RC OSCILLATOR For timing insensitive applications the “RC” device

option offers additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (Rext) and capacitor (Cext) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low Cext values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 8-8 shows how the R/C combination is connected to the PIC16CXX. For Rext values below 2.2 kΩ, the oscillator operation may become unstable, or stop completely. For very high Rext v alues (e.g. 1 MΩ), the oscillator becomes sensitive to noise, humidity and leakage. Thus, we recommend to keep Rext between 3 kΩ and 100 kΩ.

Although the oscillator will operate with no external capacitor (Cext = 0 pF), we recommend using values above 20 pF for noise and stability reasons. With no or small external capacitance, the oscillation frequency can vary dramatically due to changes in external capacitances, such as PCB trace capacitance or package lead frame capacitance.

See characterization data for desired device f or RC frequency variation from part to part due to nor mal process variation. The variation is larger for larger R (since leakage current variation will affect RC frequency more for large R) and for smaller C (since variation of input capacitance will affect RC frequency more).

See characterization data for desired device for variation of oscillator frequency due to V

DD for given Rext/

Cext values as well as frequency v ariation due to operating temperature for given R, C, and V

DD values.

The oscillator frequency, divided by 4, is available on the OSC2/CLKOUT pin, and can be used for test purposes or to synchronize other logic (see Figure 3-2 for waveform).

FIGURE 8-8: RC OSCILLATOR MODE

OSC2/CLKOUT

Cext

VDD

Rext

VSS

PIC16CXXX

OSC1

Fosc/4

Internal

clock

PIC16C71X

DS30272A-page 52  1997 Microchip Technology Inc.

8.3 Reset

The PIC16CXX differentiates between various kinds of reset:

• Power-on Reset (POR)

• MCLR

reset during normal operation

• MCLR

reset during SLEEP

• WDT Reset (normal operation)

• Brown-out Reset (BOR) (PIC16C710/711/715)

• Parity Error Reset (PIC16C715) Some registers are not affected in any reset condition;

their status is unknown on POR and unchanged in any other reset. Most other registers are reset to a “reset state” on Power-on Reset (POR), on the MCLR

and

Applicable Devices 710 71 711 715

WDT Reset, on MCLR reset during SLEEP, and Brownout Reset (BOR). They are not affected by a WDT Wake-up, which is viewed as the resumption of normal operation. The T

O and PD bits are set or cleared differently in different reset situations as indicated in Table 87, Tab le 8-8 and Table 8-9. These bits are used in software to determine the nature of the reset. See Table 810 and Table 8-11 for a full descr iption of reset states of all registers.

A simpliﬁed block diagram of the on-chip reset circuit is shown in Figure 8-9.

The PIC16C710/711/715 have a MCLR

noise ﬁlter in

the MCLR

reset path. The ﬁlter will detect and ignore

small pulses. It should be noted that a WDT Reset

does not drive

MCLR

pin low.

FIGURE 8-9: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External

Reset

MCLR/VPP Pin

OSC1/

WDT

Module

DD rise

detect

OST/PWRT

On-chip

(1)

RC OSC

WDT Time-out

Power-on Reset

OST

PWRT

Chip_Reset

10-bit Ripple-counter

Enable OST

Enable PWRT

SLEEP

See Table 8-6 for time-out situations.

Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.

2: Brown-out Reset is implemented on the PIC16C710/711/715. 3: Parity Error Reset is implemented on the PIC16C715.

Brown-out

Reset

(2)

BODEN

CLKIN

10-bit Ripple-counter

Program

Memory

Parity

(3)

MPEEN

 1997 Microchip Technology Inc. DS30272A-page 53

PIC16C71X

8.4 Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST), and Brown-out Reset (BOR)

8.4.1 POWER-ON RESET (POR)

A Power-on Reset pulse is generated on-chip when V

DD rise is detected (in the range of 1.5V - 2.1V). To

take advantage of the POR, just tie the MCLR

directly (or through a resistor) to V

DD. This will eliminate

external RC components usually needed to create a Power-on Reset. A maximum rise time for V

DD is spec-

iﬁed. See Electrical Speciﬁcations for details. When the device starts normal operation (exits the

reset condition), device operating parameters (voltage , frequency, temperature, ...) must be met to ensure operation. If these conditions are not met, the device must be held in reset until the operating conditions are met. Brown-out Reset may be used to meet the startup conditions.

For additional information, refer to Application Note AN607, "

Power-up Trouble Shooting

8.4.2 POWER-UP TIMER (PWRT)

The Power-up Timer provides a ﬁxed 72 ms nominal time-out on power-up only, from the POR. The Powerup Timer operates on an internal RC oscillator. The chip is kept in reset as long as the PWRT is active . The PWRT’ s time dela y allo ws V

DD to rise to an acceptable

level. A conﬁguration bit is provided to enable/disable the PWRT.

Applicable Devices 710 71 711 715

The power-up time delay will v ary from chip to chip due to V

DD, temperature, and process variation. See DC

parameters for details.

8.4.3 OSCILLATOR START-UP TIMER (OST)

The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is ov er. This ensures that the crystal oscillator or resonator has started and stabilized.

The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.

8.4.4 BROWN-OUT RESET (BOR)

A conﬁguration bit, BODEN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If V

DD falls below 4.0V (3.8V - 4.2V range) for

greater than parameter #35, the brown-out situation will reset the chip. A reset may not occur if V

DD falls below

4.0V for less than parameter #35. The chip will remain in Brown-out Reset until V

DD rises above BVDD. The

Power-up Timer will now be invoked and will keep the chip in RESET an additional 72 ms. If V

DD drops below

DD while the Pow er-up Timer is running, the chip will

go back into a Brown-out Reset and the Power-up Timer will be initialized. Once V

DD rises above BVDD,

the Power-up Timer will execute a 72 ms time delay. The Power-up Timer should always be enabled when Brown-out Reset is enabled. Figure 8-10 shows typical brown-out situations.

Applicable Devices 710 71 711 715

FIGURE 8-10: BROWN-OUT SITUATIONS

72 ms

VDD

Internal

Reset

BVDD

VDD

Internal

Reset

72 ms

<72 ms

72 ms

VDD

Internal

Reset

PIC16C71X

DS30272A-page 54  1997 Microchip Technology Inc.

8.4.5 TIME-OUT SEQUENCE

On power-up the time-out sequence is as follows: First PWRT time-out is inv oked after the POR time delay has expired. Then OST is activated. The total time-out will vary based on oscillator conﬁguration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 8-11, Figure 8-12, and Figure 8-13 depict time-out sequences on power-up.

Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire . Then bringing MCLR

high will begin execution immediately (Figure 8-12). This is useful for testing purposes or to synchronize more than one PIC16CXX device operating in parallel.

Table 8-10 and T able 8-11 show the reset conditions for some special function registers, while Table 8-12 and Table 8-13 show the reset conditions for all the registers.

8.4.6 POWER CONTROL/STATUS REGISTER

(PCON)

The Power Control/Status Register, PCON has up to two bits, depending upon the device.

Bit0 is Brown-out Reset Status bit, BOR

. Bit BOR is unknown on a Power-on Reset. It must then be set by the user and checked on subsequent resets to see if bit BOR

cleared, indicating a BOR occurred. The BOR bit is a "Don’t Care" bit and is not necessarily predictable if the Brown-out Reset circuitry is disabled (by clearing bit BODEN in the Conﬁguration Word).

Applicable Devices 710 71 711 715

Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset.

For the PIC16C715, bit2 is PER

(Parity Error Reset). It is cleared on a Parity Error Reset and must be set by user software. It will also be set on a Power-on Reset.

For the PIC16C715, bit7 is MPEEN (Memory Parity Error Enable). This bit reﬂects the status of the MPEEN bit in conﬁguration word. It is unaff ected by an y reset of interrupt.

8.4.7 PARITY ERROR RESET (PER)

The PIC16C715 has on-chip parity bits that can be used to verify the contents of program memory. Parity bits may be useful in applications in order to increase overall reliability of a system.

There are two parity bits for each word of Program Memory. The parity bits are computed on alternating bits of the program word. One computation is performed using even parity, the other using odd parity. As a program ex ecutes, the parity is veriﬁed. The ev en parity bit is XOR’d with the even bits in the program memory word. The odd parity bit is negated and XOR’d with the odd bits in the program memory word. When an error is detected, a reset is generated and the PER

ﬂag bit 2 in the PCON register is cleared (logic ‘0’). This indication can allow software to act on a failure. However, there is no indication of the program memory location of the failure in Program Memory. This ﬂag can only be set (logic ‘1’) by software.

The parity array is user selectable during programming. Bit 7 of the conﬁguration word located at address 2007h can be programmed (read as ‘0’) to disable parity. If left unprog rammed (read as ‘1’), parity is enabled.

Applicable Devices 710 71 711 715

TABLE 8-5: TIME-OUT IN VARIOUS SITUATIONS, PIC16C71

TABLE 8-6: TIME-OUT IN VARIOUS SITUATIONS, PIC16C710/711/715

Oscillator Conﬁguration Power-up Wake-up from SLEEP

PWRTE = 1 PWRTE = 0

XT, HS, LP 72 ms + 1024T

OSC 1024TOSC 1024 TOSC

RC 72 ms — —

Oscillator Conﬁguration Power-up

Brown-out

Wake-up from SLEEP

PWR

TE = 0 PWRTE = 1

XT, HS, LP 72 ms + 1024T

OSC 1024TOSC 72 ms + 1024TOSC 1024TOSC

RC 72 ms — 72 ms —

 1997 Microchip Technology Inc. DS30272A-page 55

PIC16C71X

TABLE 8-7: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C71

TABLE 8-8: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C710/711

TABLE 8-9: STATUS BITS AND THEIR SIGNIFICANCE, PIC16C715

TO PD

1 1 Power-on Reset 0 x Illegal, T

O is set on POR

x 0 Illegal, PD is set on POR 0 1 WDT Reset 0 0 WDT Wake-up u u MCLR

Reset during normal operation

1 0 MCLR

Reset during SLEEP or interrupt wake-up from SLEEP

POR

BOR TO PD

0 x 1 1 Power-on Reset 0 x 0 x Illegal, T

O is set on POR

0 x x 0 Illegal, PD is set on POR 1 0 x x Brown-out Reset 1 1 0 1 WDT Reset 1 1 0 0 WDT Wake-up 1 1 u u MCLR

Reset during normal operation

1 1 1 0 MCLR

Reset during SLEEP or interrupt wake-up from SLEEP

PER

POR BOR TO PD

1 0 x 1 1 Power-on Reset x 0 x 0 x Illegal, T

O is set on POR

x 0 x x 0 Illegal, PD is set on POR 1 1 0 x x Brown-out Reset 1 1 1 0 1 WDT Reset 1 1 1 0 0 WDT Wake-up 1 1 1 u u MCLR

Reset during normal operation

1 1 1 1 0 MCLR

Reset during SLEEP or interrupt wake-up from SLEEP

0 1 1 1 1 Parity Error Reset 0 0 x x x Illegal, PER

is set on POR

0 x 0 x x Illegal, PER

is set on BOR

PIC16C71X

DS30272A-page 56  1997 Microchip Technology Inc.

TABLE 8-10: RESET CONDITION FOR SPECIAL REGISTERS, PIC16C710/71/711

TABLE 8-11: RESET CONDITION FOR SPECIAL REGISTERS, PIC16C715

Condition

Program Counter

STATUS

PCON

PIC16C710/711

Power-on Reset 000h 0001 1xxx ---- --0x MCLR

Reset during normal operation 000h 000u uuuu ---- --uu

MCLR

Reset during SLEEP 000h 0001 0uuu ---- --uu WDT Reset 000h 0000 1uuu ---- --uu WDT Wake-up PC + 1 uuu0 0uuu ---- --uu Brown-out Reset (PIC16C710/711) 000h 0001 1uuu ---- --u0 Interrupt wake-up from SLEEP PC + 1

(1)

uuu1 0uuu ---- --uu

Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded

with the interrupt vector (0004h).

Condition

Program Counter

STATUS

PCON

Power-on Reset 000h 0001 1xxx u--- -10x MCLR

Reset during normal operation 000h 000u uuuu u--- -uuu MCLR

Reset during SLEEP 000h 0001 0uuu u--- -uuu WDT Reset 000h 0000 1uuu u--- -uuu WDT Wake-up PC + 1 uuu0 0uuu u--- -uuu Brown-out Reset 000h 0001 1uuu u--- -uu0 Parity Error Reset 000h uuu1 0uuu u--- -0uu Interrupt wake-up from SLEEP PC + 1

(1)

uuu1 0uuu u--- -uuu

Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

 1997 Microchip Technology Inc. DS30272A-page 57

PIC16C71X

TABLE 8-12: INITIALIZATION CONDITIONS FOR ALL REGISTERS, PIC16C710/71/711

Brown-out Reset

(5)

MCLR Resets

WDT Reset

Wake-up via

WDT or

Interrupt

W xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000h 0000h

PC + 1

(2)

STATUS 0001 1xxx

000q quuu

(3)

uuuq quuu

(3)

FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA ---x 0000 ---u 0000 ---u uuuu PORTB xxxx xxxx uuuu uuuu uuuu uuuu PCLATH ---0 0000 ---0 0000 ---u uuuu INTCON 0000 000x 0000 000u

uuuu uuuu

(1)

ADRES xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 00-0 0000 00-0 0000 uu-u uuuu OPTION 1111 1111 1111 1111 uuuu uuuu TRISA ---1 1111 ---1 1111 ---u uuuu TRISB 1111 1111 1111 1111 uuuu uuuu

PCON

(4)

---- --0u ---- --uu ---- --uu

ADCON1 ---- --00 ---- --00 ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition

Note 1: One or more bits in INTCON will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h). 3: See Table 8-10 for reset value for speciﬁc condition. 4: The PCON register is not implemented on the PIC16C71. 5: Brown-out reset is not implemented on the PIC16C71.

PIC16C71X

DS30272A-page 58  1997 Microchip Technology Inc.

TABLE 8-13: INITIALIZATION CONDITIONS FOR ALL REGISTERS, PIC16C715

Brown-out Reset

Parity Error Reset

MCLR Resets

WDT Reset

Wake-up via

WDT or

Interrupt

W xxxx xxxx uuuu uuuu uuuu uuuu INDF N/A N/A N/A TMR0 xxxx xxxx uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000

PC + 1

(2)

STATUS 0001 1xxx

000q quuu

(3)

uuuq quuu

(3)

FSR xxxx xxxx uuuu uuuu uuuu uuuu PORTA ---x 0000 ---u 0000 ---u uuuu PORTB xxxx xxxx uuuu uuuu uuuu uuuu PCLATH ---0 0000 ---0 0000 ---u uuuu INTCON 0000 000x 0000 000u

uuuu uuuu

(1)

PIR1

-0-- ---- -0-- ----

-u-- ----

(1)

ADCON0 0000 00-0 0000 00-0 uuuu uu-u OPTION 1111 1111 1111 1111 uuuu uuuu TRISA ---1 1111 ---1 1111 ---u uuuu TRISB 1111 1111 1111 1111 uuuu uuuu PIE1 -0-- ---- -0-- ---- -u-- ---- PCON ---- -qqq ---- -1uu ---- -1uu ADCON1 ---- --00 ---- --00 ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition

Note 1: One or more bits in INTCON and PIR1 will be affected (to cause wake-up).

2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector

(0004h).

3: See Table 8-11 for reset value for speciﬁc condition.

 1997 Microchip Technology Inc. DS30272A-page 59

PIC16C71X

FIGURE 8-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

FIGURE 8-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

FIGURE 8-13: TIME-OUT SEQUENCE ON POWER-UP (MCLR

TIED TO VDD)

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

VDD

MCLR

INTERNAL POR

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

TPWRT

TOST

TPWRT

TOST

VDD

MCLR

INTERNAL POR

PWR

T TIME-OUT

OST TIME-OUT

INTERNAL RESET

PIC16C71X

DS30272A-page 60  1997 Microchip Technology Inc.

FIGURE 8-14: EXTERNAL POWER-ON

RESET CIRCUIT (FOR SLOW VDD POWER-UP)

Note 1: External Power-on Reset circuit is

required only if V

DD power-up slope is too

slow. The diode D helps discharge the capacitor quickly when V

DD powers down.

2: R < 40 kΩ is recommended to make sure

that voltage drop across R does not violate the device’s electrical speciﬁcation.

3: R1 = 100Ω to 1 kΩ will limit any current

ﬂowing into MCLR from external capacitor C in the event of MCLR/

VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS).

MCLR

PIC16CXX

FIGURE 8-15: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 1

FIGURE 8-16: EXTERNAL BROWN-OUT

PROTECTION CIRCUIT 2

Note 1: This circuit will activate reset when VDD

goes below (Vz + 0.7V) where Vz = Zener voltage.

2: Internal brown-out detection on the

PIC16C710/711/715 should be disabled when using this circuit.

3: Resistors should be adjusted for the char-

acteristics of the transistor.

VDD

33k

10k

40k

MCLR

PIC16CXX

Note 1: This brown-out circuit is less expensive ,

albeit less accurate. Transistor Q1 turns off when V

DD is below a certain level

such that:

2: Internal brown-out detection on the

PIC16C710/711/715 should be disabled when using this circuit.

3: Resistors should be adjusted for the

characteristics of the transistor.

DD •

R1 + R2

= 0.7V

VDD

40k

VDD

MCLR

PIC16CXX

 1997 Microchip Technology Inc. DS30272A-page 61

PIC16C71X

8.5 Interrupts

The PIC16C71X family has 4 sources of interrupt.

The interrupt control register (INTCON) records individual interrupt requests in ﬂag bits. It also has individual and global interrupt enable bits.

A global interrupt enable bit, GIE (INTCON<7>) enables (if set) all un-masked interrupts or disables (if cleared) all interrupts. When bit GIE is enabled, and an interrupt’s ﬂag bit and mask bit are set, the interrupt will vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set regardless of the status of the GIE bit. The GIE bit is cleared on reset.

The “return from interrupt” instruction, RETFIE, exits the interrupt routine as well as sets the GIE bit, which re-enables interrupts.

The RB0/INT pin interrupt, the RB port change interrupt and the TMR0 overﬂow interrupt ﬂags are contained in the INTCON register.

The peripheral interrupt ﬂags are contained in the special function registers PIR1 and PIR2. The corresponding interrupt enable bits are contained in special function registers PIE1 and PIE2, and the peripheral interrupt enable bit is contained in special function register INTCON.

When an interrupt is responded to, the GIE bit is cleared to disable any further interrupt, the return address is pushed onto the stack and the PC is loaded with 0004h. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt ﬂag bits. The interr upt ﬂag bit(s) must be cleared in software before re-enabling interrupts to avoid recursive interrupts.

Applicable Devices 710 71 711 715

Interrupt Sources

External interrupt RB0/INT TMR0 overﬂow interrupt PORTB change interrupts (pins RB7:RB4) A/D Interrupt

Note: Individual interrupt ﬂag bits are set regard-

less of the status of their corresponding mask bit or the GIE bit.

For external interrupt events, such as the INT pin or PORTB change interrupt, the interrupt latency will be three or four instruction cycles. The exact latency depends when the interrupt event occurs (Figure 8-19). The latency is the same for one or two cycle instructions. Individual interrupt ﬂag bits are set regardless of the status of their corresponding mask bit or the GIE bit.

Note: For the PIC16C71

If an interrupt occurs while the Global Interrupt Enable (GIE) bit is being cleared, the GIE bit may unintentionally be re-enabled by the user’s Interrupt Service Routine (the RETFIE instruction). The events that would cause this to occur are:

1. An instruction clears the GIE bit while an interrupt is acknowledged.

2. The program branches to the Interrupt vector and ex ecutes the Interrupt Service Routine.

3. The Interrupt Service Routine completes with the execution of the RET- FIE instruction. This causes the GIE bit to be set (enables interrupts), and the program returns to the instruction after the one which was meant to disable interrupts.

Perform the following to ensure that interrupts are globally disabled:

LOOP BCF INTCON, GIE ; Disable global ; interrupt bit BTFSC INTCON, GIE ; Global interrupt ; disabled? GOTO LOOP ; NO, try again : ; Yes, continue ; with program ; flow

PIC16C71X

DS30272A-page 62  1997 Microchip Technology Inc.

FIGURE 8-17: INTERRUPT LOGIC, PIC16C710, 71, 711

FIGURE 8-18: INTERRUPT LOGIC, PIC16C715

RBIF RBIE

T0IF T0IE

INTF INTE

GIE

ADIE

Wakeup (If in SLEEP mode)

Interrupt to CPU

ADIF

RBIF RBIE

T0IF T0IE

INTF INTE

GIE

Wakeup (If in SLEEP mode)

Interrupt to CPU

ADIF

ADIF ADIE

 1997 Microchip Technology Inc. DS30272A-page 63

PIC16C71X

8.5.1 INT INTERRUPT External interrupt on RB0/INT pin is edge triggered:

either rising if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, ﬂag bit INTF (INTCON<1>) is set. This interr upt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the interrupt service routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE was set prior to going into SLEEP. The status of global interrupt enable bit GIE decides whether or not the processor branches to the interrupt vector following wake-up. See Section 8.8 for details on SLEEP mode.

8.5.2 TMR0 INTERRUPT An overﬂow (FFh → 00h) in the TMR0 register will set

ﬂag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 6.0)

8.5.3 PORTB INTCON CHANGE An input change on PORTB<7:4> sets ﬂag bit RBIF

(INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). (Section 5.2)

Note: For the PIC16C71

if a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the RBIF interrupt ﬂag may not get set.

FIGURE 8-19: INT PIN INTERRUPT TIMING

Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4 Q2Q1 Q3 Q4

OSC1

CLKOUT

INT pin

INTF ﬂag (INTCON<1>)

GIE bit (INTCON<7>)

INSTR

UCTION FLOW

Instruction fetched

Instruction executed

Interrupt Latency

PC+1

0004h

0005h

Inst (0004h)

Inst (0005h)

Dummy Cycle

Inst (PC)

Inst (PC+1)

Inst (PC-1)

Inst (0004h)

Dummy Cycle

Inst (PC)

—

Note

1: INTF ﬂag is sampled here (every Q1). 2: Interrupt latency = 3-4 Tcy where Tcy = instruction cycle time.

Latency is the same whether Inst (PC) is a single cycle or a 2-cycle instruction. 3: CLKOUT is available only in RC oscillator mode. 4: For minimum width of INT pulse, refer to AC specs. 5: INTF is enabled to be set anytime during the Q4-Q1 cycles.

PIC16C71X

DS30272A-page 64  1997 Microchip Technology Inc.

8.6 Context Saving During Interrupts

During an interrupt, only the return PC value is saved on the stack. Typically, users may wish to save ke y registers during an interrupt i.e., W register and STATUS register. This will have to be implemented in software.

Example 8-1 stores and restores the STATUS and W registers. The user register, STATUS_TEMP, must be deﬁned in bank 0.

The example: a) Stores the W register.

b) Stores the STATUS register in bank 0. c) Executes the ISR code. d) Restores the STATUS register (and bank select

bit).

e) Restores the W register.

EXAMPLE 8-1: SAVING STATUS AND W REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero SWAPF STATUS,W ;Swap status to be saved into W MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register : :(ISR) : SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W

 1997 Microchip Technology Inc. DS30272A-page 65

PIC16C71X

8.7 Watchdog Timer (WDT)

The Watchdog Timer is as a free running on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been stopped, for example, by execution of a SLEEP instruction. Dur- ing normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The WDT can be permanently disabled by clearing conﬁguration bit WDTE (Section 8.1).

8.7.1 WDT PERIOD The WDT has a nominal time-out period of 18 ms, (with

no prescaler). The time-out periods vary with temperature, V

and process variations from part to part (see DC specs). If longer time-out periods are desired, a prescaler with a division ratio of up to 1:128 can be

Applicable Devices 710 71 711 715

assigned to the WDT under software control by writing to the OPTION register. Thus, time-out periods up to

2.3 seconds can be realized. The CLRWDT and SLEEP instructions clear the WDT and

the postscaler, if assigned to the WDT, and prevent it from timing out and generating a device RESET condition.

The T

O bit in the STATUS register will be cleared upon

a Watchdog Timer time-out.

8.7.2 WDT PROGRAMMING CONSIDERATIONS It should also be taken into account that under worst

case conditions (V

DD = Min., Temperature = Max., and

max. WDT prescaler) it may take several seconds before a WDT time-out occurs.

Note: When a CLRWDT instruction is executed

and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed.

FIGURE 8-20: WATCHDOG TIMER BLOCK DIAGRAM

FIGURE 8-21: SUMMARY OF WATCHDOG TIMER REGISTERS

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

2007h Conﬁg. bits

(1)

BODEN

(1)

CP1 CP0

PWRTE

(1)

WDTE FOSC1 FOSC0

81h,181h OPTION

RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0

Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 8-1, Figure 8-2 and Figure 8-3 for operation of these bits.

From TMR0 Clock Source (Figure 6-6)

To TMR0 (Figure 6-6)

Postscaler

WDT Timer

WDT

Enable Bit

0 1

M U X

PSA

8 - to - 1 MUX

PS2:PS0

MUX

PSA

WDT

Time-out

Note: PSA and PS2:PS0 are bits in the OPTION register.

PIC16C71X

DS30272A-page 66  1997 Microchip Technology Inc.

8.8 Power-down Mode (SLEEP)

Power-down mode is entered by executing a SLEEP instruction.

If enabled, the Watchdog Timer will be cleared but keeps running, the PD

bit (STATUS<3>) is cleared, the

O (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O por ts maintain the status they had, before the SLEEP instruction was executed (driving high, low, or hi-impedance).

For lowest current consumption in this mode, place all I/O pins at either V

DD, or VSS, ensure no external cir-

cuitry is drawing current from the I/O pin, power-down the A/D, disable external clocks. Pull all I/O pins, that are hi-impedance inputs, high or low externally to av oid switching currents caused by ﬂoating inputs. The T0CKI input should also be at V

DD or VSS for lowest

current consumption. The contribution from on-chip pull-ups on PORTB should be considered.

The MCLR

pin must be at a logic high level (VIHMC).

8.8.1 WAKE-UP FROM SLEEP The device can wake up from SLEEP through one of

the following events:

1. External reset input on MCLR

pin.

2. Watchdog Timer Wake-up (if WDT was

enabled).

3. Interrupt from INT pin, RB port change, or some

Peripheral Interrupts.

External MCLR

Reset will cause a device reset. All other events are considered a continuation of program execution and cause a "wake-up". The T

O and PD bits in the STATUS register can be used to determine the cause of device reset. The PD

bit, which is set on

power-up, is cleared when SLEEP is in vok ed. The T

O bit is cleared if a WDT time-out occurred (and caused wake-up).

The following peripheral interrupts can wake the de vice from SLEEP:

1. TMR1 interrupt. Timer1 must be operating as

an asynchronous counter.

2. A/D conversion (when A/D clock source is RC).

Other peripherals cannot generate interrupts since during SLEEP, no on-chip Q clocks are present.

When the SLEEP instruction is being executed, the ne xt instruction (PC + 1) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instr uction and then branches to the interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction.

8.8.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and

any interrupt source has both its interrupt enable bit and interrupt ﬂag bit set, one of the following will occur:

• If the interrupt occurs before the the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Theref ore, the WDT and WDT postscaler will not be cleared, the T

O bit will not

be set and PD

bits will not be cleared.

• If the interrupt occurs during or after the execution of a SLEEP instruction, the device will immediately wake up from sleep . The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the T

O bit will be set and the PD bit will

be cleared.

Even if the ﬂag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD

bit. If the PD bit is set, the SLEEP instruction was

executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruc-

tion should be executed before a SLEEP instruction.

 1997 Microchip Technology Inc. DS30272A-page 67

PIC16C71X

FIGURE 8-22: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

OSC1

CLKOUT(4)

INT pin

INTF ﬂag (INTCON<1>)

GIE bit (INTCON<7>)

INSTRUCTION FLOW

Instruction fetched

Instruction executed

PC PC+1 PC+2

Inst(PC) = SLEEP

Inst(PC - 1)

Inst(PC + 1)

SLEEP

Processor in

SLEEP

Interrupt Latency

(Note 2)

Inst(PC + 2)

Inst(PC + 1)

Inst(0004h)

Inst(0005h)

Inst(0004h)

Dummy cycle

PC + 2 0004h 0005h

Dummy cycle

OST(2)

PC+2

Note 1: XT, HS or LP oscillator mode assumed.

2: T

OST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode.

3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference.

8.9 Program Veriﬁcation/Code Protection

If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for veriﬁcation purposes.

8.10 ID Locations

Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code-identiﬁcation numbers. These locations are not accessible during normal execution but are readable and writable during program/verify. It is recommended that only the 4 least signiﬁcant bits of the ID location are used.

8.11 In-Circuit Serial Programming

PIC16CXX microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent ﬁrmware or a custom ﬁrmware to be programmed.

Note: Microchip does not recommend code pro-

tecting windowed devices.

The device is placed into a program/verify mode by holding the RB6 and RB7 pins low while raising the MCLR

(VPP) pin from VIL to VIHH (see programming speciﬁcation). RB6 becomes the programming clock and RB7 becomes the programming data. Both RB6 and RB7 are Schmitt Trigger inputs in this mode.

After reset, to place the device into programming/verify mode, the program counter (PC) is at location 00h. A 6bit command is then supplied to the device. Depending on the command, 14-bits of program data are then supplied to or from the device, depending if the command was a load or a read. For complete details of serial programming, please refer to the PIC16C6X/7X Programming Speciﬁcations (Literature #DS30228).

FIGURE 8-23: TYPICAL IN-CIRCUIT SERIAL

PROGRAMMING CONNECTION

External Connector Signals

To Normal Connections

PIC16CXX

VSS MCLR/VPP

RB6

RB7

+5V

VPP

CLK

Data I/O

VDD

PIC16C71X

DS30272A-page 68  1997 Microchip Technology Inc.

NOTES:

 1997 Microchip Technology Inc. DS30272A-page 69

PIC16C71X

9.0 INSTRUCTION SET SUMMARY

Each PIC16CXX instruction is a 14-bit word divided into an OPCODE which speciﬁes the instruction type and one or more operands which further specify the operation of the instruction. The PIC16CXX instruction set summary in Table 9-2 lists byte-oriented, bit-ori- ented, and literal and control operations. Table 9-1 shows the opcode ﬁeld descriptions.

For byte-oriented instructions, 'f' represents a ﬁle register designator and 'd' represents a destination designator. The ﬁle register designator speciﬁes which ﬁle register is to be used by the instruction.

The destination designator speciﬁes where the result of the operation is to be placed. If 'd' is zero, the result is placed in the W register . If 'd' is one , the result is placed in the ﬁle register speciﬁed in the instruction.

For bit-oriented instructions, 'b' represents a bit ﬁeld designator which selects the number of the bit affected by the operation, while 'f' represents the number of the ﬁle in which the bit is located.

For literal and control operations, 'k' represents an eight or eleven bit constant or literal value.

TABLE 9-1: OPCODE FIELD

DESCRIPTIONS

The instruction set is highly orthogonal and is grouped into three basic categories:

Field Description

f Register ﬁle address (0x00 to 0x7F) W Working register (accumulator) b Bit address within an 8-bit ﬁle register k Literal ﬁeld, constant data or label x Don't care location (= 0 or 1)

The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools.

d Destination select; d = 0: store result in W,

d = 1: store result in ﬁle register f. Default is d = 1

label Label name

TOS Top of Stack

PC Program Counter

PCLATH

Program Counter High Latch

GIE Global Interrupt Enable bit WDT Watchdog Timer/Counter

TO Time-out bit PD Power-down bit

dest Destination either the W register or the speciﬁed

[ ] Options

( )

Contents

→

Assigned to

< >

∈

In the set of

talics

User deﬁned term (font is courier)

• Byte-oriented operations

• Bit-oriented operations

• Literal and control operations All instructions are executed within one single instruc-

tion cycle, unless a conditional test is true or the program counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 µs. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 µs.

Table 9-2 lists the instructions recognized by the MPASM assembler.

Figure 9-1 shows the general formats that the instructions can have.

All examples use the following format to represent a hexadecimal number:

0xhh

where h signiﬁes a hexadecimal digit.

FIGURE 9-1: GENERAL FORMAT FOR

INSTRUCTIONS

Note: To maintain upward compatibility with

future PIC16CXX products, do not use

the

OPTION and TRIS instructions.

Byte-oriented ﬁle register operations

13 8 7 6 0

d = 0 for destination W

OPCODE d f (FILE #)

d = 1 for destination f f = 7-bit ﬁle register address

Bit-oriented ﬁle register operations

13 10 9 7 6 0

OPCODE b (BIT #) f (FILE #)

b = 3-bit bit address f = 7-bit ﬁle register address

Literal and control operations

13 8 7 0

OPCODE k (literal)

k = 8-bit immediate value

13 11 10 0

OPCODE k (literal)

k = 11-bit immediate value

General

CALL and GOTO instructions only

PIC16C71X

DS30272A-page 70  1997 Microchip Technology Inc.

TABLE 9-2: PIC16CXX INSTRUCTION SET

Mnemonic, Operands

Description Cycles 14-Bit Opcode Status

Affected

Notes

MSb LSb

BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF

ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF

f, d f, d f

f, d f, d f, d f, d f, d f, d f, d f

f, d f, d f, d f, d f, d

Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f

1 1 1 1 1 1

1(2)

1 1 1 1 1 1 1 1 1

00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

0111 0101 0001 0001 1001 0011 1011 1010 1111 0100 1000 0000 0000 1101 1100 0010 1110 0110

dfff dfff lfff 0xxx dfff dfff dfff dfff dfff dfff dfff lfff 0xx0 dfff dfff dfff dfff dfff

ffff ffff ffff xxxx ffff ffff ffff ffff ffff ffff ffff ffff 0000 ffff ffff ffff ffff ffff

C,DC,Z Z Z Z Z Z

Z Z

C C C,DC,Z

1,2 1,2 2

1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2

1,2 1,2 1,2 1,2 1,2

BIT-ORIENTED FILE REGISTER OPERATIONS BCF

BSF BTFSC BTFSS

f, b f, b f, b f, b

Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set

1 1 (2) 1 (2)

01 01 01 01

00bb 01bb 10bb 11bb

bfff bfff bfff bfff

ffff ffff ffff ffff

1,2 1,2 3 3

LITERAL AND CONTROL OPERATIONS ADDLW

ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW

k k k

k k

Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W

11 11 10 00 10 11 11 00 11 00 00 11 11

111x 1001 0kkk 0000 1kkk 1000 00xx 0000 01xx 0000 0000 110x 1010

kkkk kkkk kkkk 0110 kkkk kkkk kkkk 0000 kkkk 0000 0110 kkkk kkkk

kkkk kkkk kkkk 0100 kkkk kkkk kkkk 1001 kkkk 1000 0011 kkkk kkkk

C,DC,Z Z

O,PD

TO,PD C,DC,Z Z

Note 1: When an I/O register is modiﬁed as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present

on the pins themselves. For example, if the data latch is '1' for a pin conﬁgured as input and is driven low by an external device, the data will be written back with a '0'.

2: If this instruction is executed on the TMR0 register (and, where applicab le , d = 1), the prescaler will be cleared if assigned

to the Timer0 Module.

3: If Program Counter (PC) is modiﬁed or a conditional test is true, the instruction requires two cycles. The second cycle is

executed as a NOP.

 1997 Microchip Technology Inc. DS30272A-page 71

PIC16C71X

9.1 Instruction Descriptions

ADDLW Add Literal and W

Syntax: [

label

] ADDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) + k → (W) Status Affected: C, DC, Z Encoding:

11 111x kkkk kkkk

Description:

The contents of the W register are added to the eight bit literal 'k' and the result is placed in the W register

. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

literal 'k'

Process

data

Write to

Example:

ADDLW 0x15

Before Instruction

W = 0x10

After Instruction

W = 0x25

ADDWF Add W and f

Syntax: [

label

] ADDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) + (f) → (dest) Status Affected: C, DC, Z Encoding:

00 0111 dfff ffff

Description:

Add the contents of the W register

with register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'

. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write to

Dest

Example

ADDWF FSR, 0

Before Instruction

W = 0x17 FSR = 0xC2

After Instruction

W = 0xD9 FSR = 0xC2

ANDLW AND Literal with W

Syntax: [

label

] ANDLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .AND. (k) → (W) Status Affected: Z Encoding:

11 1001 kkkk kkkk

Description:

The contents of W register are AND’ed with the eight bit literal 'k'. The result is placed in the W register

. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

literal "k"

Process

data

Write to

Example

ANDLW 0x5F

Before Instruction

W = 0xA3

After Instruction

W = 0x03

ANDWF AND W with f

Syntax: [

label

] ANDWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) .AND. (f) → (dest) Status Affected: Z Encoding:

00 0101 dfff ffff

Description:

AND the W register with register 'f'. If

'd' is 0 the result is stored in the W

back in register 'f'

. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write to

Dest

Example

ANDWF FSR, 1

Before Instruction

W = 0x17 FSR = 0xC2

After Instruction

W = 0x17 FSR = 0x02

PIC16C71X

DS30272A-page 72  1997 Microchip Technology Inc.

BCF Bit Clear f

Syntax: [

label

] BCF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7 Operation: 0 → (f<b>) Status Affected: None Encoding:

01 00bb bfff ffff

Description: Bit 'b' in register 'f' is cleared. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write

Example

BCF FLAG_REG, 7

Before Instruction

FLAG_REG = 0xC7

After Instruction

FLAG_REG = 0x47

BSF Bit Set f

Syntax: [

label

] BSF f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7 Operation: 1 → (f<b>) Status Affected: None Encoding:

01 01bb bfff ffff

Description:

Bit 'b' in register 'f' is set.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write

Example

BSF FLAG_REG, 7

Before Instruction

FLAG_REG = 0x0A

After Instruction

FLAG_REG = 0x8A

BTFSC Bit Test, Skip if Clear

Syntax: [

label

] BTFSC f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b ≤ 7 Operation: skip if (f<b>) = 0 Status Affected: None Encoding:

01 10bb bfff ffff

Description:

If bit 'b' in register 'f' is '1' then the next

instruction is executed.

If bit 'b', in register 'f', is '0' then the next

instruction is discarded, and a NOP is

executed instead, making this a 2TCY

instruction

. Words: 1 Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

Process

data

NOP

If Skip: (2nd Cycle)

Q1 Q2 Q3 Q4

NOP NOP NOP NOP

Example

HERE FALSE TRUE

BTFSC GOTO

•

FLAG,1 PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0,

PC = address TRUE

if FLAG<1>=1,

PC = address FALSE

 1997 Microchip Technology Inc. DS30272A-page 73

PIC16C71X

BTFSS Bit Test f, Skip if Set

Syntax: [

label

] BTFSS f,b

Operands: 0 ≤ f ≤ 127

0 ≤ b < 7 Operation: skip if (f<b>) = 1 Status Affected: None Encoding:

01 11bb bfff ffff

Description:

If bit 'b' in register 'f' is '0' then the next

instruction is executed.

If bit 'b' is '1', then the next instruction is

discarded and a NOP is executed

instead, making this a 2TCY instruction.

Words: 1 Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

Process

data

NOP

If Skip: (2nd Cycle)

Q1 Q2 Q3 Q4

NOP NOP NOP NOP

Example

HERE FALSE TRUE

BTFSC GOTO

•

FLAG,1 PROCESS_CODE

Before Instruction

PC = address HERE

After Instruction

if FLAG<1> = 0, PC = address FALSE if FLAG<1> = 1, PC = address TRUE

CALL Call Subroutine

Syntax: [

label

] CALL k Operands: 0 ≤ k ≤ 2047 Operation: (PC)+ 1→ TOS,

k → PC<10:0>,

(PCLATH<4:3>) → PC<12:11> Status Affected: None Encoding:

10 0kkk kkkk kkkk

Description:

Call Subroutine. First, return address

(PC+1) is pushed onto the stack. The

eleven bit immediate address is loaded

into PC bits <10:0>. The upper bits of

the PC are loaded from PCLATH.

CALL is a two cycle instruction.

Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4

1st Cycle

Decode Read

literal 'k',

Push PC

to Stack

Process

data

Write to

2nd Cycle

NOP NOP NOP NOP

Example

HERE CALL THERE

Before Instruction

PC = Address HERE

After Instruction

PC = Address THERE TOS= Address HERE+1

PIC16C71X

DS30272A-page 74  1997 Microchip Technology Inc.

CLRF Clear f

Syntax: [

label

] CLRF f Operands: 0 ≤ f ≤ 127 Operation: 00h → (f)

1 → Z Status Affected: Z Encoding:

00 0001 1fff ffff

Description:

The contents of register 'f' are cleared

and the Z bit is set.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write

Example

CLRF FLAG_REG

Before Instruction

FLAG_REG = 0x5A

After Instruction

FLAG_REG = 0x00 Z = 1

CLRW Clear W

Syntax: [

label

] CLRW Operands: None Operation: 00h → (W)

1 → Z Status Affected: Z Encoding:

00 0001 0xxx xxxx

Description:

W register is cleared. Zero bit (Z) is

set.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode NOP Process

data

Write to

Example

CLRW

Before Instruction

W = 0x5A

After Instruction

W = 0x00 Z = 1

CLRWDT Clear Watchdog Timer

Syntax: [

label

] CLRWDT Operands: None Operation: 00h → WDT

0 → WDT prescaler, 1 → T

1 → PD Status Affected: TO, PD Encoding:

00 0000 0110 0100

Description:

CLRWDT instruction resets the Watch-

dog Timer. It also resets the prescaler

of the WDT. Status bits TO and PD

are set.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode NOP Process

data

Clear

WDT

Counter

Example

CLRWDT

Before Instruction

WDT counter = ?

After Instruction

WDT counter = 0x00 WDT prescaler= 0

TO = 1 PD = 1

 1997 Microchip Technology Inc. DS30272A-page 75

PIC16C71X

COMF Complement f

Syntax: [

label

] COMF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f

) → (dest) Status Affected: Z Encoding:

00 1001 dfff ffff

Description:

The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f'.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write to

dest

Example

COMF REG1,0

Before Instruction

REG1 = 0x13

After Instruction

REG1 = 0x13 W = 0xEC

DECF Decrement f

Syntax: [

label

] DECF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) - 1 → (dest) Status Affected: Z Encoding:

00 0011 dfff ffff

Description:

Decrement register 'f'. If 'd' is 0 the

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'

. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write to

dest

Example

DECF CNT, 1

Before Instruction

CNT = 0x01 Z = 0

After Instruction

CNT = 0x00 Z = 1

DECFSZ Decrement f, Skip if 0

Syntax: [

label

] DECFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) - 1 → (dest); skip if result = 0 Status Affected: None Encoding:

00 1011 dfff ffff

Description:

The contents of register 'f' are decre-

mented. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

If the result is 1, the next instruction, is

executed. If the result is 0, then a NOP is

executed instead making it a 2T

instruction.

Words: 1 Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write to

dest

If Skip: (2nd Cycle)

Q1 Q2 Q3 Q4

NOP NOP NOP NOP

Example

HERE DECFSZ CNT, 1 GOTO LOOP CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT - 1 if CNT = 0, PC = address CONTINUE if CNT ≠ 0, PC = address HERE+1

PIC16C71X

DS30272A-page 76  1997 Microchip Technology Inc.

GOTO Unconditional Branch

Syntax: [

label

] GOTO k Operands: 0 ≤ k ≤ 2047 Operation: k → PC<10:0>

PCLATH<4:3> → PC<12:11> Status Affected: None Encoding:

10 1kkk kkkk kkkk

Description:

GOTO is an unconditional branch. The

eleven bit immediate value is loaded

into PC bits <10:0>. The upper bits of

PC are loaded from PCLATH<4:3>.

GOTO is a two cycle instruction.

Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4

1st Cycle

Decode Read

literal 'k'

Process

data

Write to

2nd Cycle

NOP NOP NOP NOP

Example

GOTO THERE

After Instruction

PC = Address THERE

INCF Increment f

Syntax: [

label

] INCF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) + 1 → (dest) Status Affected: Z Encoding:

00 1010 dfff ffff

Description:

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed

in the W register . If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write to

dest

Example

INCF CNT, 1

Before Instruction

CNT = 0xFF Z = 0

After Instruction

CNT = 0x00 Z = 1

 1997 Microchip Technology Inc. DS30272A-page 77

PIC16C71X

INCFSZ Increment f, Skip if 0

Syntax: [

label

] INCFSZ f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) + 1 → (dest), skip if result = 0 Status Affected: None Encoding:

00 1111 dfff ffff

Description:

The contents of register 'f' are incre-

mented. If 'd' is 0 the result is placed

in the W register . If 'd' is 1 the result is

placed back in register 'f'.

If the result is 1, the next instruction is

executed. If the result is 0, a NOP is

executed instead making it a 2TCY

instruction

. Words: 1 Cycles: 1(2) Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write to

dest

If Skip: (2nd Cycle)

Q1 Q2 Q3 Q4

NOP NOP NOP NOP

Example

HERE INCFSZ CNT, 1 GOTO LOOP CONTINUE •

•

Before Instruction

PC = address HERE

After Instruction

CNT = CNT + 1 if CNT= 0, PC = address CONTINUE if CNT≠ 0, PC = address HERE +1

IORLW Inclusive OR Literal with W

Syntax: [

label

] IORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → (W) Status Affected: Z Encoding:

11 1000 kkkk kkkk

Description:

The contents of the W register is OR’ed with the eight bit literal 'k'. The result is placed in the W register

. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

literal 'k'

Process

data

Write to

Example

IORLW 0x35

Before Instruction

W = 0x9A

After Instruction

W = 0xBF Z = 1

PIC16C71X

DS30272A-page 78  1997 Microchip Technology Inc.

IORWF Inclusive OR W with f

Syntax: [

label

] IORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) .OR. (f) → (dest) Status Affected: Z Encoding:

00 0100 dfff ffff

Description:

Inclusive OR the W register with regis-

ter 'f'. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write to

dest

Example

IORWF RESULT, 0

Before Instruction

RESULT = 0x13 W = 0x91

After Instruction

RESULT = 0x13 W = 0x93 Z = 1

MOVF Move f

Syntax: [

label

] MOVF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) → (dest) Status Affected: Z Encoding:

00 1000 dfff ffff

Description:

The contents of register f is moved to

a destination dependant upon the sta-

tus of d. If d = 0, destination is W reg-

ister. If d = 1, the destination is ﬁle

ﬁle register since status ﬂag Z is

affected.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write to

dest

Example

MOVF FSR, 0

After Instruction

W = value in FSR register Z = 1

MOVLW Move Literal to W

Syntax: [

label

] MOVLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W) Status Affected: None Encoding:

11 00xx kkkk kkkk

Description:

The eight bit literal 'k' is loaded into W register

. The don’t cares will assemble

as 0’s.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

literal 'k'

Process

data

Write to

Example

MOVLW 0x5A

After Instruction

W = 0x5A

MOVWF Move W to f

Syntax: [

label

] MOVWF f Operands: 0 ≤ f ≤ 127 Operation: (W) → (f) Status Affected: None Encoding:

00 0000 1fff ffff

Description:

Move data from W register to register 'f'

. Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write

Example

MOVWF OPTION_REG

Before Instruction

OPTION = 0xFF W = 0x4F

After Instruction

OPTION = 0x4F W = 0x4F

 1997 Microchip Technology Inc. DS30272A-page 79

PIC16C71X

NOP No Operation

Syntax: [

label

] NOP Operands: None Operation: No operation Status Affected: None Encoding:

00 0000 0xx0 0000

Description:

No operation.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode NOP NOP NOP

Example

NOP

OPTION Load Option Register

Syntax: [

label

] OPTION

Operands: None

Operation: (W) → OPTION Status Affected: None Encoding:

00 0000 0110 0010

Description:

The contents of the W register are loaded in the OPTION register. This instruction is supported for code compatibility with PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it.

Words: 1 Cycles: 1 Example

To maintain upward compatibility with future PIC16CXX products, do not use this instruction.

RETFIE Return from Interrupt

Syntax: [

label

] RETFIE Operands: None Operation: TOS → PC,

1 → GIE Status Affected: None Encoding:

00 0000 0000 1001

Description:

Return from Interrupt. Stack is POP ed

and Top of Stack (TOS) is loaded in

the PC. Interrupts are enabled by set-

ting Global Interrupt Enable bit, GIE

(INTCON<7>). This is a two cycle

instruction.

Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4

1st Cycle

Decode NOP Set the

GIE bit

Pop from

the Stack

2nd Cycle

NOP NOP NOP NOP

Example

RETFIE

After Interrupt

PC = TOS GIE = 1

PIC16C71X

DS30272A-page 80  1997 Microchip Technology Inc.

RETLW Return with Literal in W

Syntax: [

label

] RETLW k Operands: 0 ≤ k ≤ 255 Operation: k → (W);

TOS → PC Status Affected: None Encoding:

11 01xx kkkk kkkk

Description:

The W register is loaded with the eight

bit literal 'k'. The program counter is

loaded from the top of the stack (the

return address). This is a two cycle

instruction.

Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4

1st Cycle

Decode Read

literal 'k'

NOP Write to

W, Pop

from the

Stack

2nd Cycle

NOP NOP NOP NOP

Example

TABLE

CALL TABLE ;W contains table

;offset value

• ;W now has table value

•

ADDWF PC ;W = offset

RETLW k1 ;Begin table

RETLW k2 ;

•

RETLW kn ; End of table

Before Instruction

W = 0x07

After Instruction

W = value of k8

RETURN Return from Subroutine

Syntax: [

label

] RETURN Operands: None Operation: TOS → PC Status Affected: None Encoding:

00 0000 0000 1000

Description:

Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction.

Words: 1 Cycles: 2 Q Cycle Activity: Q1 Q2 Q3 Q4

1st Cycle

Decode NOP NOP Pop from

the Stack

2nd Cycle

NOP NOP NOP NOP

Example

RETURN

After Interrupt

PC = TOS

 1997 Microchip Technology Inc. DS30272A-page 81

PIC16C71X

RLF Rotate Left f through Carry

Syntax: [

label

] RLF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: See description below Status Affected: C Encoding:

00 1101 dfff ffff

Description:

The contents of register 'f' are rotated

one bit to the left through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

stored back in register 'f'.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write to

dest

Example

RLF REG1,0

Before Instruction

REG1 = 1110 0110 C = 0

After Instruction

REG1 = 1110 0110 W = 1100 1100 C = 1

RRF Rotate Right f through Carry

Syntax: [

label

] RRF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: See description below Status Affected: C Encoding:

00 1100 dfff ffff

Description:

The contents of register 'f' are rotated

one bit to the right through the Carry

Flag. If 'd' is 0 the result is placed in

the W register. If 'd' is 1 the result is

placed back in register 'f'.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write to

dest

Example

RRF REG1,0

Before Instruction

REG1 = 1110 0110 C = 0

After Instruction

REG1 = 1110 0110 W = 0111 0011 C = 0

PIC16C71X

DS30272A-page 82  1997 Microchip Technology Inc.

SLEEP

Syntax: [

label

] SLEEP Operands: None Operation: 00h → WDT,

0 → WDT prescaler, 1 → T

0 → PD Status Affected: TO, PD Encoding:

00 0000 0110 0011

Description:

The power-down status bit, PD is

cleared. Time-out status bit, TO is

set. Watchdog Timer and its pres-

caler are cleared.

The processor is put into SLEEP

mode with the oscillator stopped.

See Section 8.8 for more details.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode NOP NOP Go to

Sleep

Example: SLEEP

SUBLW Subtract W from Literal

Syntax: [

label

] SUBLW k Operands: 0 ≤ k ≤ 255 Operation: k - (W) → (W) Status Affected: C, DC, Z Encoding: 11 110x kkkk kkkk Description:

The W register is subtracted (2’s complement method) from the eight bit literal 'k'. The result is placed in the W register.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

literal 'k'

Process

data

Write to W

Example 1: SUBLW 0x02

Before Instruction

W = 1 C = ? Z = ?

After Instruction

W = 1 C = 1; result is positive Z = 0

Example 2: Before Instruction

W = 2 C = ? Z = ?

After Instruction

W = 0 C = 1; result is zero Z = 1

Example 3: Before Instruction

W = 3 C = ? Z = ?

After Instruction

W = 0xFF C = 0; result is negative Z = 0

 1997 Microchip Technology Inc. DS30272A-page 83

PIC16C71X

SUBWF Subtract W from f

Syntax: [

label

] SUBWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (f) - (W) → (dest) Status Affected: C, DC, Z Encoding: 00 0010 dfff ffff Description:

Subtract (2’s complement method) W reg-

ister from register 'f'. If 'd' is 0 the result is

stored in the W register. If 'd' is 1 the

result is stored back in register 'f'.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

Process

data

Write to

dest

Example 1: SUBWF REG1,1

Before Instruction

REG1 = 3 W = 2 C = ? Z = ?

After Instruction

REG1 = 1 W = 2 C = 1; result is positive Z = 0

Example 2: Before Instruction

REG1 = 2 W = 2 C = ? Z = ?

After Instruction

REG1 = 0 W = 2 C = 1; result is zero Z = 1

Example 3: Before Instruction

REG1 = 1 W = 2 C = ? Z = ?

After Instruction

REG1 = 0xFF W = 2 C = 0; result is negative Z = 0

SWAPF Swap Nibbles in f

Syntax: [

label

] SWAPF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1]

Operation: (f<3:0>) → (dest<7:4>),

(f<7:4>) → (dest<3:0>) Status Affected: None Encoding:

1110 dfff ffff

Description:

The upper and lower nibbles of regis-

ter 'f' are exchanged. If 'd' is 0 the

result is placed in W register. If 'd' is 1

the result is placed in register 'f'.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

Process

data

Write to

dest

Example

SWAPF REG, 0

Before Instruction

REG1 = 0xA5

After Instruction

REG1 = 0xA5 W = 0x5A

TRIS Load TRIS Register

Syntax: [

label

] TRIS f

Operands: 5 ≤ f ≤ 7

Operation: (W) → TRIS register f; Status Affected: None Encoding:

0000 0110 0fff

Description:

The instruction is supported for code

compatibility with the PIC16C5X prod-

ucts. Since TRIS registers are read-

able and writable, the user can directly

address them.

Words: 1 Cycles: 1

Example

To maintain upward compatibility with future PIC16CXX products, do not use this instruction.

PIC16C71X

DS30272A-page 84  1997 Microchip Technology Inc.

XORLW Exclusive OR Literal with W

Syntax: [

label

] XORLW k Operands: 0 ≤ k ≤ 255 Operation: (W) .XOR. k → (W) Status Affected: Z Encoding: 11 1010 kkkk kkkk Description:

The contents of the W register are XOR’ed with the eight bit literal 'k'. The result is placed in the W register.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

literal 'k'

Process

data

Write to

Example: XORLW 0xAF

Before Instruction

W = 0xB5

After Instruction

W = 0x1A

XORWF Exclusive OR W with f

Syntax: [

label

] XORWF f,d

Operands: 0 ≤ f ≤ 127

d ∈ [0,1] Operation: (W) .XOR. (f) → (dest) Status Affected: Z Encoding:

00 0110 dfff ffff

Description:

Exclusive OR the contents of the W

result is stored in the W register. If 'd'

is 1 the result is stored back in register

'f'.

Words: 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4

Decode Read

'f'

Process

data

Write to

dest

Example XORWF

REG 1

Before Instruction

REG = 0xAF W = 0xB5

After Instruction

REG = 0x1A W = 0xB5

PIC16C71X

 1997 Microchip Technology Inc. DS30272A-page 85

10.0 DEVELOPMENT SUPPORT

10.1 Development Tools

The PICmicrο microcontrollers are supported with a full range of hardware and software dev elopment tools:

• PICMASTER/PICMASTER CE Real-Time In-Circuit Emulator

• ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator

• PRO MATE



II Universal Programmer

• PICSTART



Plus Entry-Level Prototype

Programmer

• PICDEM-1 Low-Cost Demonstration Board

• PICDEM-2 Low-Cost Demonstration Board

• PICDEM-3 Low-Cost Demonstration Board

• MPASM Assembler

• MPLAB SIM Software Simulator

• MPLAB-C (C Compiler)

• Fuzzy Logic Development System (

fuzzy

TECH−MP)

10.2 PICMASTER: High Performance

Universal In-Circuit Emulator with MPLAB IDE

The PICMASTER Universal In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for all microcontrollers in the PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX families. PICMASTER is supplied with the MPLAB Integrated Development Environment (IDE), which allows editing, “make” and download, and source debugging from a single environment.

Interchangeable target probes allow the system to be easily reconﬁgured for emulation of different processors. The universal architecture of the PICMASTER allows expansion to support all new Microchip microcontrollers.

The PICMASTER Emulator System has been designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows



3.x environment were chosen to best make these fea-

tures available to you, the end user. A CE compliant version of PICMASTER is availab le for

European Union (EU) countries.

10.3 ICEPIC: Low-Cost PIC16CXXX In-Circuit Emulator

ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers.

ICEPIC is designed to operate on PC-compatible machines ranging from 286-AT



through Pentium based machines under Windows 3.x environment. ICEPIC features real time, non-intrusive emulation.

10.4 PRO MATE II: Universal Programmer

The PRO MATE II Universal Programmer is a full-featured programmer capable of operating in stand-alone mode as well as PC-hosted mode.

The PRO MATE II has programmable V

DD and VPP

supplies which allows it to verify programmed memory at V

DD min and VDD max for maximum reliability. It has

an LCD display for displaying error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In standalone mode the PRO MATE II can read, verify or program PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices. It can also set conﬁguration and code-protect bits in this mode.

10.5 PICSTART Plus Entry Level

Development System

The PICSTART programmer is an easy-to-use, lowcost prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efﬁcient. PICSTART Plus is not recommended for production programming.

PICSTART Plus supports all PIC12CXXX, PIC14C000, PIC16C5X, PIC16CXXX and PIC17CXX devices with up to 40 pins. Larger pin count devices such as the PIC16C923 and PIC16C924 may be supported with an adapter socket.

PIC16C71X

DS30272A-page 86  1997 Microchip Technology Inc.

10.6 PICDEM-1 Low-Cost PIC16/17 Demonstration Board

The PICDEM-1 is a simple board which demonstrates the capabilities of several of Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The users can program the sample microcontrollers provided with the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test ﬁrmware. The user can also connect the PICDEM-1 board to the PICMASTER emulator and download the ﬁrmware to the emulator for testing. Additional prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push-button switches and eight LEDs connected to PORTB.

10.7 PICDEM-2 Low-Cost PIC16CXX Demonstration Board

The PICDEM-2 is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board, on a PRO MATE II programmer or PICSTART-Plus, and easily test ﬁrmware. The PICMASTER emulator may also be used with the PICDEM-2 board to test ﬁrmware. Additional prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the f eatures include a RS-232 interface, push-button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I

C bus and separate headers for connec-

tion to an LCD module and a keypad.

10.8 PICDEM-3 Low-Cost PIC16CXXX Demonstration Board

The PICDEM-3 is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with a LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-3 board, on a PRO MATE II programmer or PICSTART Plus with an adapter socket, and easily test ﬁrmware. The PICMASTER emulator may also be used with the PICDEM-3 board to test ﬁrmware. Additional prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the f eatures include

an RS-232 interface, push-button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM-3 board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM-3 provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplex ed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals.

10.9 MPLAB Integrated Development Environment Software

The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcontroller market. MPLAB is a windows based application which contains:

• A full featured editor

• Three operating modes

- editor

- emulator

- simulator

• A project manager

• Customizable tool bar and key mapping

• A status bar with project information

• Extensive on-line help

MPLAB allows you to:

• Edit your source ﬁles (either assembly or ‘C’)

• One touch assemble (or compile) and download

to PIC16/17 tools (automatically updates all project information)

• Debug using:

- source ﬁles

- absolute listing ﬁle

• Transfer data dynamically via DDE (soon to be

replaced by OLE)

• Run up to four emulators on the same PC

The ability to use MPLAB with Microchip’s simulator allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured emulator with minimal retraining due to development tools.

10.10 Assembler (MPASM)

The MPASM Universal Macro Assembler is a PChosted symbolic assembler. It suppor ts all microcontroller series including the PIC12C5XX, PIC14000, PIC16C5X, PIC16CXXX, and PIC17CXX families.

MPASM offers full featured Macro capabilities, conditional assembly , and se ver al source and listing formats. It generates various object code formats to support Microchip's development tools as well as third party programmers.

MPASM allows full symbolic debugging from PICMASTER, Microchip’s Universal Emulator System.

PIC16C71X

 1997 Microchip Technology Inc. DS30272A-page 87

MPASM has the following features to assist in developing software for speciﬁc use applications.

• Provides translation of Assembler source code to object code for all Microchip microcontrollers.

• Macro assembly capability.

• Produces all the ﬁles (Object, Listing, Symbol, and special) required for symbolic debug with Microchip’s emulator systems.

• Supports Hex (default), Decimal and Octal source and listing formats.

MPASM provides a rich directive language to support programming of the PIC16/17. Directives are helpful in making the development of your assemb le source code shorter and more maintainable.

10.11 Software Simulator (MPLAB-SIM)

The MPLAB-SIM Software Simulator allows code development in a PC host environment. It allows the user to simulate the PIC16/17 series microcontrollers on an instruction level. On any given instruction, the user may examine or modify any of the data areas or provide external stimulus to any of the pins. The input/ output radix can be set by the user and the execution can be performed in; single step , ex ecute until break, or in a trace mode.

MPLAB-SIM fully supports symbolic debugging using MPLAB-C and MPASM. The Software Simulator offers the low cost ﬂexibility to develop and debug code outside of the laboratory environment making it an excellent multi-project software development tool.

10.12 C Compiler (MPLAB-C)

The MPLAB-C Code Development System is a complete ‘C’ compiler and integrated development environment for Microchip’s PIC16/17 family of microcontrollers. The compiler provides powerful integration capabilities and ease of use not found with other compilers.

For easier source level debugging, the compiler provides symbol information that is compatible with the MPLAB IDE memory display.

10.13 Fuzzy Logic Development System

(

fuzzy

TECH-MP)

fuzzy

TECH-MP fuzzy logic development tool is available in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version,

fuzzy

TECH-MP, edition for imple-

menting more complex systems. Both versions include Microchip’s

fuzzy

LAB demonstration board for hands-on experience with fuzzy logic systems implementation.

10.14 MP-DriveWay – Application Code

Generator

MP-DriveWay is an easy-to-use Windows-based Application Code Generator. With MP-DriveWay you can visually conﬁgure all the peripherals in a PIC16/17 device and, with a click of the mouse, generate all the initialization and many functional code modules in C language. The output is fully compatible with Microchip’s MPLAB-C C compiler. The code produced is highly modular and allows easy integration of your own code. MP-DriveWay is intelligent enough to maintain your code through subsequent code generation.

10.15 SEEVAL Evaluation and Programming System

The SEEVAL SEEPROM Designer’s Kit supports all Microchip 2-wire and 3-wire Serial EEPROMs. The kit includes everything necessary to read, write, erase or program special features of any Microchip SEEPROM product including Smart Serials and secure serials. The Total Endurance Disk is included to aid in tradeoff analysis and reliability calculations. The total kit can signiﬁcantly reduce time-to-market and result in an optimized system.

10.16 KEELOQ Evaluation and Programming Tools

KEELOQ evaluation and programming tools support Microchips HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a programming interface to program test transmitters.

PIC16C71X

DS30272A-page 88  1997 Microchip Technology Inc.

TABLE 10-1: DEVELOPMENT TOOLS FROM MICROCHIP

PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C75X

24CXX

25CXX

93CXX

HCS200

HCS300

HCS301

Emulator Products

PICMASTER



PICMASTER-CE

In-Circuit Emulator

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

Available

3Q97

ICEPIC Low-Cost

In-Circuit Emulator

✔ ✔ ✔ ✔ ✔ ✔

Software Tools

MPLAB

Integrated

Development

Environment

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

MPLAB C

Compiler

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

fuzzy

TECH



-MP

Explorer/Edition

Fuzzy Logic

Dev. Tool

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

MP-DriveWay

Applications

Code Generator

✔ ✔ ✔ ✔ ✔ ✔

Total Endurance

Software Model

✔

Programmers

PICSTART



Lite Ultra Low-Cost

Dev. Kit

✔ ✔ ✔ ✔

PICSTART



Plus Low-Cost

Universal Dev. Kit

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

PRO MATE



Universal

Programmer

✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

KEELOQ



Programmer

✔

Demo Boards

SEEVAL



Designers Kit

✔

PICDEM-1

✔ ✔ ✔ ✔

PICDEM-2

✔ ✔

PICDEM-3

✔

KEELOQ



Evaluation Kit

✔

 1997 Microchip Technology Inc. DS30272A-page 89

PIC16C71X

Applicable Devices 710 71 711 715

11.0 ELECTRICAL CHARACTERISTICS FOR PIC16C710 AND PIC16C711

Absolute Maximum Ratings †

Ambient temperature under bias.................................................................................................................-55 to +125˚C

Storage temperature.............................................................................................................................. -65˚C to +150˚C

Voltage on any pin with respect to V

SS (except VDD, MCLR, and RA4)..........................................-0.3V to (VDD + 0.3V)

Voltage on V

DD with respect to VSS ........................................................................................................... -0.3 to +7.5V

Voltage on MCLR

with respect to VSS................................................................................................................0 to +14V

Voltage on RA4 with respect to Vss...................................................................................................................0 to +14V

Total power dissipation (Note 1)................................................................................................................................1.0W

Maximum current out of V

SS pin ...........................................................................................................................300 mA

Maximum current into V

DD pin..............................................................................................................................250 mA

Input clamp current, I

IK (VI < 0 or VI > VDD).....................................................................................................................± 20 mA

Output clamp current, I

OK (VO < 0 or VO > VDD).............................................................................................................± 20 mA

Maximum output current sunk by any I/O pin..........................................................................................................25 mA

Maximum output current sourced by any I/O pin ....................................................................................................25 mA

Maximum current sunk by PORTA ........................................................................................................................200 mA

Maximum current sourced by PORTA...................................................................................................................200 mA

Maximum current sunk by PORTB........................................................................................................................200 mA

Maximum current sourced by PORTB...................................................................................................................200 mA

Note 1: Power dissipation is calculated as follows: Pdis = V

DD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)

TABLE 11-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR CONFIGURATIONS

AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or an y other conditions abo v e those indicated in the operation listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

OSC

PIC16C710-04 PIC16C711-04

PIC16C710-10 PIC16C711-10

PIC16C710-20 PIC16C711-20

PIC16LC710-04 PIC16LC711-04

PIC16C710/JW PIC16C711/JW

VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 µA max. at 4V Freq:4 MHz max.

VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 µA typ. at 4V Freq: 4 MHz max.

VDD: 2.5V to 6.0V IDD: 3.8 mA typ. at 3.0V IPD: 5.0 µA typ. at 3V Freq: 4 MHz max.

VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 µA max. at 4V Freq:4 MHz max.

VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 µA max. at 4V Freq: 4 MHz max.

VDD: 4.5V to 5.5V IDD: 2.7 mA typ. at 5.5V IPD: 1.5 µA typ. at 4V Freq: 4 MHz max.

VDD: 2.5V to 6.0V IDD: 3.8 mA typ. at 3.0V IPD: 5.0 µA typ. at 3V Freq: 4 MHz max.

VDD: 4.0V to 6.0V IDD: 5 mA max. at 5.5V IPD: 21 µA max. at 4V Freq: 4 MHz max.

VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD:4.5V to 5.5V

Not recommended for

use in HS mode

VDD: 4.5V to 5.5V

IDD: 13.5 mA typ. at

5.5V

IDD: 30 mA max. at

5.5V

IDD: 30 mA max. at

5.5V

IDD: 30 mA max. at

5.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V Freq: 4 MHz max. Freq: 10 MHz max. Freq:20 MHz max. Freq: 10 MHz max.

VDD: 4.0V to 6.0V IDD: 52.5 µA typ. at

32 kHz, 4.0V IPD: 0.9 µA typ. at 4.0V Freq: 200 kHz max.

Not recommended for

use in LP mode

Not recommended for

use in LP mode

VDD: 2.5V to 6.0V IDD: 48 µA max. at

32 kHz, 3.0V IPD: 5.0 µA max. at 3.0V Freq: 200 kHz max.

VDD: 2.5V to 6.0V IDD: 48 µA max. at

32 kHz, 3.0V

IPD: 5.0 µA max. at

3.0V

Freq: 200 kHz max.

PIC16C71X

DS30272A-page 90  1997 Microchip Technology Inc.

Applicable Devices 710 71 711 715

11.1 DC Characteristics: PIC16C710-04 (Commercial, Industrial, Extended) PIC16C711-04 (Commercial, Industrial, Extended) PIC16C710-10 (Commercial, Industrial, Extended) PIC16C711-10 (Commercial, Industrial, Extended) PIC16C710-20 (Commercial, Industrial, Extended) PIC16C711-20 (Commercial, Industrial, Extended)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0˚C ≤ T

A ≤ +70˚C (commercial)

-40˚C ≤ T

A ≤ +85˚C (industrial)

-40˚C ≤ T

A ≤ +125˚C (extended)

Param.

No.

Characteristic Sym Min Typ† Max Units Conditions

D001 D001A

Supply Voltage V

DD 4.0

4.5--

6.0

5.5VV

XT, RC and LP osc conﬁguration HS osc conﬁguration

D002* RAM Data Retention

Voltage (Note 1)

DR - 1.5 - V

D003 V

DD start voltage to

ensure internal Power-

on Reset signal

VPOR - VSS - V See section on Power-on Reset for details

D004* V

DD rise rate to ensure

internal Power-on Reset signal

SVDD 0.05 - - V/ms See section on Power-on Reset for details

D005 Brown-out Reset Voltage B

VDD 3.7 4.0 4.3 V BODEN conﬁguration bit is enabled

3.7 4.0 4.4 V Extended Range Only

D010

D013

Supply Current (Note 2) I

DD -

2.7

13.5530mAmA

XT, RC osc conﬁguration F

OSC = 4 MHz, VDD = 5.5V (Note 4)

HS osc conﬁguration F

OSC = 20 MHz, VDD = 5.5V

D015 Brown-out Reset Current

(Note 5)

∆I

BOR - 300* 500 µA BOR enabled VDD = 5.0V

D020 D021 D021A D021B

Power-down Current (Note 3)

PD -

10.5

1.5

42 21 24 30

µA µA µA µA

DD = 4.0V, WDT enabled, -40°C to +85°C

DD = 4.0V, WDT disabled, -0°C to +70°C

DD = 4.0V, WDT disabled, -40°C to +85°C

DD = 4.0V, WDT disabled, -40°C to +125°C

D023 Brown-out Reset Current

(Note 5)

∆I

BOR - 300* 500 µA BOR enabled VDD = 5.0V

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which V

DD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all I

DD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to V

MCLR

= VDD; WDT enabled/disabled as speciﬁed.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

DD and VSS.

4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be esti-

mated by the formula Ir = V

DD/2Rext (mA) with Rext in kOhm.

5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base I

DD or IPD measurement.

 1997 Microchip Technology Inc. DS30272A-page 91

PIC16C71X

Applicable Devices 710 71 711 715

11.2 DC Characteristics: PIC16LC710-04 (Commercial, Industrial, Extended) PIC16LC711-04 (Commercial, Industrial, Extended)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0˚C ≤ T

A ≤ +70˚C (commercial)

-40˚C ≤ T

A ≤ +85˚C (industrial)

-40˚C ≤ T

A ≤ +125˚C (extended)

Param

No.

Characteristic Sym Min Typ† Max Units Conditions

D001 Supply Voltage

Commercial/Industrial Extended

VDD

2.5

3.0

--6.0

6.0VV

LP, XT, RC osc conﬁguration (DC - 4 MHz) LP, XT, RC osc conﬁguration (DC - 4 MHz)

D002* RAM Data Retention

Voltage (Note 1)

DR - 1.5 - V

D003 V

DD start voltage to

ensure internal Poweron Reset signal

VPOR - VSS - V See section on Power-on Reset for details

D004* VDD rise rate to ensure

internal Power-on Reset signal

VDD 0.05 - - V/ms See section on Power-on Reset for details

D005 Brown-out Reset

Voltage

VDD 3.7 4.0 4.3 V BODEN conﬁguration bit is enabled

D010

D010A D015

Supply Current (Note 2)

Brown-out Reset Current (Note 5)

∆IBOR

2.0

22.5 300*

3.8

500

µA µA

XT, RC osc conﬁguration F

OSC = 4 MHz, VDD = 3.0V (Note 4)

LP osc conﬁguration F

OSC = 32 kHz, VDD = 3.0V, WDT disabled

BOR enabled V

DD = 5.0V

D020 D021 D021A D021B D023

Power-down Current (Note 3)

Brown-out Reset Current (Note 5)

∆IBOR

7.5

0.9

300*

5 5

500

µA µA µA µA µA

DD = 3.0V, WDT enabled, -40°C to +85°C

DD = 3.0V, WDT disabled, 0°C to +70°C

DD = 3.0V, WDT disabled, -40°C to +85°C

DD = 3.0V, WDT disabled, -40°C to +125°C

BOR enabled V

DD = 5.0V

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: This is the limit to which V

DD can be lowered without losing RAM data.

2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin

loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all I

DD measurements in active operation mode are:

OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to V

MCLR

= VDD; WDT enabled/disabled as speciﬁed.

3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is

measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to V

DD and VSS.

4: For RC osc conﬁguration, current through Rext is not included. The current through the resistor can be esti-

mated by the formula Ir = V

DD/2Rext (mA) with Rext in kOhm.

5: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be

added to the base I

DD or IPD measurement.

PIC16C71X

DS30272A-page 92  1997 Microchip Technology Inc.

Applicable Devices 710 71 711 715

11.3 DC Characteristics: PIC16C710-04 (Commercial, Industrial, Extended) PIC16C711-04 (Commercial, Industrial, Extended) PIC16C710-10 (Commercial, Industrial, Extended) PIC16C711-10 (Commercial, Industrial, Extended) PIC16C710-20 (Commercial, Industrial, Extended) PIC16C711-20 (Commercial, Industrial, Extended) PIC16LC710-04 (Commercial, Industrial, Extended) PIC16LC711-04 (Commercial, Industrial, Extended)

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0˚C ≤ T

A ≤ +70˚C (commercial)

-40˚C ≤ T

A ≤ +85˚C (industrial)

-40˚C ≤ T

A ≤ +125˚C (extended)

Operating voltage V

DD range as described in DC spec Section 11.1 and

Section 11.2.

Param

No.

Characteristic Sym Min T yp†Max Units Conditions

Input Low Voltage

I/O ports V

D030 with TTL buffer VSS - 0.15VDD V For entire VDD range D030A V

SS - 0.8V V 4.5 ≤ VDD ≤ 5.5V

D031 with Schmitt Trigger buffer V

SS - 0.2VDD V

D032 MCLR

, OSC1

(in RC mode)

VSS - 0.2VDD V

D033 OSC1 (in XT, HS and LP) V

SS - 0.3VDD V Note1

Input High Voltage

I/O ports V

IH -

D040 with TTL buffer 2.0 - V

DD V 4.5 ≤ VDD ≤ 5.5V

D040A 0.25V

+ 0.8V

- V

DD V For entire VDD range

D041 with Schmitt Trigger buffer 0.8V

DD - VDD V For entire VDD range

D042 MCLR

, RB0/INT 0.8VDD - VDD V

D042A OSC1 (XT, HS and LP) 0.7V

DD - VDD V Note1

D043 OSC1 (in RC mode) 0.9V

DD - VDD V

D070 PORTB weak pull-up current I

PURB 50 250 400 µA VDD = 5V, VPIN = VSS

Input Leakage Current (Notes 2, 3)

D060 I/O ports I

IL - - ±1 µA Vss ≤ VPIN ≤ VDD, Pin at hi-

impedance

D061 MCLR

, RA4/T0CKI - - ±5 µA Vss ≤ VPIN ≤ VDD

D063 OSC1 - - ±5 µA Vss ≤ VPIN ≤ VDD, XT, HS and LP

osc conﬁguration

* These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In RC oscillator conﬁguration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC16C7X be driven with external clock in RC mode.

2: The leakage current on the MCLR

pin is strongly dependent on the applied voltage lev el. The speciﬁed levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as current sourced by the pin.

 1997 Microchip Technology Inc. DS30272A-page 93

PIC16C71X

Applicable Devices 710 71 711 715

Output Low Voltage

D080 I/O ports V

OL - - 0.6 V IOL = 8.5 mA, VDD = 4.5V,

-40°C to +85°C

D080A - - 0.6 V I

OL = 7.0 mA, VDD = 4.5V,

-40°C to +125°C

D083 OSC2/CLKOUT (RC osc conﬁg) - - 0.6 V I

OL = 1.6 mA, VDD = 4.5V,

-40°C to +85°C

D083A - - 0.6 V I

OL = 1.2 mA, VDD = 4.5V,

-40°C to +125°C

Output High Voltage

D090 I/O ports (Note 3) V

OH VDD - 0.7 - - V IOH = -3.0 mA, VDD = 4.5V,

-40°C to +85°C

D090A V

DD - 0.7 - - V IOH = -2.5 mA, VDD = 4.5V,

-40°C to +125°C

D092 OSC2/CLKOUT (RC osc conﬁg) V

DD - 0.7 - - V IOH = -1.3 mA, VDD = 4.5V,

-40°C to +85°C

D092A V

DD - 0.7 - - V IOH = -1.0 mA, VDD = 4.5V,

-40°C to +125°C

D130* Open-Drain High Voltage V

OD - - 14 V RA4 pin

Capacitive Loading Specs on Output Pins

D100 OSC2 pin C

OSC2 - - 15 pF In XT, HS and LP modes when

external clock is used to drive OSC1.

D101 All I/O pins and OSC2 (in RC mode) C

IO - - 50 pF

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature 0˚C ≤ T

A ≤ +70˚C (commercial)

-40˚C ≤ T

A ≤ +85˚C (industrial)

-40˚C ≤ T

A ≤ +125˚C (extended)

Operating voltage V

DD range as described in DC spec Section 11.1 and

Section 11.2.

Param

No.

Characteristic Sym Min T yp†Max Units Conditions

* These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only

and are not tested.

Note 1: In RC oscillator conﬁguration, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the

PIC16C7X be driven with external clock in RC mode.

2: The leakage current on the MCLR

pin is strongly dependent on the applied voltage lev el. The speciﬁed levels

represent normal operating conditions. Higher leakage current may be measured at different input voltages.

3: Negative current is deﬁned as current sourced by the pin.

PIC16C71X

DS30272A-page 94  1997 Microchip Technology Inc.

Applicable Devices 710 71 711 715

11.4 Timing Parameter Symbology

The timing parameter symbols have been created following one of the following formats:

FIGURE 11-1: LOAD CONDITIONS

1. TppS2ppS

2. TppS

F Frequency T Time Lowercase letters (pp) and their meanings:

cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR

wr WR

Uppercase letters and their meanings:

F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance

VDD/2

Pin Pin

VSS

RL = 464Ω C

L = 50 pF for all pins except OSC2

15 pF for OSC2 output

Load condition 1

Load condition 2

 1997 Microchip Technology Inc. DS30272A-page 95

PIC16C71X

Applicable Devices 710 71 711 715

11.5 Timing Diagrams and Speciﬁcations FIGURE 11-2: EXTERNAL CLOCK TIMING

TABLE 11-2: EXTERNAL CLOCK TIMING REQUIREMENTS

Parameter

No.

Sym Characteristic Min Typ† Max Units Conditions

Fosc External CLKIN Frequency

(Note 1)

DC — 4 MHz XT osc mode DC — 4 MHz HS osc mode (-04) DC — 10 MHz HS osc mode (-10) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode

Oscillator Frequency (Note 1)

DC — 4 MHz RC osc mode

0.1 — 4 MHz XT osc mode 4

— —

200

MHz

kHz

HS osc mode LP osc mode

1 Tosc External CLKIN Period

(Note 1)

250 — — ns XT osc mode 250 — — ns HS osc mode (-04) 100 — — ns HS osc mode (-10)

50 — — ns HS osc mode (-20)

5 — — µs LP osc mode

Oscillator Period (Note 1)

250 — — ns RC osc mode 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 10050—

—

250 250

nsnsHS osc mode (-10)

HS osc mode (-20)

5 — — µs LP osc mode

2 T

CY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC

3 TosL,

TosH

External Clock in (OSC1) High or Low Time

50 — — ns XT oscillator

2.5 — — µs LP oscillator

10 — — ns HS oscillator

4 TosR,

TosF

External Clock in (OSC1) Rise or Fall Time

— — 25 ns XT oscillator — — 50 ns LP oscillator — — 15 ns HS oscillator

† Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All speciﬁed values are based on

characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these speciﬁed limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. OSC2 is disconnected (has no loading) for the PIC16C710/711.

OSC1

CLKOUT

Q4 Q1 Q2 Q3 Q4 Q1

PIC16C71X

DS30272A-page 96  1997 Microchip Technology Inc.

Applicable Devices 710 71 711 715

FIGURE 11-3: CLKOUT AND I/O TIMING

TABLE 11-3: CLKOUT AND I/O TIMING REQUIREMENTS

Parameter

No.

Sym Characteristic Min Typ† Max Units Conditions

10* TosH2ckL OSC1↑ to CLKOUT↓ — 15 30 ns Note 1 11* TosH2ckH OSC1↑ to CLKOUT↑ — 15 30 ns Note 1 12* TckR CLKOUT rise time — 5 15 ns Note 1 13* TckF CLKOUT fall time — 5 15 ns Note 1 14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT ↑ 0.25TCY + 25 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1 17* TosH2ioV OSC1↑ (Q1 cycle) to

Port out valid

— — 80 - 100 ns

18* TosH2ioI OSC1↑ (Q2 cycle) to

Port input invalid (I/O in hold time)

TBD — — ns

19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) TBD — — ns 20* TioR Port output rise time PIC16C710/711 — 10 25 ns

PIC16LC710/711 — — 60 ns

21* TioF Port output fall time PIC16C710/711 — 10 25 ns

PIC16LC710/711 — — 60 ns 22††* Tinp INT pin high or low time 20 — — ns 23††* Trbp RB7:RB4 change INT high or low time 20 — — ns

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

†† These parameters are asynchronous events not related to any internal clock edges.

Note 1: Measurements are taken in RC Mode where CLKOUT output is 4 x T

OSC.

Note: Refer to Figure 11-1 for load conditions.

OSC1

CLKOUT

I/O Pin (input)

I/O Pin (output)

Q2 Q3

20, 21

old value

new value

 1997 Microchip Technology Inc. DS30272A-page 97

PIC16C71X

Applicable Devices 710 71 711 715

FIGURE 11-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP

TIMER TIMING

FIGURE 11-5: BROWN-OUT RESET TIMING

TABLE 11-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,

AND BROWN-OUT RESET REQUIREMENTS

Parameter

No.

Sym Characteristic Min Typ† Max Units Conditions

30 TmcL MCLR Pulse Width (low) 1 — — µs VDD = 5V, -40˚C to +125˚C 31 Twdt Watchdog Timer Time-out Period

(No Prescaler)

7* 18 33* ms VDD = 5V, -40˚C to +125˚C

32 Tost Oscillation Start-up Timer Period — 1024TOSC — — TOSC = OSC1 period 33 Tpwrt Power up Timer Period 28* 72 132* ms VDD = 5V, -40˚C to +125˚C 34 TIOZ I/O Hi-impedance from MCLR Low

or Watchdog Timer Reset

— — 1.1 µs

35 TBOR Brown-out Reset pulse width 100 — — µs 3.8V ≤ VDD ≤ 4.2V

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

VDD

MCLR

Internal

POR

PWRT

Time-out

OSC

Time-out

Internal

RESET

Watchdog

Timer

RESET

I/O Pins

Note: Refer to Figure 11-1 for load conditions.

VDD

BVDD

PIC16C71X

DS30272A-page 98  1997 Microchip Technology Inc.

Applicable Devices 710 71 711 715

FIGURE 11-6: TIMER0 EXTERNAL CLOCK TIMINGS

TABLE 11-5: TIMER0 EXTERNAL CLOCK REQUIREMENTS

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20* — — ns Must also meet

parameter 42

With Prescaler 10* — — ns

41 Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20* — — ns

Must also meet parameter 42

With Prescaler 10* — — ns

42 Tt0P T0CKI Period Greater of:

20 ns or TCY + 40* N

— — ns N = prescale value

(2, 4,..., 256)

48 Tcke2tmrI Delay from external clock edge to timer increment 2Tosc — 7Tosc —

* These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note: Refer to Figure 11-1 for load conditions.

RA4/T0CKI

TMR0

 1997 Microchip Technology Inc. DS30272A-page 99

PIC16C71X

Applicable Devices 710 71 711 715

TABLE 11-6: A/D CONVERTER CHARACTERISTICS:

PIC16C710/711-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C710/711-10 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C710/711-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LC710/711-04 (COMMERCIAL, INDUSTRIAL, EXTENDED)

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

A01 NR Resolution — — 8-bits bit VREF = VDD, VSS ≤ AIN ≤ VREF A02 EABS Absolute error

— —

< ± 1 LSb

VREF = VDD, VSS ≤ AIN ≤ VREF

A03 EIL Integral linearity error — —

< ± 1 LSb

VREF = VDD, VSS ≤ AIN ≤ VREF

A04 EDL Differential linearity error — —

< ± 1 LSb

VREF = VDD, VSS ≤ AIN ≤ VREF

A05 EFS Full scale error — —

< ± 1 LSb

VREF = VDD, VSS ≤ AIN ≤ VREF

A06 EOFF Offset error — —

< ± 1 LSb

VREF = VDD, VSS ≤ AIN ≤ VREF

A10 — Monotonicity — guaranteed — — VSS ≤ VAIN ≤ VREF A20 VREF Reference voltage 2.5V — VDD + 0.3 V A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V A30 ZAIN Recommended impedance of

analog voltage source

— — 10.0 kΩ

A40 IAD A/D conversion current (VDD) — 180 — µA Average current consumption

when A/D is on. (Note 1)

A50 IREF VREF input current (Note 2) 10

—

1000

µAµADuring VAIN acquisition.

Based on differential of VHOLD to VAIN. To charge CHOLD see Section 7.1. During A/D Conversion cycle

* These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

Note 1: When A/D is off, it will not consume any current other than minor leakage current.

The power-down current spec includes any such leakage from the A/D module.

2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.

PIC16C71X

DS30272A-page 100  1997 Microchip Technology Inc.

Applicable Devices 710 71 711 715

FIGURE 11-7: A/D CONVERSION TIMING

TABLE 11-7: A/D CONVERSION REQUIREMENTS

Param

No.

Sym Characteristic Min Typ† Max Units Conditions

130 TAD A/D clock period PIC16C710/711 1.6 — — µs TOSC based, VREF ≥ 3.0V

PIC16LC710/711 2.0 — — µs TOSC based, VREF full range PIC16C710/711 2.0* 4.0 6.0 µs A/D RC mode PIC16LC710/711 3.0* 6.0 9.0 µs A/D RC mode

131 TCNV Conversion time

(not including S/H time). (Note 1)

— 9.5 — TAD

132 TACQ Acquisition time Note 25*20

—

µs

µs The minimum time is the ampliﬁer

settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 19.5 mV @

5.12V) from the last sampled voltage (as stated on CHOLD).

134 TGO Q4 to AD clock start — TOSC/2§ — — If the A/D clock source is selected as

RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.

135 TSWC Switching from convert → sample time 1.5§ — — TAD

* These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not

tested.

§ This speciﬁcation ensured by design.

Note 1: ADRES register may be read on the following TCY cycle.

2: See Section 7.1 for min conditions.

131

130

132

BSF ADCON0, GO

A/D CLK

A/D DATA

ADRES

ADIF

SAMPLE

OLD_DATA

SAMPLING STOPPED

DONE

NEW_DATA

OSC/2)

(1)

7 6 5 4 3 2 1 0

Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the

SLEEP instruction to be executed.

1 Tcy

Microchip Technology Inc PIC16C71-04-P, PIC16C71-04I-P, PIC16C71-04I-SO, PIC16C710-20-SO, PIC16C710-20I-P Datasheet

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