2000 Microchip Technology Inc. DS21173E-page 1
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current (typical)
- 1 µA standby current (maximum)
• 128 x 8 bit organization (93LC46A)
• 64 x 16 bit organization (93LC46B)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial interface
• Device status signal during ERASE/WRITE
cycles
• Sequential READ function
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP/SOIC and 8-pin TSSOP packages
• Available for the following temperature ranges:
BLOCK DIAGRAM
DESCRIPTION
The Microchip Technology Inc. 93LC46AX/BX are 1Kbit, low voltage serial Electrically Erasable PROMs.
The device memory is configured as x8 (93LC46A) or
x16 bits (93LC46B). Advanced CMOS technology
makes these devices ideal for low power nonvolatile
memory applications. The 93LC46AX/BX is available
in standard 8-pin DIP, 8-pin surface mount SOIC, and
TSSOP packages. The 93LC46 AX/BX are of fered only
in a 150-mil SOIC package.
PACKAGE T YPE
- Commercial (C): 0°C to +70°C
- Industrial (I): -40°C to +85°C
Vcc
Vss
DI
CS
CLK
DO
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
COUNTER
DATA
REGISTER
OUTPUT
BUFFER
MODE
DECODE
CLOCK
GENERATOR
LOGIC
93LC46A/B
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
Vcc
NC
NC
Vss
CS
CLK
DI
DO
V
CC
NC
NC
Vss
93LC46A/B
NC
Vcc
CS
CLK
NC
Vss
DO
DI
93LC46AX/BX
93LC46A/B
CS
CLK
DI
DO
1
2
3
4
8
7
6
5
Vcc
NC
NC
Vss
TSSOP
SOICSOIC
1
2
3
4
DIP
8
7
6
5
1
2
3
4
8
7
6
5
Microwire is a registered trademark of National Semiconductor Incorporated.
93LC46A/B
1K 2.5V Microwire
®
Serial EEPROM
93LC46A/B
DS21173E-page 2 2000 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
1.1 Maximum Ratings*
Vcc...................................................................................7.0V
All inputs and outputs w.r.t. Vss ...............-0.6V to Vcc +1.0V
Storage temperature.....................................-65°C to +150°C
Ambient temp. with power applied................-65°C to +125 °C
Soldering temperature of leads (10 seconds) .............+300°C
ESD protection on all pins.................................. ..............4 kV
*Notice: Stresses abov e those listed under “Maximum ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicat ed in th e o per ati o nal li st ings of this specification i s
not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-1 PIN FUNCTION TABLE
Name Function
CS Chip Select
CLK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
VSS Ground
NC No Connect
V
CC Power Supply
TABLE 1-2 DC AND AC ELECTRICAL CHARACTERISTICS
All parameters apply over the specified
operating ranges unless otherwise
noted
Commercial (C): VCC = +2.5V to +6.0V Tamb = 0°C to +70°C
Industrial (I): V
CC = +2.5V to +6.0V Tamb = -40°C to +85°C
Parameter Symbol Min. Max. Units Conditions
High level input voltage
V
IH12.0Vcc +1 V2.7V < VCC ≤ 6.0 V (Note 2)
V
IH2 0.7 VCC Vcc +1 V VCC < 2.7V
Low level input voltage
V
IL1-0.3 0.8 VVCC > 2.7V (Note 2)
V
IL2 -0.3 0.2 Vcc V VCC < 2.7V
Low level output voltage
V
OL1 — 0.4 V IOL = 2.1 mA; Vcc = 4.5V
V
OL2 — 0.2 V IOL =100 µA; Vcc = Vcc Min.
High level output voltage
V
OH12.4 — VIOH = -400 µA; Vcc = 4.5V
V
OH2VCC-0.2 — VIOH = -100 µA; Vcc = Vcc Min.
Input leakage current I
LI -10 10 µA VIN = VSS to Vcc
Output leakage current I
LO -10 10 µA VOUT = VSS to Vcc
Pin capacitance
(all inputs/outputs)
C
IN, COUT — 7pF
V
IN/VOUT = 0 V (Notes 1 & 2)
Tamb = +25°C, F
CLK = 1 MHz
Operating current
I
CC write — 1.5 mA
I
CC read
— 1
500
mA
µA
F
CLK = 2 MHz; Vcc = 6.0V
F
CLK = 1 MHz; Vcc = 3.0V
Standby current I
CCS — 1 µA CS = Vss; DI = VSS
Clock frequency FCLK —
2
1
MHz
MHz
V
CC > 4.5V
V
CC < 4.5V
Clock high time T
CKH 250 — ns
Clock low time T
CKL 250 — ns
Chip select setup time T
CSS 50 — ns Relative to CLK
Chip select hold time T
CSH 0 — ns Relative to CLK
Chip select low time T
CSL 250 — ns
Data input setup time T
DIS 100 — ns Relative to CLK
Data input hold time T
DIH 100 — ns Relative to CLK
Data output delay time T
PD — 400 ns CL = 100 pF
Data output disable time T
CZ — 100 ns CL = 100 pF (Note 2)
Status valid time T
SV — 500 ns CL = 100 pF
Program cycle time
T
WC — 6msERASE/WRITE mode
T
EC — 6 ms ERAL mode
T
WL — 15 ms WRAL mode
Endurance — 1M — cycles 25°C, V
CC = 5.0V, Block Mode (Note 3)
Note 1: This parameter is tested at Tamb = 25°C and Fclk = 1 MHz.
2: This parameter is periodically sampled and not 100% tested.
3: This application is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total
Endurance Model which may be obtained on our website.
93LC46A/B
2000 Microchip Technology Inc. DS21173E-page 3
2.0 PIN DESCRIPTION
2.1 Chip Select (CS)
A high level selects the device; a low level deselects
the device and forc es it into s tandb y mod e. How ever, a
programming cycle wh ic h is al read y i n progress will be
completed, regardless of the Chip Select (CS) input
signal. If CS is brou gh t l ow duri ng a p rogra m c yc le, th e
device will go into stand by mode as soon as the programming cycle is completed.
CS must be low for 250 ns minimum (T
CSL) between
consecutive instructions. If CS is low, the internal control logic is held in a RESET status.
2.2 Serial Clock (CLK)
The Serial Clock is used to synchronize the communication between a master device and the 93LC46AX/
BX. Opcodes, address, and data bits are clocked in on
the positive edge o f CLK. Data bits are also c locked out
on the positive edge of CL K.
CLK can be stopped anywhere in the transmission
sequence (at high or low level) and can be continued
anytime with respect to clock high time (T
CKH) and
clock low time (T
CKL). This gives the controlling master
freedom in preparing opcode, address, and data.
CLK is a “Don't Care” if CS is low (device deselected).
If CS is high, but the START condition has not been
detected, an y number of clock cy cles ca n be rec eived
by the device without changing its status (i.e., waiting
for a START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a START condition the sp ecified number of clock cycles (respectively low to high transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
data bits before an instruction is executed (Table 2-1
and Table 2-2). CLK and DI then become don't care
inputs waiting for a new START condition to be
detected.
2.3 Data In (DI)
Data In (DI) is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
2.4 Data Out (DO)
Data Out ( DO) is used in the READ mode to outpu t
data synchronously with the CLK input (T
PD after the
positive edge of CLK).
This pin also provides READY/BUSY
status information during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought high after being low for minimum chip select
low time (TCSL) and an ERASE or WRITE operation
has been initiated.
The status signal is not available on DO, if CS is held
low during th e entire ERASE or W RITE cycle. In this
case, DO is in the HIGH-Z mode. If status is checked
after the ERASE/WRITE cycle, the da ta line will be hig h
to indicate the device is ready.
TABLE 2-1 INSTRUCTION SET FOR 93LC46A
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE
1 11 A6 A5 A4 A3 A2 A1 A0 — (RDY/BSY)10
ERAL
1 00 10XXXXX — (RDY /BSY)10
EWDS
1 00 00XXXXX — HIGH-Z 10
EWEN
1 00 11XXXXX — HIGH-Z 10
READ
1 10 A6 A5 A4 A3 A2 A1 A0 — D7 - D0 18
WRITE
1 01 A6 A5 A4 A3 A2 A1 A0 D7 - D0 (RDY/BSY)18
WRAL
1 00 0 1 X X X X X D7 - D0 (RDY/BSY)18
TABLE 2-2 INSTRUCTION SET FOR 93LC46B
Instruction SB Opcode Address Data In Data Out Req. CLK Cycles
ERASE
1 11 A5 A4 A3 A2 A1 A0 — (RDY/BSY)9
ERAL
1 00 10XXXX — (RDY/BSY)9
EWDS
1 00 00XXXX — HIGH-Z 9
EWEN
1 00 11XXXX — HIGH-Z 9
READ
1 10 A5 A4 A3 A2 A1 A0 — D15 - D0 25
WRITE
1 01 A5 A4 A3 A2 A1 A0 D15 - D0 (RDY/BSY)25
WRAL
1 00 0 1 X X X X D15 - D0 (RDY/BSY)25
93LC46A/B
DS21173E-page 4 2000 Microchip Technology Inc.
3.0 FUNCTIONAL DESCRIPTION
Instructions, add resses, and wri te data are cl ocked into
the DI pin on the rising e dge of the clock (CLK ). The DO
pin is normally held in a HIGH-Z state except when
reading data from the device, or when checking the
READY/BUSY
status during a programming operation.
The READY/BUSY
status can be verified during an
ERASE/WRITE operation by polling the DO pin; DO
low indicates that programming is still in progress,
while DO high ind icates the devic e is ready . Th e DO will
enter the HIGH-Z state on the falling edge of the CS.
3.1 START Condition
The START bit is detected by the device if CS and DI
are both high with respect to the positive edge of CLK
for the first time.
Before a ST ART condi tion is detected, CS, CLK, and DI
may change in any combination (except to that of a
ST ART co ndition), w ithout re sulting i n any devic e operation (ERASE, ERAL, EWDS, EWEN, READ, WRITE,
and WRAL). As soon as CS is high, the device is no
longer in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcodes,
addresses, and data bits for any parti cular instructio n is
clocked in.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don’t care bits un til a new START condition is
detected.
3.2 Data In (DI) and Data Out (DO)
It is possible to connect the Data In (DI) and Data Out
(DO) pins together. However, with this configuration, if
A0 is a logic-high level, it is possible for a “bus c onflict”
to occur during the “dummy zero” that precedes the
READ operati on. Under such a co ndition the volta ge
level seen at DO is und efined an d will depend u pon the
relative impedances of DO and the signal source driving A0. The higher the cu rrent sourcing c apability of A0,
the higher the voltage at the DO pin.
3.3 Data Protection
During power-up, all programming modes of operation
are inhibited until Vc c has reac hed a level greater than
2.2V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
Vcc has fallen below 2.2V at nominal co nditions.
The ERASE/WRITE Disable (EWDS) and ERASE/
WRITE Enable (EWDS) commands give additional
protection against accidentally programming during
normal operation.
FIGURE 3-1: SYNCHRONOUS DATA TIMING
CS
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
CLK
DI
DO
(READ)
DO
(PROGRAM)
T
CSS
TDIS
TCKH
TCKL
TDIH
TPD
TCSH
TPD
TCZ
STATUS VALID
TSV
TCZ
Note: AC Test Conditions: VIL = 0.4V, VIH = 2.4V
93LC46A/B
2000 Microchip Technology Inc. DS21173E-page 5
3.4 ERASE
The ERASE instruction forces all data bits of the specified address to the logical “1” state. CS is brought low
following the loa din g of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle.
The DO pin indicates the READY/BUSY
status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction.
3.5 Erase All (ERAL)
The Erase All (ERAL) instruction will erase the entire
memory array to the logical “1” state. The ERAL cycle
is identical to the ERASE c yc le, exce pt f or th e d ifferent
opcode. The ERAL cycle is completely self-timed and
commences at the falling edge of the CS. Clocking of
the CLK pin is not necessary after the device has
entered the ERAL cycle.
The DO pin indicates the READY/BUSY
status of the
device, if CS is brough t high a fter a mi nimum of 250 n s
low (T
CSL) and before the entire ERAL cycle is com-
plete.
FIGURE 3-2: ERASE TIMING
FIGURE 3-3: ERAL TIMING
CS
CLK
DI
DO
T
CSL
CHECK STATUS
1
1
1A
N
AN-1 AN-2
•••
A0
T
SV TCZ
BUSY READY
HIGH-Z
T
WC
HIGH-Z
CS
CLK
DI
DO
T
CSL
CHECK STATUS
100 10X
•••
X
T
SV TCZ
BUSY READY
HIGH-Z
T
EC
HIGH-Z
Guaranteed at Vcc = 4.5V to +6.0V.
93LC46A/B
DS21173E-page 6 2000 Microchip Technology Inc.
3.6 ERASE/WRITE Disable and Enable
(EWDS/EWEN)
The 93LC46A/B powers up in the ERASE/WRITE Disable (EWDS) sta te. All programming mo des must be
preceded by an ERASE/WRITE Enable (EWEN)
instruction. Once the EWEN instruction is executed,
programming remains enabled until an EWDS instruction is executed or Vcc is removed from the device. To
protect against accidenta l data disturb ance, the EWDS
instruction can be used to disable all ERASE/WRITE
functions and should follow all programming operations. Execution of a READ instruction is independent
of both the EWEN and EWDS instructions.
3.7 READ
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 8-bit (93LC46A) or 16-bit
(93LC46B) output string. The output data bits will toggle on the rising edge of the CLK and are stable after
the specified time delay (T
PD). Sequential read is pos-
sible when CS is held hi gh. Th e memory data wi ll aut omatically cycle to the next register and output
sequentially.
FIGURE 3-4: EWDS TIMING
FIGURE 3-5: EWEN TIMING
FIGURE 3-6: READ TIMING
CS
CLK
DI
10
000X
•••
X
T
CSL
1X
CS
CLK
DI
00 1 1X
TCSL
•••
CS
CLK
DI
DO
110
An
••• A0
HIGH-Z
0Dx
•••
D0 Dx
•••
D0
•••
Dx D0
93LC46A/B
2000 Microchip Technology Inc. DS21173E-page 7
3.8 WRITE
The WRITE instruction i s f oll owed by 8 bits (93LC46A)
or 16 bits (93LC46B) of data which are written into the
specified address. After the la st data bit is put on the DI
pin, the falling edge of CS initiates the self-timed autoerase and programming cycle.
The DO pin indicates the READY/BUSY
status of the
device, if CS is broug ht high a fter a mi nimum of 250 n s
low (T CSL) and before th e entire w rite cycle i s complet e.
DO at logical “0” indicates that programming is still in
progress. DO at logical “1” indicates that the register at
the specified address has been written with the data
specified and the device is ready for another instruction.
3.9 Write All (WRAL)
The Write All (WRAL) instruction will write the entire
memory array with the data specified in the command.
The WRAL cycle is completely self-timed and commences at the falling edge of the CS. Clocking of the
CLK pin is not necessary after the device has entered
the WRAL cycle. The WRAL comm and does include an
automatic ERAL cycle for the device. Therefore, the
WRAL instruction does not req uire an ERAL instruct ion
but the chip must be in the EWEN status.
The DO pin indicates the READY/BUSY
status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL).
FIGURE 3-7: WRITE TIMING
FIGURE 3-8: WRAL TIMING
CS
CLK
DI
DO
1
0
1An
•••
A0 Dx
•••
D0
BUSY
READY
HIGH-Z
HIGH-Z
Twc
T
CSL
TCZ
TSV
CS
CLK
DI
DO
HIGH-Z
1
0
0
01X
•••
X
Dx
•••
D0
HIGH-Z
BUSY
READY
T
WL
Guaranteed at Vcc = 4.5V to +6.0V.
TCSL
TSV
TCZ
93LC46A/B
DS21173E-page 8 2000 Microchip Technology Inc.
NOTES:
93LC46A/B
2000 Microchip Technology Inc. DS21173E-page 9
NOTES:
93LC46A/B
DS21173E-page 10 2000 Microchip Technology Inc.
NOTES:
93LC46A/B
2000 Microchip Technology Inc. DS21173E-page 11
93LC46A/B PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
Package:
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
SM = Plastic SOIC (208 mil Body), 8-lead
ST = TSSOP , 8-le ad
Temperature Blank = 0
°C to +70°C
Range: I =-40°C to +85°C
Device:
93LC46A 1K Microwire Serial EEPROM (x8)
93LC46AT 1K Microwire Serial EEPROM (x8)
Tape and Reel
93LC46AX 1K Microwire Serial EEPROM (x8)
in alternate pinout (SN only)
93LC46AXT 1K Microwire Serial EEPROM (x8)
in alternate pinout, Tape and Reel (SN only)
93LC46B 1K Microwire Serial EEPROM (x16)
93LC46BT 1K Microwire Serial EEPROM (x16)
Tape and Reel
93LC46BX 1K Microwire Serial EEPROM (x16)
in alternate pinout (SN only)
93LC46BXT 1K Microwire Serial EEPROM (x16)
in alternate pinout, Tape and Reel (SN only)
93LC46A/B — /P
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
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Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by
updates. It is your respo nsibilit y to en sure t hat you r app licatio n mee ts with y our sp ecifica tions. N o re presen tation or warra nty is given and n o liability is
assumed by Micro chip Technology Incorporate d with respe ct t o the accur acy or u se of such infor mation, or infrin gemen t of patents or other in tellectua l
property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with
express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property righ ts. The Microchip lo go and name are reg istered tradema rks of Microchip Technology Inc. in the U.S.A. and other countries. All rights
reserved. All other trademarks mentioned herein are the property of their respective companies.
DS21173E-page 12 2000 Microchip Technology Inc.
All rights reserved. © 2001 Microchip Technology Incorporated. Printed in the USA. 2/01 Printed on recycled paper.
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Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro
®
8-bit MCUs, KEELOQ
®
code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 certified.
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