Microchip Technology Inc 24LCS52T-I-ST, 24LCS52T-I-SN, 24LCS52T-I-P, 24LCS52T-ST, 24LCS52T-SN Datasheet
...
C
24LCS52
2
2K 2.5V I
C
Serial EEPROM with Software Write Protect
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10 µ A standby current typical at 5.5V
-5 µ A standby current typical at 3.0V
• Organized as a single block of 256 bytes (256 x 8)
• Software write protection for lower 128 bytes
• Hardware write protection for entire array
• 2-wire serial interface bus, I
• 100kHz (2.5V) and 400kHz (5V) compatibility
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 16 bytes
• 3.5 ms typical write cycle time for page-write
• 10,000,000 erase/write cycles guaranteed
• ESD protection >4,000V
• Data retention > 200 years
• 8-pin DIP, SOIC or TSSOP packages
• Available for extended temperature ranges
- Commercial (C): 0 ° C to +70 ° C
- Industrial (I): -40 ° C to +85 ° C
2
compatible
DESCRIPTION
The Microchip Technology Inc. 24LCS52 is a 2K bit
Electrically Erasable PROM capable of operation
across a broad voltage range (2.5V to 5.5V). This
device has a software write protect feature for the lower
half of the array, as well as an external pin that can be
used to write protect the entire array. The software write
protect feature is enabled by sending the device a special command, and once this feature has been enabled,
it cannot be reversed. In addition to the software protect feature, there is a WP pin that can be used to write
protect the entire array, regardless of whether the software write protect register has been written or not. This
allows the system designer to protect none, half or all of
the array, depending on the application. The device is
organized as a single block of 256 x 8-bit memory with
a 2-wire serial interface. Low voltage design permits
operation down to 2.5 volts with typical standby and
active currents of only 5 µ A and 1 mA respectively. The
device has a page-write capability for up to 16 bytes of
data. The device is available in the standard 8-pin DIP,
8-pin SOIC and TSSOP packages.
PACKA GE TYPES
PDIP/SOIC
A0
1
A1
2
A2
3
Vss
4
TSSOP
1
A0
2
A1
3
A2
Vss
4
BLOCK DIAGRAM
A0 A1 A2
I/O
Control
Logic
SDA
Vcc
Vss
SCL
WP
Memory
Control
Logic
24LCS52
24LCS52
XDEC
Vcc
8
WP
7
SCL
6
SDA
5
Vcc
8
WP
7
SCL
6
SDA
5
HV Generator
Software write
protected area
(00h-7Fh)
Standard
Array
Write Protect
Circuitry
YDEC
SENSE AMP
R/W CONTROL
2
I
C is a trademark of Philips Corporation.
1996 Microchip Technology Inc.
Preliminary
DS21166B-page 1
24LCS52
µ
µ
µ
µ
1.0 ELECTRICAL
TABLE 1-1: PIN FUNCTION TABLE
CHARACTERISTICS
1.1 Maxim
CC
V
...................................................................................7.0V
All inputs and outputs w.r.t. V
Storage temperature.....................................-65˚C to +150˚C
Ambient temp. with power applied................-65˚C to +125˚C
Soldering temperature of leads (10 seconds).............+300˚C
ESD protection on all pins............................................. ≥ 4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-2: DC CHARACTERISTICS
SCL and SDA pins:
High level input voltage
Low level input voltage V
Hysteresis of Schmitt trigger inputs V
Low level output voltage V
Input leakage current
All I/O pins I
WP pin I
Output leakage current I
Pin capacitance (all inputs/outputs) C
Operating current I
Standby current I
Note: This parameter is periodically sampled and not 100% tested.
um Ratings*
SS
............... -0.6V to V
Parameter Symbol Min. Max. Units Conditions
CC
+1.0V
A0, A1, A2
V
= +2.5V to +5.5V Commercial (C): Tamb = 0˚C to +70˚C
CC
V
IH
IL
HYS
OL
LI
LI
LO
IN
,
C
OUT
Write — 3 mA V
CC
I
CC
Read — 1 mA V
CCS
.7 V
CC
.05 V
CC
-10 10
-10 50
-10 10
—10pFV
—30
Name Function
SS
V
SDA
SCL
CC
V
Ground
Serial Address/Data I/O
Serial Clock
+2.5V to 5.5V Power Supply
Chip Selects
WP
Hardware Write Protect
Industrial (I): Tamb = -40˚C to +85˚C
V
CC
.3 V
V
— V (Note)
.40 V I
AV
A WP = V
AV
µ
AV
100
AV
OL
= 3.0 mA, V
= 0.1V to 5.5V, WP = Vss
IN
CC
= 0.1V to 5.5V
OUT
CC
= 5.0V (Note)
Tamb = 25˚C, F
= 5.5V, SCL = 400 kHz
CC
CC
= 5.5V, SCL = 400 kHz
= 3.0V, SDA = SCL = V
CC
CC
= 5.5V, SDA = SCL = V
CC
= 2.5V
CLK
= 1 MHz
CC
CC
FIGURE 1-1: BUS TIMING START/STOP
SCL
SU:STA
T
SDA
DS21166B-page 2
START STOP
THD:STA
Preliminary
VHYS
TSU:STO
1996 Microchip Technology Inc.
TABLE 1-3: AC CHARACTERISTICS
24LCS52
Parameter Symbol
Vcc = 2.5-5.5V
STD MODE
Vcc = 4.5 - 5.5V
FAST MODE
Units Remarks
Min. Max. Min. Max.
Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T
HIGH
HD
CLK
LOW
R
F
:
STA
— 100 — 400 kHz
4000 — 600 — ns
4700 — 1300 — ns
— 1000 — 300 ns
— 300 — 300 ns
(Note 1)
(Note 1)
4000 — 600 — ns After this period the first
clock pulse is generated
START condition setup time T
SU
STA
:
4700 — 600 — ns Only relevant for repeated
START condition
Data input hold time T
Data input setup time T
STOP condition setup time T
Output valid from clock T
Bus free time T
HD
SU
SU
:
:
:
AA
BUF
DAT
DAT
STO
0—0—ns
(Note 2)
250 — 100 — ns
4000 — 600 — ns
— 3500 — 900 ns
(Note 2)
4700 — 1300 — ns Time the bus must be free
before a new transmission
can start
Output fall time from V
minimum to V
IL
IH
maximum
Input filter spike suppression
T
OF
SP
T
— 250 20 +0.1 CB250 ns (Note 1), CB ≤ 100 pF
—50—50ns
(Note 3)
(SDA and SCL pins)
Write cycle time T
WR
Endurance 10M — 10M — cycles 25 ° C, V
— 10 — 10 ms Byte or Page mode
CC
= 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP
and V
specifications are due to new Schmitt trigger inputs which provide improved
HYS
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
FIGURE 1-2: BUS TIMING DATA
TF
TLOW
SCL
SDA
SDA
OUT
1996 Microchip Technology Inc.
SU:STA
T
IN
TSP
TAA
THD:STA
THD:STA
THIGH
THD:DAT TSU:DAT
TAA
Preliminary
TR
TSU:STO
TBUF
DS21166B-page 3
24LCS52
2.0 FUNCTIONAL DESCRIPTION
The 24LCS52 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24LCS52
works as slave. Both master and slave can operate as
transmitter or receiver but the master device determines which mode is activated.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a STAR T condition. All
commands must be preceded by a START condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
Note: The 24LCS52 does not generate any
acknowledge bits if an internal programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition.
3.6 Device Addressing
A control byte is the first byte received following the
START condition from the master device. The first part
of the control byte consists of a 4-bit control code which
is set to 1010 for normal read and write operations and
0110 for writing to the write protect register. The control
byte is followed by three chip select bits (A2, A1, A0).
The chip select bits allow the use of up to eight
24LCS52 devices on the same bus and are used to
determine which device is accessed. The chip select
bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the
device to respond. The device will not acknowledge if
you attempt a read command with the control code set
to 0110.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(A) (B) (C) (D) (A)(C)
SCL
SDA
START
CONDITION
DS21166B-page 4 Preliminary 1996 Microchip Technology Inc.
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
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