Microchip Technology Inc 24LC64-I-ST, 24LC64-I-SN, 24LC64-I-SM, 24LC64-I-P, 24LC64-E-ST Datasheet
...
M
2
64K I
DEVICE SELECTION TABLE
Part
Number
24AA64 1.8-5.5V 400 kHz
24LC64 2.5-5.5V 400 kHz
†
100 kHz for Vcc < 2.5V.
‡
100 kHz for E temperature range.
FEATURES
• Low power CMOS technology
- Maximum write current 3 mA at 5.5V
- Maximum read current 400 µ A at 5.5V
- Standby current 100 nA typical at 5.5V
• 2-wire serial interface bus, I
• Cascadable for up to eight devices
• Self-timed ERASE/WRITE cycle
• 32-byte page or byte write modes available
• 5 ms max write cycle time
• Hardware write protect for entire array
• Output slope control to eliminate ground bounce
• Schmitt trigger inputs for noise suppression
• 1,000,000 erase/write cycles guaranteed
• Electrostatic discharge protection > 4000V
• Data retention > 200 years
• 8-pin PDIP, SOIC (150 and 208 mil) and TSSOP
packages; 14-pin SOIC package
• Temperature ranges:
- Industrial (I): -40 ° C to +85 ° C
- Automotive (E) -40 ° C to +125 ° C
Vcc
Range
Max Clock
Frequency
2
C compatible
™
C
CMOS Serial EEPROM
Temp
Ranges
†
‡
I
I, E
24AA64/24LC64
P ACKA GE TYPE
PDIP
1
A0
2
A1
3
A2
4
Vss
SOIC
TSSOP
A0
A1
A2
SS
V
WP
Vcc
A0
A1
1
2
3
4
1
2
3
4
BLOCK DIAGRAM
A0…A2
WP
24xx64
24xx64
24xx64
8
7
6
5
8
7
6
5
8
7
6
5
Vcc
WP
SCL
SDA
VCC
WP
SCL
SDA
SCL
SDA
Vss
A2
HV GENERATOR
DESCRIPTION
I/O
The Microchip Technology Inc. 24AA64/24LC64
(24xx64*) is a 8K x 8 (64K bit) Serial Electrically Erasable PROM capable of operation across a broad voltage range (1.8V to 5.5V). It has been developed for
advanced, low power applications such as personal
communications or data acquisition. This device also
has a page-write capability of up to 32 bytes of data.
This device is capable of both random and sequential
reads up to the 64K boundary. Functional address lines
allow up to eight devices on the same bus , for up to 512
Kbits address space. This device is available in the
standard 8-pin plastic DIP, 8-pin SOIC (150 and
208 mil), and 8-pin TSSOP.
2
C is a trademark of Philips Corporation.
I
*24xx64 is used in this document as a generic part number for the 24AA64/24LC64 devices.
1998 Microchip Technology Inc. DS21189B-page 1
CONTROL
LOGIC
I/O
SDA
VCC
VSS
SCL
MEMORY
CONTROL
LOGIC
XDEC
EEPROM
ARRAY
PAGE LATCHES
YDEC
SENSE AMP
R/W CONTROL
24AA64/24LC64
≥
µ
µ
µ
1.0 ELECTRICAL
TABLE 1-1 PIN FUNCTION TABLE
CHARACTERISTICS
1.1 Maximum Ratings*
Vcc.................................................................................................7.0V
All inputs and outputs w.r.t. Vss...............................-0.6V to Vcc +1.0V
Storage temperature................................................... -65˚C to +150˚C
Ambient temp. with power applied............................... -65˚C to +125˚C
Soldering temperature of leads (10 seconds)........................... +300˚C
ESD protection on all pins........................................................... ≥ 4 kV
*Notice: Stresses above those listed under “Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at those or any other conditions
above those indicated in the operational listings of this specification is
not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
TABLE 1-2 DC CHARACTERISTICS
All parameters apply across the
recommended operating ranges
Industrial (I): V
Automotive (E): V
unless otherwise noted.
Parameter Symbol Min Max Units Conditions
A0, A1, A2,
SCL, SDA, and WP pins:
High level input voltage V
Low level input voltage V
Hysteresis of Schmitt Trigger
V
IH
IL
HYS
inputs (SDA, SCL pins)
Low level output voltage V
Input leakage current I
Output leakage current I
Pin capacitance
OL
LI
LO
IN
OUT
C
, C
(all inputs/outputs)
Operating current I
Standby current I
CC
Write — 3 mA V
CC
I
Read — 400
CCS
Note: This parameter is periodically sampled and not 100% tested.
CC
= +1.8V to 5.5V Tamb = -40 ° C to +85 ° C
= 4.5V to 5.5V Tamb = -40 ° C to 125 ° C
CC
0.7 V
CC
— 0.3 V
CC
0.05 V
— 0.40 V I
-10 10
-10 10
—10pFV
—1 µ A SCL = SDA = V
Name Function
A0,A1,A2 User Configurable Chip Selects
SS
V
Ground
SDA Serial Data
SCL Serial Clock
WP Write Protect Input
CC
V
+1.8 to 5.5V (24AA64)
+2.5 to 5.5V (24LC64)
—V
VVV
0.2 V
CC
CC
—VV
AV
AV
AV
2.5V
CC
V
CC
< 2.5V
CC
> 2.5V (Note)
OL
= 3.0 mA @ V
OL
I
= 2.1 mA @ V
IN
= Vss to V
V
= Vss or V
IN
OUT
= Vss to V
CC
= 5.0V (Note)
Tamb = 25˚C, f
CC
= 5.5V
CC
= 5.5V, SCL = 400 kHz
CC
, WP = V
, WP = V
CC
CC
= 1 MHz
c
CC
A0, A1, A2, WP = V
CC
CC
= 5.5V
SS
= 4.5V
= 2.5V
SS
CC
FIGURE 1-1: BUS TIMING DATA
TF
SCL
SDA
IN
SDA
OUT
WP
DS21189B-page 2
TSU:STA
TSP
TLOW
THD:STA
THIGH
THD:DAT TSU:DAT TSU:STO
TAA
(protected)
(unprotected)
VHYS
TR
TSU:WP
TBUF
THD:WP
1998 Microchip Technology Inc.
TABLE 1-3 AC CHARACTERISTICS
24AA64/24LC64
≤
≤
All parameters apply across the specified operating ranges unless otherwise noted.
Parameter Symbol Min Max Units Conditions
Clock frequency F
Clock high time THIGH 4000
Clock low time TLOW 4700
SDA and SCL rise time
(Note 1)
SDA and SCL fall time T
START condition hold time THD:STA 4000
START condition setup time TSU:STA 4700
Data input hold time THD:DAT 0 — ns (Note 2)
Data input setup time TSU:DAT 250
STOP condition setup time TSU:STO 4000
WP setup time TSU:WP 4000
WP hold time THD:WP 4700
Output valid from clock
(Note 2)
Bus free time: Time the bus must be
free before a new transmission can
start
Output fall time from VIH
minimum to VIL maximum
Input filter spike suppression
(SDA and SCL pins)
Write cycle time (byte or page) TWC —5
Endurance 1M — cycles 25°C, V
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but guaranteed b y characterization. F or endurance estimates in a specific application, please
consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.
SP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike
Industrial (I): V
Automotive (E): V
CLK
TR —
F — 300 ns (Note 1)
TAA —
TBUF 4700
TOF 10 250 ns CB ≤ 100 pF (Note 1)
TSP — 50 ns (Notes 1 and 3)
CC
= +1.8V to 5.5V Tamb = -40 ° C to +85 ° C
CC
= +4.5V to 5.5V Tamb = -40 ° C to 125 ° C
—
—
—
4000
600
4700
1300
—
—
4000
600
4700
600
250
100
4000
600
4000
600
4000
1300
—
—
4700
1300
100
100
400
—
—
—
—
—
—
1000
1000
300
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3500
3500
900
—
—
—
kHz 4.5V ≤ V
1.8V ≤ V
2.5V ≤ VCC ≤ 5.5V
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
ns 4.5V ≤ VCC ≤ 5.5V (E Temp range)
1.8V ≤ VCC ≤ 2.5V
2.5V ≤ VCC ≤ 5.5V
ms
CC
CC
CC = 5.0V, Block Mode (Note 4)
5.5V (E Temp range)
2.5V
1998 Microchip Technology Inc. DS21189B-page 3
24AA64/24LC64
2.0 PIN DESCRIPTIONS
2.1 A0, A1, A2 Chip Address Inputs
The A0,A1,A2 inputs are used by the 24xx64 for multiple device operation. The levels on these inputs are
compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight devices may be connected to the same b us
by using different chip select bit combinations. These
inputs must be connected to either V
CC or VSS.
2.2 SDA Serial Data
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an opendrain terminal, therefore, the SDA b us requires a pullup
resistor to V
400 kHz)
For normal data transfer SD A is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP conditions.
CC (typical 10 kΩ for 100 kHz, 2 kΩ for
2.3 SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.4 WP
This pin can be connected to either Vss, Vcc or left
floating. An internal pull-down resistor on this pin will
keep the device in the unprotected state if left floating.
If tied to Vss or left floating, normal memory operation
is enabled (read/write the entire memory 0000-1FFF).
If tied to V
operations are not affected.
CC, WRITE operations are inhibited. Read
3.0 FUNCTIONAL DESCRIPTION
The 24xx64 supports a bi-directional two-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data as a receiver. The bus must be controlled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions while the 24xx64
works as a slave. Both master and slav e can operate as
a transmitter or receiver but the master device determines which mode is activated.
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenev er the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1 Bus not Busy (A)
Both data and clock lines remain HIGH.
4.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condition.
4.3 Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must end with a STOP condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
4.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
Note: The 24xx64 does not generate any
acknowledge bits if an internal programming cycle is in progress.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LO W during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. During reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
case, the slave (24xx64) will leave the data line HIGH
to enable the master to generate the STOP condition.
DS21189B-page 4 1998 Microchip Technology Inc.
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