Microchip Technology Inc 24LC41-P Datasheet



1996 Microchip Technology Inc. DS21140B-page 1

FEATURES

• Single supply with operation down to 2.5V

• Completely implements DDC1  /DDC2  interface
for monitor identification

• Separate high speed 2-wire bus for
microcontroller access to 4K-bit Serial EEPROM

• Low power CMOS technology

• 2 mA active current typical

• 20 µ A standby current typical at 5.5V

• Dual 2-wire serial interface bus

• Hardware write-protect for both ports

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes (DDC port) or
16 bytes (4K Port)

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• 1,000,000 erase/write cycles guaranteed

• Data retention > 40 years

• 8-pin PDIP package

• Available for extended temperature ranges

DESCRIPTION

The Microchip Technology Inc. 24LC41 is a dual-port
128 x 8 and 512 x 8-bit Electrically Erasable PROM
(EEPROM). This device is designed for use in applica­tions requiring storage and serial transmission of con­figuration and control information. Three modes of
operation have been implemented:

• Transmit-Only Mode for the DDC Monitor Port

• Bi-directional Mode for the DDC Monitor Port

• Bi-directional, industry-standard 2-wire bus for the
4K Microcontroller Access Port

Upon power-up, the DDC Monitor Port will be in the
Transmit-Only Mode, repeatedly sending a serial bit
stream of the entire memory array contents, clocked by
the VCLK/DWP

pin. A valid high to low transition on the
DSCL pin will cause the device to enter the bi-direc­tional Mode, with byte-selectable read/write capability
of the memory array. The 4K-bit microcontroller port is
completely independent of the DDC port, therefore, it
can be accessed continuously by a microcontroller
without interrupting DDC transmission activity. The
24LC41 is available in a standard 8-pin PDIP package
in both commercial and industrial temperature ranges.

- Commercial (C): 0 ° C to +70 ° C

- Industrial (I): -40 ° C to +85 ° C

PACKA GE TYPE

BLOCK DIAGRAM

24LC41

DSCL

VCLK/DWP

VSS

MSDA

1
2

3

4

8
7

6

5

DSDA

VCC

MWP

MSCL

PDIP

EDID T able

1K Bit

4K Bit
Serial

EEPROM

MSDA

MSCL

MWP

DSDA

VCLK/DWP

DSCL

DDC Monitor Port

Microcontroller Access Port

24LC41

1K/4K 2.5V Dual Mode, Dual Port I

2

C



Serial EEPROM

DDC is a trademark of the Video Electronics Standards Association.
I

2

C is a trademark of Philips Corporation.

24LC41

DS21140B-page 2



1996 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maxim

um Ratings*

V

CC

...................................................................................7.0V

All inputs and outputs w.r.t. V

SS

............... -0.6V to V

CC

+1.0V

Storage temperature.....................................-65˚C to +150˚C

Ambient temp. with power applied................-65˚C to +125˚C

Soldering temperature of leads (10 seconds).............+300˚C

ESD protection on all pins ..................................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name Function

DSCL Serial Clock for DDC Bi-directional

Mode (DDC2)

DSDA Serial Address and Data I/O

(DDC Bus)

VCLK/DWP

Serial Clock for DDC transmit-only
mode (DDC1)/Write Protect

MSCL Serial clock for 4K-bit MCU port

MSDA Serial Address and Data I/O for

4K-bit MCU port

MWP Hardware write-protect for 4K-bit

MCU port

V

SS

Ground

V

CC

+2.5V to +5.5V power supply

TABLE 1-2: DC CHARACTERISTICS

V

CC

= +2.5V to 5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40˚C to +85˚C

Parameter Symbol Min Max Units Conditions

DSCL, DSDA, MSCL & MSDA pins:

High level input voltage
Low level input voltage

V

IH

V

IL

.7 V

CC

——.3 V

CC

V
V

Input levels on VCLK/DWP

pin:
High level input voltage
Low level input voltage

V

IH

V

IL

2.0
—.8.2 V

CC

VVV

CC

≥

2.7V (Note)

V

CC

< 2.7V (Note)

Hysteresis of Schmitt trigger inputs V

HYS

.05 V

CC

— V Note 1

Low level output voltage V

OL1

—.4VI

OL

= 3 mA, V

CC

= 2.5V (Note)

Low level output voltage V

OL2

—.6VI

OL

= 6 mA, V

CC

= 2.5V

Input leakage current I

LI

-10 10

µ

AV

IN

=.1V to V

CC

Output leakage current I

LO

-10 10

µ

AV

OUT

=.1V to V

CC

Pin capacitance (all inputs/outputs) C

IN

, C

OUT

—10pFV

CC

= 5.0V (Note),

Tamb = 25 ° C, F

CLK

= 1 MHz

Operating current I

CC

Write

I

CC

Read

—
—

3
1

mAmAV

CC

= 5.5V, DSCL or MSCL = 400

kHz

Standby current I

CCS

—
—

60

200

µ A µ

A

V

CC

= 3.0V, DSDA or MSDA =

DSCL or MSCL = V

CC

V

CC

= 5.5V, DSDA or MSDA =

DSCL or MSCL = V

CC

Note: This parameter is periodically sampled and not 100% tested.



1996 Microchip Technology Inc. DS21140B-page 3

24LC41

TABLE 1-3: AC CHARACTERISTICS (DDC MONITOR AND MICROCONTROLLER ACCESS

PORTS)

DDC Monitor Port (Bi-directional Mode) and Microcontroller Access Port

Parameter Symbol

Standard Mode

Vcc = 4.5 - 5.5V

Fast Mode

Units Remarks

Min Max Min Max

Clock frequency (DSCL and
MSCL)

F

CLK

— 100 — 400 kHz

Clock high time (DSCL and
MSCL)

T

HIGH

4000 — 600 — ns

Clock low time (DSCL and
MSCL)

T

LOW

4700 — 1300 — ns

DSCL, DSDA, MSCL &
MSDA rise time

T

R

— 1000 — 300 ns (Note 1)

DSCL, DSDA, MSCL &
MSDA fall time

T

F

— 300 — 300 ns (Note 1)

START condition hold time T

HD

:

STA

4000 — 600 — ns After this period the first

clock pulse is generated

START condition setup time T

SU

:

STA

4700 — 600 — ns Only relevant for repeated

START condition

Data input hold time T

HD

:

DAT

0 — 0 — ns (Note 2)

Data input setup time T

SU

:

DAT

250 — 100 — ns

STOP condition setup time T

SU

:

STO

4000 — 600 — ns

Output valid from clock T

AA

— 3500 — 900 ns (Note 2)

Bus free time T

BUF

4700 — 1300 — ns Time the bus must be free

before a new transmission
can start

Output fall time from V

IH

min to V

IL

max

T

OF

— 250 20 + .1

C

B

250 ns (Note 1), C

B

≤

100 pF

Input filter spike suppres­sion (DSCL, DSDA, MSCL
& MSDA pins)

T

SP

— 50 — 50 ns (Note 3)

Write cycle time T

WR

— 10 — 10 ms Byte or Page mode

DDC Monitor Port Transmit-Only Mode Parameters

Output valid from VCLK/
DWP

T

VAA

— 2000 — 1000 ns

VCLK/DWP

high time T

VHIGH

4000 — 600 — ns

VCLK/DWP

low time T

VLOW

4700 — 1300 — ns

Mode transition time T

VHZ

— 500 — 500 ns

Transmit-Only power up
time

T

VPU

0—0—ns

Endurance — 10M — 10M — cycles 25 ° C, Vcc = 5.0V, Block

Mode (Note 4)

Note 1: Not 100% tested. C

B

= total capacitance of one bus line in pF.

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of DSCL or MSCL to avoid unintended generation of START or ST OP
conditions.

3: The combined T

SP

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

noise and spike suppression. This eliminates the need for a T

I

specification for standard operation.

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific

application, please consult the Total Endurance Model which can be obtained on our BBS or website.

24LC41

DS21140B-page 4



1996 Microchip Technology Inc.

2.0 FUNCTIONAL DESCRIPTION

2.1 DDC Monitor P

ort

The DDC Monitor Port operates in two modes, the
Transmit-Only Mode and the bi-directional Mode. There
is a separate 2-wire protocol to support each mode,
each having a separate clock input and sharing a com­mon data line (DSDA). The device enters the Transmit­Only Mode upon power-up. In this mode, the device
transmits data bits on the DSDA pin in response to a
clock signal on the VCLK/DWP

pin. The device will
remain in this mode until a valid high to low transition is
placed on the DSCL input. When a valid transition on
DSCL is recognized, the device will switch into the bi­directional Mode. The only way to switch the device
back to the Transmit-Only Mode is to remove power
from the device.

2.1.1 TRANSMIT-ONLY MODE
The device will power up in the Transmit-Only Mode.

This mode supports a unidirectional 2-wire protocol for
transmission of the contents of the memory array. This
device requires that it be initialized prior to valid data
being sent in the Transmit-Only Mode (Section 2.1.2).

In this mode, data is transmitted on the DSDA pin in 8­bit bytes, each followed by a ninth, null bit (Figure 2-1).
The clock source for the Transmit-Only Mode is pro­vided on the VCLK/DWP

pin, and a data bit is output on
the rising edge on this pin. The eight bits in each byte
are transmitted by most significant bit first. Each byte
within the memory array will be output in sequence.
When the last byte in the memory array is transmitted,
the output will wrap around to the first location and con­tinue. The bi-directional Mode Clock (DSCL) pin must
be held high for the device to remain in the Transmit­Only Mode.

2.1.2 INITIALIZATION PROCEDURE
After V

CC

has stabilized, the device will be in the Trans­mit-Only Mode. Nine clock cycles on the VCLK/DWP
pin must be given to the device for it to perform internal
sychronization. During this period, the DSDA pin will be
in a high impedance state. On the rising edge of the
tenth clock cycle, the device will output the first valid
data bit which will be the most significant bit of a byte.
The device will power up at an indeterminate byte
address (Figure 2-2).

FIGURE 2-1: TRANSMIT-ONLY MODE

FIGURE 2-2: DEVICE INITIALIZATION

DSCL

DSDA

VCLK/DWP

TVAA TVAA

Bit 1 (LSB)

Null Bit

Bit 1 (MSB) Bit 7

TVLOWTVHIGH

TVAA TVAA

Bit 8 Bit 7High Impedance for 9 clock cycles

TVPU

12 891011

SCL

SDA

VCLK/DWP

Vcc