Microchip Technology Inc 24LC32A-MT Datasheet



1997 Microchip Technology Inc. DS21225A-page 1

M

24LC32A MODULE

FEATURES

• ISO 7816 compliant contact locations

• Single supply with operation down to 2.5V

- Maximum write current 3 mA at 6.0V

- Maximum read current 150 µ A at 6.0V

- Standby current 1 µ A max at 2.5V

• Two wire serial interface bus, I

2

C 

compatible

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• Self-timed ERASE and WRITE cycles

• Power on/off data protection circuitry

• 1,000,000 ERASE/WRITE cycles guaranteed

• 32 byte page or byte write modes available

• Schmitt trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 2 ms typical write cycle time, byte or page

• Electrostatic discharge protection > 4000V

• Data retention > 200 years

• 8-pin PDIP and SOIC packages

• Temperature ranges:

DESCRIPTION

The Microchip Technology Inc. 24LC32A is a 4K x 8
(32K bit) Serial Electrically Erasable PROM in an ISO
micromodule for use in smart card applications. The
device has a page-write capability of up to 32 bytes.

ISO MODULE LAYOUT

BLOCK DIAGRAM

- Commercial: 0˚C to +70˚C

VSS

SDA

SCL

V

DD

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

VCC
VSS

I/O

32K I

2

C™ Serial EEPROM in ISO Micromodule

I

2

C is a trademark of Philips Corporation.

24LC32A MODULE

DS21225A-page 2



1997 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maxim

um Ratings*

V

CC

........................................................................7.0V

All inputs and outputs w.r.t. V

SS

......-0.6V to V

CC

+1.0V

Storage temperature ..........................-65˚C to +150˚C

Ambient temp. with power applied...... -65˚C to +125˚C

Soldering temperature of leads (10 seconds) ..+300˚C

ESD protection on all pins .....................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum Ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTIONS

Name Function

V

SS

Ground
SDA Serial Data
SCL Serial Clock
V

CC

+2.5V to 6.0V Power Supply

TABLE 1-2: DC CHARACTERISTICS

Vcc = +2.5V to 6.0V
Commercial (C):Tamb = 0˚C to +70 ° C

Parameter Symbol Min Typ Max Units Conditions

SCL and SDA pins:

High level input voltage V

IH

.7 V

CC

— V

Low level input voltage V

IL

— .3 Vcc V

Hysteresis of Schmitt Trigger
inputs

V

HYS

.05 V

CC

— V Note 1

Low level output voltage V

OL

— .40 V I

OL

= 3.0 mA @ V

CC

= 4.5V

I

OL

= 2.1 mA @ V

CC

= 2.5V

Input leakage current I

LI

-10 10

µ

A V

IN

= .1V to V

CC

Output leakage current I

LO

-10 10

µ

A V

OUT

= .1V to V

CC

Pin capacitance
(all inputs/outputs)

C

IN

,C

OUT

— 10 pF V

CC

= 5.0V (Note 1)

Tamb = 25˚C, f

c

= 1 MHz

Operating current I

CC

Write — 3 mA V

CC

= 6.0V

I

CC

Read — 400

µ

A V

CC

= 6.0V, SCL = 400Khz

Standby current I

CCS

— 1 µ A 5 µ A SCL = SDA = V

CC

= 5.0V

I

CCS

1 µ

A V

CC

= 2.5V (Note 1)

Note 1: This parameter is periodically sampled and not 100% tested.

24LC32A MODULE



1997 Microchip Technology Inc. DS21225A-page 3

FIGURE 1-1: BUS TIMING DATA

TABLE 1-3: AC CHARACTERISTICS

Parameter Symbol

Vcc = 2.5 - 6.0V

STD. MODE

Vcc = 4.5 - 6.0V

FAST MODE

Units Remarks

Min Max Min Max

Clock frequency F

CLK

— 100 — 400 kHz

Clock high time T

HIGH

4000 — 600 — ns

Clock low time T

LOW

4700 — 1300 — ns

SDA and SCL rise time T

R

— 1000 — 300 ns Note 1

SDA and SCL fall time T

F

— 300 — 300 ns Note 1

START condition hold
time

T

HD

:

STA

4000 — 600 — ns After this period the first clock pulse

is generated

START condition setup
time

T

SU

:

STA

4700 — 600 — ns Only relevant for repeated START

condition

Data input hold time T

HD

:

DAT

0 — 0 — ns

Data input setup time T

SU

:

DAT

250 — 100 — ns

STOP condition setup
time

T

SU

:

STO

4000 — 600 — ns

Output valid from clock T

AA

— 3500 — 900 ns Note 2

Bus free time T

BUF

4700 — 1300 — ns Time the bus must be free before a

new transmission can start

Output fall time from V

IH

min to V

IL

max

T

OF

— 250 20

+0.1C

B

250 ns Note 1, C

B

≤

100 pF

Input filter spike sup­pression (SDA and SCL
pins)

T

SP

— 50 — 50 ns Note 3

Write cycle time T

WR

— 5 — 5 ms Byte or Page mode

Note 1: Not 100% tested. C

B

= total capacitance of one bus line in pF.

2:

As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3:

The combined T

SP

and V

HYS

specifications are due to Schmitt trigger inputs which provide improved noise

and spike suppression. This eliminates the need for a Ti specification for standard operation.

SCL

SDA

IN

TSU:STA

SDA
OUT

THD:STA

TLOW

THIGH

TR

TBUFTAA

TAA

THD:DAT TSU:DAT TSU:STO

TSP

TF

24LC32A MODULE

DS21225A-page 4



1997 Microchip Technology Inc.

2.0 PIN DESCRIPTIONS

2.1 SD

A (Serial Data)

This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V

CC (typical 10KΩ for 100 kHz, 1KΩ for 400

kHz)
For normal data transfer SD A is allowed to change only

during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi­tions.

2.2 SCL (Serial Clock)

This input is used to synchronize the data transfer from
and to the device.

3.0 FUNCTIONAL DESCRIPTION

The 24LC32A supports a bidirectional two-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver . The bus must be con­trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions, while the 24LC32A
works as slave. Both master and slave can operate as
transmitter or receiver but the master device deter­mines which mode is activated.

24LC32A MODULE

 1997 Microchip Technology Inc. DS21225A-page 5

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus
is not busy.

• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (See Figure 4-1).

4.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

4.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi­tion.

4.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

4.4 Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.

4.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.

A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LO W during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur­ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
case, the slave (24LC32A) will lea ve the data line HIGH
to enable the master to generate the STOP condition.
(See Figure 4-2)

FIGURE 4-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

FIGURE 4-2: ACKNOWLEDGE TIMING

Note: The 24LC32A does not generate any

acknowledge bits if an internal program­ming cycle is in progress.

SCL

SDA

START

CONDITION

DATA OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

(A) (B) (D) (D) (C) (A)

SCL

987654321 1 2 3

Transmitter must release the SDA line at this point allowing the Receiver
to pull the SDA line low to acknowledge the previous eight bits of data.

Receiver must release the SDA line at this point
so the Transmitter can continue sending data.

Data from transmitter

Data from transmitter

SDA

Acknowledge

Bit