Microchip Technology Inc 24LC21-I-P, 24LC21-SN, 24LC21-P, 24LC21T-I-SN, 24LC21T-I-P Datasheet
C
24LC21
2
1K 2.5V Dual Mode I
C
Serial EEPROM
FEATURES
• Single supply with operation down to 2.5V
• Completely implements DDC1 /DDC2 interface for monitor identification
• Low power CMOS technology
- 1 mA active current typical
- 10 µ A standby current typical at 5.5V
• 2-wire serial interface bus, I
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Factory programming (QTP) available
• 1,000,000 erase/write cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
- Commercial (C): 0˚C to +70˚C
- Industrial (I): -40˚C to +85˚C
2
compatible
DESCRIPTION
The Microchip Technology Inc. 24LC21 is a 128 x 8 bit
Electrically Erasable PROM. This device is designed for
use in applications requiring storage and serial transmission of configuration and control information. Two
modes of operation have been implemented: Transmit
Only Mode and Bi-Directional Mode. Upon power-up,
the device will be in the Transmit Only Mode, sending a
serial bit stream of the entire memory array contents,
clocked by the VCLK pin. A valid high to low transition
on the SCL pin will cause the device to enter the
Bi-Directional Mode, with byte selectable read/write
capability of the memory array. The 24LC21 is available
in a standard 8-pin PDIP and SOIC package in both
commercial and industrial temperature ranges.
PACKA GE TYPES
PDIP
NC
1
NC
2
NC
3
V
4
SS
SOIC
1
2
3
4
V
NC
NC
NC
SS
BLOCK DIAGRAM
VCLK
I/O
CONTROL
LOGIC
SDA SCL
MEMORY
CONTROL
LOGIC
24LC21
24LC21
XDEC
8
VCC
7
VCLK
6
SCL
5
SDA
8
V
CC
7
VCLK
5
SCL
5
SDA
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
V
CC
VSS
DDC is a trademark of the Video Electronics StandarDs Association.
2
I
C is a trademark of Philips Corporation.
1996 Microchip Technology Inc. DS21095F-page 1
SENSE AMP
R/W CONTROL
24LC21
≥
µ
µ
µ A µ
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maxim
CC
V
...................................................................................7.0V
All inputs and outputs w.r.t. V
Storage temperature.....................................-65˚C to +150˚C
Ambient temp. with power applied................-65˚C to +125˚C
Soldering temperature of leads (10 seconds).............+300˚C
ESD protection on all pins ..................................................≥ 4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
um Ratings*
SS
............... -0.6V to V
CC
+1.0V
TABLE 1-1: PIN FUNCTION TABLE
TABLE 1-2: DC CHARACTERISTICS
CC
V
= +2.5V to 5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40˚C to +85˚C
Parameter Symbol Min Max Units Conditions
SCL and SDA pins:
High level input voltage
Low level input voltage
IH
V
V
IL
Input levels on VCLK pin:
High level input voltage
Low level input voltage
Hysteresis of Schmitt trigger inputs V
Low level output voltage V
Low level output voltage V
Input leakage current I
Output leakage current I
Pin capacitance (all inputs/outputs) C
Operating current I
Standby current I
I
CC
CC
V
V
IN
, C
Read
CCS
IH
IL
HYS
OL1
OL2
LI
LO
OUT
Write
Note 1: This parameter is periodically sampled and not 100% tested.
2: V
LCK
must be grounded.
CC
.7 V
—
.3 V
2.0
—
.2 V
.05 V
CC
—.4VI
—.6VI
-10 10
-10 10
—10pFV
—
—
—
—
Name Function
V
SS
Ground
SDA Serial Address/Data I/O
SCL Serial Clock (Bi-Directional Mode)
VCLK Serial Clock (Transmit-Only Mode)
V
CC
+2.5V to 5.5V Power Supply
NC No Connection
—
CC
.8
CC
V
V
V
V
CC
V
2.7V (Note 1)
CC
V
< 2.7V (Note 1)
— V (Note 1)
OL
= 3 mA, V
= 6 mA, V
OL
AV
AV
IN
= .1V to V
= .1V to V
OUT
CC
= 5.0V (Note1),
Tamb = 25 ° C, F
3
mAmAV
= 5.5V, SCL = 400 kHz
CC
CC
= 2.5V (Note 1)
= 2.5V
CC
CC
CC
CLK
= 1 MHz
1
30
100
A
CC
V
= 3.0V, SDA = SCL = V
V
= 5.5V, SDA = SCL = V
CC
(Note 2)
CC
CC
DS21095F-page 2
1996 Microchip Technology Inc.
TABLE 1-3: AC CHARACTERISTICS
≤
24LC21
Parameter Symbol
Standard Mode
Vcc= 4.5 - 5.5V
Fast Mode
Units Remarks
Min Max Min Max
Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T
HD
CLK
HIGH
LOW
R
F
STA
:
— 100 — 400 kHz
4000 — 600 — ns
4700 — 1300 — ns
— 1000 — 300 ns (Note 1)
— 300 — 300 ns (Note 1)
4000 — 600 — ns After this period the first clock
pulse is generated
START condition setup
time
Data input hold time T
Data input setup time T
STOP condition setup time T
Output valid from clock T
Bus free time T
T
SU
:
4700 — 600 — ns Only relevant for repeated
STA
START condition
HD
DAT
SU
SU
:
:
STO
:
AA
BUF
DAT
0 — 0 — ns (Note 2)
250 — 100 — ns
4000 — 600 — ns
— 3500 — 900 ns (Note 2)
4700 — 1300 — ns Time the bus must be free
before a new transmission
can start
Output fall time from V
min to V
IL
max
Input filter spike suppres-
IH
OF
T
SP
T
— 250 20 + .1
B
C
250 ns (Note 1), C
— 50 — 50 ns (Note 3)
B
100 pF
sion (SDA and SCL pins)
Write cycle time T
WR
— 10 — 10 ms Byte or Page mode
Transmit-Only Mode Parameters
Output valid from VCLK T
VCLK high time T
VCLK low time T
Mode transition time T
Transmit-Only power up
VAA
VHIGH
VLOW
VHZ
T
VPU
— 2000 — 1000 ns
4000 — 600 — ns
4700 — 1300 — ns
— 500 — 500 ns
0—0—ns
time
Endurance — 10M — 10M — cycles 25 ° C, Vcc = 5.0V , Block Mode
(Note 4)
= total capacitance of one bus line in pF.
Note 1: Not 100% tested. C
B
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (min-
imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
noise and spike suppression. This eliminates the need for a T
SP
and V
HYS
specifications are due to new Schmitt trigger inputs which provide improved
specification for standard operation.
I
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
1996 Microchip Technology Inc. DS21095F-page 3
24LC21
2.0 FUNCTIONAL DESCRIPTION
The 24LC21 operates in two modes, the Transmit-Only
Mode and the Bi-Directional Mode. There is a separate
two wire protocol to support each mode, each having a
separate clock input and sharing a common data line
(SDA). The device enters the Transmit-Only Mode upon
power-up. In this mode, the device transmits data bits
on the SDA pin in response to a clock signal on the
VCLK pin. The device will remain in this mode until a
valid high to low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the Bi-Directional Mode. The only
way to switch the device back to the Transmit-Only
Mode is to remove power from the device.
2.1 T
The device will power up in the Transmit-Only Mode.
This mode supports a unidirectional two wire protocol
for transmission of the contents of the memory array.
This device requires that it be initialized prior to valid
data being sent in the Transmit-Only Mode (see Initialization Procedure, below). In this mode, data is transmitted on the SDA pin in 8 bit bytes, each followed by a
FIGURE 2-1: TRANSMIT ONLY MODE
ransmit-Only Mode
ninth, null bit (see Figure 2-1). The clock source for the
Transmit-Only Mode is provided on the VCLK pin, and
a data bit is output on the rising edge on this pin. The
eight bits in each byte are transmitted most significant
bit first. Each byte within the memory array will be output in sequence. When the last byte in the memory
array is transmitted, the output will wrap around to the
first location and continue. The Bi-Directional Mode
Clock (SCL) pin must be held high for the device to
remain in the Transmit-Only Mode.
2.2 Initialization Pr
After V
mit-Only Mode. Nine clock cycles on the VCLK pin must
be given to the device for it to perform internal synchronization. During this period, the SDA pin will be in a high
impedance state. On the rising edge of the tenth clock
cycle, the device will output the first valid data bit which
will be the most significant bit of a byte. The device will
power up at an indeterminate byte address. (See
Figure 2-2).
has stabilized, the device will be in the Trans-
CC
ocedure
SCL
TVAA TVAA
SDA
BIT 1 (LSB)
VCLK
TVLOWTVHIGH
FIGURE 2-2: DEVICE INITIALIZATION
VCC
SCL
SDA
TVPU
NULL BIT
BIT 1 (MSB) BIT 7
TVAA TVAA
BIT 8BIT 7HIGH IMPEDANCE FOR 9 CLOCK CYCLES
VCLK
DS21095F-page 4
12 891011
1996 Microchip Technology Inc.
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