Datasheet 24LC21-I-P, 24LC21-SN, 24LC21-P, 24LC21T-I-SN, 24LC21T-I-P Datasheet (Microchip Technology Inc)



C 

24LC21

2

1K 2.5V Dual Mode I



C

Serial EEPROM

FEATURES

• Single supply with operation down to 2.5V

• Completely implements DDC1  /DDC2  inter­face for monitor identification

• Low power CMOS technology

- 1 mA active current typical

- 10 µ A standby current typical at 5.5V

• 2-wire serial interface bus, I

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 8 bytes

• 100 kHz (2.5V) and 400 kHz (5V) compatibility

• Factory programming (QTP) available

• 1,000,000 erase/write cycles guaranteed

• Data retention > 200 years

• 8-pin PDIP and SOIC package

• Available for extended temperature ranges

- Commercial (C): 0˚C to +70˚C

- Industrial (I): -40˚C to +85˚C

2

compatible

DESCRIPTION

The Microchip Technology Inc. 24LC21 is a 128 x 8 bit
Electrically Erasable PROM. This device is designed for
use in applications requiring storage and serial trans­mission of configuration and control information. Two
modes of operation have been implemented: Transmit
Only Mode and Bi-Directional Mode. Upon power-up,
the device will be in the Transmit Only Mode, sending a
serial bit stream of the entire memory array contents,
clocked by the VCLK pin. A valid high to low transition
on the SCL pin will cause the device to enter the
Bi-Directional Mode, with byte selectable read/write
capability of the memory array. The 24LC21 is available
in a standard 8-pin PDIP and SOIC package in both
commercial and industrial temperature ranges.

PACKA GE TYPES

PDIP

NC

1

NC

2

NC

3

V

4

SS

SOIC

1
2

3

4

V

NC
NC

NC

SS

BLOCK DIAGRAM

VCLK

I/O

CONTROL

LOGIC

SDA SCL

MEMORY

CONTROL

LOGIC

24LC21

24LC21

XDEC

8

VCC

7

VCLK

6

SCL

5

SDA

8

V

CC

7

VCLK

5

SCL

5

SDA

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

V

CC

VSS

DDC is a trademark of the Video Electronics StandarDs Association.

2

I

C is a trademark of Philips Corporation.

1996 Microchip Technology Inc. DS21095F-page 1

SENSE AMP

R/W CONTROL

24LC21



≥

µ

µ

µ A µ

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maxim

CC

V

...................................................................................7.0V

All inputs and outputs w.r.t. V

Storage temperature.....................................-65˚C to +150˚C

Ambient temp. with power applied................-65˚C to +125˚C

Soldering temperature of leads (10 seconds).............+300˚C

ESD protection on all pins ..................................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

um Ratings*

SS

............... -0.6V to V

CC

+1.0V

TABLE 1-1: PIN FUNCTION TABLE

TABLE 1-2: DC CHARACTERISTICS

CC

V

= +2.5V to 5.5V
Commercial (C): Tamb = 0˚C to +70˚C
Industrial (I): Tamb = -40˚C to +85˚C

Parameter Symbol Min Max Units Conditions

SCL and SDA pins:

High level input voltage
Low level input voltage

IH

V

V

IL

Input levels on VCLK pin:

High level input voltage

Low level input voltage
Hysteresis of Schmitt trigger inputs V
Low level output voltage V
Low level output voltage V
Input leakage current I
Output leakage current I
Pin capacitance (all inputs/outputs) C

Operating current I

Standby current I

I

CC

CC

V

V

IN

, C

Read

CCS

IH

IL
HYS
OL1
OL2

LI

LO

OUT

Write

Note 1: This parameter is periodically sampled and not 100% tested.

2: V

LCK

must be grounded.

CC

.7 V

—

.3 V

2.0
—

.2 V

.05 V

CC

—.4VI
—.6VI

-10 10

-10 10
—10pFV

—
—

—
—

Name Function

V

SS

Ground

SDA Serial Address/Data I/O

SCL Serial Clock (Bi-Directional Mode)

VCLK Serial Clock (Transmit-Only Mode)

V

CC

+2.5V to 5.5V Power Supply

NC No Connection

—

CC

.8

CC

V
V

V
V

CC

V

2.7V (Note 1)

CC

V

< 2.7V (Note 1)

— V (Note 1)

OL

= 3 mA, V
= 6 mA, V

OL

AV
AV

IN

= .1V to V

= .1V to V

OUT
CC

= 5.0V (Note1),

Tamb = 25 ° C, F

3

mAmAV

= 5.5V, SCL = 400 kHz

CC

CC

= 2.5V (Note 1)
= 2.5V

CC

CC

CC

CLK

= 1 MHz

1

30

100

A

CC

V

= 3.0V, SDA = SCL = V

V

= 5.5V, SDA = SCL = V

CC

(Note 2)

CC
CC

DS21095F-page 2

1996 Microchip Technology Inc.

TABLE 1-3: AC CHARACTERISTICS



≤

24LC21

Parameter Symbol

Standard Mode

Vcc= 4.5 - 5.5V

Fast Mode

Units Remarks

Min Max Min Max

Clock frequency F
Clock high time T
Clock low time T
SDA and SCL rise time T
SDA and SCL fall time T
START condition hold time T

HD

CLK

HIGH

LOW

R
F

STA

:

— 100 — 400 kHz
4000 — 600 — ns
4700 — 1300 — ns

— 1000 — 300 ns (Note 1)

— 300 — 300 ns (Note 1)
4000 — 600 — ns After this period the first clock

pulse is generated

START condition setup
time

Data input hold time T
Data input setup time T
STOP condition setup time T
Output valid from clock T
Bus free time T

T

SU

:

4700 — 600 — ns Only relevant for repeated

STA

START condition

HD

DAT
SU
SU

:
:

STO

:

AA

BUF

DAT

0 — 0 — ns (Note 2)

250 — 100 — ns

4000 — 600 — ns

— 3500 — 900 ns (Note 2)

4700 — 1300 — ns Time the bus must be free

before a new transmission
can start

Output fall time from V
min to V

IL

max

Input filter spike suppres-

IH

OF

T

SP

T

— 250 20 + .1

B

C

250 ns (Note 1), C

— 50 — 50 ns (Note 3)

B

100 pF

sion (SDA and SCL pins)
Write cycle time T

WR

— 10 — 10 ms Byte or Page mode

Transmit-Only Mode Parameters

Output valid from VCLK T
VCLK high time T
VCLK low time T
Mode transition time T
Transmit-Only power up

VAA

VHIGH

VLOW

VHZ

T

VPU

— 2000 — 1000 ns
4000 — 600 — ns
4700 — 1300 — ns

— 500 — 500 ns

0—0—ns

time
Endurance — 10M — 10M — cycles 25 ° C, Vcc = 5.0V , Block Mode

(Note 4)

= total capacitance of one bus line in pF.

Note 1: Not 100% tested. C

B

2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (min-

imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined T

noise and spike suppression. This eliminates the need for a T

SP

and V

HYS

specifications are due to new Schmitt trigger inputs which provide improved

specification for standard operation.

I

4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-

cation, please consult the Total Endurance Model which can be obtained on our BBS or website.

1996 Microchip Technology Inc. DS21095F-page 3

24LC21



2.0 FUNCTIONAL DESCRIPTION

The 24LC21 operates in two modes, the Transmit-Only
Mode and the Bi-Directional Mode. There is a separate
two wire protocol to support each mode, each having a
separate clock input and sharing a common data line
(SDA). The device enters the Transmit-Only Mode upon
power-up. In this mode, the device transmits data bits
on the SDA pin in response to a clock signal on the
VCLK pin. The device will remain in this mode until a
valid high to low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the Bi-Directional Mode. The only
way to switch the device back to the Transmit-Only
Mode is to remove power from the device.

2.1 T

The device will power up in the Transmit-Only Mode.
This mode supports a unidirectional two wire protocol
for transmission of the contents of the memory array.
This device requires that it be initialized prior to valid
data being sent in the Transmit-Only Mode (see Initial­ization Procedure, below). In this mode, data is trans­mitted on the SDA pin in 8 bit bytes, each followed by a

FIGURE 2-1: TRANSMIT ONLY MODE

ransmit-Only Mode

ninth, null bit (see Figure 2-1). The clock source for the
Transmit-Only Mode is provided on the VCLK pin, and
a data bit is output on the rising edge on this pin. The
eight bits in each byte are transmitted most significant
bit first. Each byte within the memory array will be out­put in sequence. When the last byte in the memory
array is transmitted, the output will wrap around to the
first location and continue. The Bi-Directional Mode
Clock (SCL) pin must be held high for the device to
remain in the Transmit-Only Mode.

2.2 Initialization Pr

After V
mit-Only Mode. Nine clock cycles on the VCLK pin must
be given to the device for it to perform internal synchro­nization. During this period, the SDA pin will be in a high
impedance state. On the rising edge of the tenth clock
cycle, the device will output the first valid data bit which
will be the most significant bit of a byte. The device will
power up at an indeterminate byte address. (See
Figure 2-2).

has stabilized, the device will be in the Trans-

CC

ocedure

SCL

TVAA TVAA

SDA

BIT 1 (LSB)

VCLK

TVLOWTVHIGH

FIGURE 2-2: DEVICE INITIALIZATION

VCC

SCL

SDA

TVPU

NULL BIT

BIT 1 (MSB) BIT 7

TVAA TVAA

BIT 8BIT 7HIGH IMPEDANCE FOR 9 CLOCK CYCLES

VCLK

DS21095F-page 4

12 891011

1996 Microchip Technology Inc.

24LC21

3.0 BI-DIRECTIONAL MODE

The 24LC21 can be switched into the Bi-Directional
Mode (see Figure 3-1) by applying a valid high to low
transition on the Bi-Directional Mode Clock (SCL).
When the device has been switched into the Bi-Direc­tional Mode, the VCLK input is disregarded, with the
exception that a logic high level is required to enable
write capability. This mode supports a two wire bi-direc­tional data transmission protocol. In this protocol, a
device that sends data on the bus is defined to be the
transmitter, and a device that receives data from the
bus is defined to be the receiver. The bus must be con­trolled by a master device that generates the Bi-Direc­tional Mode Clock (SCL), controls access to the bus
and generates the START and STOP conditions, while
the 24LC21 acts as the slave. Both master and slave
can operate as transmitter or receiver, but the master
device determines which mode is activated.

3.1 Bi-Directional Mode Bus Characteristics

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus is

not busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (see Figure 3-2).

3.1.1 BUS NOT BUSY (A)

Both data and clock lines remain HIGH.

3.1.2 START DATA TRANSFER (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a STAR T condition. All
commands must be preceded by a START condition.

3.1.3 STOP DATA TRANSFER (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

FIGURE 3-1: MODE TRANSITION

Transmit Only Mode

SCL

TVHZ

SDA

VCLK

Bi-Directional Mode

FIGURE 3-2: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

VHYS

SCL

TSU:STA

SDA

THD:STA

TSU:STO

START STOP

 1996 Microchip Technology Inc. DS21095F-page 5

24LC21

3.1.4 DATA VALID (D)
The state of the data line represents valid data when,

after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last
eight will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.

3.1.5 ACKNOWLEDGE
Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

Note: The 24LC21 does not generate any

acknowledge bits if an internal program­ming cycle is in progress.

The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.

FIGURE 3-3: BUS TIMING START/STOP

SCL

TSU:STA

SDA

START STOP

THD:STA

FIGURE 3-4: BUS TIMING DATA

TF

THIGH

TLOW

SCL

TSU:STA

SDA

IN

SDA
OUT

TSP

TAA

THD:STA

THD:STA

VHYS

THD:DAT TSU:DAT

TAA

TSU:STO

TR

TSU:STO

TBUF

DS21095F-page 6  1996 Microchip Technology Inc.

24LC21

3.1.6 SLAVE ADDRESS
After generating a START condition, the bus master

transmits the slave address consisting of a 7-bit device
code (1010) for the 24LC21, followed by three don’t
care bits.

The eighth bit of slave address determines if the master
device wants to read or write to the 24LC21 (see
Figure 3-5).

The 24LC21 monitors the bus for its corresponding
slave address all the time. It generates an acknowledge
bit if the slave address was true and it is not in a pro­gramming mode.

Operation Control Code Chip Select R/W

Read 1010 XXX 1

Write 1010 XXX 0

FIGURE 3-5: CONTROL BYTE

ALLOCATION

STAR T READ/WRITE

SLAVE ADDRESS

R/W

A

4.0 WRITE OPERATION

4.1 Byte Write

Following the start signal from the master, the slave
address (4 bits), the don’t care bits (3 bits) and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24LC21. After receiving
another acknowledge signal from the 24LC21 the mas­ter device will transmit the data word to be written into
the addressed memory location. The 24LC21 acknowl­edges again and the master generates a stop condi­tion. This initiates the internal write cycle, and during
this time the 24LC21 will not generate acknowledge
signals (see Figure 4-1).

It is required that VCLK be held at a logic high level in
order to program the device. This applies to byte write
and page write operation. Note that VCLK can go low
while the device is in its self-timed program operation
and not affect programming.

4.2 Page Write

1010XXX

FIGURE 4-1: BYTE WRITE

S

BUS ACTIVITY
MASTER

T
A
R
T

CONTROL

BYTE

The write control byte, word address and the first data
byte are transmitted to the 24LC21 in the same way as
in a byte write. But instead of generating a stop condi­tion the master transmits up to eight data bytes to the
24LC21 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains con­stant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter­nal write cycle will begin (see Figure 4-2).

It is required that VCLK be held at a logic high level in
order to program the device. This applies to byte write
and page write operation. Note that VCLK can go low
while the device is in its self-timed program operation
and not affect programming.

WORD

ADDRESS

DATA

S
T
O
P

SDA LINE

BUS ACTIVITY

VCLK

 1996 Microchip Technology Inc. DS21095F-page 7

S P

A
C
K

A
C
K

A
C
K

24LC21

FIGURE 4-2: PAGE WRITE

S

BUS ACTIVITY
MASTER

T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n DATA n + 15

DATA n + 1

S
T
O
P

SDA LINE

BUS ACTIVITY

VCLK

S P

A
C
K

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com­mand has been issued from the master, the device ini­tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send­ing a start condition followed by the control byte for a
write command (R/W
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for the flow diagram.

= 0). If the device is still busy with

A
C
K

A
C
K

A
C
K

FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

A
C
K

Send Control Byte

with R/W = 0

Did Device

Acknowledge

NO

(ACK = 0)?

YES

Next

Operation

6.0 WRITE PROTECTION

When using the 24LC21 in the Bi-Directional Mode, the
VCLK pin operates as the write protect control pin. Set­ting VCLK high allows normal write operations, while
setting VCLK low prevents writing to any location in the
array. Connecting the VCLK pin to V
24LC21 to operate as a serial ROM, although this con­figuration would prevent using the device in the Trans­mit-Only Mode.

SS would allow the

DS21095F-page 8  1996 Microchip Technology Inc.

24LC21

7.0 READ OPERATION

Read operations are initiated in the same way as write
operations with the exception that the R/W
slave address is set to one. There are three basic types
of read operations: current address read, random read
and sequential read.

7.1 Current Address Read

The 24LC21 contains an address counter that main­tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address
with R/W

bit set to one, the 24LC21 issues an acknowl­edge and transmits the eight bit data word. The master
will not acknowledge the transfer but does generate a
stop condition and the 24LC21 discontinues transmis­sion (Figure 7-1).

7.2 Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC21 as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is

bit of the

set. Then the master issues the control byte again but
with the R/W

bit set to a one. The 24LC21 will then
issue an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LC21 discon­tinues transmission (Figure 7-2).

7.3 Sequential Read

Sequential reads are initiated in the same way as a ran­dom read except that after the 24LC21 transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC21 to transmit the next sequentially
addressed 8 bit word (see Figure 7-3).

To provide sequential reads the 24LC21 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.

7.4 Noise Protection

The 24LC21 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the V
is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

CC

FIGURE 7-1: CURRENT ADDRESS READ

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

T
A
R
T

CONTROL

SP

FIGURE 7-2: RANDOM READ

S
T

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

CONTROL

A

BYTE

R
T

S P

A
C
K

BYTE

WORD

ADDRESS (n)

A
C
K

A
C
K

S
T
A
R
T

S

CONTROL

BYTE

DATA n

A
C
K

DATA n

S
T
O
P

N
O

A

C

K

S
T
O
P

N

O

A
C
K

 1996 Microchip Technology Inc. DS21095F-page 9

24LC21

FIGURE 7-3: SEQUENTIAL READ

BUS ACTIVITY
MASTER

CONTROL

BYTE

DATA n DATA n + 1 DATA n + 2 DATA n + X

S
T
O
P

SDA LINE

BUS ACTIVITY

A
C
K

A
C
K

8.0 PIN DESCRIPTIONS

8.1 SDA

This pin is used to transfer addresses and data into and
out of the device, when the device is in the Bi-Direc­tional Mode. In the Transmit-Only Mode, which only
allows data to be read from the device, data is also
transferred on the SDA pin. This pin is an open drain
terminal, therefore the SDA bus requires a pullup resis­tor to V

CC (typical 10KΩ for 100 kHz, 1KΩ for 400 kHz).

For normal data transfer in the Bi-Directional Mode,
SDA is allowed to change only during SCL low.
Changes during SCL high are reserved for indicating
the START and STOP conditions.

P

A
C
K

A
C
K

N
O

A
C
K

8.2 SCL

This pin is the clock input for the Bi-Directional Mode,
and is used to synchronize data transfer to and from the
device. It is also used as the signaling input to switch
the device from the Transmit Only Mode to the Bi-Direc­tional Mode. It must remain high for the chip to continue
operation in the Transmit Only Mode.

8.3 VCLK

This pin is the clock input for the Transmit Only Mode.
In the Transmit Only Mode, each bit is clocked out on
the rising edge of this signal. In the Bi-Directional
Mode, a high logic level is required on this pin to enable
write capability.

DS21095F-page 10  1996 Microchip Technology Inc.

24LC21

24LC21 Product Identification System

To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.

24LC21 -/P

Package: P = Plastic DIP (300 mil Body), 8-lead

Temperature Blank = 0˚C to +70˚C
Range: I = -40˚C to +85˚C

Device: 24LC21 Dual Mode I

SN = Plastic SOIC (150 mil Body), 8-lead

2

C Serial EEPROM

2

24LC21T Dual Mode I

C Serial EEPROM (Tape and Reel)

 1996 Microchip Technology Inc. DS21095F-page 11

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Tel: [phone] Fax: [phone]

Korea

Microchip Technology
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku,
Seoul, Korea
Tel: [phone] Fax: [phone]

Singapore

Microchip Technology
200 Middle Road
#10-03 Prime Centre
Singapore 188980
Tel: [phone] Fax: [phone]

Taiwan, R.O.C

Microchip Technology
10F-1C 207
Tung Hua North Road
Taipei, Taiwan, ROC
Tel: [phone] Fax: [phone]

EUROPE

United Kingdom

Arizona Microchip Technology Ltd.
Unit 6, The Courtyard
Meadow Bank, Furlong Road
Bourne End, Buckinghamshire SL8 5AJ
Tel: [phone] Fax: [phone]

France

Arizona Microchip Technology SARL
Zone Industrielle de la Bonde
2 Rue du Buisson aux Fraises
91300 Massy - France
Tel: [phone] Fax: [phone]

Germany

Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 Muenchen, Germany
Tel: [phone] Fax: [phone]

Italy

Arizona Microchip Technology SRL
Centro Direzionale Colleone Pas Taurus 1
Viale Colleoni 1
20041 Agrate Brianza
Milan Italy
Tel: [phone] Fax: [phone]

JAPAN

Microchip Technology Intl. Inc.
Benex S-1 6F
3-18-20, Shin Yokohama
Kohoku-Ku, Y okohama
Kanagawa 222 Japan
Tel: [phone] Fax: [phone]

9/3/96

All rights reserved.  1996, Microchip Technology Incorporated, USA. 9/96

Printed on recycled paper.

Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No repre­sentation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement
of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not autho­rized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and
name are registered trademarks of Microchip Technology Inc. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS21095F-page 12  1996 Microchip Technology Inc.