Datasheet 24LC16B-SN, 24LC16B-P Datasheet (Microchip Technology Inc)

 2000 Microchip Technology Inc. Preliminary DS20070L-page 1

FEATURES

• Single supply with operation down to 2.5V

• Low power CMOS technology

- 1 mA active current typical

-10 µA standby current typical at 5.5V

-5 µA standby current typical at 3.0V

• Organized as 8 blocks of 256 bytes (8 x 256 x 8)

• 2-wire serial interface bus, I

2

C compatible

• Schmitt trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz (E-temp) and 400 kHz (C/I-temp)
compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 16 bytes

• 2 ms typical write cycle time for page-write

• Hardware write protect for entire memory

• Can be operated as a serial ROM

• Factory programming (QTP) available

• ESD protection > 4,000V

• 1,000,000 erase/write cycles guaranteed

• Data retention > 200 years

• 8-pin DIP, 8-lead SOIC, 8-lead TSSOP packages

• Available for extended temperature ranges

DESCRIPTION

The Microchip Technology Inc. 24LC16B is a 16K bit
Electrically Erasable PROM. The device is organized
as eight blocks of 256 x 8 bit memory with a 2-wire
serial interface. Low voltage design permits operation
down to 2.5 volts with standby and active currents of
only 5 µA and 1 mA respectively. The 24LC16B also
has a page-write capability for up to 16 bytes of data.
The 24LC16B is available in the standard 8-pin DIP
surface mount SOIC and TSSOP packages.

PACKAGE TYPES

BLOCK DIAGRAM

- Commercial (C): 0°C

to

+70°C

- Industrial (I): -40°C

to

+85°C

- Automotive (E): -40°C

to

+125°C

24LC16B

A0

A1

A2

V

SS

1

2

3

4

8

7

6

5

VCC

WP

SCL

SDA

24LC16B

A0

A1

A2

V

SS

1

2

3

4

8

7

6

5

V

CC

WP

SCL

SDA

8-Lead PDIP

8-Lead SOIC

24LC16B

A0

A1

A2

V

SS

1

2

3

4

8

7

6

5

VCC

WP

SCL

SDA

8-Lead TSSOP

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

WP

SDA SCL

VCC
VSS

I2C is a trademark of Philips Corporation.

24LC16B

16K 2.5V I2C™ Serial EEPROM

24LC16B

DS20070L-page 2 Preliminary  2000 Microchip Technology Inc.

1.0 ELECTRICAL
CHARACTERISTICS

1.1 Maximum Ratings*

VCC...................................................................................7.0V

All inputs and outputs w.r.t. V

SS ............... -0.3V to VCC +1.0V

Storage temperature .....................................-65°C to +150°C

Ambient temp. with power applied ................-65°C to +125°C

Soldering temperature of leads (10 seconds) .............+300°C

ESD protection on all pins

..................................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

TABLE 1-2: DC CHARACTERISTICS

FIGURE 1-1: BUS TIMING START/STOP

Name Function

VSS

Ground

SDA Serial Address/Data I/O

SCL Serial Clock

WP Write Protect Input

V

CC +2.5V to 5.5V Power Supply

A0, A1, A2 No Internal Connection

Vcc = +2.5V to +5.5V
Commercial (C): Tamb = 0°C to +70°C
Industrial (I): Tamb = -40°C to +85°C
Automotive (E) Tamb = -40°C to +125°C

Parameter Symbol Min Max Units Conditions

WP, SCL and SDA pins:

High level input voltage

V

IH .7 VCC — V

Low level input voltage

V

IL — .3 VCC V

Hysteresis of Schmitt trigger
inputs

V

HYS .05 VCC — V (Note)

Low level output voltage

V

OL — .40 V IOL = 3.0 mA, VCC = 2.5V

Input leakage current I

LI -10 10 µAVIN = .1V to VCC

Output leakage current ILO -10 10 µΑ VOUT = .1V to VCC

Pin capacitance
(all inputs/outputs)

CIN, COUT — 10 pF VCC = 5.0V (Note)

Ta m b = 25 °C, F

CLK = 1MHz

Operating current

ICC write

I

CC read

—
—

3
1

mAmAV

CC = 5.5V, SCL = 400 kHz

Standby current ICCS —

—

30

100

µΑµΑVCC = 3.0V, SDA = SCL = VCC

VCC = 5.5V, SDA = SCL = VCC
WP = VSS

Note: This parameter is periodically sampled and not 100% tested.

TSU:STA

THD:STA

VHYS

TSU:STO

START STOP

SCL

SDA

 2000 Microchip Technology Inc. Preliminary DS20070L-page 3

24LC16B

TABLE 1-3: AC CHARACTERISTICS

VCC = +2.5V to 5.5V

Commercial (C): Tamb = 0°C to +70°C
Industrial (I): Tamb = -40°C to +85°C
Automotive (E): Tamb = -40°C to 125°C

Parameter Symbol Min Max Units Conditions

Clock frequency

Fclk

—
—

400
100

kHz 4.5V ≤ VCC ≤ 5.5V

2.5V

≤ VCC ≤ 5.5V (E-temp range)

Clock high time T

high

600

4000

—
—

ns 4.5V ≤ VCC ≤ 5.5V

2.5V

≤ VCC ≤ 5.5V (E-temp range)

Clock low time

T

LOW 1300

4700

—
—

ns 4.5V ≤ VCC ≤ 5.5V

2.5V

≤ VCC ≤ 5.5V (E-temp range)

SDA and SCL rise time

(Note 1)

T

R —

—

300

1000

ns 4.5V ≤ VCC ≤ 5.5V (Note 1)

2.5V

≤ VCC ≤ 5.5V (E-temp range) (Note 1)

SDA and SCL fall time

T

F — 300 ns (Note 1)

START condition hold time

T

HD:STA 600

4000

—
—

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V

≤ VCC ≤ 5.5V (E-temp range)

START condition setup time

T

SU:STA 600

4700

—
—

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V

≤ VCC ≤ 5.5V (E-temp range)

Data input hold time

T

HD:DAT 0 — ns (Note 2)

Data input setup time

T

SU:DAT 100

250

—
—

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V

≤ VCC ≤ 5.5V (E-temp range)

STOP condition setup time

T

SU:STO 600

4000

—
—

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V

≤ VCC ≤ 5.5V (E-temp range)

Output valid from clock

(Note 2)

T

AA —

—

900

3500

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V

≤ Vcc ≤ 5.5V (E-temp range)

Bus free time: Time the bus must be
free before a new transmission can
start

T

BUF 1300

4700

—
—

ns 4.5V ≤ Vcc ≤ 5.5V

2.5V

≤ VCC ≤ 5.5V (E-temp range)

Output fall time from V

IH

minimum to VIL maximum

T

OF 20+0.1CB

—

250
250

ns

4.5V≤ VCC ≤ 5.5V

2.5V

≤ VCC ≤ 5.5V (E-temp range)

Input filter spike suppression
(SDA and SCL pins)

T

SP — 50 ns (Notes 1 and 3)

Write cycle time (byte or page)

T

WC — 5ms

Endurance

1M — cycles

25°C, Vcc = 5.0V, Block Mode (Note 4)

Note 1: Not 100% tested. C

B

= total capacitance of one bus line in pF.

Note 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum

300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

Note 3: The combined TSP and VHYS specifications are due to new Schmitt trigger inputs which provide improved noise spike

suppression. This eliminates the need for a TI specification for standard operation.

Note 4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application,

please consult the Total Endurance Model which can be obtained on Microchip’s website.

24LC16B

DS20070L-page 4 Preliminary  2000 Microchip Technology Inc.

FIGURE 1-2: BUS TIMING DATA

TSU:STA

TF

TLOW

THIGH

TR

THD:DAT TSU:DAT

TSU:STO

THD:STA

TBUF

TAA

TAA

TSP

THD:STA

SCL

SCL

IN

SCL

OUT

 2000 Microchip Technology Inc. Preliminary DS20070L-page 5

24LC16B

2.0 FUNCTIONAL DESCRIPTION

The 24LC16B supports a Bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24LC16B
works as slave. Both, master and slave can operate as
transmitter or receiver but the master device deter­mines which mode is activated.

3.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus
is not busy.

• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.

3.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six­teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24LC16B) will leave the data line
HIGH to enable the master to generate the STOP con­dition.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note: The 24LC16B does not generate any

acknowledge bits if an internal program­ming cycle is in progress.

SCL

SDA

(A) (B) (D) (D) (A)(C)

START

CONDITION

ADDRESS OR

ACKN OWLED GE

VAL ID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

24LC16B

DS20070L-page 6 Preliminary  2000 Microchip Technology Inc.

3.6 Device Addressing

A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a four bit control code, for the 24LC16B this
is set as 1010 binary for read and write operations. The
next three bits of the control byte are the block select
bits (B2, B1, B0). They are used by the master device
to select which of the eight 256 word blocks of memory
are to be accessed. These bits are in effect the three
most significant bits of the word address. It should be
noted that the protocol limits the size of the memory to
eight blocks of 256 words, therefore the protocol can
support only one 24LC16B per system.

The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24LC16B monitors
the SDA bus checking the device type identifier being
transmitted, upon a 1010 code the slave device outputs
an acknowledge signal on the SDA line. Depending on
the state of the R/W

bit, the 24LC16B will select a read

or write operation.

FIGURE 3-2: CONTROL BYTE ALLOCATION

Operation Control

Code

Block Select R/W

Read 1010 Block Address 1

Write 1010 Block Address 0

X = Don’t care

1010B2B1B0

R/W

A

START READ/WRITE

SLAVE ADDRESS

 2000 Microchip Technology Inc. Preliminary DS20070L-page 7

24LC16B

4.0 WRITE OPERATION

4.1 Byte Write

Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W

bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted
by the master is the word address and will be written
into the address pointer of the 24LC16B. After receiv­ing another acknowledge signal from the 24LC16B the
master device will transmit the data word to be written
into the addressed memory location. The 24LC16B
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and
during this time the 24LC16B will not generate
acknowledge signals (Figure 4-1).

4.2 Page Write

The write control byte, word address and the first data
byte are transmitted to the 24LC16B in the same way
as in a byte write. But instead of generating a stop con­dition the master transmits up to 16 data bytes to the
24LC16B which are temporarily stored in the on-chip
page buffer and will be written into the memory after the

master has transmitted a stop condition. After the
receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter­nal write cycle will begin (Figure 4-2).

FIGURE 4-1: BYTE WRITE

FIGURE 4-2: PAGE WRITE

Note: Page write operations are limited to writing

bytes within a single physical page,
regardless

of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer multi­ples of the page buffer size (or ‘page size’)
and end at addresses that are integer mul­tiples of [page size - 1]. If a page write com­mand attempts to write across a physical
page boundary, the result is that the data
wraps around to the beginning of the cur­rent page (overwriting data previously
stored there), instead of being written to
the next page as might be expected. It is
therefore necessary for the application
software to prevent page write operations
that would attempt to cross a page bound­ary.

S P

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

WORD

ADDRESS

DATA

A
C
K

A
C
K

A
C
K

S P

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n DATA n + 15

S
T
O
P

A
C
K

A
C
K

A
C
K

A
C
K

A
C
K

DATA n + 1

24LC16B

DS20070L-page 8 Preliminary  2000 Microchip Technology Inc.

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com­mand has been issued from the master, the device ini­tiates the internally timed write cycle. ACK polling can
be initiated immediately. This involves the master send­ing a start condition followed by the control byte for a
write command (R/W

= 0). If the device is still busy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 5-1 for flow diagram.

FIGURE 5-1: ACKNOWLEDGE POLLING FLOW

6.0 WRITE PROTECTION

The 24LC16B can be used as a serial ROM when the
WP pin is connected to V

CC. Programming will be inhib-

ited and the entire memory will be write-protected.

7.0 READ OPERATION

Read operations are initiated in the same way as write
operations with the exception that the R/W

bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random
read, and sequential read.

7.1 Current Address Read

The 24LC16B contains an address counter that main­tains the address of the last word accessed, internally
incremented by one. Therefore, if the previous access
(either a read or write operation) was to address n, the
next current address read operation would access data
from address n + 1. Upon receipt of the slave address
with R/W

bit set to one, the 24LC16B issues an
acknowledge and transmits the eight bit data word. The
master will not acknowledge the transfer but does gen­erate a stop condition and the 24LC16B discontinues
transmission (Figure 7-1).

7.2 Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC16B as part of a write operation. After the word
address is sent, the master generates a start condition
following the acknowledge. This terminates the write
operation, but not before the internal address pointer is
set. Then the master issues the control byte again but
with the R/W

bit set to a one. The 24LC16B will then
issue an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24LC16B dis­continues transmission (Figure 7-2).

7.3 Sequential Read

Sequential reads are initiated in the same way as a ran­dom read except that after the 24LC16B transmits the
first data byte, the master issues an acknowledge as
opposed to a stop condition in a random read. This
directs the 24LC16B to transmit the next sequentially
addressed 8-bit word (Figure 7-3).

To provide sequential reads the 24LC16B contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.

7.4 Noise Protection

The 24LC16B employs a VCC threshold detector circuit
which disables the internal erase/write logic if the V

CC

is below 1.5 volts at nominal conditions.

The SCL and SDA inputs have Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Next

Operation

NO

YES

 2000 Microchip Technology Inc. Preliminary DS20070L-page 9

24LC16B

FIGURE 7-1: CURRENT ADDRESS READ

FIGURE 7-2: RANDOM READ

FIGURE 7-3: SEQUENTIAL READ

8.0 PIN DESCRIPTIONS

8.1 SDA Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pullup
resistor to V

CC (typical 10KΩ for 100 kHz, 2 KΩ for

400 kHz).

For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi­tions.

8.2 SCL Serial Clock

This input is used to synchronize the data transfer from
and to the device.

8.3 WP

This pin must be connected to either VSS or VCC.

If tied to Vss normal memory operation is enabled
(read/write the entire memory 000-7FF).

If tied to V

CC, WRITE operations are inhibited. The

entire memory will be write-protected. Read operations
are not affected.

This feature allows the user to use the 24LC16B as a
serial ROM when WP is enabled (tied to V

CC).

8.4 A0, A1, A2

These pins are not used by the 24LC16B. They may be
left floating or tied to either V

SS or VCC.

SP

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

DATA n

A
C
K

N
O

A
C
K

S P

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

A
C
K

WORD

ADDRESS (n)

CONTROL

BYTE

S
T
A
R
T

DATA (n)

A
C
K

A
C
K

N
O

A
C
K

P

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

CONTROL

BYTE

A
C
K

N
O

A
C
K

DATA n DATA n + 1 DATA n + 2 DATA n + X

A
C
K

A
C
K

A
C
K

24LC16B

DS20070L-page 10 Preliminary  2000 Microchip Technology Inc.

NOTES:

 2000 Microchip Technology Inc. Preliminary DS20070L-page 11

24LC16B

24LC16B PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Sales and Support

24LC16B - T /P

Package: P = Plastic DIP (300 mil Body) 8-lead

SN = Plastic SOIC (150 mil Body),8-lead

ST = Plastic TSSOP, 8-lead

Temperature Blank = 0°C to +70°C
Range: I=–40°C to +85°C

E=–40°C to +125°C

Device: 24LC16B = 16K I

2

C Serial EEPROM

24LC16BT = 16K I

2

C Serial EEPROM (Tape and Reel)

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom­mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: [phone].

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Register on our web site (www.microchip.com/cn) to receive the most current information on our products.

Information contained in this publication regarding device applications and the like is inten ded through suggestion only and may be superseded by updates.
It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by
Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights
arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written
approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property
rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other
trademarks mentioned herein are the property of their respective companies.

DS20070L-page 12 

2000 Microchip Technology Inc.

All rights reserved. © 2000 Microchip Technology Incorporated. Printed in the USA. 3/00 Printed on recycled paper.

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Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa 222-0033 Japan
Tel: [phone] Fax: [phone]

Korea

Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea
Tel: [phone] Fax: [phone]

Shanghai

Microchip Technology
Unit B701, Far East International Plaza,
No. 317, Xianxia Road
Shanghai, 200051 P.R.C
Tel: [phone] Fax: [phone]

ASIA/PACIFIC (continued)

Singapore

Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore 188980
Tel: [phone] Fax: [phone]

Taiwan, R.O.C

Microchip Technology Taiwan
10F-1C 207
Tung Hua North Road
Taip e i , Ta i w a n , R O C
Tel: [phone] Fax: [phone]

EUROPE

Denmark

Microchip Technology Denmark ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: [phone] Fax: [phone]

France

Arizona Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: [phone] Fax: [phone]

Germany

Arizona Microchip Technology GmbH
Gustav-Heinemann-Ring 125
D-81739 München, Germany
Tel: [phone] Fax: [phone]

Italy

Arizona Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: [phone] Fax: [phone]

United Kingdom

Arizona Microchip Technology Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: [phone] Fax: [phone]

01/21/00

WORLDWIDE SALES AND SERVICE

Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999. The
Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro

®

8-bit MCUs, KEELOQ

®

code hopping
devices, Serial EEPROMs and microperipheral
products. In addition, Microchip’s quality
system for the design and manufacture of
development systems is ISO 9001 cer tified.