Microchip Technology Inc 24LC08B-MT, 24LC16B-MT Datasheet



1997 Microchip Technology Inc. DS21224A-page 1

M

24LC08B/16B MODULES

FEATURES

• ISO 7816 compliant contact locations

• Single supply with operation from 2.5-5.5V

• Low power CMOS technology

- 1 mA active current typical

- 10 µ A standby current typical at 5.5V

• Organized as 4 or 8 blocks of 256 bytes
(4 x 256 x 8) or (8 x 256 x 8)

• 2-wire serial interface bus, I

2

C 

compatible

• Schmitt trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz (2.5V) and 400kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 16 bytes

• 2 ms typical write cycle time for page-write

• ESD protection > 4,000V

• 1,000,000 ERASE/WRITE cycles guaranteed

• Data retention > 200 years

• Temperature range

DESCRIPTION

The Microchip Technology Inc. 24LC08B/16B are 8K
and 16K bit Electrically Erasable PROMs in ISO mod­ules for smart card applications. The device is orga­nized as four or eight bloc ks of 256 x 8-bit memory with
a 2-wire serial interface. The 24LC08B and 24LC16B
also have a page-write capability for up to 16 bytes of
data.

ISO MODULE LAYOUT

BLOCK DIAGRAM

- Commercial (C): 0˚C to +70˚C

VSS

SDA

SCL

V

DD

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA SCL

V

CC

VSS

8K/16K I

2

C

™

Serial EEPROMs in ISO Micromodules

I

2

C is a trademark of Philips Corporation.

24LC08B/16B MODULES

DS21224A-page 2



1997 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maxim

um Ratings*

V

CC

...................................................................................7.0V

All inputs and outputs w.r.t. V

SS

................-0.6V to V

CC

+1.0V

Storage temperature.....................................-65˚C to +150˚C

Ambient temp. with power applied................. -65˚C to +125˚C

Soldering temperature of leads (10 seconds).............+300˚C

ESD protection on all pins ..................................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name Function

V

SS

Ground

SDA Serial Data

SCL Serial Clock
V

CC

+2.5V to 5.5V Power Supply

TABLE 1-2 DC CHARACTERISTICS

All Parameters apply across the speci­fied operating ranges unless otherwise
noted.

Commercial (C): Tamb = 0˚C to +70˚C, V

CC

= 2.5V to 5.5V

Parameter Symbol Min. Max. Units Conditions

SCL and SDA pins:

High level input voltage V

IH

0.7 V

CC

V (Note)

Low level input voltage V

IL

0.3 V

CC

V (Note)

Hysteresis of Schmitt trigger inputs V

HYS

0.05 V

CC

— V Vcc ≥ 2.5V (Note)

Low level output voltage V

OL

0.40 V I

OL

= 3.0 mA, V

CC

= 4.5V

I

OL

= 2.1 mA, V

CC

= 2.5V

Input leakage current I

LI

-10 10

µ

A V

IN

= V

CC

or V

SS

Output leakage current I

LO

-10 10

µ

A V

OUT

= V

CC

or V

SS

Pin capacitance (all inputs/outputs) C

IN

,

C

OUT

— 10 pF V

CC

= 5.0V (Note)

Tamb = 25˚C, f = 1 MHz

Operating current I

CC

Write — 3 mA V

CC

= 5.5V, SCL = 400 kHz

I

CC

Read — 1 mA V

CC

= 5.5V, SCL = 400 kHz

Standby current I

CCS

— 100

µ

A V

CC

= 5.5V, SDA = SCL = V

CC

Note: This parameter is periodically sampled and not 100% tested.

24LC08B/16B MODULES



1997 Microchip Technology Inc. DS21224A-page 3

TABLE 1-3 AC CHARACTERISTICS

FIGURE 1-1: BUS TIMING DATA

All parameters apply across the specified operat­ing ranges unless otherwise noted.

Vcc = 2.5V to 5.5V
Commercial (C): Tamb = 0 ° C to +70 ° C

Parameter Symbol

Vcc = 2.5V - 5.5V

STD MODE

Vcc = 4.5V - 5.5V

FAST MODE

Units Remarks

Min. Max. Min. Max.

Clock frequency F

CLK

— 100 — 400 kHz

Clock high time T

HIGH

4000 — 600 — ns

Clock low time T

LOW

4700 — 1300 — ns

SDA and SCL rise time T

R

— 1000 — 300 ns (Note 1)

SDA and SCL fall time T

F

— 300 — 300 ns (Note 1)

START condition hold time T

HD

:

STA

4000 — 600 — ns After this period the first

clock pulse is generated

START condition setup time T

SU

:

STA

4700 — 600 — ns Only relevant for repeated

START condition

Data input hold time T

HD

:

DAT

0 — 0 — ns (Note 2)

Data input setup time T

SU

:

DAT

250 — 100 — ns

STOP condition setup time T

SU

:

STO

4000 — 600 — ns

Output valid from clock T

AA

— 3500 — 900 ns (Note 2)

Bus free time T

BUF

4700 — 1300 — ns Time the bus must be free

before a new transmission
can start

Output fall time from V

IH

minimum to V

IL

maximum

T

OF

— 250 20 +0.1

C

B

250 ns (Note 1), C

B

≤

100 pF

Input filter spike suppression
(SDA and SCL pins)

T

SP

— 50 — 50 ns (Notes 1, 3)

Write cycle time T

WC

— 10 — 10 ms Byte or Page mode

Endurance 1M — 1M — cycles 25 ° C, V

CC

= 5.0V, Block

Mode (Note 4)

Note 1: Not 100% tested. C

B

= total capacitance of one bus line in pF.

2:

As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3:

The combined T

SP

and V

HYS

specifications are due to Schmitt trigger inputs which provide improved noise

spike suppression. This eliminates the need for a TI specification for standard operation.

4:

This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.

TSU:STA

TF

TLOW

THIGH

TR

THD:DAT TSU:DAT

TSU:STO

THD:STA

TBUF

TAA

TAA

TSP

THD:STA

SCL

SDA

IN

SDA
OUT

24LC08B/16B MODULES

DS21224A-page 4  1997 Microchip Technology Inc.

2.0 PAD DESCRIPTIONS

2.1 SDA (Serial Data)

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V

CC (typical 10Ω).

For normal data transfer SD A is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi­tions.

2.2 SCL (Serial Clock)

This input is used to synchronize the data transfer from
and to the device.

3.0 FUNCTIONAL DESCRIPTION

The 24LC08B/16B supports a Bi-directional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener­ates the START and STOP conditions, while the
24LC08B/16B works as slave. Both, master and slave
can operate as transmitter or receiver but the master
device determines which mode is activated.

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus
is not busy.

• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 5-2).

4.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

4.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi­tion.

4.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

4.4 Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.

24LC08B/16B MODULES

 1997 Microchip Technology Inc. DS21224A-page 5

4.5 Acknowledge

Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.

The device that acknowledges, has to pull down the
SDA line during the acknowledge cloc k pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by NOT generating an acknowledge
bit on the last byte that has been clocked out of the
slave. In this case, the slave (24LC08B/16B) will leave
the data line HIGH to enable the master to generate the
STOP condition.

5.0 DEVICE ADDRESSING

A control byte is the first byte received following the
start condition from the master device. The control byte
consists of a 4-bit control code, for the 24LC08B/16B
this is set as 1010 binary for read and write operations.
The next three bits of the control byte are the block
select bits (B2, B1, B0). They are used by the master
device to select which of the eight 256 word blocks of
memory are to be accessed. These bits are in effect the
three most significant bits of the word address.

The last bit of the control byte defines the operation to
be performed. When set to one a read operation is
selected, when set to zero a write operation is selected.
Following the start condition, the 24LC08B/16B moni­tors the SDA bus checking the device type identifier
being transmitted, upon a 1010 code the slave device
outputs an acknowledge signal on the SDA line.
Depending on the state of the R/W

bit, the 24LC08B/

16B will select a read or write operation.

FIGURE 5-1: CONTROL BYTE

ALLOCATION

FIGURE 5-2: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

Note: The 24LC08B/16B does not generate any

acknowledge bits if an internal program­ming cycle is in progress.

Operation

Control

Code

Block Select R/W

Read 1010 Block Address 1
Write 1010 Block Address 0

SLAVE ADDRESS

1 0 1 0 B2 B1 B0

R/W A

START READ/WRITE

(A) (B) (D) (D) (A)(C)

START

CONDITION

ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

SCL

SDA

24LC08B/16B MODULES

DS21224A-page 6  1997 Microchip Technology Inc.

6.0 WRITE OPERATIONS

6.1 Byte Write

Following the start condition from the master, the
device code (4 bits), the block address (3 bits), and the
R/W

bit which is a logic low is placed onto the bus by
the master transmitter. This indicates to the addressed
slave receiver that a b yte with a word address will follo w
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the ne xt byte transmitted b y
the master is the word address and will be written into
the address pointer of the 24LC08B/16B. After receiv­ing another acknowledge signal from the 24LC08B/16B
the master device will transmit the data word to be writ­ten into the addressed memory location. The 24LC08B/
16B acknowledges again and the master generates a
stop condition. This initiates the internal write cycle,
and during this time the 24LC08B/16B will not generate
acknowledge signals (Figure 6-1).

6.2 Page Write

The write control byte, word address and the first data
byte are transmitted to the 24LC08B/16B in the same
way as in a byte write. But instead of generating a stop
condition the master transmits up to 16 data bytes to
the 24LC08B/16B which are temporarily stored in the
on-chip page buffer and will be written into the memory
after the master has transmitted a stop condition. After
the receipt of each word, the four lower order address
pointer bits are internally incremented by one. The
higher order seven bits of the word address remains
constant. If the master should transmit more than 16
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter­nal write cycle will begin (Figure 6-2).

FIGURE 6-1: BYTE WRITE

FIGURE 6-2: PAGE WRITE

S P

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

WORD

ADDRESS

DATA

A
C
K

A
C
K

A
C
K

S P

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n DATA n + 15

S
T
O
P

A
C
K

A
C
K

A
C
K

A
C
K

A
C
K

DATA n + 1

24LC08B/16B MODULES

 1997 Microchip Technology Inc. DS21224A-page 7

7.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the stop condition for a write com­mand has been issued from the master, the device ini­tiates the internally timed write cycle. ACK polling can
be initiated immediately . This inv olv es the master send­ing a start condition followed by the control byte for a
write command (R/W

= 0). If the de vice is still b usy with
the write cycle, then no ACK will be returned. If the
cycle is complete, then the device will return the ACK
and the master can then proceed with the next read or
write command. See Figure 7-1 for flow diagram.

FIGURE 7-1: ACKNOWLEDGE POLLING

FLOW

8.0 READ OPERATIONS

Read operations are initiated in the same way as write
operations with the exception that the R/W

bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random
read, and sequential read.

8.1 Current Address Read

The 24LC08B/16B contains an address counter that
maintains the address of the last word accessed, inter­nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W

bit set to one, the
24LC08B/16B issues an acknowledge and transmits
the 8-bit data word. The master will not acknowledge
the transfer but does generate a stop condition and the
24LC08B/16B discontinues transmission (Figure 8-1).

8.2 Random Read

Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24LC08B/16B as part of a write operation. After the
word address is sent, the master generates a start con­dition following the acknowledge. This terminates the
write operation, but not before the internal address
pointer is set. Then the master issues the control byte
again but with the R/W

bit set to a one.The 24LC08B/
16B will then issue an acknowledge and transmits the
8-bit data word. The master will not acknowledge the
transfer but does generate a stop condition and the
24LC08B/16B discontinues transmission (Figure 8-2).

8.3 Sequential Read

Sequential reads are initiated in the same way as a ran­dom read except that after the 24LC08B/16B transmits
the first data byte, the master issues an acknowledge
as opposed to a stop condition in a random read. This
directs the 24LC08B/16B to transmit the next sequen­tially addressed 8 bit word (Figure 8-3).

To provide sequential reads the 24LC08B/16B contains
an internal address pointer which is incremented by
one at the completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.

8.4 Noise Protection

The 24LC08B/16B employs a VCC threshold detector
circuit which disables the internal erase/write logic if
the V

CC is below 1.5 volts at nominal conditions.

The SCL and SDA inputs hav e Schmitt trigger and filter
circuits which suppress noise spikes to assure proper
device operation even on a noisy bus.

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Next

Operation

NO

YES

24LC08B/16B MODULES

DS21224A-page 8  1997 Microchip Technology Inc.

FIGURE 8-1: CURRENT ADDRESS READ

FIGURE 8-2: RANDOM READ

FIGURE 8-3: SEQUENTIAL READ

S P

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

DATA n

A
C
K

N
O

A
C
K

S P

S

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
A
R
T

S
T
O
P

CONTROL

BYTE

A
C
K

WORD

ADDRESS (n)

CONTROL

BYTE

S
T
A
R
T

DATA (n)

A
C
K

A
C
K

N

O

A
C
K

P

BUS ACTIVITY
MASTER

SDA LINE

BUS ACTIVITY

S
T
O
P

CONTROL

BYTE

A
C
K

N
O

A
C
K

DATA n DATA n + 1 DATA n + 2 DATA n + X

A
C
K

A
C
K

A
C
K

24LC08B/16B MODULES

 1997 Microchip Technology Inc. DS21224A-page 9

9.0 SHIPPING METHOD

The micromodules will be shipped to customers in
clear plastic trays. Each tray holds 150 modules, and
the trays can be stack ed in a manner similar to shipping
die in waffle packs. A tray drawing with dimensions is
shown in Figure 9-1.

FIGURE 9-1: TRAY DIMENSIONS

SMART CARD MODULES

14.000 [355.60]

12.040 [305.82]

9.374 [238.09]

0.500 [12.70]

0.980 [24.89] TYP

0.860 [21.84] TYP.

0.617 [15.68]

0.905 [22.99]

R 0.300 [7.62] TYP

R 0.270 [6.86] TYP

8.145 [206.88]

ANTISTATIC

24LC08B/16B MODULES

DS21224A-page 10  1997 Microchip Technology Inc.

FIGURE 9-2: MODULE DIMENSIONS

0.465 ± 0.002

[11.80 ± 0.05]

0.419 ± 0.002

[10.63 ± 0.05]

A A

0.270 [6.86] MAX.

0.232 ± 0.002

[5.90 ± 0.05]

R. 0.059 [1.50] (4X)

0.090 [2.29] MIN EPOXY

FREE AREA (TYP.)

0.1043 ± 0.002

[2.65 ± 0.05]

(8x)

0.146 ± 0.002

[3.71 ± 0.05]

0.174 ± 0.002

[4.42 ± 0.05]

0.209 ± 0.002

[5.31 ± 0.05]

TYP.

DEVICE SIDE

CONTACT SIDE

0.1043 ± 0.002

[2.65 ± 0.05]

0.285 [7.24] MAX

VIA HOLES (8x)

I.D. ¯ 0.026 [0.66]

O.D. ¯ 0.042 [1.06]

GOLD FLASH 3-7

0.004 [0.10] MAX.

COPPER BASE NICKEL PLATED, 150 MIN

GLOB SIZE

0.007 [0.18] MAX.

SECTION A-A

FR4 TAPE

DIE

m

IN

m

IN

0.015 [0.38] MAX.

0.0235 [0.60] MAX.

24LC08B/16B MODULES

 1997 Microchip Technology Inc. DS21224A-page 11

24LC08B/16B MODULES PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Sales and Support

Package: MT = Micromodules in trays

Temperature
Range:

Blank = 0˚C to +70˚C

Device:

24LC08B 8K bit 2.5V I

2

C Serial EEPROM in ISO Module

24LC16B 16K bit 2.5V I2C Serial EEPROM in ISO Module

24LC08B/16B — /MT

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom­mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office.

2. The Microchip Corporate Literature Center U.S. FAX: [phone].

3. The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or
warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other
intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express
written approval by Microchip. No licenses are convey ed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks
of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS21224A-page 12



1997 Microchip Technology Inc.

M

All rights reserved. © 1997, Microchip Technology Incorporated, USA. 9/97 Printed on recycled paper.

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