Microchip Technology Inc 24LC08B-MT, 24LC16B-MT Datasheet



1997 Microchip Technology Inc. DS21224A-page 1

M

24LC08B/16B MODULES

FEATURES

• ISO 7816 compliant contact locations

• Single supply with operation from 2.5-5.5V

• Low power CMOS technology

- 1 mA active current typical

- 10 µ A standby current typical at 5.5V

• Organized as 4 or 8 blocks of 256 bytes
(4 x 256 x 8) or (8 x 256 x 8)

• 2-wire serial interface bus, I

2

C 

compatible

• Schmitt trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 100 kHz (2.5V) and 400kHz (5V) compatibility

• Self-timed write cycle (including auto-erase)

• Page-write buffer for up to 16 bytes

• 2 ms typical write cycle time for page-write

• ESD protection > 4,000V

• 1,000,000 ERASE/WRITE cycles guaranteed

• Data retention > 200 years

• Temperature range

DESCRIPTION

The Microchip Technology Inc. 24LC08B/16B are 8K
and 16K bit Electrically Erasable PROMs in ISO mod­ules for smart card applications. The device is orga­nized as four or eight bloc ks of 256 x 8-bit memory with
a 2-wire serial interface. The 24LC08B and 24LC16B
also have a page-write capability for up to 16 bytes of
data.

ISO MODULE LAYOUT

BLOCK DIAGRAM

- Commercial (C): 0˚C to +70˚C

VSS

SDA

SCL

V

DD

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA SCL

V

CC

VSS

8K/16K I

2

C

™

Serial EEPROMs in ISO Micromodules

I

2

C is a trademark of Philips Corporation.

24LC08B/16B MODULES

DS21224A-page 2



1997 Microchip Technology Inc.

1.0 ELECTRICAL CHARACTERISTICS

1.1 Maxim

um Ratings*

V

CC

...................................................................................7.0V

All inputs and outputs w.r.t. V

SS

................-0.6V to V

CC

+1.0V

Storage temperature.....................................-65˚C to +150˚C

Ambient temp. with power applied................. -65˚C to +125˚C

Soldering temperature of leads (10 seconds).............+300˚C

ESD protection on all pins ..................................................≥ 4 kV

*Notice: Stresses above those listed under “Maximum ratings”

may cause permanent damage to the device. This is a stress rat­ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name Function

V

SS

Ground

SDA Serial Data

SCL Serial Clock
V

CC

+2.5V to 5.5V Power Supply

TABLE 1-2 DC CHARACTERISTICS

All Parameters apply across the speci­fied operating ranges unless otherwise
noted.

Commercial (C): Tamb = 0˚C to +70˚C, V

CC

= 2.5V to 5.5V

Parameter Symbol Min. Max. Units Conditions

SCL and SDA pins:

High level input voltage V

IH

0.7 V

CC

V (Note)

Low level input voltage V

IL

0.3 V

CC

V (Note)

Hysteresis of Schmitt trigger inputs V

HYS

0.05 V

CC

— V Vcc ≥ 2.5V (Note)

Low level output voltage V

OL

0.40 V I

OL

= 3.0 mA, V

CC

= 4.5V

I

OL

= 2.1 mA, V

CC

= 2.5V

Input leakage current I

LI

-10 10

µ

A V

IN

= V

CC

or V

SS

Output leakage current I

LO

-10 10

µ

A V

OUT

= V

CC

or V

SS

Pin capacitance (all inputs/outputs) C

IN

,

C

OUT

— 10 pF V

CC

= 5.0V (Note)

Tamb = 25˚C, f = 1 MHz

Operating current I

CC

Write — 3 mA V

CC

= 5.5V, SCL = 400 kHz

I

CC

Read — 1 mA V

CC

= 5.5V, SCL = 400 kHz

Standby current I

CCS

— 100

µ

A V

CC

= 5.5V, SDA = SCL = V

CC

Note: This parameter is periodically sampled and not 100% tested.

24LC08B/16B MODULES



1997 Microchip Technology Inc. DS21224A-page 3

TABLE 1-3 AC CHARACTERISTICS

FIGURE 1-1: BUS TIMING DATA

All parameters apply across the specified operat­ing ranges unless otherwise noted.

Vcc = 2.5V to 5.5V
Commercial (C): Tamb = 0 ° C to +70 ° C

Parameter Symbol

Vcc = 2.5V - 5.5V

STD MODE

Vcc = 4.5V - 5.5V

FAST MODE

Units Remarks

Min. Max. Min. Max.

Clock frequency F

CLK

— 100 — 400 kHz

Clock high time T

HIGH

4000 — 600 — ns

Clock low time T

LOW

4700 — 1300 — ns

SDA and SCL rise time T

R

— 1000 — 300 ns (Note 1)

SDA and SCL fall time T

F

— 300 — 300 ns (Note 1)

START condition hold time T

HD

:

STA

4000 — 600 — ns After this period the first

clock pulse is generated

START condition setup time T

SU

:

STA

4700 — 600 — ns Only relevant for repeated

START condition

Data input hold time T

HD

:

DAT

0 — 0 — ns (Note 2)

Data input setup time T

SU

:

DAT

250 — 100 — ns

STOP condition setup time T

SU

:

STO

4000 — 600 — ns

Output valid from clock T

AA

— 3500 — 900 ns (Note 2)

Bus free time T

BUF

4700 — 1300 — ns Time the bus must be free

before a new transmission
can start

Output fall time from V

IH

minimum to V

IL

maximum

T

OF

— 250 20 +0.1

C

B

250 ns (Note 1), C

B

≤

100 pF

Input filter spike suppression
(SDA and SCL pins)

T

SP

— 50 — 50 ns (Notes 1, 3)

Write cycle time T

WC

— 10 — 10 ms Byte or Page mode

Endurance 1M — 1M — cycles 25 ° C, V

CC

= 5.0V, Block

Mode (Note 4)

Note 1: Not 100% tested. C

B

= total capacitance of one bus line in pF.

2:

As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3:

The combined T

SP

and V

HYS

specifications are due to Schmitt trigger inputs which provide improved noise

spike suppression. This eliminates the need for a TI specification for standard operation.

4:

This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific
application, please consult the Total Endurance Model which can be obtained on our BBS or website.

TSU:STA

TF

TLOW

THIGH

TR

THD:DAT TSU:DAT

TSU:STO

THD:STA

TBUF

TAA

TAA

TSP

THD:STA

SCL

SDA

IN

SDA
OUT

24LC08B/16B MODULES

DS21224A-page 4  1997 Microchip Technology Inc.

2.0 PAD DESCRIPTIONS

2.1 SDA (Serial Data)

This is a Bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal, therefore the SDA bus requires a pull-up
resistor to V

CC (typical 10Ω).

For normal data transfer SD A is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi­tions.

2.2 SCL (Serial Clock)

This input is used to synchronize the data transfer from
and to the device.

3.0 FUNCTIONAL DESCRIPTION

The 24LC08B/16B supports a Bi-directional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener­ates the START and STOP conditions, while the
24LC08B/16B works as slave. Both, master and slave
can operate as transmitter or receiver but the master
device determines which mode is activated.

4.0 BUS CHARACTERISTICS

The following bus protocol has been defined:

• Data transfer may be initiated only when the bus
is not busy.

• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been
defined (Figure 5-2).

4.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

4.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi­tion.

4.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.

4.4 Data Valid (D)

The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.

Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.