Microchip Technology Inc 24LC02B-SN, 24LC02B-PN, 24LC01BT-SN Datasheet
1999 Microchip Technology Inc. DS20071J-page 1
24LC01B/02B
FEATURES
• Single supply with operation down to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 10 µA standby current typical at 5.5V
- 5 µA standby current typical at 3.0V
• Organized as a single block of
128 bytes (128 x 8 ) -1K or 256 bytes (256 x 8) -2K
• 2-wire serial interface bus, I
2
C™ compatible
• 100 kHz (2.5V) and 400kHz (5.0V) compatibility
• Self-timed write cycle (including auto-e rase)
• Page-write buffer for up to 8 bytes
• 2 ms typical write cycle time for page-write
• Hardware write protect for entire memory
• Can be operated as a serial ROM
• ESD protection > 3,000V
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
• 8 pin DIP, SOIC, TSSOP* or SOT-23* package
• Available for temperature ranges
DESCRIPTION
The Microchip Technology Inc. 24LC01B and 24LC 02B
are 1K bit and 2K bit Electrically Er asab le PR OMs. Th e
devices are organi zed as a single bloc k of 128 x 8 bit or
256 x 8 bit memory with a two wire serial interface . Low
voltage desig n p ermits oper ation d own to 2. 5 v olt s with
a standby and active currents of only 5 µA and 1 mA
respectively. The 24LC01B and 24LC02B also have
page-write capability for up to 8 bytes of data. The
24LC01B an d 24LC02B ar e available in the stan dard
8-pin DIP and an 8-pin surface mount SOIC package.
The SOT-23 and TSSOP packag es are av ailab le f or the
24LC01B.
PAC KAGE TYPES
BLOCK DIAGRAM
- Commercial (C): 0°C to +70°C
- Industrial (I): -40°C to +85°C
24LC01B/02B
1
2
3
4
8
7
6
5
A0
A1
A2
Vss
Vcc
WP
SCL
SDA
PDIP, SOIC
TSSOP*
15
4
3
24LC01B
SCL
VSS
SDA
WP
Vcc
2
SOT-23*
* Available for 24LC01B only
24LC01B/02B
A0
A1
A2
V
SS
Vcc
WP
SCL
SDA
1
2
3
4
8
7
6
5
HV GENERATOR
EEPROM
ARRAY
PAGE LATCHES
YDEC
XDEC
SENSE AMP
R/W CONTROL
MEMORY
CONTROL
LOGIC
I/O
CONTROL
LOGIC
WP
SDA SCL
V
CC
VSS
1K/2K 2.5V I2C™ Serial EEPROM
* Available for 24LC01B only
24LC01B/02B
DS20071J-page 2 1999 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
1.1 Maximum Ratings*
VCC...................................................................................7.0V
All inputs and outputs w.r .t. V
SS ............... -0.6V to VCC +1.0V
Storage temperature.....................................-65°C to +150°C
Ambient temp. with power applied ................ - 65°C to +125°C
Soldering temperature of leads (10 seconds).............+300°C
ESD protection on all pins.............................................> 3 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
TABLE 1-1: PIN FUNCTION TABLE
FIGURE 1-1: BUS TIMING START/STOP
Name Function
V
SS
SDA
SCL
WP
V
CC
A0, A1, A2
Ground
Serial Address/Data I/O
Serial Clock
Write Protect Input
+2.5V to 5.5V Power Supply
No Internal Connection
TABLE 1-1: DC CHARACTERISTICS
VCC = +2.5V to +5.5V Commercial (C): Tamb = 0°C to +70°C
Industrial (I): Tamb = -40°C to +85°C
Parameter Symbol Min. Max. Units Conditions
WP, SCL and SDA pins:
High level input voltage
V
IH .7 VCC V
Low level input voltage V
IL .3 VCC V
Hysteresis of Schmidt trigger inputs V
HYS .05 VCC — V (Note)
Low level output voltage VOL .40 V IOL = 3.0 mA, VCC = 2.5V
Input leakage current ILI -10 10 µA VIN = .1V to 5.5V
Output leakage current I
LO -10 10 µA VOUT = .1V to 5.5V
Pin capacitance (all inputs/outputs) CIN,
C
OUT
—10pFVCC = 5.0V (Note 1)
Tamb = 25°C, F
CLK = 1 MHz
Operating current I
CC Write — 3 mA VCC = 5.5V, SCL = 400 kHz
ICC Read — 1 mA
Standby current ICCS —30µAVCC = 3.0V, SDA = SCL = VCC
100 µA VCC = 5.5V, SDA = SCL = VCC
WP = VSS
Note: This parameter is periodically sampled and not 100% tested.
SCL
SDA
T
SU:STA
THD:STA
START STOP
VHYS
TSU:STO
24LC01B/02B
1999 Microchip Technology Inc. DS20071J-page 3
TABLE 1-2: AC CHARACTERISTICS
FIGURE 1-2: BUS TIMING DATA
Parameter Symbol
Standard Mode
Vcc = 4.5 - 5.5V
Fast Mode
Units Remarks
Min. Max. Min. Max.
Clock frequency F
CLK — 100 — 400 kHz
Clock high time THIGH 4000 — 600 — ns
Clock low time T
LOW 4700 — 1300 — ns
SDA and SCL rise time TR — 1000 — 300 ns (Note 1)
SDA and SCL fall time TF — 300 — 300 ns (Note 1)
START condition hold time T
HD:STA 4000 — 600 — ns After this period the first
clock pulse is generated
START condition setup time T
SU:STA 4700 — 600 — ns Only relevant for repeated
START condition
Data input hold time T
HD:DAT 0 — 0 — ns (Note 2)
Data input setup time TSU:DAT 250 — 100 — ns
STOP condition setup time T
SU:STO 4000 — 600 — ns
Output valid from clock TAA — 3500 — 900 ns (Note 2)
Bus free time TBUF 4700 — 1300 — ns Time the bus must be free
before a new transmission
can start
Output fall time from VIH
minimum to VIL maximum
T
OF — 250 20 +0.1
CB
250 ns (Note 1), CB ð 100 pF
Input filter spike suppression
(SDA and SCL pins)
T
SP — 50 — 50 ns (Note 3)
Write cycle time T
WR — 10 — 10 ms Byte or Page mode
Endurance — 1M — 1M — cycles 25°C, Vcc = 5.0V, Block
Mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3: The combined T
SP and VHYS specifications are due to new Schmitt trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This par am ete r i s no t t ested but guaranteed by characterization. For endurance esti ma tes i n a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our website.
SCL
SDA
IN
SDA
OUT
T
HD:STA
TSU:STA
TF
THIGH
TR
TSU:STOTSU:DATTHD:DAT
TBUFTAA
THD:STA
TAA
TSP
TLOW
24LC01B/02B
DS20071J-page 4 1999 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
The 24LC01B/02B supports a bi-directional two wire
bus and data transmission protocol. A device that
sends data onto the bus is defined as transmitter, and
a device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), co ntrols th e bu s acce ss, an d gen erates the START and STOP conditions, while the
24LC01B/02B works as slave. Both ma ster and slave
can operate as transmitter or receiver but the master
device determines which mode is activated.
3.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line w hil e the clock line is HI GH w ill b e
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (F igure 3-1).
3.1 Bus Not Busy (A)
Both data and clock lines remain HIGH.
3.2 Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3 Stop Data Transfer (C)
A LOW to HIGH trans ition of the SDA line while the
clock (SCL) is HIGH determi n es a STOP con dit i on . A ll
operations must be ended with a STOP condition.
3.4 Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is det ermined by the master device
and is theoreti cally unli mited , althoug h only the las t sixteen will be store d wh en doi ng a write ope ratio n. Whe n
an overwrite doe s occur i t will r eplac e data in a fi rst in
first out fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line du ring the acknowledge clock pulse in such a
way that the SDA line is stable LOW dur ing the HIGH
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has be en clocke d out of the slav e. In thi s case,
the slave must leave the data li ne HI GH to e nable the
master to generate the STOP condition.
FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note: The 24LC01B/02B does not generate any
acknowledge bits if an internal programming cycle is in progress .
SCL
SDA
(
A) (B) (D) (D) (C) (A)
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
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